drivers/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "kvm.h"
  19 #include "x86.h"
  20 #include "x86_emulate.h"
  21 #include "irq.h"
  22 #include "vmx.h"
  23 #include "segment_descriptor.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 struct vmcs {
  42         u32 revision_id;
  43         u32 abort;
  44         char data[0];
  45 };
  46
  47 struct vcpu_vmx {
  48         struct kvm_vcpu       vcpu;
  49         int                   launched;
  50         u8                    fail;
  51         u32                   idt_vectoring_info;
  52         struct kvm_msr_entry *guest_msrs;
  53         struct kvm_msr_entry *host_msrs;
  54         int                   nmsrs;
  55         int                   save_nmsrs;
  56         int                   msr_offset_efer;
  57 #ifdef CONFIG_X86_64
  58         int                   msr_offset_kernel_gs_base;
  59 #endif
  60         struct vmcs          *vmcs;
  61         struct {
  62                 int           loaded;
  63                 u16           fs_sel, gs_sel, ldt_sel;
  64                 int           gs_ldt_reload_needed;
  65                 int           fs_reload_needed;
  66                 int           guest_efer_loaded;
  67         } host_state;
  68         struct {
  69                 struct {
  70                         bool pending;
  71                         u8 vector;
  72                         unsigned rip;
  73                 } irq;
  74         } rmode;
  75 };
  76
  77 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  78 {
  79         return container_of(vcpu, struct vcpu_vmx, vcpu);
  80 }
  81
  82 static int init_rmode_tss(struct kvm *kvm);
  83
  84 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  85 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  86
  87 static struct page *vmx_io_bitmap_a;
  88 static struct page *vmx_io_bitmap_b;
  89
  90 static struct vmcs_config {
  91         int size;
  92         int order;
  93         u32 revision_id;
  94         u32 pin_based_exec_ctrl;
  95         u32 cpu_based_exec_ctrl;
  96         u32 cpu_based_2nd_exec_ctrl;
  97         u32 vmexit_ctrl;
  98         u32 vmentry_ctrl;
  99 } vmcs_config;
 100
 101 #define VMX_SEGMENT_FIELD(seg)                                  \
 102         [VCPU_SREG_##seg] = {                                   \
 103                 .selector = GUEST_##seg##_SELECTOR,             \
 104                 .base = GUEST_##seg##_BASE,                     \
 105                 .limit = GUEST_##seg##_LIMIT,                   \
 106                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 107         }
 108
 109 static struct kvm_vmx_segment_field {
 110         unsigned selector;
 111         unsigned base;
 112         unsigned limit;
 113         unsigned ar_bytes;
 114 } kvm_vmx_segment_fields[] = {
 115         VMX_SEGMENT_FIELD(CS),
 116         VMX_SEGMENT_FIELD(DS),
 117         VMX_SEGMENT_FIELD(ES),
 118         VMX_SEGMENT_FIELD(FS),
 119         VMX_SEGMENT_FIELD(GS),
 120         VMX_SEGMENT_FIELD(SS),
 121         VMX_SEGMENT_FIELD(TR),
 122         VMX_SEGMENT_FIELD(LDTR),
 123 };
 124
 125 /*
 126  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 127  * away by decrementing the array size.
 128  */
 129 static const u32 vmx_msr_index[] = {
 130 #ifdef CONFIG_X86_64
 131         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 132 #endif
 133         MSR_EFER, MSR_K6_STAR,
 134 };
 135 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 136
 137 static void load_msrs(struct kvm_msr_entry *e, int n)
 138 {
 139         int i;
 140
 141         for (i = 0; i < n; ++i)
 142                 wrmsrl(e[i].index, e[i].data);
 143 }
 144
 145 static void save_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 rdmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static inline int is_page_fault(u32 intr_info)
 154 {
 155         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 156                              INTR_INFO_VALID_MASK)) ==
 157                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 158 }
 159
 160 static inline int is_no_device(u32 intr_info)
 161 {
 162         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 163                              INTR_INFO_VALID_MASK)) ==
 164                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 165 }
 166
 167 static inline int is_invalid_opcode(u32 intr_info)
 168 {
 169         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 170                              INTR_INFO_VALID_MASK)) ==
 171                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 172 }
 173
 174 static inline int is_external_interrupt(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 177                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 178 }
 179
 180 static inline int cpu_has_vmx_tpr_shadow(void)
 181 {
 182         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 183 }
 184
 185 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 186 {
 187         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 188 }
 189
 190 static inline int cpu_has_secondary_exec_ctrls(void)
 191 {
 192         return (vmcs_config.cpu_based_exec_ctrl &
 193                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 194 }
 195
 196 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
 197 {
 198         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 199                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 200 }
 201
 202 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 203 {
 204         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 205                 (irqchip_in_kernel(kvm)));
 206 }
 207
 208 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 209 {
 210         int i;
 211
 212         for (i = 0; i < vmx->nmsrs; ++i)
 213                 if (vmx->guest_msrs[i].index == msr)
 214                         return i;
 215         return -1;
 216 }
 217
 218 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 219 {
 220         int i;
 221
 222         i = __find_msr_index(vmx, msr);
 223         if (i >= 0)
 224                 return &vmx->guest_msrs[i];
 225         return NULL;
 226 }
 227
 228 static void vmcs_clear(struct vmcs *vmcs)
 229 {
 230         u64 phys_addr = __pa(vmcs);
 231         u8 error;
 232
 233         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 234                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 235                       : "cc", "memory");
 236         if (error)
 237                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 238                        vmcs, phys_addr);
 239 }
 240
 241 static void __vcpu_clear(void *arg)
 242 {
 243         struct vcpu_vmx *vmx = arg;
 244         int cpu = raw_smp_processor_id();
 245
 246         if (vmx->vcpu.cpu == cpu)
 247                 vmcs_clear(vmx->vmcs);
 248         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 249                 per_cpu(current_vmcs, cpu) = NULL;
 250         rdtscll(vmx->vcpu.host_tsc);
 251 }
 252
 253 static void vcpu_clear(struct vcpu_vmx *vmx)
 254 {
 255         if (vmx->vcpu.cpu == -1)
 256                 return;
 257         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 258         vmx->launched = 0;
 259 }
 260
 261 static unsigned long vmcs_readl(unsigned long field)
 262 {
 263         unsigned long value;
 264
 265         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 266                       : "=a"(value) : "d"(field) : "cc");
 267         return value;
 268 }
 269
 270 static u16 vmcs_read16(unsigned long field)
 271 {
 272         return vmcs_readl(field);
 273 }
 274
 275 static u32 vmcs_read32(unsigned long field)
 276 {
 277         return vmcs_readl(field);
 278 }
 279
 280 static u64 vmcs_read64(unsigned long field)
 281 {
 282 #ifdef CONFIG_X86_64
 283         return vmcs_readl(field);
 284 #else
 285         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 286 #endif
 287 }
 288
 289 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 290 {
 291         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 292                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 293         dump_stack();
 294 }
 295
 296 static void vmcs_writel(unsigned long field, unsigned long value)
 297 {
 298         u8 error;
 299
 300         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 301                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 302         if (unlikely(error))
 303                 vmwrite_error(field, value);
 304 }
 305
 306 static void vmcs_write16(unsigned long field, u16 value)
 307 {
 308         vmcs_writel(field, value);
 309 }
 310
 311 static void vmcs_write32(unsigned long field, u32 value)
 312 {
 313         vmcs_writel(field, value);
 314 }
 315
 316 static void vmcs_write64(unsigned long field, u64 value)
 317 {
 318 #ifdef CONFIG_X86_64
 319         vmcs_writel(field, value);
 320 #else
 321         vmcs_writel(field, value);
 322         asm volatile ("");
 323         vmcs_writel(field+1, value >> 32);
 324 #endif
 325 }
 326
 327 static void vmcs_clear_bits(unsigned long field, u32 mask)
 328 {
 329         vmcs_writel(field, vmcs_readl(field) & ~mask);
 330 }
 331
 332 static void vmcs_set_bits(unsigned long field, u32 mask)
 333 {
 334         vmcs_writel(field, vmcs_readl(field) | mask);
 335 }
 336
 337 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 338 {
 339         u32 eb;
 340
 341         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 342         if (!vcpu->fpu_active)
 343                 eb |= 1u << NM_VECTOR;
 344         if (vcpu->guest_debug.enabled)
 345                 eb |= 1u << 1;
 346         if (vcpu->rmode.active)
 347                 eb = ~0;
 348         vmcs_write32(EXCEPTION_BITMAP, eb);
 349 }
 350
 351 static void reload_tss(void)
 352 {
 353 #ifndef CONFIG_X86_64
 354
 355         /*
 356          * VT restores TR but not its size.  Useless.
 357          */
 358         struct descriptor_table gdt;
 359         struct segment_descriptor *descs;
 360
 361         get_gdt(&gdt);
 362         descs = (void *)gdt.base;
 363         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 364         load_TR_desc();
 365 #endif
 366 }
 367
 368 static void load_transition_efer(struct vcpu_vmx *vmx)
 369 {
 370         int efer_offset = vmx->msr_offset_efer;
 371         u64 host_efer = vmx->host_msrs[efer_offset].data;
 372         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 373         u64 ignore_bits;
 374
 375         if (efer_offset < 0)
 376                 return;
 377         /*
 378          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 379          * outside long mode
 380          */
 381         ignore_bits = EFER_NX | EFER_SCE;
 382 #ifdef CONFIG_X86_64
 383         ignore_bits |= EFER_LMA | EFER_LME;
 384         /* SCE is meaningful only in long mode on Intel */
 385         if (guest_efer & EFER_LMA)
 386                 ignore_bits &= ~(u64)EFER_SCE;
 387 #endif
 388         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 389                 return;
 390
 391         vmx->host_state.guest_efer_loaded = 1;
 392         guest_efer &= ~ignore_bits;
 393         guest_efer |= host_efer & ignore_bits;
 394         wrmsrl(MSR_EFER, guest_efer);
 395         vmx->vcpu.stat.efer_reload++;
 396 }
 397
 398 static void reload_host_efer(struct vcpu_vmx *vmx)
 399 {
 400         if (vmx->host_state.guest_efer_loaded) {
 401                 vmx->host_state.guest_efer_loaded = 0;
 402                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 403         }
 404 }
 405
 406 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 407 {
 408         struct vcpu_vmx *vmx = to_vmx(vcpu);
 409
 410         if (vmx->host_state.loaded)
 411                 return;
 412
 413         vmx->host_state.loaded = 1;
 414         /*
 415          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 416          * allow segment selectors with cpl > 0 or ti == 1.
 417          */
 418         vmx->host_state.ldt_sel = read_ldt();
 419         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 420         vmx->host_state.fs_sel = read_fs();
 421         if (!(vmx->host_state.fs_sel & 7)) {
 422                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 423                 vmx->host_state.fs_reload_needed = 0;
 424         } else {
 425                 vmcs_write16(HOST_FS_SELECTOR, 0);
 426                 vmx->host_state.fs_reload_needed = 1;
 427         }
 428         vmx->host_state.gs_sel = read_gs();
 429         if (!(vmx->host_state.gs_sel & 7))
 430                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 431         else {
 432                 vmcs_write16(HOST_GS_SELECTOR, 0);
 433                 vmx->host_state.gs_ldt_reload_needed = 1;
 434         }
 435
 436 #ifdef CONFIG_X86_64
 437         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 438         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 439 #else
 440         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 441         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 442 #endif
 443
 444 #ifdef CONFIG_X86_64
 445         if (is_long_mode(&vmx->vcpu))
 446                 save_msrs(vmx->host_msrs +
 447                           vmx->msr_offset_kernel_gs_base, 1);
 448
 449 #endif
 450         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 451         load_transition_efer(vmx);
 452 }
 453
 454 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 455 {
 456         unsigned long flags;
 457
 458         if (!vmx->host_state.loaded)
 459                 return;
 460
 461         ++vmx->vcpu.stat.host_state_reload;
 462         vmx->host_state.loaded = 0;
 463         if (vmx->host_state.fs_reload_needed)
 464                 load_fs(vmx->host_state.fs_sel);
 465         if (vmx->host_state.gs_ldt_reload_needed) {
 466                 load_ldt(vmx->host_state.ldt_sel);
 467                 /*
 468                  * If we have to reload gs, we must take care to
 469                  * preserve our gs base.
 470                  */
 471                 local_irq_save(flags);
 472                 load_gs(vmx->host_state.gs_sel);
 473 #ifdef CONFIG_X86_64
 474                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 475 #endif
 476                 local_irq_restore(flags);
 477         }
 478         reload_tss();
 479         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 480         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 481         reload_host_efer(vmx);
 482 }
 483
 484 /*
 485  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 486  * vcpu mutex is already taken.
 487  */
 488 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 489 {
 490         struct vcpu_vmx *vmx = to_vmx(vcpu);
 491         u64 phys_addr = __pa(vmx->vmcs);
 492         u64 tsc_this, delta;
 493
 494         if (vcpu->cpu != cpu) {
 495                 vcpu_clear(vmx);
 496                 kvm_migrate_apic_timer(vcpu);
 497         }
 498
 499         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 500                 u8 error;
 501
 502                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 503                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 504                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 505                               : "cc");
 506                 if (error)
 507                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 508                                vmx->vmcs, phys_addr);
 509         }
 510
 511         if (vcpu->cpu != cpu) {
 512                 struct descriptor_table dt;
 513                 unsigned long sysenter_esp;
 514
 515                 vcpu->cpu = cpu;
 516                 /*
 517                  * Linux uses per-cpu TSS and GDT, so set these when switching
 518                  * processors.
 519                  */
 520                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 521                 get_gdt(&dt);
 522                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 523
 524                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 525                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 526
 527                 /*
 528                  * Make sure the time stamp counter is monotonous.
 529                  */
 530                 rdtscll(tsc_this);
 531                 delta = vcpu->host_tsc - tsc_this;
 532                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
 533         }
 534 }
 535
 536 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 537 {
 538         vmx_load_host_state(to_vmx(vcpu));
 539 }
 540
 541 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 542 {
 543         if (vcpu->fpu_active)
 544                 return;
 545         vcpu->fpu_active = 1;
 546         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 547         if (vcpu->cr0 & X86_CR0_TS)
 548                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 549         update_exception_bitmap(vcpu);
 550 }
 551
 552 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 553 {
 554         if (!vcpu->fpu_active)
 555                 return;
 556         vcpu->fpu_active = 0;
 557         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 558         update_exception_bitmap(vcpu);
 559 }
 560
 561 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 562 {
 563         vcpu_clear(to_vmx(vcpu));
 564 }
 565
 566 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 567 {
 568         return vmcs_readl(GUEST_RFLAGS);
 569 }
 570
 571 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 572 {
 573         if (vcpu->rmode.active)
 574                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 575         vmcs_writel(GUEST_RFLAGS, rflags);
 576 }
 577
 578 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 579 {
 580         unsigned long rip;
 581         u32 interruptibility;
 582
 583         rip = vmcs_readl(GUEST_RIP);
 584         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 585         vmcs_writel(GUEST_RIP, rip);
 586
 587         /*
 588          * We emulated an instruction, so temporary interrupt blocking
 589          * should be removed, if set.
 590          */
 591         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 592         if (interruptibility & 3)
 593                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 594                              interruptibility & ~3);
 595         vcpu->interrupt_window_open = 1;
 596 }
 597
 598 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 599 {
 600         printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
 601                vmcs_readl(GUEST_RIP));
 602         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 603         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 604                      GP_VECTOR |
 605                      INTR_TYPE_EXCEPTION |
 606                      INTR_INFO_DELIEVER_CODE_MASK |
 607                      INTR_INFO_VALID_MASK);
 608 }
 609
 610 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
 611 {
 612         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 613                      UD_VECTOR |
 614                      INTR_TYPE_EXCEPTION |
 615                      INTR_INFO_VALID_MASK);
 616 }
 617
 618 /*
 619  * Swap MSR entry in host/guest MSR entry array.
 620  */
 621 #ifdef CONFIG_X86_64
 622 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 623 {
 624         struct kvm_msr_entry tmp;
 625
 626         tmp = vmx->guest_msrs[to];
 627         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 628         vmx->guest_msrs[from] = tmp;
 629         tmp = vmx->host_msrs[to];
 630         vmx->host_msrs[to] = vmx->host_msrs[from];
 631         vmx->host_msrs[from] = tmp;
 632 }
 633 #endif
 634
 635 /*
 636  * Set up the vmcs to automatically save and restore system
 637  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 638  * mode, as fiddling with msrs is very expensive.
 639  */
 640 static void setup_msrs(struct vcpu_vmx *vmx)
 641 {
 642         int save_nmsrs;
 643
 644         save_nmsrs = 0;
 645 #ifdef CONFIG_X86_64
 646         if (is_long_mode(&vmx->vcpu)) {
 647                 int index;
 648
 649                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 650                 if (index >= 0)
 651                         move_msr_up(vmx, index, save_nmsrs++);
 652                 index = __find_msr_index(vmx, MSR_LSTAR);
 653                 if (index >= 0)
 654                         move_msr_up(vmx, index, save_nmsrs++);
 655                 index = __find_msr_index(vmx, MSR_CSTAR);
 656                 if (index >= 0)
 657                         move_msr_up(vmx, index, save_nmsrs++);
 658                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 659                 if (index >= 0)
 660                         move_msr_up(vmx, index, save_nmsrs++);
 661                 /*
 662                  * MSR_K6_STAR is only needed on long mode guests, and only
 663                  * if efer.sce is enabled.
 664                  */
 665                 index = __find_msr_index(vmx, MSR_K6_STAR);
 666                 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
 667                         move_msr_up(vmx, index, save_nmsrs++);
 668         }
 669 #endif
 670         vmx->save_nmsrs = save_nmsrs;
 671
 672 #ifdef CONFIG_X86_64
 673         vmx->msr_offset_kernel_gs_base =
 674                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 675 #endif
 676         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 677 }
 678
 679 /*
 680  * reads and returns guest's timestamp counter "register"
 681  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 682  */
 683 static u64 guest_read_tsc(void)
 684 {
 685         u64 host_tsc, tsc_offset;
 686
 687         rdtscll(host_tsc);
 688         tsc_offset = vmcs_read64(TSC_OFFSET);
 689         return host_tsc + tsc_offset;
 690 }
 691
 692 /*
 693  * writes 'guest_tsc' into guest's timestamp counter "register"
 694  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 695  */
 696 static void guest_write_tsc(u64 guest_tsc)
 697 {
 698         u64 host_tsc;
 699
 700         rdtscll(host_tsc);
 701         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 702 }
 703
 704 /*
 705  * Reads an msr value (of 'msr_index') into 'pdata'.
 706  * Returns 0 on success, non-0 otherwise.
 707  * Assumes vcpu_load() was already called.
 708  */
 709 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 710 {
 711         u64 data;
 712         struct kvm_msr_entry *msr;
 713
 714         if (!pdata) {
 715                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 716                 return -EINVAL;
 717         }
 718
 719         switch (msr_index) {
 720 #ifdef CONFIG_X86_64
 721         case MSR_FS_BASE:
 722                 data = vmcs_readl(GUEST_FS_BASE);
 723                 break;
 724         case MSR_GS_BASE:
 725                 data = vmcs_readl(GUEST_GS_BASE);
 726                 break;
 727         case MSR_EFER:
 728                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 729 #endif
 730         case MSR_IA32_TIME_STAMP_COUNTER:
 731                 data = guest_read_tsc();
 732                 break;
 733         case MSR_IA32_SYSENTER_CS:
 734                 data = vmcs_read32(GUEST_SYSENTER_CS);
 735                 break;
 736         case MSR_IA32_SYSENTER_EIP:
 737                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 738                 break;
 739         case MSR_IA32_SYSENTER_ESP:
 740                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 741                 break;
 742         default:
 743                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 744                 if (msr) {
 745                         data = msr->data;
 746                         break;
 747                 }
 748                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 749         }
 750
 751         *pdata = data;
 752         return 0;
 753 }
 754
 755 /*
 756  * Writes msr value into into the appropriate "register".
 757  * Returns 0 on success, non-0 otherwise.
 758  * Assumes vcpu_load() was already called.
 759  */
 760 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 761 {
 762         struct vcpu_vmx *vmx = to_vmx(vcpu);
 763         struct kvm_msr_entry *msr;
 764         int ret = 0;
 765
 766         switch (msr_index) {
 767 #ifdef CONFIG_X86_64
 768         case MSR_EFER:
 769                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 770                 if (vmx->host_state.loaded) {
 771                         reload_host_efer(vmx);
 772                         load_transition_efer(vmx);
 773                 }
 774                 break;
 775         case MSR_FS_BASE:
 776                 vmcs_writel(GUEST_FS_BASE, data);
 777                 break;
 778         case MSR_GS_BASE:
 779                 vmcs_writel(GUEST_GS_BASE, data);
 780                 break;
 781 #endif
 782         case MSR_IA32_SYSENTER_CS:
 783                 vmcs_write32(GUEST_SYSENTER_CS, data);
 784                 break;
 785         case MSR_IA32_SYSENTER_EIP:
 786                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 787                 break;
 788         case MSR_IA32_SYSENTER_ESP:
 789                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 790                 break;
 791         case MSR_IA32_TIME_STAMP_COUNTER:
 792                 guest_write_tsc(data);
 793                 break;
 794         default:
 795                 msr = find_msr_entry(vmx, msr_index);
 796                 if (msr) {
 797                         msr->data = data;
 798                         if (vmx->host_state.loaded)
 799                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 800                         break;
 801                 }
 802                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 803         }
 804
 805         return ret;
 806 }
 807
 808 /*
 809  * Sync the rsp and rip registers into the vcpu structure.  This allows
 810  * registers to be accessed by indexing vcpu->regs.
 811  */
 812 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 813 {
 814         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 815         vcpu->rip = vmcs_readl(GUEST_RIP);
 816 }
 817
 818 /*
 819  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 820  * modification.
 821  */
 822 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 823 {
 824         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
 825         vmcs_writel(GUEST_RIP, vcpu->rip);
 826 }
 827
 828 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 829 {
 830         unsigned long dr7 = 0x400;
 831         int old_singlestep;
 832
 833         old_singlestep = vcpu->guest_debug.singlestep;
 834
 835         vcpu->guest_debug.enabled = dbg->enabled;
 836         if (vcpu->guest_debug.enabled) {
 837                 int i;
 838
 839                 dr7 |= 0x200;  /* exact */
 840                 for (i = 0; i < 4; ++i) {
 841                         if (!dbg->breakpoints[i].enabled)
 842                                 continue;
 843                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 844                         dr7 |= 2 << (i*2);    /* global enable */
 845                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 846                 }
 847
 848                 vcpu->guest_debug.singlestep = dbg->singlestep;
 849         } else
 850                 vcpu->guest_debug.singlestep = 0;
 851
 852         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 853                 unsigned long flags;
 854
 855                 flags = vmcs_readl(GUEST_RFLAGS);
 856                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 857                 vmcs_writel(GUEST_RFLAGS, flags);
 858         }
 859
 860         update_exception_bitmap(vcpu);
 861         vmcs_writel(GUEST_DR7, dr7);
 862
 863         return 0;
 864 }
 865
 866 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 867 {
 868         struct vcpu_vmx *vmx = to_vmx(vcpu);
 869         u32 idtv_info_field;
 870
 871         idtv_info_field = vmx->idt_vectoring_info;
 872         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 873                 if (is_external_interrupt(idtv_info_field))
 874                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 875                 else
 876                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 877         }
 878         return -1;
 879 }
 880
 881 static __init int cpu_has_kvm_support(void)
 882 {
 883         unsigned long ecx = cpuid_ecx(1);
 884         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 885 }
 886
 887 static __init int vmx_disabled_by_bios(void)
 888 {
 889         u64 msr;
 890
 891         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 892         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 893                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 894             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 895         /* locked but not enabled */
 896 }
 897
 898 static void hardware_enable(void *garbage)
 899 {
 900         int cpu = raw_smp_processor_id();
 901         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 902         u64 old;
 903
 904         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 905         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 906                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 907             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 908                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 909                 /* enable and lock */
 910                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 911                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 912                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 913         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 914         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 915                       : "memory", "cc");
 916 }
 917
 918 static void hardware_disable(void *garbage)
 919 {
 920         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 921 }
 922
 923 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 924                                       u32 msr, u32 *result)
 925 {
 926         u32 vmx_msr_low, vmx_msr_high;
 927         u32 ctl = ctl_min | ctl_opt;
 928
 929         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 930
 931         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 932         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 933
 934         /* Ensure minimum (required) set of control bits are supported. */
 935         if (ctl_min & ~ctl)
 936                 return -EIO;
 937
 938         *result = ctl;
 939         return 0;
 940 }
 941
 942 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 943 {
 944         u32 vmx_msr_low, vmx_msr_high;
 945         u32 min, opt;
 946         u32 _pin_based_exec_control = 0;
 947         u32 _cpu_based_exec_control = 0;
 948         u32 _cpu_based_2nd_exec_control = 0;
 949         u32 _vmexit_control = 0;
 950         u32 _vmentry_control = 0;
 951
 952         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 953         opt = 0;
 954         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 955                                 &_pin_based_exec_control) < 0)
 956                 return -EIO;
 957
 958         min = CPU_BASED_HLT_EXITING |
 959 #ifdef CONFIG_X86_64
 960               CPU_BASED_CR8_LOAD_EXITING |
 961               CPU_BASED_CR8_STORE_EXITING |
 962 #endif
 963               CPU_BASED_USE_IO_BITMAPS |
 964               CPU_BASED_MOV_DR_EXITING |
 965               CPU_BASED_USE_TSC_OFFSETING;
 966         opt = CPU_BASED_TPR_SHADOW |
 967               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 968         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 969                                 &_cpu_based_exec_control) < 0)
 970                 return -EIO;
 971 #ifdef CONFIG_X86_64
 972         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
 973                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 974                                            ~CPU_BASED_CR8_STORE_EXITING;
 975 #endif
 976         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
 977                 min = 0;
 978                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
 979                         SECONDARY_EXEC_WBINVD_EXITING;
 980                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
 981                                         &_cpu_based_2nd_exec_control) < 0)
 982                         return -EIO;
 983         }
 984 #ifndef CONFIG_X86_64
 985         if (!(_cpu_based_2nd_exec_control &
 986                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
 987                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
 988 #endif
 989
 990         min = 0;
 991 #ifdef CONFIG_X86_64
 992         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 993 #endif
 994         opt = 0;
 995         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
 996                                 &_vmexit_control) < 0)
 997                 return -EIO;
 998
 999         min = opt = 0;
1000         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1001                                 &_vmentry_control) < 0)
1002                 return -EIO;
1003
1004         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1005
1006         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1007         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1008                 return -EIO;
1009
1010 #ifdef CONFIG_X86_64
1011         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1012         if (vmx_msr_high & (1u<<16))
1013                 return -EIO;
1014 #endif
1015
1016         /* Require Write-Back (WB) memory type for VMCS accesses. */
1017         if (((vmx_msr_high >> 18) & 15) != 6)
1018                 return -EIO;
1019
1020         vmcs_conf->size = vmx_msr_high & 0x1fff;
1021         vmcs_conf->order = get_order(vmcs_config.size);
1022         vmcs_conf->revision_id = vmx_msr_low;
1023
1024         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1025         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1026         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1027         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1028         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1029
1030         return 0;
1031 }
1032
1033 static struct vmcs *alloc_vmcs_cpu(int cpu)
1034 {
1035         int node = cpu_to_node(cpu);
1036         struct page *pages;
1037         struct vmcs *vmcs;
1038
1039         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1040         if (!pages)
1041                 return NULL;
1042         vmcs = page_address(pages);
1043         memset(vmcs, 0, vmcs_config.size);
1044         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1045         return vmcs;
1046 }
1047
1048 static struct vmcs *alloc_vmcs(void)
1049 {
1050         return alloc_vmcs_cpu(raw_smp_processor_id());
1051 }
1052
1053 static void free_vmcs(struct vmcs *vmcs)
1054 {
1055         free_pages((unsigned long)vmcs, vmcs_config.order);
1056 }
1057
1058 static void free_kvm_area(void)
1059 {
1060         int cpu;
1061
1062         for_each_online_cpu(cpu)
1063                 free_vmcs(per_cpu(vmxarea, cpu));
1064 }
1065
1066 static __init int alloc_kvm_area(void)
1067 {
1068         int cpu;
1069
1070         for_each_online_cpu(cpu) {
1071                 struct vmcs *vmcs;
1072
1073                 vmcs = alloc_vmcs_cpu(cpu);
1074                 if (!vmcs) {
1075                         free_kvm_area();
1076                         return -ENOMEM;
1077                 }
1078
1079                 per_cpu(vmxarea, cpu) = vmcs;
1080         }
1081         return 0;
1082 }
1083
1084 static __init int hardware_setup(void)
1085 {
1086         if (setup_vmcs_config(&vmcs_config) < 0)
1087                 return -EIO;
1088         return alloc_kvm_area();
1089 }
1090
1091 static __exit void hardware_unsetup(void)
1092 {
1093         free_kvm_area();
1094 }
1095
1096 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1097 {
1098         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1099
1100         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1101                 vmcs_write16(sf->selector, save->selector);
1102                 vmcs_writel(sf->base, save->base);
1103                 vmcs_write32(sf->limit, save->limit);
1104                 vmcs_write32(sf->ar_bytes, save->ar);
1105         } else {
1106                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1107                         << AR_DPL_SHIFT;
1108                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1109         }
1110 }
1111
1112 static void enter_pmode(struct kvm_vcpu *vcpu)
1113 {
1114         unsigned long flags;
1115
1116         vcpu->rmode.active = 0;
1117
1118         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1119         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1120         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1121
1122         flags = vmcs_readl(GUEST_RFLAGS);
1123         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1124         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1125         vmcs_writel(GUEST_RFLAGS, flags);
1126
1127         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1128                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1129
1130         update_exception_bitmap(vcpu);
1131
1132         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1133         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1134         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1135         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1136
1137         vmcs_write16(GUEST_SS_SELECTOR, 0);
1138         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1139
1140         vmcs_write16(GUEST_CS_SELECTOR,
1141                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1142         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1143 }
1144
1145 static gva_t rmode_tss_base(struct kvm *kvm)
1146 {
1147         if (!kvm->tss_addr) {
1148                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1149                                  kvm->memslots[0].npages - 3;
1150                 return base_gfn << PAGE_SHIFT;
1151         }
1152         return kvm->tss_addr;
1153 }
1154
1155 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1156 {
1157         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1158
1159         save->selector = vmcs_read16(sf->selector);
1160         save->base = vmcs_readl(sf->base);
1161         save->limit = vmcs_read32(sf->limit);
1162         save->ar = vmcs_read32(sf->ar_bytes);
1163         vmcs_write16(sf->selector, save->base >> 4);
1164         vmcs_write32(sf->base, save->base & 0xfffff);
1165         vmcs_write32(sf->limit, 0xffff);
1166         vmcs_write32(sf->ar_bytes, 0xf3);
1167 }
1168
1169 static void enter_rmode(struct kvm_vcpu *vcpu)
1170 {
1171         unsigned long flags;
1172
1173         vcpu->rmode.active = 1;
1174
1175         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1176         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1177
1178         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1179         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1180
1181         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1182         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1183
1184         flags = vmcs_readl(GUEST_RFLAGS);
1185         vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1186
1187         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1188
1189         vmcs_writel(GUEST_RFLAGS, flags);
1190         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1191         update_exception_bitmap(vcpu);
1192
1193         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1194         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1195         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1196
1197         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1198         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1199         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1200                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1201         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1202
1203         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1204         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1205         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1206         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1207
1208         kvm_mmu_reset_context(vcpu);
1209         init_rmode_tss(vcpu->kvm);
1210 }
1211
1212 #ifdef CONFIG_X86_64
1213
1214 static void enter_lmode(struct kvm_vcpu *vcpu)
1215 {
1216         u32 guest_tr_ar;
1217
1218         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1219         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1220                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1221                        __FUNCTION__);
1222                 vmcs_write32(GUEST_TR_AR_BYTES,
1223                              (guest_tr_ar & ~AR_TYPE_MASK)
1224                              | AR_TYPE_BUSY_64_TSS);
1225         }
1226
1227         vcpu->shadow_efer |= EFER_LMA;
1228
1229         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1230         vmcs_write32(VM_ENTRY_CONTROLS,
1231                      vmcs_read32(VM_ENTRY_CONTROLS)
1232                      | VM_ENTRY_IA32E_MODE);
1233 }
1234
1235 static void exit_lmode(struct kvm_vcpu *vcpu)
1236 {
1237         vcpu->shadow_efer &= ~EFER_LMA;
1238
1239         vmcs_write32(VM_ENTRY_CONTROLS,
1240                      vmcs_read32(VM_ENTRY_CONTROLS)
1241                      & ~VM_ENTRY_IA32E_MODE);
1242 }
1243
1244 #endif
1245
1246 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1247 {
1248         vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1249         vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1250 }
1251
1252 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1253 {
1254         vmx_fpu_deactivate(vcpu);
1255
1256         if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1257                 enter_pmode(vcpu);
1258
1259         if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1260                 enter_rmode(vcpu);
1261
1262 #ifdef CONFIG_X86_64
1263         if (vcpu->shadow_efer & EFER_LME) {
1264                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1265                         enter_lmode(vcpu);
1266                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1267                         exit_lmode(vcpu);
1268         }
1269 #endif
1270
1271         vmcs_writel(CR0_READ_SHADOW, cr0);
1272         vmcs_writel(GUEST_CR0,
1273                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1274         vcpu->cr0 = cr0;
1275
1276         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1277                 vmx_fpu_activate(vcpu);
1278 }
1279
1280 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1281 {
1282         vmcs_writel(GUEST_CR3, cr3);
1283         if (vcpu->cr0 & X86_CR0_PE)
1284                 vmx_fpu_deactivate(vcpu);
1285 }
1286
1287 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1288 {
1289         vmcs_writel(CR4_READ_SHADOW, cr4);
1290         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1291                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1292         vcpu->cr4 = cr4;
1293 }
1294
1295 #ifdef CONFIG_X86_64
1296
1297 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1298 {
1299         struct vcpu_vmx *vmx = to_vmx(vcpu);
1300         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1301
1302         vcpu->shadow_efer = efer;
1303         if (efer & EFER_LMA) {
1304                 vmcs_write32(VM_ENTRY_CONTROLS,
1305                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1306                                      VM_ENTRY_IA32E_MODE);
1307                 msr->data = efer;
1308
1309         } else {
1310                 vmcs_write32(VM_ENTRY_CONTROLS,
1311                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1312                                      ~VM_ENTRY_IA32E_MODE);
1313
1314                 msr->data = efer & ~EFER_LME;
1315         }
1316         setup_msrs(vmx);
1317 }
1318
1319 #endif
1320
1321 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1322 {
1323         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1324
1325         return vmcs_readl(sf->base);
1326 }
1327
1328 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1329                             struct kvm_segment *var, int seg)
1330 {
1331         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1332         u32 ar;
1333
1334         var->base = vmcs_readl(sf->base);
1335         var->limit = vmcs_read32(sf->limit);
1336         var->selector = vmcs_read16(sf->selector);
1337         ar = vmcs_read32(sf->ar_bytes);
1338         if (ar & AR_UNUSABLE_MASK)
1339                 ar = 0;
1340         var->type = ar & 15;
1341         var->s = (ar >> 4) & 1;
1342         var->dpl = (ar >> 5) & 3;
1343         var->present = (ar >> 7) & 1;
1344         var->avl = (ar >> 12) & 1;
1345         var->l = (ar >> 13) & 1;
1346         var->db = (ar >> 14) & 1;
1347         var->g = (ar >> 15) & 1;
1348         var->unusable = (ar >> 16) & 1;
1349 }
1350
1351 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1352 {
1353         u32 ar;
1354
1355         if (var->unusable)
1356                 ar = 1 << 16;
1357         else {
1358                 ar = var->type & 15;
1359                 ar |= (var->s & 1) << 4;
1360                 ar |= (var->dpl & 3) << 5;
1361                 ar |= (var->present & 1) << 7;
1362                 ar |= (var->avl & 1) << 12;
1363                 ar |= (var->l & 1) << 13;
1364                 ar |= (var->db & 1) << 14;
1365                 ar |= (var->g & 1) << 15;
1366         }
1367         if (ar == 0) /* a 0 value means unusable */
1368                 ar = AR_UNUSABLE_MASK;
1369
1370         return ar;
1371 }
1372
1373 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1374                             struct kvm_segment *var, int seg)
1375 {
1376         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1377         u32 ar;
1378
1379         if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1380                 vcpu->rmode.tr.selector = var->selector;
1381                 vcpu->rmode.tr.base = var->base;
1382                 vcpu->rmode.tr.limit = var->limit;
1383                 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1384                 return;
1385         }
1386         vmcs_writel(sf->base, var->base);
1387         vmcs_write32(sf->limit, var->limit);
1388         vmcs_write16(sf->selector, var->selector);
1389         if (vcpu->rmode.active && var->s) {
1390                 /*
1391                  * Hack real-mode segments into vm86 compatibility.
1392                  */
1393                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1394                         vmcs_writel(sf->base, 0xf0000);
1395                 ar = 0xf3;
1396         } else
1397                 ar = vmx_segment_access_rights(var);
1398         vmcs_write32(sf->ar_bytes, ar);
1399 }
1400
1401 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1402 {
1403         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1404
1405         *db = (ar >> 14) & 1;
1406         *l = (ar >> 13) & 1;
1407 }
1408
1409 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1410 {
1411         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1412         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1413 }
1414
1415 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1416 {
1417         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1418         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1419 }
1420
1421 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1422 {
1423         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1424         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1425 }
1426
1427 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1428 {
1429         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1430         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1431 }
1432
1433 static int init_rmode_tss(struct kvm *kvm)
1434 {
1435         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1436         u16 data = 0;
1437         int r;
1438
1439         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1440         if (r < 0)
1441                 return 0;
1442         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1443         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1444         if (r < 0)
1445                 return 0;
1446         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1447         if (r < 0)
1448                 return 0;
1449         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1450         if (r < 0)
1451                 return 0;
1452         data = ~0;
1453         r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1454                         sizeof(u8));
1455         if (r < 0)
1456                 return 0;
1457         return 1;
1458 }
1459
1460 static void seg_setup(int seg)
1461 {
1462         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1463
1464         vmcs_write16(sf->selector, 0);
1465         vmcs_writel(sf->base, 0);
1466         vmcs_write32(sf->limit, 0xffff);
1467         vmcs_write32(sf->ar_bytes, 0x93);
1468 }
1469
1470 static int alloc_apic_access_page(struct kvm *kvm)
1471 {
1472         struct kvm_userspace_memory_region kvm_userspace_mem;
1473         int r = 0;
1474
1475         mutex_lock(&kvm->lock);
1476         if (kvm->apic_access_page)
1477                 goto out;
1478         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1479         kvm_userspace_mem.flags = 0;
1480         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1481         kvm_userspace_mem.memory_size = PAGE_SIZE;
1482         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1483         if (r)
1484                 goto out;
1485         kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1486 out:
1487         mutex_unlock(&kvm->lock);
1488         return r;
1489 }
1490
1491 /*
1492  * Sets up the vmcs for emulated real mode.
1493  */
1494 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1495 {
1496         u32 host_sysenter_cs;
1497         u32 junk;
1498         unsigned long a;
1499         struct descriptor_table dt;
1500         int i;
1501         unsigned long kvm_vmx_return;
1502         u32 exec_control;
1503
1504         /* I/O */
1505         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1506         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1507
1508         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1509
1510         /* Control */
1511         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1512                 vmcs_config.pin_based_exec_ctrl);
1513
1514         exec_control = vmcs_config.cpu_based_exec_ctrl;
1515         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1516                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1517 #ifdef CONFIG_X86_64
1518                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1519                                 CPU_BASED_CR8_LOAD_EXITING;
1520 #endif
1521         }
1522         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1523
1524         if (cpu_has_secondary_exec_ctrls()) {
1525                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
1526                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1527                         exec_control &=
1528                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1529                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
1530         }
1531
1532         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1533         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1534         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1535
1536         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1537         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1538         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1539
1540         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1541         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1542         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1543         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1544         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1545         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1546 #ifdef CONFIG_X86_64
1547         rdmsrl(MSR_FS_BASE, a);
1548         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1549         rdmsrl(MSR_GS_BASE, a);
1550         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1551 #else
1552         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1553         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1554 #endif
1555
1556         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1557
1558         get_idt(&dt);
1559         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1560
1561         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1562         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1563         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1564         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1565         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1566
1567         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1568         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1569         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1570         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1571         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1572         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1573
1574         for (i = 0; i < NR_VMX_MSR; ++i) {
1575                 u32 index = vmx_msr_index[i];
1576                 u32 data_low, data_high;
1577                 u64 data;
1578                 int j = vmx->nmsrs;
1579
1580                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1581                         continue;
1582                 if (wrmsr_safe(index, data_low, data_high) < 0)
1583                         continue;
1584                 data = data_low | ((u64)data_high << 32);
1585                 vmx->host_msrs[j].index = index;
1586                 vmx->host_msrs[j].reserved = 0;
1587                 vmx->host_msrs[j].data = data;
1588                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1589                 ++vmx->nmsrs;
1590         }
1591
1592         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1593
1594         /* 22.2.1, 20.8.1 */
1595         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1596
1597         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1598         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1599
1600         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1601                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1602                         return -ENOMEM;
1603
1604         return 0;
1605 }
1606
1607 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1608 {
1609         struct vcpu_vmx *vmx = to_vmx(vcpu);
1610         u64 msr;
1611         int ret;
1612
1613         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1614                 ret = -ENOMEM;
1615                 goto out;
1616         }
1617
1618         vmx->vcpu.rmode.active = 0;
1619
1620         vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1621         set_cr8(&vmx->vcpu, 0);
1622         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1623         if (vmx->vcpu.vcpu_id == 0)
1624                 msr |= MSR_IA32_APICBASE_BSP;
1625         kvm_set_apic_base(&vmx->vcpu, msr);
1626
1627         fx_init(&vmx->vcpu);
1628
1629         /*
1630          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1631          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1632          */
1633         if (vmx->vcpu.vcpu_id == 0) {
1634                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1635                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1636         } else {
1637                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1638                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1639         }
1640         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1641         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1642
1643         seg_setup(VCPU_SREG_DS);
1644         seg_setup(VCPU_SREG_ES);
1645         seg_setup(VCPU_SREG_FS);
1646         seg_setup(VCPU_SREG_GS);
1647         seg_setup(VCPU_SREG_SS);
1648
1649         vmcs_write16(GUEST_TR_SELECTOR, 0);
1650         vmcs_writel(GUEST_TR_BASE, 0);
1651         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1652         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1653
1654         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1655         vmcs_writel(GUEST_LDTR_BASE, 0);
1656         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1657         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1658
1659         vmcs_write32(GUEST_SYSENTER_CS, 0);
1660         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1661         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1662
1663         vmcs_writel(GUEST_RFLAGS, 0x02);
1664         if (vmx->vcpu.vcpu_id == 0)
1665                 vmcs_writel(GUEST_RIP, 0xfff0);
1666         else
1667                 vmcs_writel(GUEST_RIP, 0);
1668         vmcs_writel(GUEST_RSP, 0);
1669
1670         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1671         vmcs_writel(GUEST_DR7, 0x400);
1672
1673         vmcs_writel(GUEST_GDTR_BASE, 0);
1674         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1675
1676         vmcs_writel(GUEST_IDTR_BASE, 0);
1677         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1678
1679         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1680         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1681         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1682
1683         guest_write_tsc(0);
1684
1685         /* Special registers */
1686         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1687
1688         setup_msrs(vmx);
1689
1690         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1691
1692         if (cpu_has_vmx_tpr_shadow()) {
1693                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1694                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1695                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1696                                      page_to_phys(vmx->vcpu.apic->regs_page));
1697                 vmcs_write32(TPR_THRESHOLD, 0);
1698         }
1699
1700         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1701                 vmcs_write64(APIC_ACCESS_ADDR,
1702                              page_to_phys(vmx->vcpu.kvm->apic_access_page));
1703
1704         vmx->vcpu.cr0 = 0x60000010;
1705         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1706         vmx_set_cr4(&vmx->vcpu, 0);
1707 #ifdef CONFIG_X86_64
1708         vmx_set_efer(&vmx->vcpu, 0);
1709 #endif
1710         vmx_fpu_activate(&vmx->vcpu);
1711         update_exception_bitmap(&vmx->vcpu);
1712
1713         return 0;
1714
1715 out:
1716         return ret;
1717 }
1718
1719 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1720 {
1721         struct vcpu_vmx *vmx = to_vmx(vcpu);
1722
1723         if (vcpu->rmode.active) {
1724                 vmx->rmode.irq.pending = true;
1725                 vmx->rmode.irq.vector = irq;
1726                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1727                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1728                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1729                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1730                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1731                 return;
1732         }
1733         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1734                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1735 }
1736
1737 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1738 {
1739         int word_index = __ffs(vcpu->irq_summary);
1740         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1741         int irq = word_index * BITS_PER_LONG + bit_index;
1742
1743         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1744         if (!vcpu->irq_pending[word_index])
1745                 clear_bit(word_index, &vcpu->irq_summary);
1746         vmx_inject_irq(vcpu, irq);
1747 }
1748
1749
1750 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1751                                        struct kvm_run *kvm_run)
1752 {
1753         u32 cpu_based_vm_exec_control;
1754
1755         vcpu->interrupt_window_open =
1756                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1757                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1758
1759         if (vcpu->interrupt_window_open &&
1760             vcpu->irq_summary &&
1761             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1762                 /*
1763                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1764                  */
1765                 kvm_do_inject_irq(vcpu);
1766
1767         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1768         if (!vcpu->interrupt_window_open &&
1769             (vcpu->irq_summary || kvm_run->request_interrupt_window))
1770                 /*
1771                  * Interrupts blocked.  Wait for unblock.
1772                  */
1773                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1774         else
1775                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1776         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1777 }
1778
1779 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1780 {
1781         int ret;
1782         struct kvm_userspace_memory_region tss_mem = {
1783                 .slot = 8,
1784                 .guest_phys_addr = addr,
1785                 .memory_size = PAGE_SIZE * 3,
1786                 .flags = 0,
1787         };
1788
1789         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1790         if (ret)
1791                 return ret;
1792         kvm->tss_addr = addr;
1793         return 0;
1794 }
1795
1796 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1797 {
1798         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1799
1800         set_debugreg(dbg->bp[0], 0);
1801         set_debugreg(dbg->bp[1], 1);
1802         set_debugreg(dbg->bp[2], 2);
1803         set_debugreg(dbg->bp[3], 3);
1804
1805         if (dbg->singlestep) {
1806                 unsigned long flags;
1807
1808                 flags = vmcs_readl(GUEST_RFLAGS);
1809                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1810                 vmcs_writel(GUEST_RFLAGS, flags);
1811         }
1812 }
1813
1814 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1815                                   int vec, u32 err_code)
1816 {
1817         if (!vcpu->rmode.active)
1818                 return 0;
1819
1820         /*
1821          * Instruction with address size override prefix opcode 0x67
1822          * Cause the #SS fault with 0 error code in VM86 mode.
1823          */
1824         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1825                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1826                         return 1;
1827         return 0;
1828 }
1829
1830 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1831 {
1832         struct vcpu_vmx *vmx = to_vmx(vcpu);
1833         u32 intr_info, error_code;
1834         unsigned long cr2, rip;
1835         u32 vect_info;
1836         enum emulation_result er;
1837
1838         vect_info = vmx->idt_vectoring_info;
1839         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1840
1841         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1842                                                 !is_page_fault(intr_info))
1843                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1844                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1845
1846         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1847                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1848                 set_bit(irq, vcpu->irq_pending);
1849                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1850         }
1851
1852         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1853                 return 1;  /* already handled by vmx_vcpu_run() */
1854
1855         if (is_no_device(intr_info)) {
1856                 vmx_fpu_activate(vcpu);
1857                 return 1;
1858         }
1859
1860         if (is_invalid_opcode(intr_info)) {
1861                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1862                 if (er != EMULATE_DONE)
1863                         vmx_inject_ud(vcpu);
1864
1865                 return 1;
1866         }
1867
1868         error_code = 0;
1869         rip = vmcs_readl(GUEST_RIP);
1870         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1871                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1872         if (is_page_fault(intr_info)) {
1873                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1874                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1875         }
1876
1877         if (vcpu->rmode.active &&
1878             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1879                                                                 error_code)) {
1880                 if (vcpu->halt_request) {
1881                         vcpu->halt_request = 0;
1882                         return kvm_emulate_halt(vcpu);
1883                 }
1884                 return 1;
1885         }
1886
1887         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1888             (INTR_TYPE_EXCEPTION | 1)) {
1889                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1890                 return 0;
1891         }
1892         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1893         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1894         kvm_run->ex.error_code = error_code;
1895         return 0;
1896 }
1897
1898 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1899                                      struct kvm_run *kvm_run)
1900 {
1901         ++vcpu->stat.irq_exits;
1902         return 1;
1903 }
1904
1905 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1906 {
1907         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1908         return 0;
1909 }
1910
1911 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1912 {
1913         unsigned long exit_qualification;
1914         int size, down, in, string, rep;
1915         unsigned port;
1916
1917         ++vcpu->stat.io_exits;
1918         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1919         string = (exit_qualification & 16) != 0;
1920
1921         if (string) {
1922                 if (emulate_instruction(vcpu,
1923                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1924                         return 0;
1925                 return 1;
1926         }
1927
1928         size = (exit_qualification & 7) + 1;
1929         in = (exit_qualification & 8) != 0;
1930         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1931         rep = (exit_qualification & 32) != 0;
1932         port = exit_qualification >> 16;
1933
1934         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1935 }
1936
1937 static void
1938 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1939 {
1940         /*
1941          * Patch in the VMCALL instruction:
1942          */
1943         hypercall[0] = 0x0f;
1944         hypercall[1] = 0x01;
1945         hypercall[2] = 0xc1;
1946 }
1947
1948 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1949 {
1950         unsigned long exit_qualification;
1951         int cr;
1952         int reg;
1953
1954         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1955         cr = exit_qualification & 15;
1956         reg = (exit_qualification >> 8) & 15;
1957         switch ((exit_qualification >> 4) & 3) {
1958         case 0: /* mov to cr */
1959                 switch (cr) {
1960                 case 0:
1961                         vcpu_load_rsp_rip(vcpu);
1962                         set_cr0(vcpu, vcpu->regs[reg]);
1963                         skip_emulated_instruction(vcpu);
1964                         return 1;
1965                 case 3:
1966                         vcpu_load_rsp_rip(vcpu);
1967                         set_cr3(vcpu, vcpu->regs[reg]);
1968                         skip_emulated_instruction(vcpu);
1969                         return 1;
1970                 case 4:
1971                         vcpu_load_rsp_rip(vcpu);
1972                         set_cr4(vcpu, vcpu->regs[reg]);
1973                         skip_emulated_instruction(vcpu);
1974                         return 1;
1975                 case 8:
1976                         vcpu_load_rsp_rip(vcpu);
1977                         set_cr8(vcpu, vcpu->regs[reg]);
1978                         skip_emulated_instruction(vcpu);
1979                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1980                         return 0;
1981                 };
1982                 break;
1983         case 2: /* clts */
1984                 vcpu_load_rsp_rip(vcpu);
1985                 vmx_fpu_deactivate(vcpu);
1986                 vcpu->cr0 &= ~X86_CR0_TS;
1987                 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1988                 vmx_fpu_activate(vcpu);
1989                 skip_emulated_instruction(vcpu);
1990                 return 1;
1991         case 1: /*mov from cr*/
1992                 switch (cr) {
1993                 case 3:
1994                         vcpu_load_rsp_rip(vcpu);
1995                         vcpu->regs[reg] = vcpu->cr3;
1996                         vcpu_put_rsp_rip(vcpu);
1997                         skip_emulated_instruction(vcpu);
1998                         return 1;
1999                 case 8:
2000                         vcpu_load_rsp_rip(vcpu);
2001                         vcpu->regs[reg] = get_cr8(vcpu);
2002                         vcpu_put_rsp_rip(vcpu);
2003                         skip_emulated_instruction(vcpu);
2004                         return 1;
2005                 }
2006                 break;
2007         case 3: /* lmsw */
2008                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2009
2010                 skip_emulated_instruction(vcpu);
2011                 return 1;
2012         default:
2013                 break;
2014         }
2015         kvm_run->exit_reason = 0;
2016         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2017                (int)(exit_qualification >> 4) & 3, cr);
2018         return 0;
2019 }
2020
2021 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2022 {
2023         unsigned long exit_qualification;
2024         unsigned long val;
2025         int dr, reg;
2026
2027         /*
2028          * FIXME: this code assumes the host is debugging the guest.
2029          *        need to deal with guest debugging itself too.
2030          */
2031         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2032         dr = exit_qualification & 7;
2033         reg = (exit_qualification >> 8) & 15;
2034         vcpu_load_rsp_rip(vcpu);
2035         if (exit_qualification & 16) {
2036                 /* mov from dr */
2037                 switch (dr) {
2038                 case 6:
2039                         val = 0xffff0ff0;
2040                         break;
2041                 case 7:
2042                         val = 0x400;
2043                         break;
2044                 default:
2045                         val = 0;
2046                 }
2047                 vcpu->regs[reg] = val;
2048         } else {
2049                 /* mov to dr */
2050         }
2051         vcpu_put_rsp_rip(vcpu);
2052         skip_emulated_instruction(vcpu);
2053         return 1;
2054 }
2055
2056 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2057 {
2058         kvm_emulate_cpuid(vcpu);
2059         return 1;
2060 }
2061
2062 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2063 {
2064         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2065         u64 data;
2066
2067         if (vmx_get_msr(vcpu, ecx, &data)) {
2068                 vmx_inject_gp(vcpu, 0);
2069                 return 1;
2070         }
2071
2072         /* FIXME: handling of bits 32:63 of rax, rdx */
2073         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2074         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2075         skip_emulated_instruction(vcpu);
2076         return 1;
2077 }
2078
2079 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2080 {
2081         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2082         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2083                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2084
2085         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2086                 vmx_inject_gp(vcpu, 0);
2087                 return 1;
2088         }
2089
2090         skip_emulated_instruction(vcpu);
2091         return 1;
2092 }
2093
2094 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2095                                       struct kvm_run *kvm_run)
2096 {
2097         return 1;
2098 }
2099
2100 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2101                                    struct kvm_run *kvm_run)
2102 {
2103         u32 cpu_based_vm_exec_control;
2104
2105         /* clear pending irq */
2106         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2107         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2108         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2109         /*
2110          * If the user space waits to inject interrupts, exit as soon as
2111          * possible
2112          */
2113         if (kvm_run->request_interrupt_window &&
2114             !vcpu->irq_summary) {
2115                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2116                 ++vcpu->stat.irq_window_exits;
2117                 return 0;
2118         }
2119         return 1;
2120 }
2121
2122 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2123 {
2124         skip_emulated_instruction(vcpu);
2125         return kvm_emulate_halt(vcpu);
2126 }
2127
2128 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2129 {
2130         skip_emulated_instruction(vcpu);
2131         kvm_emulate_hypercall(vcpu);
2132         return 1;
2133 }
2134
2135 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2136 {
2137         skip_emulated_instruction(vcpu);
2138         /* TODO: Add support for VT-d/pass-through device */
2139         return 1;
2140 }
2141
2142 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2143 {
2144         u64 exit_qualification;
2145         enum emulation_result er;
2146         unsigned long offset;
2147
2148         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2149         offset = exit_qualification & 0xffful;
2150
2151         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2152
2153         if (er !=  EMULATE_DONE) {
2154                 printk(KERN_ERR
2155                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2156                        offset);
2157                 return -ENOTSUPP;
2158         }
2159         return 1;
2160 }
2161
2162 /*
2163  * The exit handlers return 1 if the exit was handled fully and guest execution
2164  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2165  * to be done to userspace and return 0.
2166  */
2167 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2168                                       struct kvm_run *kvm_run) = {
2169         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2170         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2171         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2172         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2173         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2174         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2175         [EXIT_REASON_CPUID]                   = handle_cpuid,
2176         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2177         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2178         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2179         [EXIT_REASON_HLT]                     = handle_halt,
2180         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2181         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2182         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2183         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2184 };
2185
2186 static const int kvm_vmx_max_exit_handlers =
2187         ARRAY_SIZE(kvm_vmx_exit_handlers);
2188
2189 /*
2190  * The guest has exited.  See if we can fix it or if we need userspace
2191  * assistance.
2192  */
2193 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2194 {
2195         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2196         struct vcpu_vmx *vmx = to_vmx(vcpu);
2197         u32 vectoring_info = vmx->idt_vectoring_info;
2198
2199         if (unlikely(vmx->fail)) {
2200                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2201                 kvm_run->fail_entry.hardware_entry_failure_reason
2202                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2203                 return 0;
2204         }
2205
2206         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2207                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2208                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2209                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2210         if (exit_reason < kvm_vmx_max_exit_handlers
2211             && kvm_vmx_exit_handlers[exit_reason])
2212                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2213         else {
2214                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2215                 kvm_run->hw.hardware_exit_reason = exit_reason;
2216         }
2217         return 0;
2218 }
2219
2220 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2221 {
2222 }
2223
2224 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2225 {
2226         int max_irr, tpr;
2227
2228         if (!vm_need_tpr_shadow(vcpu->kvm))
2229                 return;
2230
2231         if (!kvm_lapic_enabled(vcpu) ||
2232             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2233                 vmcs_write32(TPR_THRESHOLD, 0);
2234                 return;
2235         }
2236
2237         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2238         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2239 }
2240
2241 static void enable_irq_window(struct kvm_vcpu *vcpu)
2242 {
2243         u32 cpu_based_vm_exec_control;
2244
2245         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2246         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2247         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2248 }
2249
2250 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2251 {
2252         struct vcpu_vmx *vmx = to_vmx(vcpu);
2253         u32 idtv_info_field, intr_info_field;
2254         int has_ext_irq, interrupt_window_open;
2255         int vector;
2256
2257         update_tpr_threshold(vcpu);
2258
2259         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2260         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2261         idtv_info_field = vmx->idt_vectoring_info;
2262         if (intr_info_field & INTR_INFO_VALID_MASK) {
2263                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2264                         /* TODO: fault when IDT_Vectoring */
2265                         printk(KERN_ERR "Fault when IDT_Vectoring\n");
2266                 }
2267                 if (has_ext_irq)
2268                         enable_irq_window(vcpu);
2269                 return;
2270         }
2271         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2272                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2273                     == INTR_TYPE_EXT_INTR
2274                     && vcpu->rmode.active) {
2275                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2276
2277                         vmx_inject_irq(vcpu, vect);
2278                         if (unlikely(has_ext_irq))
2279                                 enable_irq_window(vcpu);
2280                         return;
2281                 }
2282
2283                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2284                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2285                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2286
2287                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2288                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2289                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2290                 if (unlikely(has_ext_irq))
2291                         enable_irq_window(vcpu);
2292                 return;
2293         }
2294         if (!has_ext_irq)
2295                 return;
2296         interrupt_window_open =
2297                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2298                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2299         if (interrupt_window_open) {
2300                 vector = kvm_cpu_get_interrupt(vcpu);
2301                 vmx_inject_irq(vcpu, vector);
2302                 kvm_timer_intr_post(vcpu, vector);
2303         } else
2304                 enable_irq_window(vcpu);
2305 }
2306
2307 /*
2308  * Failure to inject an interrupt should give us the information
2309  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2310  * when fetching the interrupt redirection bitmap in the real-mode
2311  * tss, this doesn't happen.  So we do it ourselves.
2312  */
2313 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2314 {
2315         vmx->rmode.irq.pending = 0;
2316         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2317                 return;
2318         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2319         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2320                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2321                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2322                 return;
2323         }
2324         vmx->idt_vectoring_info =
2325                 VECTORING_INFO_VALID_MASK
2326                 | INTR_TYPE_EXT_INTR
2327                 | vmx->rmode.irq.vector;
2328 }
2329
2330 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2331 {
2332         struct vcpu_vmx *vmx = to_vmx(vcpu);
2333         u32 intr_info;
2334
2335         /*
2336          * Loading guest fpu may have cleared host cr0.ts
2337          */
2338         vmcs_writel(HOST_CR0, read_cr0());
2339
2340         asm(
2341                 /* Store host registers */
2342 #ifdef CONFIG_X86_64
2343                 "push %%rdx; push %%rbp;"
2344                 "push %%rcx \n\t"
2345 #else
2346                 "push %%edx; push %%ebp;"
2347                 "push %%ecx \n\t"
2348 #endif
2349                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2350                 /* Check if vmlaunch of vmresume is needed */
2351                 "cmpl $0, %c[launched](%0) \n\t"
2352                 /* Load guest registers.  Don't clobber flags. */
2353 #ifdef CONFIG_X86_64
2354                 "mov %c[cr2](%0), %%rax \n\t"
2355                 "mov %%rax, %%cr2 \n\t"
2356                 "mov %c[rax](%0), %%rax \n\t"
2357                 "mov %c[rbx](%0), %%rbx \n\t"
2358                 "mov %c[rdx](%0), %%rdx \n\t"
2359                 "mov %c[rsi](%0), %%rsi \n\t"
2360                 "mov %c[rdi](%0), %%rdi \n\t"
2361                 "mov %c[rbp](%0), %%rbp \n\t"
2362                 "mov %c[r8](%0),  %%r8  \n\t"
2363                 "mov %c[r9](%0),  %%r9  \n\t"
2364                 "mov %c[r10](%0), %%r10 \n\t"
2365                 "mov %c[r11](%0), %%r11 \n\t"
2366                 "mov %c[r12](%0), %%r12 \n\t"
2367                 "mov %c[r13](%0), %%r13 \n\t"
2368                 "mov %c[r14](%0), %%r14 \n\t"
2369                 "mov %c[r15](%0), %%r15 \n\t"
2370                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2371 #else
2372                 "mov %c[cr2](%0), %%eax \n\t"
2373                 "mov %%eax,   %%cr2 \n\t"
2374                 "mov %c[rax](%0), %%eax \n\t"
2375                 "mov %c[rbx](%0), %%ebx \n\t"
2376                 "mov %c[rdx](%0), %%edx \n\t"
2377                 "mov %c[rsi](%0), %%esi \n\t"
2378                 "mov %c[rdi](%0), %%edi \n\t"
2379                 "mov %c[rbp](%0), %%ebp \n\t"
2380                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2381 #endif
2382                 /* Enter guest mode */
2383                 "jne .Llaunched \n\t"
2384                 ASM_VMX_VMLAUNCH "\n\t"
2385                 "jmp .Lkvm_vmx_return \n\t"
2386                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2387                 ".Lkvm_vmx_return: "
2388                 /* Save guest registers, load host registers, keep flags */
2389 #ifdef CONFIG_X86_64
2390                 "xchg %0,     (%%rsp) \n\t"
2391                 "mov %%rax, %c[rax](%0) \n\t"
2392                 "mov %%rbx, %c[rbx](%0) \n\t"
2393                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2394                 "mov %%rdx, %c[rdx](%0) \n\t"
2395                 "mov %%rsi, %c[rsi](%0) \n\t"
2396                 "mov %%rdi, %c[rdi](%0) \n\t"
2397                 "mov %%rbp, %c[rbp](%0) \n\t"
2398                 "mov %%r8,  %c[r8](%0) \n\t"
2399                 "mov %%r9,  %c[r9](%0) \n\t"
2400                 "mov %%r10, %c[r10](%0) \n\t"
2401                 "mov %%r11, %c[r11](%0) \n\t"
2402                 "mov %%r12, %c[r12](%0) \n\t"
2403                 "mov %%r13, %c[r13](%0) \n\t"
2404                 "mov %%r14, %c[r14](%0) \n\t"
2405                 "mov %%r15, %c[r15](%0) \n\t"
2406                 "mov %%cr2, %%rax   \n\t"
2407                 "mov %%rax, %c[cr2](%0) \n\t"
2408
2409                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2410 #else
2411                 "xchg %0, (%%esp) \n\t"
2412                 "mov %%eax, %c[rax](%0) \n\t"
2413                 "mov %%ebx, %c[rbx](%0) \n\t"
2414                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2415                 "mov %%edx, %c[rdx](%0) \n\t"
2416                 "mov %%esi, %c[rsi](%0) \n\t"
2417                 "mov %%edi, %c[rdi](%0) \n\t"
2418                 "mov %%ebp, %c[rbp](%0) \n\t"
2419                 "mov %%cr2, %%eax  \n\t"
2420                 "mov %%eax, %c[cr2](%0) \n\t"
2421
2422                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2423 #endif
2424                 "setbe %c[fail](%0) \n\t"
2425               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2426                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2427                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2428                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RAX])),
2429                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBX])),
2430                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RCX])),
2431                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDX])),
2432                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RSI])),
2433                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDI])),
2434                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBP])),
2435 #ifdef CONFIG_X86_64
2436                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R8])),
2437                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R9])),
2438                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R10])),
2439                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R11])),
2440                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R12])),
2441                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R13])),
2442                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R14])),
2443                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R15])),
2444 #endif
2445                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.cr2))
2446               : "cc", "memory"
2447 #ifdef CONFIG_X86_64
2448                 , "rbx", "rdi", "rsi"
2449                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2450 #else
2451                 , "ebx", "edi", "rsi"
2452 #endif
2453               );
2454
2455         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2456         if (vmx->rmode.irq.pending)
2457                 fixup_rmode_irq(vmx);
2458
2459         vcpu->interrupt_window_open =
2460                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2461
2462         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2463         vmx->launched = 1;
2464
2465         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2466
2467         /* We need to handle NMIs before interrupts are enabled */
2468         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2469                 asm("int $2");
2470 }
2471
2472 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2473                                   unsigned long addr,
2474                                   u32 err_code)
2475 {
2476         struct vcpu_vmx *vmx = to_vmx(vcpu);
2477         u32 vect_info = vmx->idt_vectoring_info;
2478
2479         ++vcpu->stat.pf_guest;
2480
2481         if (is_page_fault(vect_info)) {
2482                 printk(KERN_DEBUG "inject_page_fault: "
2483                        "double fault 0x%lx @ 0x%lx\n",
2484                        addr, vmcs_readl(GUEST_RIP));
2485                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2486                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2487                              DF_VECTOR |
2488                              INTR_TYPE_EXCEPTION |
2489                              INTR_INFO_DELIEVER_CODE_MASK |
2490                              INTR_INFO_VALID_MASK);
2491                 return;
2492         }
2493         vcpu->cr2 = addr;
2494         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2495         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2496                      PF_VECTOR |
2497                      INTR_TYPE_EXCEPTION |
2498                      INTR_INFO_DELIEVER_CODE_MASK |
2499                      INTR_INFO_VALID_MASK);
2500
2501 }
2502
2503 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2504 {
2505         struct vcpu_vmx *vmx = to_vmx(vcpu);
2506
2507         if (vmx->vmcs) {
2508                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2509                 free_vmcs(vmx->vmcs);
2510                 vmx->vmcs = NULL;
2511         }
2512 }
2513
2514 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2515 {
2516         struct vcpu_vmx *vmx = to_vmx(vcpu);
2517
2518         vmx_free_vmcs(vcpu);
2519         kfree(vmx->host_msrs);
2520         kfree(vmx->guest_msrs);
2521         kvm_vcpu_uninit(vcpu);
2522         kmem_cache_free(kvm_vcpu_cache, vmx);
2523 }
2524
2525 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2526 {
2527         int err;
2528         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2529         int cpu;
2530
2531         if (!vmx)
2532                 return ERR_PTR(-ENOMEM);
2533
2534         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2535         if (err)
2536                 goto free_vcpu;
2537
2538         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2539         if (!vmx->guest_msrs) {
2540                 err = -ENOMEM;
2541                 goto uninit_vcpu;
2542         }
2543
2544         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2545         if (!vmx->host_msrs)
2546                 goto free_guest_msrs;
2547
2548         vmx->vmcs = alloc_vmcs();
2549         if (!vmx->vmcs)
2550                 goto free_msrs;
2551
2552         vmcs_clear(vmx->vmcs);
2553
2554         cpu = get_cpu();
2555         vmx_vcpu_load(&vmx->vcpu, cpu);
2556         err = vmx_vcpu_setup(vmx);
2557         vmx_vcpu_put(&vmx->vcpu);
2558         put_cpu();
2559         if (err)
2560                 goto free_vmcs;
2561
2562         return &vmx->vcpu;
2563
2564 free_vmcs:
2565         free_vmcs(vmx->vmcs);
2566 free_msrs:
2567         kfree(vmx->host_msrs);
2568 free_guest_msrs:
2569         kfree(vmx->guest_msrs);
2570 uninit_vcpu:
2571         kvm_vcpu_uninit(&vmx->vcpu);
2572 free_vcpu:
2573         kmem_cache_free(kvm_vcpu_cache, vmx);
2574         return ERR_PTR(err);
2575 }
2576
2577 static void __init vmx_check_processor_compat(void *rtn)
2578 {
2579         struct vmcs_config vmcs_conf;
2580
2581         *(int *)rtn = 0;
2582         if (setup_vmcs_config(&vmcs_conf) < 0)
2583                 *(int *)rtn = -EIO;
2584         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2585                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2586                                 smp_processor_id());
2587                 *(int *)rtn = -EIO;
2588         }
2589 }
2590
2591 static struct kvm_x86_ops vmx_x86_ops = {
2592         .cpu_has_kvm_support = cpu_has_kvm_support,
2593         .disabled_by_bios = vmx_disabled_by_bios,
2594         .hardware_setup = hardware_setup,
2595         .hardware_unsetup = hardware_unsetup,
2596         .check_processor_compatibility = vmx_check_processor_compat,
2597         .hardware_enable = hardware_enable,
2598         .hardware_disable = hardware_disable,
2599
2600         .vcpu_create = vmx_create_vcpu,
2601         .vcpu_free = vmx_free_vcpu,
2602         .vcpu_reset = vmx_vcpu_reset,
2603
2604         .prepare_guest_switch = vmx_save_host_state,
2605         .vcpu_load = vmx_vcpu_load,
2606         .vcpu_put = vmx_vcpu_put,
2607         .vcpu_decache = vmx_vcpu_decache,
2608
2609         .set_guest_debug = set_guest_debug,
2610         .guest_debug_pre = kvm_guest_debug_pre,
2611         .get_msr = vmx_get_msr,
2612         .set_msr = vmx_set_msr,
2613         .get_segment_base = vmx_get_segment_base,
2614         .get_segment = vmx_get_segment,
2615         .set_segment = vmx_set_segment,
2616         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2617         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2618         .set_cr0 = vmx_set_cr0,
2619         .set_cr3 = vmx_set_cr3,
2620         .set_cr4 = vmx_set_cr4,
2621 #ifdef CONFIG_X86_64
2622         .set_efer = vmx_set_efer,
2623 #endif
2624         .get_idt = vmx_get_idt,
2625         .set_idt = vmx_set_idt,
2626         .get_gdt = vmx_get_gdt,
2627         .set_gdt = vmx_set_gdt,
2628         .cache_regs = vcpu_load_rsp_rip,
2629         .decache_regs = vcpu_put_rsp_rip,
2630         .get_rflags = vmx_get_rflags,
2631         .set_rflags = vmx_set_rflags,
2632
2633         .tlb_flush = vmx_flush_tlb,
2634         .inject_page_fault = vmx_inject_page_fault,
2635
2636         .inject_gp = vmx_inject_gp,
2637
2638         .run = vmx_vcpu_run,
2639         .handle_exit = kvm_handle_exit,
2640         .skip_emulated_instruction = skip_emulated_instruction,
2641         .patch_hypercall = vmx_patch_hypercall,
2642         .get_irq = vmx_get_irq,
2643         .set_irq = vmx_inject_irq,
2644         .inject_pending_irq = vmx_intr_assist,
2645         .inject_pending_vectors = do_interrupt_requests,
2646
2647         .set_tss_addr = vmx_set_tss_addr,
2648 };
2649
2650 static int __init vmx_init(void)
2651 {
2652         void *iova;
2653         int r;
2654
2655         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2656         if (!vmx_io_bitmap_a)
2657                 return -ENOMEM;
2658
2659         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2660         if (!vmx_io_bitmap_b) {
2661                 r = -ENOMEM;
2662                 goto out;
2663         }
2664
2665         /*
2666          * Allow direct access to the PC debug port (it is often used for I/O
2667          * delays, but the vmexits simply slow things down).
2668          */
2669         iova = kmap(vmx_io_bitmap_a);
2670         memset(iova, 0xff, PAGE_SIZE);
2671         clear_bit(0x80, iova);
2672         kunmap(vmx_io_bitmap_a);
2673
2674         iova = kmap(vmx_io_bitmap_b);
2675         memset(iova, 0xff, PAGE_SIZE);
2676         kunmap(vmx_io_bitmap_b);
2677
2678         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2679         if (r)
2680                 goto out1;
2681
2682         if (bypass_guest_pf)
2683                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2684
2685         return 0;
2686
2687 out1:
2688         __free_page(vmx_io_bitmap_b);
2689 out:
2690         __free_page(vmx_io_bitmap_a);
2691         return r;
2692 }
2693
2694 static void __exit vmx_exit(void)
2695 {
2696         __free_page(vmx_io_bitmap_b);
2697         __free_page(vmx_io_bitmap_a);
2698
2699         kvm_exit();
2700 }
2701
2702 module_init(vmx_init)
2703 module_exit(vmx_exit)