2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
21 #include <linux/module.h>
23 #include <linux/highmem.h>
27 #include "segment_descriptor.h"
30 MODULE_AUTHOR("Qumranet");
31 MODULE_LICENSE("GPL");
33 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
34 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
42 static struct vmcs_descriptor {
48 #define VMX_SEGMENT_FIELD(seg) \
49 [VCPU_SREG_##seg] = { \
50 .selector = GUEST_##seg##_SELECTOR, \
51 .base = GUEST_##seg##_BASE, \
52 .limit = GUEST_##seg##_LIMIT, \
53 .ar_bytes = GUEST_##seg##_AR_BYTES, \
56 static struct kvm_vmx_segment_field {
61 } kvm_vmx_segment_fields[] = {
62 VMX_SEGMENT_FIELD(CS),
63 VMX_SEGMENT_FIELD(DS),
64 VMX_SEGMENT_FIELD(ES),
65 VMX_SEGMENT_FIELD(FS),
66 VMX_SEGMENT_FIELD(GS),
67 VMX_SEGMENT_FIELD(SS),
68 VMX_SEGMENT_FIELD(TR),
69 VMX_SEGMENT_FIELD(LDTR),
72 static const u32 vmx_msr_index[] = {
74 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
76 MSR_EFER, MSR_K6_STAR,
78 #define NR_VMX_MSR (sizeof(vmx_msr_index) / sizeof(*vmx_msr_index))
80 static inline int is_page_fault(u32 intr_info)
82 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
83 INTR_INFO_VALID_MASK)) ==
84 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
87 static inline int is_external_interrupt(u32 intr_info)
89 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
90 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
93 static struct vmx_msr_entry *find_msr_entry(struct kvm_vcpu *vcpu, u32 msr)
97 for (i = 0; i < vcpu->nmsrs; ++i)
98 if (vcpu->guest_msrs[i].index == msr)
99 return &vcpu->guest_msrs[i];
103 static void vmcs_clear(struct vmcs *vmcs)
105 u64 phys_addr = __pa(vmcs);
108 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
109 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
112 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
116 static void __vcpu_clear(void *arg)
118 struct kvm_vcpu *vcpu = arg;
119 int cpu = raw_smp_processor_id();
121 if (vcpu->cpu == cpu)
122 vmcs_clear(vcpu->vmcs);
123 if (per_cpu(current_vmcs, cpu) == vcpu->vmcs)
124 per_cpu(current_vmcs, cpu) = NULL;
127 static unsigned long vmcs_readl(unsigned long field)
131 asm volatile (ASM_VMX_VMREAD_RDX_RAX
132 : "=a"(value) : "d"(field) : "cc");
136 static u16 vmcs_read16(unsigned long field)
138 return vmcs_readl(field);
141 static u32 vmcs_read32(unsigned long field)
143 return vmcs_readl(field);
146 static u64 vmcs_read64(unsigned long field)
149 return vmcs_readl(field);
151 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
155 static void vmcs_writel(unsigned long field, unsigned long value)
159 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
160 : "=q"(error) : "a"(value), "d"(field) : "cc" );
162 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
163 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
166 static void vmcs_write16(unsigned long field, u16 value)
168 vmcs_writel(field, value);
171 static void vmcs_write32(unsigned long field, u32 value)
173 vmcs_writel(field, value);
176 static void vmcs_write64(unsigned long field, u64 value)
179 vmcs_writel(field, value);
181 vmcs_writel(field, value);
183 vmcs_writel(field+1, value >> 32);
188 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
189 * vcpu mutex is already taken.
191 static struct kvm_vcpu *vmx_vcpu_load(struct kvm_vcpu *vcpu)
193 u64 phys_addr = __pa(vcpu->vmcs);
198 if (vcpu->cpu != cpu) {
199 smp_call_function(__vcpu_clear, vcpu, 0, 1);
203 if (per_cpu(current_vmcs, cpu) != vcpu->vmcs) {
206 per_cpu(current_vmcs, cpu) = vcpu->vmcs;
207 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
208 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
211 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
212 vcpu->vmcs, phys_addr);
215 if (vcpu->cpu != cpu) {
216 struct descriptor_table dt;
217 unsigned long sysenter_esp;
221 * Linux uses per-cpu TSS and GDT, so set these when switching
224 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
226 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
228 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
229 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
234 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
239 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
241 return vmcs_readl(GUEST_RFLAGS);
244 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
246 vmcs_writel(GUEST_RFLAGS, rflags);
249 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
252 u32 interruptibility;
254 rip = vmcs_readl(GUEST_RIP);
255 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
256 vmcs_writel(GUEST_RIP, rip);
259 * We emulated an instruction, so temporary interrupt blocking
260 * should be removed, if set.
262 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
263 if (interruptibility & 3)
264 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
265 interruptibility & ~3);
266 vcpu->interrupt_window_open = 1;
269 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
271 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
272 vmcs_readl(GUEST_RIP));
273 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
274 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
276 INTR_TYPE_EXCEPTION |
277 INTR_INFO_DELIEVER_CODE_MASK |
278 INTR_INFO_VALID_MASK);
282 * reads and returns guest's timestamp counter "register"
283 * guest_tsc = host_tsc + tsc_offset -- 21.3
285 static u64 guest_read_tsc(void)
287 u64 host_tsc, tsc_offset;
290 tsc_offset = vmcs_read64(TSC_OFFSET);
291 return host_tsc + tsc_offset;
295 * writes 'guest_tsc' into guest's timestamp counter "register"
296 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
298 static void guest_write_tsc(u64 guest_tsc)
303 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
306 static void reload_tss(void)
308 #ifndef CONFIG_X86_64
311 * VT restores TR but not its size. Useless.
313 struct descriptor_table gdt;
314 struct segment_descriptor *descs;
317 descs = (void *)gdt.base;
318 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
324 * Reads an msr value (of 'msr_index') into 'pdata'.
325 * Returns 0 on success, non-0 otherwise.
326 * Assumes vcpu_load() was already called.
328 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
331 struct vmx_msr_entry *msr;
334 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
341 data = vmcs_readl(GUEST_FS_BASE);
344 data = vmcs_readl(GUEST_GS_BASE);
347 return kvm_get_msr_common(vcpu, msr_index, pdata);
349 case MSR_IA32_TIME_STAMP_COUNTER:
350 data = guest_read_tsc();
352 case MSR_IA32_SYSENTER_CS:
353 data = vmcs_read32(GUEST_SYSENTER_CS);
355 case MSR_IA32_SYSENTER_EIP:
356 data = vmcs_read32(GUEST_SYSENTER_EIP);
358 case MSR_IA32_SYSENTER_ESP:
359 data = vmcs_read32(GUEST_SYSENTER_ESP);
362 msr = find_msr_entry(vcpu, msr_index);
367 return kvm_get_msr_common(vcpu, msr_index, pdata);
375 * Writes msr value into into the appropriate "register".
376 * Returns 0 on success, non-0 otherwise.
377 * Assumes vcpu_load() was already called.
379 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
381 struct vmx_msr_entry *msr;
385 return kvm_set_msr_common(vcpu, msr_index, data);
387 vmcs_writel(GUEST_FS_BASE, data);
390 vmcs_writel(GUEST_GS_BASE, data);
393 case MSR_IA32_SYSENTER_CS:
394 vmcs_write32(GUEST_SYSENTER_CS, data);
396 case MSR_IA32_SYSENTER_EIP:
397 vmcs_write32(GUEST_SYSENTER_EIP, data);
399 case MSR_IA32_SYSENTER_ESP:
400 vmcs_write32(GUEST_SYSENTER_ESP, data);
402 case MSR_IA32_TIME_STAMP_COUNTER: {
403 guest_write_tsc(data);
407 msr = find_msr_entry(vcpu, msr_index);
412 return kvm_set_msr_common(vcpu, msr_index, data);
421 * Sync the rsp and rip registers into the vcpu structure. This allows
422 * registers to be accessed by indexing vcpu->regs.
424 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
426 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
427 vcpu->rip = vmcs_readl(GUEST_RIP);
431 * Syncs rsp and rip back into the vmcs. Should be called after possible
434 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
436 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
437 vmcs_writel(GUEST_RIP, vcpu->rip);
440 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
442 unsigned long dr7 = 0x400;
443 u32 exception_bitmap;
446 exception_bitmap = vmcs_read32(EXCEPTION_BITMAP);
447 old_singlestep = vcpu->guest_debug.singlestep;
449 vcpu->guest_debug.enabled = dbg->enabled;
450 if (vcpu->guest_debug.enabled) {
453 dr7 |= 0x200; /* exact */
454 for (i = 0; i < 4; ++i) {
455 if (!dbg->breakpoints[i].enabled)
457 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
458 dr7 |= 2 << (i*2); /* global enable */
459 dr7 |= 0 << (i*4+16); /* execution breakpoint */
462 exception_bitmap |= (1u << 1); /* Trap debug exceptions */
464 vcpu->guest_debug.singlestep = dbg->singlestep;
466 exception_bitmap &= ~(1u << 1); /* Ignore debug exceptions */
467 vcpu->guest_debug.singlestep = 0;
470 if (old_singlestep && !vcpu->guest_debug.singlestep) {
473 flags = vmcs_readl(GUEST_RFLAGS);
474 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
475 vmcs_writel(GUEST_RFLAGS, flags);
478 vmcs_write32(EXCEPTION_BITMAP, exception_bitmap);
479 vmcs_writel(GUEST_DR7, dr7);
484 static __init int cpu_has_kvm_support(void)
486 unsigned long ecx = cpuid_ecx(1);
487 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
490 static __init int vmx_disabled_by_bios(void)
494 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
495 return (msr & 5) == 1; /* locked but not enabled */
498 static __init void hardware_enable(void *garbage)
500 int cpu = raw_smp_processor_id();
501 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
504 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
506 /* enable and lock */
507 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | 5);
508 write_cr4(read_cr4() | CR4_VMXE); /* FIXME: not cpu hotplug safe */
509 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
513 static void hardware_disable(void *garbage)
515 asm volatile (ASM_VMX_VMXOFF : : : "cc");
518 static __init void setup_vmcs_descriptor(void)
520 u32 vmx_msr_low, vmx_msr_high;
522 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
523 vmcs_descriptor.size = vmx_msr_high & 0x1fff;
524 vmcs_descriptor.order = get_order(vmcs_descriptor.size);
525 vmcs_descriptor.revision_id = vmx_msr_low;
528 static struct vmcs *alloc_vmcs_cpu(int cpu)
530 int node = cpu_to_node(cpu);
534 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_descriptor.order);
537 vmcs = page_address(pages);
538 memset(vmcs, 0, vmcs_descriptor.size);
539 vmcs->revision_id = vmcs_descriptor.revision_id; /* vmcs revision id */
543 static struct vmcs *alloc_vmcs(void)
545 return alloc_vmcs_cpu(raw_smp_processor_id());
548 static void free_vmcs(struct vmcs *vmcs)
550 free_pages((unsigned long)vmcs, vmcs_descriptor.order);
553 static __exit void free_kvm_area(void)
557 for_each_online_cpu(cpu)
558 free_vmcs(per_cpu(vmxarea, cpu));
561 extern struct vmcs *alloc_vmcs_cpu(int cpu);
563 static __init int alloc_kvm_area(void)
567 for_each_online_cpu(cpu) {
570 vmcs = alloc_vmcs_cpu(cpu);
576 per_cpu(vmxarea, cpu) = vmcs;
581 static __init int hardware_setup(void)
583 setup_vmcs_descriptor();
584 return alloc_kvm_area();
587 static __exit void hardware_unsetup(void)
592 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
594 if (vcpu->rmode.active)
595 vmcs_write32(EXCEPTION_BITMAP, ~0);
597 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
600 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
602 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
604 if (vmcs_readl(sf->base) == save->base) {
605 vmcs_write16(sf->selector, save->selector);
606 vmcs_writel(sf->base, save->base);
607 vmcs_write32(sf->limit, save->limit);
608 vmcs_write32(sf->ar_bytes, save->ar);
610 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
612 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
616 static void enter_pmode(struct kvm_vcpu *vcpu)
620 vcpu->rmode.active = 0;
622 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
623 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
624 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
626 flags = vmcs_readl(GUEST_RFLAGS);
627 flags &= ~(IOPL_MASK | X86_EFLAGS_VM);
628 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
629 vmcs_writel(GUEST_RFLAGS, flags);
631 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~CR4_VME_MASK) |
632 (vmcs_readl(CR4_READ_SHADOW) & CR4_VME_MASK));
634 update_exception_bitmap(vcpu);
636 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
637 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
638 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
639 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
641 vmcs_write16(GUEST_SS_SELECTOR, 0);
642 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
644 vmcs_write16(GUEST_CS_SELECTOR,
645 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
646 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
649 static int rmode_tss_base(struct kvm* kvm)
651 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
652 return base_gfn << PAGE_SHIFT;
655 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
657 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
659 save->selector = vmcs_read16(sf->selector);
660 save->base = vmcs_readl(sf->base);
661 save->limit = vmcs_read32(sf->limit);
662 save->ar = vmcs_read32(sf->ar_bytes);
663 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
664 vmcs_write32(sf->limit, 0xffff);
665 vmcs_write32(sf->ar_bytes, 0xf3);
668 static void enter_rmode(struct kvm_vcpu *vcpu)
672 vcpu->rmode.active = 1;
674 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
675 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
677 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
678 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
680 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
681 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
683 flags = vmcs_readl(GUEST_RFLAGS);
684 vcpu->rmode.save_iopl = (flags & IOPL_MASK) >> IOPL_SHIFT;
686 flags |= IOPL_MASK | X86_EFLAGS_VM;
688 vmcs_writel(GUEST_RFLAGS, flags);
689 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | CR4_VME_MASK);
690 update_exception_bitmap(vcpu);
692 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
693 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
694 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
696 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
697 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
698 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
700 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
701 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
702 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
703 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
708 static void enter_lmode(struct kvm_vcpu *vcpu)
712 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
713 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
714 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
716 vmcs_write32(GUEST_TR_AR_BYTES,
717 (guest_tr_ar & ~AR_TYPE_MASK)
718 | AR_TYPE_BUSY_64_TSS);
721 vcpu->shadow_efer |= EFER_LMA;
723 find_msr_entry(vcpu, MSR_EFER)->data |= EFER_LMA | EFER_LME;
724 vmcs_write32(VM_ENTRY_CONTROLS,
725 vmcs_read32(VM_ENTRY_CONTROLS)
726 | VM_ENTRY_CONTROLS_IA32E_MASK);
729 static void exit_lmode(struct kvm_vcpu *vcpu)
731 vcpu->shadow_efer &= ~EFER_LMA;
733 vmcs_write32(VM_ENTRY_CONTROLS,
734 vmcs_read32(VM_ENTRY_CONTROLS)
735 & ~VM_ENTRY_CONTROLS_IA32E_MASK);
740 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
742 if (vcpu->rmode.active && (cr0 & CR0_PE_MASK))
745 if (!vcpu->rmode.active && !(cr0 & CR0_PE_MASK))
749 if (vcpu->shadow_efer & EFER_LME) {
750 if (!is_paging(vcpu) && (cr0 & CR0_PG_MASK))
752 if (is_paging(vcpu) && !(cr0 & CR0_PG_MASK))
757 vmcs_writel(CR0_READ_SHADOW, cr0);
758 vmcs_writel(GUEST_CR0,
759 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
764 * Used when restoring the VM to avoid corrupting segment registers
766 static void vmx_set_cr0_no_modeswitch(struct kvm_vcpu *vcpu, unsigned long cr0)
768 vcpu->rmode.active = ((cr0 & CR0_PE_MASK) == 0);
769 update_exception_bitmap(vcpu);
770 vmcs_writel(CR0_READ_SHADOW, cr0);
771 vmcs_writel(GUEST_CR0,
772 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
776 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
778 vmcs_writel(GUEST_CR3, cr3);
781 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
783 vmcs_writel(CR4_READ_SHADOW, cr4);
784 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
785 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
791 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
793 struct vmx_msr_entry *msr = find_msr_entry(vcpu, MSR_EFER);
795 vcpu->shadow_efer = efer;
796 if (efer & EFER_LMA) {
797 vmcs_write32(VM_ENTRY_CONTROLS,
798 vmcs_read32(VM_ENTRY_CONTROLS) |
799 VM_ENTRY_CONTROLS_IA32E_MASK);
803 vmcs_write32(VM_ENTRY_CONTROLS,
804 vmcs_read32(VM_ENTRY_CONTROLS) &
805 ~VM_ENTRY_CONTROLS_IA32E_MASK);
807 msr->data = efer & ~EFER_LME;
813 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
815 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
817 return vmcs_readl(sf->base);
820 static void vmx_get_segment(struct kvm_vcpu *vcpu,
821 struct kvm_segment *var, int seg)
823 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
826 var->base = vmcs_readl(sf->base);
827 var->limit = vmcs_read32(sf->limit);
828 var->selector = vmcs_read16(sf->selector);
829 ar = vmcs_read32(sf->ar_bytes);
830 if (ar & AR_UNUSABLE_MASK)
833 var->s = (ar >> 4) & 1;
834 var->dpl = (ar >> 5) & 3;
835 var->present = (ar >> 7) & 1;
836 var->avl = (ar >> 12) & 1;
837 var->l = (ar >> 13) & 1;
838 var->db = (ar >> 14) & 1;
839 var->g = (ar >> 15) & 1;
840 var->unusable = (ar >> 16) & 1;
843 static void vmx_set_segment(struct kvm_vcpu *vcpu,
844 struct kvm_segment *var, int seg)
846 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
849 vmcs_writel(sf->base, var->base);
850 vmcs_write32(sf->limit, var->limit);
851 vmcs_write16(sf->selector, var->selector);
856 ar |= (var->s & 1) << 4;
857 ar |= (var->dpl & 3) << 5;
858 ar |= (var->present & 1) << 7;
859 ar |= (var->avl & 1) << 12;
860 ar |= (var->l & 1) << 13;
861 ar |= (var->db & 1) << 14;
862 ar |= (var->g & 1) << 15;
864 if (ar == 0) /* a 0 value means unusable */
865 ar = AR_UNUSABLE_MASK;
866 vmcs_write32(sf->ar_bytes, ar);
869 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
871 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
873 *db = (ar >> 14) & 1;
877 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
879 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
880 dt->base = vmcs_readl(GUEST_IDTR_BASE);
883 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
885 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
886 vmcs_writel(GUEST_IDTR_BASE, dt->base);
889 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
891 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
892 dt->base = vmcs_readl(GUEST_GDTR_BASE);
895 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
897 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
898 vmcs_writel(GUEST_GDTR_BASE, dt->base);
901 static int init_rmode_tss(struct kvm* kvm)
903 struct page *p1, *p2, *p3;
904 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
907 p1 = _gfn_to_page(kvm, fn++);
908 p2 = _gfn_to_page(kvm, fn++);
909 p3 = _gfn_to_page(kvm, fn);
911 if (!p1 || !p2 || !p3) {
912 kvm_printf(kvm,"%s: gfn_to_page failed\n", __FUNCTION__);
916 page = kmap_atomic(p1, KM_USER0);
917 memset(page, 0, PAGE_SIZE);
918 *(u16*)(page + 0x66) = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
919 kunmap_atomic(page, KM_USER0);
921 page = kmap_atomic(p2, KM_USER0);
922 memset(page, 0, PAGE_SIZE);
923 kunmap_atomic(page, KM_USER0);
925 page = kmap_atomic(p3, KM_USER0);
926 memset(page, 0, PAGE_SIZE);
927 *(page + RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1) = ~0;
928 kunmap_atomic(page, KM_USER0);
933 static void vmcs_write32_fixedbits(u32 msr, u32 vmcs_field, u32 val)
935 u32 msr_high, msr_low;
937 rdmsr(msr, msr_low, msr_high);
941 vmcs_write32(vmcs_field, val);
944 static void seg_setup(int seg)
946 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
948 vmcs_write16(sf->selector, 0);
949 vmcs_writel(sf->base, 0);
950 vmcs_write32(sf->limit, 0xffff);
951 vmcs_write32(sf->ar_bytes, 0x93);
955 * Sets up the vmcs for emulated real mode.
957 static int vmx_vcpu_setup(struct kvm_vcpu *vcpu)
959 u32 host_sysenter_cs;
962 struct descriptor_table dt;
966 extern asmlinkage void kvm_vmx_return(void);
968 if (!init_rmode_tss(vcpu->kvm)) {
973 memset(vcpu->regs, 0, sizeof(vcpu->regs));
974 vcpu->regs[VCPU_REGS_RDX] = get_rdx_init_val();
976 vcpu->apic_base = 0xfee00000 |
977 /*for vcpu 0*/ MSR_IA32_APICBASE_BSP |
978 MSR_IA32_APICBASE_ENABLE;
983 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
984 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
986 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
987 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
988 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
989 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
991 seg_setup(VCPU_SREG_DS);
992 seg_setup(VCPU_SREG_ES);
993 seg_setup(VCPU_SREG_FS);
994 seg_setup(VCPU_SREG_GS);
995 seg_setup(VCPU_SREG_SS);
997 vmcs_write16(GUEST_TR_SELECTOR, 0);
998 vmcs_writel(GUEST_TR_BASE, 0);
999 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1000 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1002 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1003 vmcs_writel(GUEST_LDTR_BASE, 0);
1004 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1005 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1007 vmcs_write32(GUEST_SYSENTER_CS, 0);
1008 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1009 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1011 vmcs_writel(GUEST_RFLAGS, 0x02);
1012 vmcs_writel(GUEST_RIP, 0xfff0);
1013 vmcs_writel(GUEST_RSP, 0);
1015 vmcs_writel(GUEST_CR3, 0);
1017 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1018 vmcs_writel(GUEST_DR7, 0x400);
1020 vmcs_writel(GUEST_GDTR_BASE, 0);
1021 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1023 vmcs_writel(GUEST_IDTR_BASE, 0);
1024 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1026 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1027 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1028 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1031 vmcs_write64(IO_BITMAP_A, 0);
1032 vmcs_write64(IO_BITMAP_B, 0);
1036 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1038 /* Special registers */
1039 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1042 vmcs_write32_fixedbits(MSR_IA32_VMX_PINBASED_CTLS,
1043 PIN_BASED_VM_EXEC_CONTROL,
1044 PIN_BASED_EXT_INTR_MASK /* 20.6.1 */
1045 | PIN_BASED_NMI_EXITING /* 20.6.1 */
1047 vmcs_write32_fixedbits(MSR_IA32_VMX_PROCBASED_CTLS,
1048 CPU_BASED_VM_EXEC_CONTROL,
1049 CPU_BASED_HLT_EXITING /* 20.6.2 */
1050 | CPU_BASED_CR8_LOAD_EXITING /* 20.6.2 */
1051 | CPU_BASED_CR8_STORE_EXITING /* 20.6.2 */
1052 | CPU_BASED_UNCOND_IO_EXITING /* 20.6.2 */
1053 | CPU_BASED_INVDPG_EXITING
1054 | CPU_BASED_MOV_DR_EXITING
1055 | CPU_BASED_USE_TSC_OFFSETING /* 21.3 */
1058 vmcs_write32(EXCEPTION_BITMAP, 1 << PF_VECTOR);
1059 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
1060 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
1061 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1063 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1064 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1065 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1067 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1068 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1069 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1070 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1071 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1072 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1073 #ifdef CONFIG_X86_64
1074 rdmsrl(MSR_FS_BASE, a);
1075 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1076 rdmsrl(MSR_GS_BASE, a);
1077 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1079 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1080 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1083 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1086 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1089 vmcs_writel(HOST_RIP, (unsigned long)kvm_vmx_return); /* 22.2.5 */
1091 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1092 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1093 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1094 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1095 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1096 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1098 for (i = 0; i < NR_VMX_MSR; ++i) {
1099 u32 index = vmx_msr_index[i];
1100 u32 data_low, data_high;
1102 int j = vcpu->nmsrs;
1104 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1106 data = data_low | ((u64)data_high << 32);
1107 vcpu->host_msrs[j].index = index;
1108 vcpu->host_msrs[j].reserved = 0;
1109 vcpu->host_msrs[j].data = data;
1110 vcpu->guest_msrs[j] = vcpu->host_msrs[j];
1113 printk(KERN_DEBUG "kvm: msrs: %d\n", vcpu->nmsrs);
1115 nr_good_msrs = vcpu->nmsrs - NR_BAD_MSRS;
1116 vmcs_writel(VM_ENTRY_MSR_LOAD_ADDR,
1117 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1118 vmcs_writel(VM_EXIT_MSR_STORE_ADDR,
1119 virt_to_phys(vcpu->guest_msrs + NR_BAD_MSRS));
1120 vmcs_writel(VM_EXIT_MSR_LOAD_ADDR,
1121 virt_to_phys(vcpu->host_msrs + NR_BAD_MSRS));
1122 vmcs_write32_fixedbits(MSR_IA32_VMX_EXIT_CTLS, VM_EXIT_CONTROLS,
1123 (HOST_IS_64 << 9)); /* 22.2,1, 20.7.1 */
1124 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, nr_good_msrs); /* 22.2.2 */
1125 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1126 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, nr_good_msrs); /* 22.2.2 */
1129 /* 22.2.1, 20.8.1 */
1130 vmcs_write32_fixedbits(MSR_IA32_VMX_ENTRY_CTLS,
1131 VM_ENTRY_CONTROLS, 0);
1132 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1134 #ifdef CONFIG_X86_64
1135 vmcs_writel(VIRTUAL_APIC_PAGE_ADDR, 0);
1136 vmcs_writel(TPR_THRESHOLD, 0);
1139 vmcs_writel(CR0_GUEST_HOST_MASK, KVM_GUEST_CR0_MASK);
1140 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1142 vcpu->cr0 = 0x60000010;
1143 vmx_set_cr0(vcpu, vcpu->cr0); // enter rmode
1144 vmx_set_cr4(vcpu, 0);
1145 #ifdef CONFIG_X86_64
1146 vmx_set_efer(vcpu, 0);
1155 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1160 unsigned long flags;
1161 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1162 u16 sp = vmcs_readl(GUEST_RSP);
1163 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1165 if (sp > ss_limit || sp - 6 > sp) {
1166 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1168 vmcs_readl(GUEST_RSP),
1169 vmcs_readl(GUEST_SS_BASE),
1170 vmcs_read32(GUEST_SS_LIMIT));
1174 if (kvm_read_guest(vcpu, irq * sizeof(ent), sizeof(ent), &ent) !=
1176 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1180 flags = vmcs_readl(GUEST_RFLAGS);
1181 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1182 ip = vmcs_readl(GUEST_RIP);
1185 if (kvm_write_guest(vcpu, ss_base + sp - 2, 2, &flags) != 2 ||
1186 kvm_write_guest(vcpu, ss_base + sp - 4, 2, &cs) != 2 ||
1187 kvm_write_guest(vcpu, ss_base + sp - 6, 2, &ip) != 2) {
1188 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1192 vmcs_writel(GUEST_RFLAGS, flags &
1193 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1194 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1195 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1196 vmcs_writel(GUEST_RIP, ent[0]);
1197 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1200 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1202 int word_index = __ffs(vcpu->irq_summary);
1203 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1204 int irq = word_index * BITS_PER_LONG + bit_index;
1206 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1207 if (!vcpu->irq_pending[word_index])
1208 clear_bit(word_index, &vcpu->irq_summary);
1210 if (vcpu->rmode.active) {
1211 inject_rmode_irq(vcpu, irq);
1214 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1215 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1219 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1220 struct kvm_run *kvm_run)
1222 u32 cpu_based_vm_exec_control;
1224 vcpu->interrupt_window_open =
1225 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1226 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1228 if (vcpu->interrupt_window_open &&
1229 vcpu->irq_summary &&
1230 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1232 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1234 kvm_do_inject_irq(vcpu);
1236 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1237 if (!vcpu->interrupt_window_open &&
1238 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1240 * Interrupts blocked. Wait for unblock.
1242 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1244 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1245 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1248 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1250 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1252 set_debugreg(dbg->bp[0], 0);
1253 set_debugreg(dbg->bp[1], 1);
1254 set_debugreg(dbg->bp[2], 2);
1255 set_debugreg(dbg->bp[3], 3);
1257 if (dbg->singlestep) {
1258 unsigned long flags;
1260 flags = vmcs_readl(GUEST_RFLAGS);
1261 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1262 vmcs_writel(GUEST_RFLAGS, flags);
1266 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1267 int vec, u32 err_code)
1269 if (!vcpu->rmode.active)
1272 if (vec == GP_VECTOR && err_code == 0)
1273 if (emulate_instruction(vcpu, NULL, 0, 0) == EMULATE_DONE)
1278 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1280 u32 intr_info, error_code;
1281 unsigned long cr2, rip;
1283 enum emulation_result er;
1285 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1286 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1288 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1289 !is_page_fault(intr_info)) {
1290 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1291 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1294 if (is_external_interrupt(vect_info)) {
1295 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1296 set_bit(irq, vcpu->irq_pending);
1297 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1300 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) { /* nmi */
1305 rip = vmcs_readl(GUEST_RIP);
1306 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1307 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1308 if (is_page_fault(intr_info)) {
1309 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1311 spin_lock(&vcpu->kvm->lock);
1312 if (!vcpu->mmu.page_fault(vcpu, cr2, error_code)) {
1313 spin_unlock(&vcpu->kvm->lock);
1317 er = emulate_instruction(vcpu, kvm_run, cr2, error_code);
1318 spin_unlock(&vcpu->kvm->lock);
1323 case EMULATE_DO_MMIO:
1324 ++kvm_stat.mmio_exits;
1325 kvm_run->exit_reason = KVM_EXIT_MMIO;
1328 vcpu_printf(vcpu, "%s: emulate fail\n", __FUNCTION__);
1335 if (vcpu->rmode.active &&
1336 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1340 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1341 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1344 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1345 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1346 kvm_run->ex.error_code = error_code;
1350 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1351 struct kvm_run *kvm_run)
1353 ++kvm_stat.irq_exits;
1358 static int get_io_count(struct kvm_vcpu *vcpu, u64 *count)
1365 if ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_VM)) {
1368 u32 cs_ar = vmcs_read32(GUEST_CS_AR_BYTES);
1370 countr_size = (cs_ar & AR_L_MASK) ? 8:
1371 (cs_ar & AR_DB_MASK) ? 4: 2;
1374 rip = vmcs_readl(GUEST_RIP);
1375 if (countr_size != 8)
1376 rip += vmcs_readl(GUEST_CS_BASE);
1378 n = kvm_read_guest(vcpu, rip, sizeof(inst), &inst);
1380 for (i = 0; i < n; i++) {
1381 switch (((u8*)&inst)[i]) {
1394 countr_size = (countr_size == 2) ? 4: (countr_size >> 1);
1402 *count = vcpu->regs[VCPU_REGS_RCX] & (~0ULL >> (64 - countr_size));
1406 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1408 u64 exit_qualification;
1410 ++kvm_stat.io_exits;
1411 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1412 kvm_run->exit_reason = KVM_EXIT_IO;
1413 if (exit_qualification & 8)
1414 kvm_run->io.direction = KVM_EXIT_IO_IN;
1416 kvm_run->io.direction = KVM_EXIT_IO_OUT;
1417 kvm_run->io.size = (exit_qualification & 7) + 1;
1418 kvm_run->io.string = (exit_qualification & 16) != 0;
1419 kvm_run->io.string_down
1420 = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1421 kvm_run->io.rep = (exit_qualification & 32) != 0;
1422 kvm_run->io.port = exit_qualification >> 16;
1423 if (kvm_run->io.string) {
1424 if (!get_io_count(vcpu, &kvm_run->io.count))
1426 kvm_run->io.address = vmcs_readl(GUEST_LINEAR_ADDRESS);
1428 kvm_run->io.value = vcpu->regs[VCPU_REGS_RAX]; /* rax */
1432 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1434 u64 address = vmcs_read64(EXIT_QUALIFICATION);
1435 int instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1436 spin_lock(&vcpu->kvm->lock);
1437 vcpu->mmu.inval_page(vcpu, address);
1438 spin_unlock(&vcpu->kvm->lock);
1439 vmcs_writel(GUEST_RIP, vmcs_readl(GUEST_RIP) + instruction_length);
1443 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1445 u64 exit_qualification;
1449 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1450 cr = exit_qualification & 15;
1451 reg = (exit_qualification >> 8) & 15;
1452 switch ((exit_qualification >> 4) & 3) {
1453 case 0: /* mov to cr */
1456 vcpu_load_rsp_rip(vcpu);
1457 set_cr0(vcpu, vcpu->regs[reg]);
1458 skip_emulated_instruction(vcpu);
1461 vcpu_load_rsp_rip(vcpu);
1462 set_cr3(vcpu, vcpu->regs[reg]);
1463 skip_emulated_instruction(vcpu);
1466 vcpu_load_rsp_rip(vcpu);
1467 set_cr4(vcpu, vcpu->regs[reg]);
1468 skip_emulated_instruction(vcpu);
1471 vcpu_load_rsp_rip(vcpu);
1472 set_cr8(vcpu, vcpu->regs[reg]);
1473 skip_emulated_instruction(vcpu);
1477 case 1: /*mov from cr*/
1480 vcpu_load_rsp_rip(vcpu);
1481 vcpu->regs[reg] = vcpu->cr3;
1482 vcpu_put_rsp_rip(vcpu);
1483 skip_emulated_instruction(vcpu);
1486 printk(KERN_DEBUG "handle_cr: read CR8 "
1487 "cpu erratum AA15\n");
1488 vcpu_load_rsp_rip(vcpu);
1489 vcpu->regs[reg] = vcpu->cr8;
1490 vcpu_put_rsp_rip(vcpu);
1491 skip_emulated_instruction(vcpu);
1496 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1498 skip_emulated_instruction(vcpu);
1503 kvm_run->exit_reason = 0;
1504 printk(KERN_ERR "kvm: unhandled control register: op %d cr %d\n",
1505 (int)(exit_qualification >> 4) & 3, cr);
1509 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1511 u64 exit_qualification;
1516 * FIXME: this code assumes the host is debugging the guest.
1517 * need to deal with guest debugging itself too.
1519 exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
1520 dr = exit_qualification & 7;
1521 reg = (exit_qualification >> 8) & 15;
1522 vcpu_load_rsp_rip(vcpu);
1523 if (exit_qualification & 16) {
1535 vcpu->regs[reg] = val;
1539 vcpu_put_rsp_rip(vcpu);
1540 skip_emulated_instruction(vcpu);
1544 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1546 kvm_run->exit_reason = KVM_EXIT_CPUID;
1550 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1552 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1555 if (vmx_get_msr(vcpu, ecx, &data)) {
1556 vmx_inject_gp(vcpu, 0);
1560 /* FIXME: handling of bits 32:63 of rax, rdx */
1561 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
1562 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
1563 skip_emulated_instruction(vcpu);
1567 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1569 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
1570 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
1571 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
1573 if (vmx_set_msr(vcpu, ecx, data) != 0) {
1574 vmx_inject_gp(vcpu, 0);
1578 skip_emulated_instruction(vcpu);
1582 static void post_kvm_run_save(struct kvm_vcpu *vcpu,
1583 struct kvm_run *kvm_run)
1585 kvm_run->if_flag = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) != 0;
1586 kvm_run->cr8 = vcpu->cr8;
1587 kvm_run->apic_base = vcpu->apic_base;
1588 kvm_run->ready_for_interrupt_injection = (vcpu->interrupt_window_open &&
1589 vcpu->irq_summary == 0);
1592 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
1593 struct kvm_run *kvm_run)
1596 * If the user space waits to inject interrupts, exit as soon as
1599 if (kvm_run->request_interrupt_window &&
1600 !vcpu->irq_summary &&
1601 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF)) {
1602 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1603 ++kvm_stat.irq_window_exits;
1609 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1611 skip_emulated_instruction(vcpu);
1612 if (vcpu->irq_summary)
1615 kvm_run->exit_reason = KVM_EXIT_HLT;
1616 ++kvm_stat.halt_exits;
1621 * The exit handlers return 1 if the exit was handled fully and guest execution
1622 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
1623 * to be done to userspace and return 0.
1625 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
1626 struct kvm_run *kvm_run) = {
1627 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
1628 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
1629 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
1630 [EXIT_REASON_INVLPG] = handle_invlpg,
1631 [EXIT_REASON_CR_ACCESS] = handle_cr,
1632 [EXIT_REASON_DR_ACCESS] = handle_dr,
1633 [EXIT_REASON_CPUID] = handle_cpuid,
1634 [EXIT_REASON_MSR_READ] = handle_rdmsr,
1635 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
1636 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
1637 [EXIT_REASON_HLT] = handle_halt,
1640 static const int kvm_vmx_max_exit_handlers =
1641 sizeof(kvm_vmx_exit_handlers) / sizeof(*kvm_vmx_exit_handlers);
1644 * The guest has exited. See if we can fix it or if we need userspace
1647 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1649 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1650 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
1652 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
1653 exit_reason != EXIT_REASON_EXCEPTION_NMI )
1654 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
1655 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
1656 kvm_run->instruction_length = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1657 if (exit_reason < kvm_vmx_max_exit_handlers
1658 && kvm_vmx_exit_handlers[exit_reason])
1659 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
1661 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1662 kvm_run->hw.hardware_exit_reason = exit_reason;
1668 * Check if userspace requested an interrupt window, and that the
1669 * interrupt window is open.
1671 * No need to exit to userspace if we already have an interrupt queued.
1673 static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
1674 struct kvm_run *kvm_run)
1676 return (!vcpu->irq_summary &&
1677 kvm_run->request_interrupt_window &&
1678 vcpu->interrupt_window_open &&
1679 (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF));
1682 static int vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1685 u16 fs_sel, gs_sel, ldt_sel;
1686 int fs_gs_ldt_reload_needed;
1690 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1691 * allow segment selectors with cpl > 0 or ti == 1.
1695 ldt_sel = read_ldt();
1696 fs_gs_ldt_reload_needed = (fs_sel & 7) | (gs_sel & 7) | ldt_sel;
1697 if (!fs_gs_ldt_reload_needed) {
1698 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1699 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1701 vmcs_write16(HOST_FS_SELECTOR, 0);
1702 vmcs_write16(HOST_GS_SELECTOR, 0);
1705 #ifdef CONFIG_X86_64
1706 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1707 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1709 vmcs_writel(HOST_FS_BASE, segment_base(fs_sel));
1710 vmcs_writel(HOST_GS_BASE, segment_base(gs_sel));
1713 do_interrupt_requests(vcpu, kvm_run);
1715 if (vcpu->guest_debug.enabled)
1716 kvm_guest_debug_pre(vcpu);
1718 fx_save(vcpu->host_fx_image);
1719 fx_restore(vcpu->guest_fx_image);
1721 save_msrs(vcpu->host_msrs, vcpu->nmsrs);
1722 load_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1725 /* Store host registers */
1727 #ifdef CONFIG_X86_64
1728 "push %%rax; push %%rbx; push %%rdx;"
1729 "push %%rsi; push %%rdi; push %%rbp;"
1730 "push %%r8; push %%r9; push %%r10; push %%r11;"
1731 "push %%r12; push %%r13; push %%r14; push %%r15;"
1733 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1735 "pusha; push %%ecx \n\t"
1736 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
1738 /* Check if vmlaunch of vmresume is needed */
1740 /* Load guest registers. Don't clobber flags. */
1741 #ifdef CONFIG_X86_64
1742 "mov %c[cr2](%3), %%rax \n\t"
1743 "mov %%rax, %%cr2 \n\t"
1744 "mov %c[rax](%3), %%rax \n\t"
1745 "mov %c[rbx](%3), %%rbx \n\t"
1746 "mov %c[rdx](%3), %%rdx \n\t"
1747 "mov %c[rsi](%3), %%rsi \n\t"
1748 "mov %c[rdi](%3), %%rdi \n\t"
1749 "mov %c[rbp](%3), %%rbp \n\t"
1750 "mov %c[r8](%3), %%r8 \n\t"
1751 "mov %c[r9](%3), %%r9 \n\t"
1752 "mov %c[r10](%3), %%r10 \n\t"
1753 "mov %c[r11](%3), %%r11 \n\t"
1754 "mov %c[r12](%3), %%r12 \n\t"
1755 "mov %c[r13](%3), %%r13 \n\t"
1756 "mov %c[r14](%3), %%r14 \n\t"
1757 "mov %c[r15](%3), %%r15 \n\t"
1758 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
1760 "mov %c[cr2](%3), %%eax \n\t"
1761 "mov %%eax, %%cr2 \n\t"
1762 "mov %c[rax](%3), %%eax \n\t"
1763 "mov %c[rbx](%3), %%ebx \n\t"
1764 "mov %c[rdx](%3), %%edx \n\t"
1765 "mov %c[rsi](%3), %%esi \n\t"
1766 "mov %c[rdi](%3), %%edi \n\t"
1767 "mov %c[rbp](%3), %%ebp \n\t"
1768 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
1770 /* Enter guest mode */
1772 ASM_VMX_VMLAUNCH "\n\t"
1773 "jmp kvm_vmx_return \n\t"
1774 "launched: " ASM_VMX_VMRESUME "\n\t"
1775 ".globl kvm_vmx_return \n\t"
1777 /* Save guest registers, load host registers, keep flags */
1778 #ifdef CONFIG_X86_64
1779 "xchg %3, 0(%%rsp) \n\t"
1780 "mov %%rax, %c[rax](%3) \n\t"
1781 "mov %%rbx, %c[rbx](%3) \n\t"
1782 "pushq 0(%%rsp); popq %c[rcx](%3) \n\t"
1783 "mov %%rdx, %c[rdx](%3) \n\t"
1784 "mov %%rsi, %c[rsi](%3) \n\t"
1785 "mov %%rdi, %c[rdi](%3) \n\t"
1786 "mov %%rbp, %c[rbp](%3) \n\t"
1787 "mov %%r8, %c[r8](%3) \n\t"
1788 "mov %%r9, %c[r9](%3) \n\t"
1789 "mov %%r10, %c[r10](%3) \n\t"
1790 "mov %%r11, %c[r11](%3) \n\t"
1791 "mov %%r12, %c[r12](%3) \n\t"
1792 "mov %%r13, %c[r13](%3) \n\t"
1793 "mov %%r14, %c[r14](%3) \n\t"
1794 "mov %%r15, %c[r15](%3) \n\t"
1795 "mov %%cr2, %%rax \n\t"
1796 "mov %%rax, %c[cr2](%3) \n\t"
1797 "mov 0(%%rsp), %3 \n\t"
1799 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
1800 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
1801 "pop %%rbp; pop %%rdi; pop %%rsi;"
1802 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
1804 "xchg %3, 0(%%esp) \n\t"
1805 "mov %%eax, %c[rax](%3) \n\t"
1806 "mov %%ebx, %c[rbx](%3) \n\t"
1807 "pushl 0(%%esp); popl %c[rcx](%3) \n\t"
1808 "mov %%edx, %c[rdx](%3) \n\t"
1809 "mov %%esi, %c[rsi](%3) \n\t"
1810 "mov %%edi, %c[rdi](%3) \n\t"
1811 "mov %%ebp, %c[rbp](%3) \n\t"
1812 "mov %%cr2, %%eax \n\t"
1813 "mov %%eax, %c[cr2](%3) \n\t"
1814 "mov 0(%%esp), %3 \n\t"
1816 "pop %%ecx; popa \n\t"
1821 : "r"(vcpu->launched), "d"((unsigned long)HOST_RSP),
1823 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
1824 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
1825 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
1826 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
1827 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
1828 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
1829 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
1830 #ifdef CONFIG_X86_64
1831 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
1832 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
1833 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
1834 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
1835 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
1836 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
1837 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
1838 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
1840 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
1845 save_msrs(vcpu->guest_msrs, NR_BAD_MSRS);
1846 load_msrs(vcpu->host_msrs, NR_BAD_MSRS);
1848 fx_save(vcpu->guest_fx_image);
1849 fx_restore(vcpu->host_fx_image);
1850 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
1852 #ifndef CONFIG_X86_64
1853 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
1856 kvm_run->exit_type = 0;
1858 kvm_run->exit_type = KVM_EXIT_TYPE_FAIL_ENTRY;
1859 kvm_run->exit_reason = vmcs_read32(VM_INSTRUCTION_ERROR);
1861 if (fs_gs_ldt_reload_needed) {
1865 * If we have to reload gs, we must take care to
1866 * preserve our gs base.
1868 local_irq_disable();
1870 #ifdef CONFIG_X86_64
1871 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
1878 kvm_run->exit_type = KVM_EXIT_TYPE_VM_EXIT;
1879 if (kvm_handle_exit(kvm_run, vcpu)) {
1880 /* Give scheduler a change to reschedule. */
1881 if (signal_pending(current)) {
1882 ++kvm_stat.signal_exits;
1883 post_kvm_run_save(vcpu, kvm_run);
1887 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
1888 ++kvm_stat.request_irq_exits;
1889 post_kvm_run_save(vcpu, kvm_run);
1898 post_kvm_run_save(vcpu, kvm_run);
1902 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1904 vmcs_writel(GUEST_CR3, vmcs_readl(GUEST_CR3));
1907 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
1911 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1913 ++kvm_stat.pf_guest;
1915 if (is_page_fault(vect_info)) {
1916 printk(KERN_DEBUG "inject_page_fault: "
1917 "double fault 0x%lx @ 0x%lx\n",
1918 addr, vmcs_readl(GUEST_RIP));
1919 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
1920 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1922 INTR_TYPE_EXCEPTION |
1923 INTR_INFO_DELIEVER_CODE_MASK |
1924 INTR_INFO_VALID_MASK);
1928 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
1929 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1931 INTR_TYPE_EXCEPTION |
1932 INTR_INFO_DELIEVER_CODE_MASK |
1933 INTR_INFO_VALID_MASK);
1937 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
1940 on_each_cpu(__vcpu_clear, vcpu, 0, 1);
1941 free_vmcs(vcpu->vmcs);
1946 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
1948 vmx_free_vmcs(vcpu);
1951 static int vmx_create_vcpu(struct kvm_vcpu *vcpu)
1955 vcpu->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1956 if (!vcpu->guest_msrs)
1959 vcpu->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
1960 if (!vcpu->host_msrs)
1961 goto out_free_guest_msrs;
1963 vmcs = alloc_vmcs();
1974 kfree(vcpu->host_msrs);
1975 vcpu->host_msrs = NULL;
1977 out_free_guest_msrs:
1978 kfree(vcpu->guest_msrs);
1979 vcpu->guest_msrs = NULL;
1984 static struct kvm_arch_ops vmx_arch_ops = {
1985 .cpu_has_kvm_support = cpu_has_kvm_support,
1986 .disabled_by_bios = vmx_disabled_by_bios,
1987 .hardware_setup = hardware_setup,
1988 .hardware_unsetup = hardware_unsetup,
1989 .hardware_enable = hardware_enable,
1990 .hardware_disable = hardware_disable,
1992 .vcpu_create = vmx_create_vcpu,
1993 .vcpu_free = vmx_free_vcpu,
1995 .vcpu_load = vmx_vcpu_load,
1996 .vcpu_put = vmx_vcpu_put,
1998 .set_guest_debug = set_guest_debug,
1999 .get_msr = vmx_get_msr,
2000 .set_msr = vmx_set_msr,
2001 .get_segment_base = vmx_get_segment_base,
2002 .get_segment = vmx_get_segment,
2003 .set_segment = vmx_set_segment,
2004 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2005 .set_cr0 = vmx_set_cr0,
2006 .set_cr0_no_modeswitch = vmx_set_cr0_no_modeswitch,
2007 .set_cr3 = vmx_set_cr3,
2008 .set_cr4 = vmx_set_cr4,
2009 #ifdef CONFIG_X86_64
2010 .set_efer = vmx_set_efer,
2012 .get_idt = vmx_get_idt,
2013 .set_idt = vmx_set_idt,
2014 .get_gdt = vmx_get_gdt,
2015 .set_gdt = vmx_set_gdt,
2016 .cache_regs = vcpu_load_rsp_rip,
2017 .decache_regs = vcpu_put_rsp_rip,
2018 .get_rflags = vmx_get_rflags,
2019 .set_rflags = vmx_set_rflags,
2021 .tlb_flush = vmx_flush_tlb,
2022 .inject_page_fault = vmx_inject_page_fault,
2024 .inject_gp = vmx_inject_gp,
2026 .run = vmx_vcpu_run,
2027 .skip_emulated_instruction = skip_emulated_instruction,
2028 .vcpu_setup = vmx_vcpu_setup,
2031 static int __init vmx_init(void)
2033 return kvm_init_arch(&vmx_arch_ops, THIS_MODULE);
2036 static void __exit vmx_exit(void)
2041 module_init(vmx_init)
2042 module_exit(vmx_exit)