2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
7 * Copyright (C) 2006 Qumranet, Inc.
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
19 #include "x86_emulate.h"
22 #include "segment_descriptor.h"
24 #include <linux/module.h>
25 #include <linux/kernel.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/moduleparam.h>
34 MODULE_AUTHOR("Qumranet");
35 MODULE_LICENSE("GPL");
37 static int bypass_guest_pf = 1;
38 module_param(bypass_guest_pf, bool, 0);
50 struct kvm_msr_entry *guest_msrs;
51 struct kvm_msr_entry *host_msrs;
56 int msr_offset_kernel_gs_base;
61 u16 fs_sel, gs_sel, ldt_sel;
62 int gs_ldt_reload_needed;
64 int guest_efer_loaded;
69 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
71 return container_of(vcpu, struct vcpu_vmx, vcpu);
74 static int init_rmode_tss(struct kvm *kvm);
76 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
77 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
79 static struct page *vmx_io_bitmap_a;
80 static struct page *vmx_io_bitmap_b;
82 static struct vmcs_config {
86 u32 pin_based_exec_ctrl;
87 u32 cpu_based_exec_ctrl;
92 #define VMX_SEGMENT_FIELD(seg) \
93 [VCPU_SREG_##seg] = { \
94 .selector = GUEST_##seg##_SELECTOR, \
95 .base = GUEST_##seg##_BASE, \
96 .limit = GUEST_##seg##_LIMIT, \
97 .ar_bytes = GUEST_##seg##_AR_BYTES, \
100 static struct kvm_vmx_segment_field {
105 } kvm_vmx_segment_fields[] = {
106 VMX_SEGMENT_FIELD(CS),
107 VMX_SEGMENT_FIELD(DS),
108 VMX_SEGMENT_FIELD(ES),
109 VMX_SEGMENT_FIELD(FS),
110 VMX_SEGMENT_FIELD(GS),
111 VMX_SEGMENT_FIELD(SS),
112 VMX_SEGMENT_FIELD(TR),
113 VMX_SEGMENT_FIELD(LDTR),
117 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
118 * away by decrementing the array size.
120 static const u32 vmx_msr_index[] = {
122 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
124 MSR_EFER, MSR_K6_STAR,
126 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
128 static void load_msrs(struct kvm_msr_entry *e, int n)
132 for (i = 0; i < n; ++i)
133 wrmsrl(e[i].index, e[i].data);
136 static void save_msrs(struct kvm_msr_entry *e, int n)
140 for (i = 0; i < n; ++i)
141 rdmsrl(e[i].index, e[i].data);
144 static inline int is_page_fault(u32 intr_info)
146 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
147 INTR_INFO_VALID_MASK)) ==
148 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
151 static inline int is_no_device(u32 intr_info)
153 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
154 INTR_INFO_VALID_MASK)) ==
155 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
158 static inline int is_invalid_opcode(u32 intr_info)
160 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
161 INTR_INFO_VALID_MASK)) ==
162 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
165 static inline int is_external_interrupt(u32 intr_info)
167 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
168 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
171 static inline int cpu_has_vmx_tpr_shadow(void)
173 return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
176 static inline int vm_need_tpr_shadow(struct kvm *kvm)
178 return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
181 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
185 for (i = 0; i < vmx->nmsrs; ++i)
186 if (vmx->guest_msrs[i].index == msr)
191 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
195 i = __find_msr_index(vmx, msr);
197 return &vmx->guest_msrs[i];
201 static void vmcs_clear(struct vmcs *vmcs)
203 u64 phys_addr = __pa(vmcs);
206 asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
207 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
210 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
214 static void __vcpu_clear(void *arg)
216 struct vcpu_vmx *vmx = arg;
217 int cpu = raw_smp_processor_id();
219 if (vmx->vcpu.cpu == cpu)
220 vmcs_clear(vmx->vmcs);
221 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
222 per_cpu(current_vmcs, cpu) = NULL;
223 rdtscll(vmx->vcpu.host_tsc);
226 static void vcpu_clear(struct vcpu_vmx *vmx)
228 if (vmx->vcpu.cpu == -1)
230 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
234 static unsigned long vmcs_readl(unsigned long field)
238 asm volatile (ASM_VMX_VMREAD_RDX_RAX
239 : "=a"(value) : "d"(field) : "cc");
243 static u16 vmcs_read16(unsigned long field)
245 return vmcs_readl(field);
248 static u32 vmcs_read32(unsigned long field)
250 return vmcs_readl(field);
253 static u64 vmcs_read64(unsigned long field)
256 return vmcs_readl(field);
258 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
262 static noinline void vmwrite_error(unsigned long field, unsigned long value)
264 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
265 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
269 static void vmcs_writel(unsigned long field, unsigned long value)
273 asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
274 : "=q"(error) : "a"(value), "d"(field) : "cc" );
276 vmwrite_error(field, value);
279 static void vmcs_write16(unsigned long field, u16 value)
281 vmcs_writel(field, value);
284 static void vmcs_write32(unsigned long field, u32 value)
286 vmcs_writel(field, value);
289 static void vmcs_write64(unsigned long field, u64 value)
292 vmcs_writel(field, value);
294 vmcs_writel(field, value);
296 vmcs_writel(field+1, value >> 32);
300 static void vmcs_clear_bits(unsigned long field, u32 mask)
302 vmcs_writel(field, vmcs_readl(field) & ~mask);
305 static void vmcs_set_bits(unsigned long field, u32 mask)
307 vmcs_writel(field, vmcs_readl(field) | mask);
310 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
314 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
315 if (!vcpu->fpu_active)
316 eb |= 1u << NM_VECTOR;
317 if (vcpu->guest_debug.enabled)
319 if (vcpu->rmode.active)
321 vmcs_write32(EXCEPTION_BITMAP, eb);
324 static void reload_tss(void)
326 #ifndef CONFIG_X86_64
329 * VT restores TR but not its size. Useless.
331 struct descriptor_table gdt;
332 struct segment_descriptor *descs;
335 descs = (void *)gdt.base;
336 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
341 static void load_transition_efer(struct vcpu_vmx *vmx)
343 int efer_offset = vmx->msr_offset_efer;
344 u64 host_efer = vmx->host_msrs[efer_offset].data;
345 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
351 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
354 ignore_bits = EFER_NX | EFER_SCE;
356 ignore_bits |= EFER_LMA | EFER_LME;
357 /* SCE is meaningful only in long mode on Intel */
358 if (guest_efer & EFER_LMA)
359 ignore_bits &= ~(u64)EFER_SCE;
361 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
364 vmx->host_state.guest_efer_loaded = 1;
365 guest_efer &= ~ignore_bits;
366 guest_efer |= host_efer & ignore_bits;
367 wrmsrl(MSR_EFER, guest_efer);
368 vmx->vcpu.stat.efer_reload++;
371 static void reload_host_efer(struct vcpu_vmx *vmx)
373 if (vmx->host_state.guest_efer_loaded) {
374 vmx->host_state.guest_efer_loaded = 0;
375 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
379 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
381 struct vcpu_vmx *vmx = to_vmx(vcpu);
383 if (vmx->host_state.loaded)
386 vmx->host_state.loaded = 1;
388 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
389 * allow segment selectors with cpl > 0 or ti == 1.
391 vmx->host_state.ldt_sel = read_ldt();
392 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
393 vmx->host_state.fs_sel = read_fs();
394 if (!(vmx->host_state.fs_sel & 7)) {
395 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
396 vmx->host_state.fs_reload_needed = 0;
398 vmcs_write16(HOST_FS_SELECTOR, 0);
399 vmx->host_state.fs_reload_needed = 1;
401 vmx->host_state.gs_sel = read_gs();
402 if (!(vmx->host_state.gs_sel & 7))
403 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
405 vmcs_write16(HOST_GS_SELECTOR, 0);
406 vmx->host_state.gs_ldt_reload_needed = 1;
410 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
411 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
413 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
414 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
418 if (is_long_mode(&vmx->vcpu)) {
419 save_msrs(vmx->host_msrs +
420 vmx->msr_offset_kernel_gs_base, 1);
423 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
424 load_transition_efer(vmx);
427 static void vmx_load_host_state(struct vcpu_vmx *vmx)
431 if (!vmx->host_state.loaded)
434 vmx->host_state.loaded = 0;
435 if (vmx->host_state.fs_reload_needed)
436 load_fs(vmx->host_state.fs_sel);
437 if (vmx->host_state.gs_ldt_reload_needed) {
438 load_ldt(vmx->host_state.ldt_sel);
440 * If we have to reload gs, we must take care to
441 * preserve our gs base.
443 local_irq_save(flags);
444 load_gs(vmx->host_state.gs_sel);
446 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
448 local_irq_restore(flags);
451 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
452 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
453 reload_host_efer(vmx);
457 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
458 * vcpu mutex is already taken.
460 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
462 struct vcpu_vmx *vmx = to_vmx(vcpu);
463 u64 phys_addr = __pa(vmx->vmcs);
466 if (vcpu->cpu != cpu) {
468 kvm_migrate_apic_timer(vcpu);
471 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
474 per_cpu(current_vmcs, cpu) = vmx->vmcs;
475 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
476 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
479 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
480 vmx->vmcs, phys_addr);
483 if (vcpu->cpu != cpu) {
484 struct descriptor_table dt;
485 unsigned long sysenter_esp;
489 * Linux uses per-cpu TSS and GDT, so set these when switching
492 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
494 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
496 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
497 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
500 * Make sure the time stamp counter is monotonous.
503 delta = vcpu->host_tsc - tsc_this;
504 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
508 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
510 vmx_load_host_state(to_vmx(vcpu));
511 kvm_put_guest_fpu(vcpu);
514 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
516 if (vcpu->fpu_active)
518 vcpu->fpu_active = 1;
519 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
520 if (vcpu->cr0 & X86_CR0_TS)
521 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
522 update_exception_bitmap(vcpu);
525 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
527 if (!vcpu->fpu_active)
529 vcpu->fpu_active = 0;
530 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
531 update_exception_bitmap(vcpu);
534 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
536 vcpu_clear(to_vmx(vcpu));
539 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
541 return vmcs_readl(GUEST_RFLAGS);
544 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
546 if (vcpu->rmode.active)
547 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
548 vmcs_writel(GUEST_RFLAGS, rflags);
551 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
554 u32 interruptibility;
556 rip = vmcs_readl(GUEST_RIP);
557 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
558 vmcs_writel(GUEST_RIP, rip);
561 * We emulated an instruction, so temporary interrupt blocking
562 * should be removed, if set.
564 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
565 if (interruptibility & 3)
566 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
567 interruptibility & ~3);
568 vcpu->interrupt_window_open = 1;
571 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
573 printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
574 vmcs_readl(GUEST_RIP));
575 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
576 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
578 INTR_TYPE_EXCEPTION |
579 INTR_INFO_DELIEVER_CODE_MASK |
580 INTR_INFO_VALID_MASK);
583 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
585 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
587 INTR_TYPE_EXCEPTION |
588 INTR_INFO_VALID_MASK);
592 * Swap MSR entry in host/guest MSR entry array.
595 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
597 struct kvm_msr_entry tmp;
599 tmp = vmx->guest_msrs[to];
600 vmx->guest_msrs[to] = vmx->guest_msrs[from];
601 vmx->guest_msrs[from] = tmp;
602 tmp = vmx->host_msrs[to];
603 vmx->host_msrs[to] = vmx->host_msrs[from];
604 vmx->host_msrs[from] = tmp;
609 * Set up the vmcs to automatically save and restore system
610 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
611 * mode, as fiddling with msrs is very expensive.
613 static void setup_msrs(struct vcpu_vmx *vmx)
619 if (is_long_mode(&vmx->vcpu)) {
622 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
624 move_msr_up(vmx, index, save_nmsrs++);
625 index = __find_msr_index(vmx, MSR_LSTAR);
627 move_msr_up(vmx, index, save_nmsrs++);
628 index = __find_msr_index(vmx, MSR_CSTAR);
630 move_msr_up(vmx, index, save_nmsrs++);
631 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
633 move_msr_up(vmx, index, save_nmsrs++);
635 * MSR_K6_STAR is only needed on long mode guests, and only
636 * if efer.sce is enabled.
638 index = __find_msr_index(vmx, MSR_K6_STAR);
639 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
640 move_msr_up(vmx, index, save_nmsrs++);
643 vmx->save_nmsrs = save_nmsrs;
646 vmx->msr_offset_kernel_gs_base =
647 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
649 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
653 * reads and returns guest's timestamp counter "register"
654 * guest_tsc = host_tsc + tsc_offset -- 21.3
656 static u64 guest_read_tsc(void)
658 u64 host_tsc, tsc_offset;
661 tsc_offset = vmcs_read64(TSC_OFFSET);
662 return host_tsc + tsc_offset;
666 * writes 'guest_tsc' into guest's timestamp counter "register"
667 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
669 static void guest_write_tsc(u64 guest_tsc)
674 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
678 * Reads an msr value (of 'msr_index') into 'pdata'.
679 * Returns 0 on success, non-0 otherwise.
680 * Assumes vcpu_load() was already called.
682 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
685 struct kvm_msr_entry *msr;
688 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
695 data = vmcs_readl(GUEST_FS_BASE);
698 data = vmcs_readl(GUEST_GS_BASE);
701 return kvm_get_msr_common(vcpu, msr_index, pdata);
703 case MSR_IA32_TIME_STAMP_COUNTER:
704 data = guest_read_tsc();
706 case MSR_IA32_SYSENTER_CS:
707 data = vmcs_read32(GUEST_SYSENTER_CS);
709 case MSR_IA32_SYSENTER_EIP:
710 data = vmcs_readl(GUEST_SYSENTER_EIP);
712 case MSR_IA32_SYSENTER_ESP:
713 data = vmcs_readl(GUEST_SYSENTER_ESP);
716 msr = find_msr_entry(to_vmx(vcpu), msr_index);
721 return kvm_get_msr_common(vcpu, msr_index, pdata);
729 * Writes msr value into into the appropriate "register".
730 * Returns 0 on success, non-0 otherwise.
731 * Assumes vcpu_load() was already called.
733 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
735 struct vcpu_vmx *vmx = to_vmx(vcpu);
736 struct kvm_msr_entry *msr;
742 ret = kvm_set_msr_common(vcpu, msr_index, data);
743 if (vmx->host_state.loaded) {
744 reload_host_efer(vmx);
745 load_transition_efer(vmx);
749 vmcs_writel(GUEST_FS_BASE, data);
752 vmcs_writel(GUEST_GS_BASE, data);
755 case MSR_IA32_SYSENTER_CS:
756 vmcs_write32(GUEST_SYSENTER_CS, data);
758 case MSR_IA32_SYSENTER_EIP:
759 vmcs_writel(GUEST_SYSENTER_EIP, data);
761 case MSR_IA32_SYSENTER_ESP:
762 vmcs_writel(GUEST_SYSENTER_ESP, data);
764 case MSR_IA32_TIME_STAMP_COUNTER:
765 guest_write_tsc(data);
768 msr = find_msr_entry(vmx, msr_index);
771 if (vmx->host_state.loaded)
772 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
775 ret = kvm_set_msr_common(vcpu, msr_index, data);
782 * Sync the rsp and rip registers into the vcpu structure. This allows
783 * registers to be accessed by indexing vcpu->regs.
785 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
787 vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
788 vcpu->rip = vmcs_readl(GUEST_RIP);
792 * Syncs rsp and rip back into the vmcs. Should be called after possible
795 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
797 vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
798 vmcs_writel(GUEST_RIP, vcpu->rip);
801 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
803 unsigned long dr7 = 0x400;
806 old_singlestep = vcpu->guest_debug.singlestep;
808 vcpu->guest_debug.enabled = dbg->enabled;
809 if (vcpu->guest_debug.enabled) {
812 dr7 |= 0x200; /* exact */
813 for (i = 0; i < 4; ++i) {
814 if (!dbg->breakpoints[i].enabled)
816 vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
817 dr7 |= 2 << (i*2); /* global enable */
818 dr7 |= 0 << (i*4+16); /* execution breakpoint */
821 vcpu->guest_debug.singlestep = dbg->singlestep;
823 vcpu->guest_debug.singlestep = 0;
825 if (old_singlestep && !vcpu->guest_debug.singlestep) {
828 flags = vmcs_readl(GUEST_RFLAGS);
829 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
830 vmcs_writel(GUEST_RFLAGS, flags);
833 update_exception_bitmap(vcpu);
834 vmcs_writel(GUEST_DR7, dr7);
839 static int vmx_get_irq(struct kvm_vcpu *vcpu)
843 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
844 if (idtv_info_field & INTR_INFO_VALID_MASK) {
845 if (is_external_interrupt(idtv_info_field))
846 return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
848 printk("pending exception: not handled yet\n");
853 static __init int cpu_has_kvm_support(void)
855 unsigned long ecx = cpuid_ecx(1);
856 return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
859 static __init int vmx_disabled_by_bios(void)
863 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
864 return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
865 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
866 == MSR_IA32_FEATURE_CONTROL_LOCKED;
867 /* locked but not enabled */
870 static void hardware_enable(void *garbage)
872 int cpu = raw_smp_processor_id();
873 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
876 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
877 if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
878 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
879 != (MSR_IA32_FEATURE_CONTROL_LOCKED |
880 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
881 /* enable and lock */
882 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
883 MSR_IA32_FEATURE_CONTROL_LOCKED |
884 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
885 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
886 asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
890 static void hardware_disable(void *garbage)
892 asm volatile (ASM_VMX_VMXOFF : : : "cc");
895 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
896 u32 msr, u32* result)
898 u32 vmx_msr_low, vmx_msr_high;
899 u32 ctl = ctl_min | ctl_opt;
901 rdmsr(msr, vmx_msr_low, vmx_msr_high);
903 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
904 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
906 /* Ensure minimum (required) set of control bits are supported. */
914 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
916 u32 vmx_msr_low, vmx_msr_high;
918 u32 _pin_based_exec_control = 0;
919 u32 _cpu_based_exec_control = 0;
920 u32 _vmexit_control = 0;
921 u32 _vmentry_control = 0;
923 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
925 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
926 &_pin_based_exec_control) < 0)
929 min = CPU_BASED_HLT_EXITING |
931 CPU_BASED_CR8_LOAD_EXITING |
932 CPU_BASED_CR8_STORE_EXITING |
934 CPU_BASED_USE_IO_BITMAPS |
935 CPU_BASED_MOV_DR_EXITING |
936 CPU_BASED_USE_TSC_OFFSETING;
938 opt = CPU_BASED_TPR_SHADOW;
942 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
943 &_cpu_based_exec_control) < 0)
946 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
947 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
948 ~CPU_BASED_CR8_STORE_EXITING;
953 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
956 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
957 &_vmexit_control) < 0)
961 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
962 &_vmentry_control) < 0)
965 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
967 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
968 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
972 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
973 if (vmx_msr_high & (1u<<16))
977 /* Require Write-Back (WB) memory type for VMCS accesses. */
978 if (((vmx_msr_high >> 18) & 15) != 6)
981 vmcs_conf->size = vmx_msr_high & 0x1fff;
982 vmcs_conf->order = get_order(vmcs_config.size);
983 vmcs_conf->revision_id = vmx_msr_low;
985 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
986 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
987 vmcs_conf->vmexit_ctrl = _vmexit_control;
988 vmcs_conf->vmentry_ctrl = _vmentry_control;
993 static struct vmcs *alloc_vmcs_cpu(int cpu)
995 int node = cpu_to_node(cpu);
999 pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1002 vmcs = page_address(pages);
1003 memset(vmcs, 0, vmcs_config.size);
1004 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1008 static struct vmcs *alloc_vmcs(void)
1010 return alloc_vmcs_cpu(raw_smp_processor_id());
1013 static void free_vmcs(struct vmcs *vmcs)
1015 free_pages((unsigned long)vmcs, vmcs_config.order);
1018 static void free_kvm_area(void)
1022 for_each_online_cpu(cpu)
1023 free_vmcs(per_cpu(vmxarea, cpu));
1026 static __init int alloc_kvm_area(void)
1030 for_each_online_cpu(cpu) {
1033 vmcs = alloc_vmcs_cpu(cpu);
1039 per_cpu(vmxarea, cpu) = vmcs;
1044 static __init int hardware_setup(void)
1046 if (setup_vmcs_config(&vmcs_config) < 0)
1048 return alloc_kvm_area();
1051 static __exit void hardware_unsetup(void)
1056 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1058 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1060 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1061 vmcs_write16(sf->selector, save->selector);
1062 vmcs_writel(sf->base, save->base);
1063 vmcs_write32(sf->limit, save->limit);
1064 vmcs_write32(sf->ar_bytes, save->ar);
1066 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1068 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1072 static void enter_pmode(struct kvm_vcpu *vcpu)
1074 unsigned long flags;
1076 vcpu->rmode.active = 0;
1078 vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1079 vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1080 vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1082 flags = vmcs_readl(GUEST_RFLAGS);
1083 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1084 flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1085 vmcs_writel(GUEST_RFLAGS, flags);
1087 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1088 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1090 update_exception_bitmap(vcpu);
1092 fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1093 fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1094 fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1095 fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1097 vmcs_write16(GUEST_SS_SELECTOR, 0);
1098 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1100 vmcs_write16(GUEST_CS_SELECTOR,
1101 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1102 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1105 static gva_t rmode_tss_base(struct kvm* kvm)
1107 gfn_t base_gfn = kvm->memslots[0].base_gfn + kvm->memslots[0].npages - 3;
1108 return base_gfn << PAGE_SHIFT;
1111 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1113 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1115 save->selector = vmcs_read16(sf->selector);
1116 save->base = vmcs_readl(sf->base);
1117 save->limit = vmcs_read32(sf->limit);
1118 save->ar = vmcs_read32(sf->ar_bytes);
1119 vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1120 vmcs_write32(sf->limit, 0xffff);
1121 vmcs_write32(sf->ar_bytes, 0xf3);
1124 static void enter_rmode(struct kvm_vcpu *vcpu)
1126 unsigned long flags;
1128 vcpu->rmode.active = 1;
1130 vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1131 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1133 vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1134 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1136 vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1137 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1139 flags = vmcs_readl(GUEST_RFLAGS);
1140 vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1142 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1144 vmcs_writel(GUEST_RFLAGS, flags);
1145 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1146 update_exception_bitmap(vcpu);
1148 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1149 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1150 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1152 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1153 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1154 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1155 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1156 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1158 fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1159 fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1160 fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1161 fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1163 kvm_mmu_reset_context(vcpu);
1164 init_rmode_tss(vcpu->kvm);
1167 #ifdef CONFIG_X86_64
1169 static void enter_lmode(struct kvm_vcpu *vcpu)
1173 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1174 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1175 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1177 vmcs_write32(GUEST_TR_AR_BYTES,
1178 (guest_tr_ar & ~AR_TYPE_MASK)
1179 | AR_TYPE_BUSY_64_TSS);
1182 vcpu->shadow_efer |= EFER_LMA;
1184 find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1185 vmcs_write32(VM_ENTRY_CONTROLS,
1186 vmcs_read32(VM_ENTRY_CONTROLS)
1187 | VM_ENTRY_IA32E_MODE);
1190 static void exit_lmode(struct kvm_vcpu *vcpu)
1192 vcpu->shadow_efer &= ~EFER_LMA;
1194 vmcs_write32(VM_ENTRY_CONTROLS,
1195 vmcs_read32(VM_ENTRY_CONTROLS)
1196 & ~VM_ENTRY_IA32E_MODE);
1201 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1203 vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1204 vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1207 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1209 vmx_fpu_deactivate(vcpu);
1211 if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1214 if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1217 #ifdef CONFIG_X86_64
1218 if (vcpu->shadow_efer & EFER_LME) {
1219 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1221 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1226 vmcs_writel(CR0_READ_SHADOW, cr0);
1227 vmcs_writel(GUEST_CR0,
1228 (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1231 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1232 vmx_fpu_activate(vcpu);
1235 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1237 vmcs_writel(GUEST_CR3, cr3);
1238 if (vcpu->cr0 & X86_CR0_PE)
1239 vmx_fpu_deactivate(vcpu);
1242 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1244 vmcs_writel(CR4_READ_SHADOW, cr4);
1245 vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1246 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1250 #ifdef CONFIG_X86_64
1252 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1254 struct vcpu_vmx *vmx = to_vmx(vcpu);
1255 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1257 vcpu->shadow_efer = efer;
1258 if (efer & EFER_LMA) {
1259 vmcs_write32(VM_ENTRY_CONTROLS,
1260 vmcs_read32(VM_ENTRY_CONTROLS) |
1261 VM_ENTRY_IA32E_MODE);
1265 vmcs_write32(VM_ENTRY_CONTROLS,
1266 vmcs_read32(VM_ENTRY_CONTROLS) &
1267 ~VM_ENTRY_IA32E_MODE);
1269 msr->data = efer & ~EFER_LME;
1276 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1278 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1280 return vmcs_readl(sf->base);
1283 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1284 struct kvm_segment *var, int seg)
1286 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1289 var->base = vmcs_readl(sf->base);
1290 var->limit = vmcs_read32(sf->limit);
1291 var->selector = vmcs_read16(sf->selector);
1292 ar = vmcs_read32(sf->ar_bytes);
1293 if (ar & AR_UNUSABLE_MASK)
1295 var->type = ar & 15;
1296 var->s = (ar >> 4) & 1;
1297 var->dpl = (ar >> 5) & 3;
1298 var->present = (ar >> 7) & 1;
1299 var->avl = (ar >> 12) & 1;
1300 var->l = (ar >> 13) & 1;
1301 var->db = (ar >> 14) & 1;
1302 var->g = (ar >> 15) & 1;
1303 var->unusable = (ar >> 16) & 1;
1306 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1313 ar = var->type & 15;
1314 ar |= (var->s & 1) << 4;
1315 ar |= (var->dpl & 3) << 5;
1316 ar |= (var->present & 1) << 7;
1317 ar |= (var->avl & 1) << 12;
1318 ar |= (var->l & 1) << 13;
1319 ar |= (var->db & 1) << 14;
1320 ar |= (var->g & 1) << 15;
1322 if (ar == 0) /* a 0 value means unusable */
1323 ar = AR_UNUSABLE_MASK;
1328 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1329 struct kvm_segment *var, int seg)
1331 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1334 if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1335 vcpu->rmode.tr.selector = var->selector;
1336 vcpu->rmode.tr.base = var->base;
1337 vcpu->rmode.tr.limit = var->limit;
1338 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1341 vmcs_writel(sf->base, var->base);
1342 vmcs_write32(sf->limit, var->limit);
1343 vmcs_write16(sf->selector, var->selector);
1344 if (vcpu->rmode.active && var->s) {
1346 * Hack real-mode segments into vm86 compatibility.
1348 if (var->base == 0xffff0000 && var->selector == 0xf000)
1349 vmcs_writel(sf->base, 0xf0000);
1352 ar = vmx_segment_access_rights(var);
1353 vmcs_write32(sf->ar_bytes, ar);
1356 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1358 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1360 *db = (ar >> 14) & 1;
1361 *l = (ar >> 13) & 1;
1364 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1366 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1367 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1370 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1372 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1373 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1376 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1378 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1379 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1382 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1384 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1385 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1388 static int init_rmode_tss(struct kvm* kvm)
1390 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1394 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1397 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1398 r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1401 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1404 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1408 r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1415 static void seg_setup(int seg)
1417 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1419 vmcs_write16(sf->selector, 0);
1420 vmcs_writel(sf->base, 0);
1421 vmcs_write32(sf->limit, 0xffff);
1422 vmcs_write32(sf->ar_bytes, 0x93);
1426 * Sets up the vmcs for emulated real mode.
1428 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1430 u32 host_sysenter_cs;
1433 struct descriptor_table dt;
1436 unsigned long kvm_vmx_return;
1440 if (!init_rmode_tss(vmx->vcpu.kvm)) {
1445 vmx->vcpu.rmode.active = 0;
1447 vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1448 set_cr8(&vmx->vcpu, 0);
1449 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1450 if (vmx->vcpu.vcpu_id == 0)
1451 msr |= MSR_IA32_APICBASE_BSP;
1452 kvm_set_apic_base(&vmx->vcpu, msr);
1454 fx_init(&vmx->vcpu);
1457 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1458 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
1460 if (vmx->vcpu.vcpu_id == 0) {
1461 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1462 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1464 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1465 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1467 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1468 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1470 seg_setup(VCPU_SREG_DS);
1471 seg_setup(VCPU_SREG_ES);
1472 seg_setup(VCPU_SREG_FS);
1473 seg_setup(VCPU_SREG_GS);
1474 seg_setup(VCPU_SREG_SS);
1476 vmcs_write16(GUEST_TR_SELECTOR, 0);
1477 vmcs_writel(GUEST_TR_BASE, 0);
1478 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1479 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1481 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1482 vmcs_writel(GUEST_LDTR_BASE, 0);
1483 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1484 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1486 vmcs_write32(GUEST_SYSENTER_CS, 0);
1487 vmcs_writel(GUEST_SYSENTER_ESP, 0);
1488 vmcs_writel(GUEST_SYSENTER_EIP, 0);
1490 vmcs_writel(GUEST_RFLAGS, 0x02);
1491 if (vmx->vcpu.vcpu_id == 0)
1492 vmcs_writel(GUEST_RIP, 0xfff0);
1494 vmcs_writel(GUEST_RIP, 0);
1495 vmcs_writel(GUEST_RSP, 0);
1497 //todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0
1498 vmcs_writel(GUEST_DR7, 0x400);
1500 vmcs_writel(GUEST_GDTR_BASE, 0);
1501 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1503 vmcs_writel(GUEST_IDTR_BASE, 0);
1504 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1506 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1507 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1508 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1511 vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1512 vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1516 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1518 /* Special registers */
1519 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1522 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1523 vmcs_config.pin_based_exec_ctrl);
1525 exec_control = vmcs_config.cpu_based_exec_ctrl;
1526 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1527 exec_control &= ~CPU_BASED_TPR_SHADOW;
1528 #ifdef CONFIG_X86_64
1529 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1530 CPU_BASED_CR8_LOAD_EXITING;
1533 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1535 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1536 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1537 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
1539 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
1540 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
1541 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
1543 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
1544 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1545 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1546 vmcs_write16(HOST_FS_SELECTOR, read_fs()); /* 22.2.4 */
1547 vmcs_write16(HOST_GS_SELECTOR, read_gs()); /* 22.2.4 */
1548 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
1549 #ifdef CONFIG_X86_64
1550 rdmsrl(MSR_FS_BASE, a);
1551 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1552 rdmsrl(MSR_GS_BASE, a);
1553 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1555 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1556 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1559 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
1562 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
1564 asm ("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1565 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1566 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1567 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1568 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1570 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1571 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1572 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1573 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
1574 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1575 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
1577 for (i = 0; i < NR_VMX_MSR; ++i) {
1578 u32 index = vmx_msr_index[i];
1579 u32 data_low, data_high;
1583 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1585 if (wrmsr_safe(index, data_low, data_high) < 0)
1587 data = data_low | ((u64)data_high << 32);
1588 vmx->host_msrs[j].index = index;
1589 vmx->host_msrs[j].reserved = 0;
1590 vmx->host_msrs[j].data = data;
1591 vmx->guest_msrs[j] = vmx->host_msrs[j];
1597 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1599 /* 22.2.1, 20.8.1 */
1600 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1602 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
1604 #ifdef CONFIG_X86_64
1605 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1606 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1607 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1608 page_to_phys(vmx->vcpu.apic->regs_page));
1609 vmcs_write32(TPR_THRESHOLD, 0);
1612 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1613 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1615 vmx->vcpu.cr0 = 0x60000010;
1616 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); // enter rmode
1617 vmx_set_cr4(&vmx->vcpu, 0);
1618 #ifdef CONFIG_X86_64
1619 vmx_set_efer(&vmx->vcpu, 0);
1621 vmx_fpu_activate(&vmx->vcpu);
1622 update_exception_bitmap(&vmx->vcpu);
1630 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1632 struct vcpu_vmx *vmx = to_vmx(vcpu);
1634 vmx_vcpu_setup(vmx);
1637 static void inject_rmode_irq(struct kvm_vcpu *vcpu, int irq)
1642 unsigned long flags;
1643 unsigned long ss_base = vmcs_readl(GUEST_SS_BASE);
1644 u16 sp = vmcs_readl(GUEST_RSP);
1645 u32 ss_limit = vmcs_read32(GUEST_SS_LIMIT);
1647 if (sp > ss_limit || sp < 6 ) {
1648 vcpu_printf(vcpu, "%s: #SS, rsp 0x%lx ss 0x%lx limit 0x%x\n",
1650 vmcs_readl(GUEST_RSP),
1651 vmcs_readl(GUEST_SS_BASE),
1652 vmcs_read32(GUEST_SS_LIMIT));
1656 if (emulator_read_std(irq * sizeof(ent), &ent, sizeof(ent), vcpu) !=
1658 vcpu_printf(vcpu, "%s: read guest err\n", __FUNCTION__);
1662 flags = vmcs_readl(GUEST_RFLAGS);
1663 cs = vmcs_readl(GUEST_CS_BASE) >> 4;
1664 ip = vmcs_readl(GUEST_RIP);
1667 if (emulator_write_emulated(ss_base + sp - 2, &flags, 2, vcpu) != X86EMUL_CONTINUE ||
1668 emulator_write_emulated(ss_base + sp - 4, &cs, 2, vcpu) != X86EMUL_CONTINUE ||
1669 emulator_write_emulated(ss_base + sp - 6, &ip, 2, vcpu) != X86EMUL_CONTINUE) {
1670 vcpu_printf(vcpu, "%s: write guest err\n", __FUNCTION__);
1674 vmcs_writel(GUEST_RFLAGS, flags &
1675 ~( X86_EFLAGS_IF | X86_EFLAGS_AC | X86_EFLAGS_TF));
1676 vmcs_write16(GUEST_CS_SELECTOR, ent[1]) ;
1677 vmcs_writel(GUEST_CS_BASE, ent[1] << 4);
1678 vmcs_writel(GUEST_RIP, ent[0]);
1679 vmcs_writel(GUEST_RSP, (vmcs_readl(GUEST_RSP) & ~0xffff) | (sp - 6));
1682 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1684 if (vcpu->rmode.active) {
1685 inject_rmode_irq(vcpu, irq);
1688 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1689 irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1692 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1694 int word_index = __ffs(vcpu->irq_summary);
1695 int bit_index = __ffs(vcpu->irq_pending[word_index]);
1696 int irq = word_index * BITS_PER_LONG + bit_index;
1698 clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1699 if (!vcpu->irq_pending[word_index])
1700 clear_bit(word_index, &vcpu->irq_summary);
1701 vmx_inject_irq(vcpu, irq);
1705 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1706 struct kvm_run *kvm_run)
1708 u32 cpu_based_vm_exec_control;
1710 vcpu->interrupt_window_open =
1711 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1712 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1714 if (vcpu->interrupt_window_open &&
1715 vcpu->irq_summary &&
1716 !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1718 * If interrupts enabled, and not blocked by sti or mov ss. Good.
1720 kvm_do_inject_irq(vcpu);
1722 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1723 if (!vcpu->interrupt_window_open &&
1724 (vcpu->irq_summary || kvm_run->request_interrupt_window))
1726 * Interrupts blocked. Wait for unblock.
1728 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1730 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1731 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1734 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1736 struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1738 set_debugreg(dbg->bp[0], 0);
1739 set_debugreg(dbg->bp[1], 1);
1740 set_debugreg(dbg->bp[2], 2);
1741 set_debugreg(dbg->bp[3], 3);
1743 if (dbg->singlestep) {
1744 unsigned long flags;
1746 flags = vmcs_readl(GUEST_RFLAGS);
1747 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1748 vmcs_writel(GUEST_RFLAGS, flags);
1752 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1753 int vec, u32 err_code)
1755 if (!vcpu->rmode.active)
1759 * Instruction with address size override prefix opcode 0x67
1760 * Cause the #SS fault with 0 error code in VM86 mode.
1762 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1763 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1768 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1770 u32 intr_info, error_code;
1771 unsigned long cr2, rip;
1773 enum emulation_result er;
1776 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
1777 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1779 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1780 !is_page_fault(intr_info)) {
1781 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1782 "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1785 if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1786 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1787 set_bit(irq, vcpu->irq_pending);
1788 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1791 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1792 return 1; /* already handled by vmx_vcpu_run() */
1794 if (is_no_device(intr_info)) {
1795 vmx_fpu_activate(vcpu);
1799 if (is_invalid_opcode(intr_info)) {
1800 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1801 if (er != EMULATE_DONE)
1802 vmx_inject_ud(vcpu);
1808 rip = vmcs_readl(GUEST_RIP);
1809 if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1810 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1811 if (is_page_fault(intr_info)) {
1812 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1814 mutex_lock(&vcpu->kvm->lock);
1815 r = kvm_mmu_page_fault(vcpu, cr2, error_code);
1817 mutex_unlock(&vcpu->kvm->lock);
1821 mutex_unlock(&vcpu->kvm->lock);
1825 er = emulate_instruction(vcpu, kvm_run, cr2, error_code, 0);
1826 mutex_unlock(&vcpu->kvm->lock);
1831 case EMULATE_DO_MMIO:
1832 ++vcpu->stat.mmio_exits;
1835 kvm_report_emulation_failure(vcpu, "pagetable");
1842 if (vcpu->rmode.active &&
1843 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1845 if (vcpu->halt_request) {
1846 vcpu->halt_request = 0;
1847 return kvm_emulate_halt(vcpu);
1852 if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) == (INTR_TYPE_EXCEPTION | 1)) {
1853 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1856 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1857 kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1858 kvm_run->ex.error_code = error_code;
1862 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1863 struct kvm_run *kvm_run)
1865 ++vcpu->stat.irq_exits;
1869 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1871 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1875 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1877 unsigned long exit_qualification;
1878 int size, down, in, string, rep;
1881 ++vcpu->stat.io_exits;
1882 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1883 string = (exit_qualification & 16) != 0;
1886 if (emulate_instruction(vcpu,
1887 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1892 size = (exit_qualification & 7) + 1;
1893 in = (exit_qualification & 8) != 0;
1894 down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1895 rep = (exit_qualification & 32) != 0;
1896 port = exit_qualification >> 16;
1898 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1902 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1905 * Patch in the VMCALL instruction:
1907 hypercall[0] = 0x0f;
1908 hypercall[1] = 0x01;
1909 hypercall[2] = 0xc1;
1912 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1914 unsigned long exit_qualification;
1918 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1919 cr = exit_qualification & 15;
1920 reg = (exit_qualification >> 8) & 15;
1921 switch ((exit_qualification >> 4) & 3) {
1922 case 0: /* mov to cr */
1925 vcpu_load_rsp_rip(vcpu);
1926 set_cr0(vcpu, vcpu->regs[reg]);
1927 skip_emulated_instruction(vcpu);
1930 vcpu_load_rsp_rip(vcpu);
1931 set_cr3(vcpu, vcpu->regs[reg]);
1932 skip_emulated_instruction(vcpu);
1935 vcpu_load_rsp_rip(vcpu);
1936 set_cr4(vcpu, vcpu->regs[reg]);
1937 skip_emulated_instruction(vcpu);
1940 vcpu_load_rsp_rip(vcpu);
1941 set_cr8(vcpu, vcpu->regs[reg]);
1942 skip_emulated_instruction(vcpu);
1943 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1948 vcpu_load_rsp_rip(vcpu);
1949 vmx_fpu_deactivate(vcpu);
1950 vcpu->cr0 &= ~X86_CR0_TS;
1951 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1952 vmx_fpu_activate(vcpu);
1953 skip_emulated_instruction(vcpu);
1955 case 1: /*mov from cr*/
1958 vcpu_load_rsp_rip(vcpu);
1959 vcpu->regs[reg] = vcpu->cr3;
1960 vcpu_put_rsp_rip(vcpu);
1961 skip_emulated_instruction(vcpu);
1964 vcpu_load_rsp_rip(vcpu);
1965 vcpu->regs[reg] = get_cr8(vcpu);
1966 vcpu_put_rsp_rip(vcpu);
1967 skip_emulated_instruction(vcpu);
1972 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
1974 skip_emulated_instruction(vcpu);
1979 kvm_run->exit_reason = 0;
1980 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
1981 (int)(exit_qualification >> 4) & 3, cr);
1985 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1987 unsigned long exit_qualification;
1992 * FIXME: this code assumes the host is debugging the guest.
1993 * need to deal with guest debugging itself too.
1995 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1996 dr = exit_qualification & 7;
1997 reg = (exit_qualification >> 8) & 15;
1998 vcpu_load_rsp_rip(vcpu);
1999 if (exit_qualification & 16) {
2011 vcpu->regs[reg] = val;
2015 vcpu_put_rsp_rip(vcpu);
2016 skip_emulated_instruction(vcpu);
2020 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2022 kvm_emulate_cpuid(vcpu);
2026 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2028 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2031 if (vmx_get_msr(vcpu, ecx, &data)) {
2032 vmx_inject_gp(vcpu, 0);
2036 /* FIXME: handling of bits 32:63 of rax, rdx */
2037 vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2038 vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2039 skip_emulated_instruction(vcpu);
2043 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2045 u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2046 u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2047 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2049 if (vmx_set_msr(vcpu, ecx, data) != 0) {
2050 vmx_inject_gp(vcpu, 0);
2054 skip_emulated_instruction(vcpu);
2058 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2059 struct kvm_run *kvm_run)
2064 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2065 struct kvm_run *kvm_run)
2067 u32 cpu_based_vm_exec_control;
2069 /* clear pending irq */
2070 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2071 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2072 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2074 * If the user space waits to inject interrupts, exit as soon as
2077 if (kvm_run->request_interrupt_window &&
2078 !vcpu->irq_summary) {
2079 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2080 ++vcpu->stat.irq_window_exits;
2086 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2088 skip_emulated_instruction(vcpu);
2089 return kvm_emulate_halt(vcpu);
2092 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2094 skip_emulated_instruction(vcpu);
2095 kvm_emulate_hypercall(vcpu);
2100 * The exit handlers return 1 if the exit was handled fully and guest execution
2101 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
2102 * to be done to userspace and return 0.
2104 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2105 struct kvm_run *kvm_run) = {
2106 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
2107 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
2108 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
2109 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
2110 [EXIT_REASON_CR_ACCESS] = handle_cr,
2111 [EXIT_REASON_DR_ACCESS] = handle_dr,
2112 [EXIT_REASON_CPUID] = handle_cpuid,
2113 [EXIT_REASON_MSR_READ] = handle_rdmsr,
2114 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
2115 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
2116 [EXIT_REASON_HLT] = handle_halt,
2117 [EXIT_REASON_VMCALL] = handle_vmcall,
2118 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold
2121 static const int kvm_vmx_max_exit_handlers =
2122 ARRAY_SIZE(kvm_vmx_exit_handlers);
2125 * The guest has exited. See if we can fix it or if we need userspace
2128 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2130 u32 vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2131 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2132 struct vcpu_vmx *vmx = to_vmx(vcpu);
2134 if (unlikely(vmx->fail)) {
2135 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2136 kvm_run->fail_entry.hardware_entry_failure_reason
2137 = vmcs_read32(VM_INSTRUCTION_ERROR);
2141 if ( (vectoring_info & VECTORING_INFO_VALID_MASK) &&
2142 exit_reason != EXIT_REASON_EXCEPTION_NMI )
2143 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2144 "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2145 if (exit_reason < kvm_vmx_max_exit_handlers
2146 && kvm_vmx_exit_handlers[exit_reason])
2147 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2149 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2150 kvm_run->hw.hardware_exit_reason = exit_reason;
2155 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2159 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2163 if (!vm_need_tpr_shadow(vcpu->kvm))
2166 if (!kvm_lapic_enabled(vcpu) ||
2167 ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2168 vmcs_write32(TPR_THRESHOLD, 0);
2172 tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2173 vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2176 static void enable_irq_window(struct kvm_vcpu *vcpu)
2178 u32 cpu_based_vm_exec_control;
2180 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2181 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2182 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2185 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2187 u32 idtv_info_field, intr_info_field;
2188 int has_ext_irq, interrupt_window_open;
2191 kvm_inject_pending_timer_irqs(vcpu);
2192 update_tpr_threshold(vcpu);
2194 has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2195 intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2196 idtv_info_field = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2197 if (intr_info_field & INTR_INFO_VALID_MASK) {
2198 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2199 /* TODO: fault when IDT_Vectoring */
2200 printk(KERN_ERR "Fault when IDT_Vectoring\n");
2203 enable_irq_window(vcpu);
2206 if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2207 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2208 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2209 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2211 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2212 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2213 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2214 if (unlikely(has_ext_irq))
2215 enable_irq_window(vcpu);
2220 interrupt_window_open =
2221 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2222 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2223 if (interrupt_window_open) {
2224 vector = kvm_cpu_get_interrupt(vcpu);
2225 vmx_inject_irq(vcpu, vector);
2226 kvm_timer_intr_post(vcpu, vector);
2228 enable_irq_window(vcpu);
2231 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2233 struct vcpu_vmx *vmx = to_vmx(vcpu);
2237 * Loading guest fpu may have cleared host cr0.ts
2239 vmcs_writel(HOST_CR0, read_cr0());
2242 /* Store host registers */
2243 #ifdef CONFIG_X86_64
2244 "push %%rax; push %%rbx; push %%rdx;"
2245 "push %%rsi; push %%rdi; push %%rbp;"
2246 "push %%r8; push %%r9; push %%r10; push %%r11;"
2247 "push %%r12; push %%r13; push %%r14; push %%r15;"
2249 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2251 "pusha; push %%ecx \n\t"
2252 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2254 /* Check if vmlaunch of vmresume is needed */
2256 /* Load guest registers. Don't clobber flags. */
2257 #ifdef CONFIG_X86_64
2258 "mov %c[cr2](%3), %%rax \n\t"
2259 "mov %%rax, %%cr2 \n\t"
2260 "mov %c[rax](%3), %%rax \n\t"
2261 "mov %c[rbx](%3), %%rbx \n\t"
2262 "mov %c[rdx](%3), %%rdx \n\t"
2263 "mov %c[rsi](%3), %%rsi \n\t"
2264 "mov %c[rdi](%3), %%rdi \n\t"
2265 "mov %c[rbp](%3), %%rbp \n\t"
2266 "mov %c[r8](%3), %%r8 \n\t"
2267 "mov %c[r9](%3), %%r9 \n\t"
2268 "mov %c[r10](%3), %%r10 \n\t"
2269 "mov %c[r11](%3), %%r11 \n\t"
2270 "mov %c[r12](%3), %%r12 \n\t"
2271 "mov %c[r13](%3), %%r13 \n\t"
2272 "mov %c[r14](%3), %%r14 \n\t"
2273 "mov %c[r15](%3), %%r15 \n\t"
2274 "mov %c[rcx](%3), %%rcx \n\t" /* kills %3 (rcx) */
2276 "mov %c[cr2](%3), %%eax \n\t"
2277 "mov %%eax, %%cr2 \n\t"
2278 "mov %c[rax](%3), %%eax \n\t"
2279 "mov %c[rbx](%3), %%ebx \n\t"
2280 "mov %c[rdx](%3), %%edx \n\t"
2281 "mov %c[rsi](%3), %%esi \n\t"
2282 "mov %c[rdi](%3), %%edi \n\t"
2283 "mov %c[rbp](%3), %%ebp \n\t"
2284 "mov %c[rcx](%3), %%ecx \n\t" /* kills %3 (ecx) */
2286 /* Enter guest mode */
2287 "jne .Llaunched \n\t"
2288 ASM_VMX_VMLAUNCH "\n\t"
2289 "jmp .Lkvm_vmx_return \n\t"
2290 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2291 ".Lkvm_vmx_return: "
2292 /* Save guest registers, load host registers, keep flags */
2293 #ifdef CONFIG_X86_64
2294 "xchg %3, (%%rsp) \n\t"
2295 "mov %%rax, %c[rax](%3) \n\t"
2296 "mov %%rbx, %c[rbx](%3) \n\t"
2297 "pushq (%%rsp); popq %c[rcx](%3) \n\t"
2298 "mov %%rdx, %c[rdx](%3) \n\t"
2299 "mov %%rsi, %c[rsi](%3) \n\t"
2300 "mov %%rdi, %c[rdi](%3) \n\t"
2301 "mov %%rbp, %c[rbp](%3) \n\t"
2302 "mov %%r8, %c[r8](%3) \n\t"
2303 "mov %%r9, %c[r9](%3) \n\t"
2304 "mov %%r10, %c[r10](%3) \n\t"
2305 "mov %%r11, %c[r11](%3) \n\t"
2306 "mov %%r12, %c[r12](%3) \n\t"
2307 "mov %%r13, %c[r13](%3) \n\t"
2308 "mov %%r14, %c[r14](%3) \n\t"
2309 "mov %%r15, %c[r15](%3) \n\t"
2310 "mov %%cr2, %%rax \n\t"
2311 "mov %%rax, %c[cr2](%3) \n\t"
2312 "mov (%%rsp), %3 \n\t"
2314 "pop %%rcx; pop %%r15; pop %%r14; pop %%r13; pop %%r12;"
2315 "pop %%r11; pop %%r10; pop %%r9; pop %%r8;"
2316 "pop %%rbp; pop %%rdi; pop %%rsi;"
2317 "pop %%rdx; pop %%rbx; pop %%rax \n\t"
2319 "xchg %3, (%%esp) \n\t"
2320 "mov %%eax, %c[rax](%3) \n\t"
2321 "mov %%ebx, %c[rbx](%3) \n\t"
2322 "pushl (%%esp); popl %c[rcx](%3) \n\t"
2323 "mov %%edx, %c[rdx](%3) \n\t"
2324 "mov %%esi, %c[rsi](%3) \n\t"
2325 "mov %%edi, %c[rdi](%3) \n\t"
2326 "mov %%ebp, %c[rbp](%3) \n\t"
2327 "mov %%cr2, %%eax \n\t"
2328 "mov %%eax, %c[cr2](%3) \n\t"
2329 "mov (%%esp), %3 \n\t"
2331 "pop %%ecx; popa \n\t"
2335 : "r"(vmx->launched), "d"((unsigned long)HOST_RSP),
2337 [rax]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RAX])),
2338 [rbx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBX])),
2339 [rcx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RCX])),
2340 [rdx]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDX])),
2341 [rsi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RSI])),
2342 [rdi]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RDI])),
2343 [rbp]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_RBP])),
2344 #ifdef CONFIG_X86_64
2345 [r8 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R8 ])),
2346 [r9 ]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R9 ])),
2347 [r10]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R10])),
2348 [r11]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R11])),
2349 [r12]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R12])),
2350 [r13]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R13])),
2351 [r14]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R14])),
2352 [r15]"i"(offsetof(struct kvm_vcpu, regs[VCPU_REGS_R15])),
2354 [cr2]"i"(offsetof(struct kvm_vcpu, cr2))
2357 vcpu->interrupt_window_open = (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2359 asm ("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2362 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2364 /* We need to handle NMIs before interrupts are enabled */
2365 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2369 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2373 u32 vect_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2375 ++vcpu->stat.pf_guest;
2377 if (is_page_fault(vect_info)) {
2378 printk(KERN_DEBUG "inject_page_fault: "
2379 "double fault 0x%lx @ 0x%lx\n",
2380 addr, vmcs_readl(GUEST_RIP));
2381 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2382 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2384 INTR_TYPE_EXCEPTION |
2385 INTR_INFO_DELIEVER_CODE_MASK |
2386 INTR_INFO_VALID_MASK);
2390 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2391 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2393 INTR_TYPE_EXCEPTION |
2394 INTR_INFO_DELIEVER_CODE_MASK |
2395 INTR_INFO_VALID_MASK);
2399 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2401 struct vcpu_vmx *vmx = to_vmx(vcpu);
2404 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2405 free_vmcs(vmx->vmcs);
2410 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2412 struct vcpu_vmx *vmx = to_vmx(vcpu);
2414 vmx_free_vmcs(vcpu);
2415 kfree(vmx->host_msrs);
2416 kfree(vmx->guest_msrs);
2417 kvm_vcpu_uninit(vcpu);
2418 kmem_cache_free(kvm_vcpu_cache, vmx);
2421 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2424 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2428 return ERR_PTR(-ENOMEM);
2430 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2434 if (irqchip_in_kernel(kvm)) {
2435 err = kvm_create_lapic(&vmx->vcpu);
2440 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2441 if (!vmx->guest_msrs) {
2446 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2447 if (!vmx->host_msrs)
2448 goto free_guest_msrs;
2450 vmx->vmcs = alloc_vmcs();
2454 vmcs_clear(vmx->vmcs);
2457 vmx_vcpu_load(&vmx->vcpu, cpu);
2458 err = vmx_vcpu_setup(vmx);
2459 vmx_vcpu_put(&vmx->vcpu);
2467 free_vmcs(vmx->vmcs);
2469 kfree(vmx->host_msrs);
2471 kfree(vmx->guest_msrs);
2473 kvm_vcpu_uninit(&vmx->vcpu);
2475 kmem_cache_free(kvm_vcpu_cache, vmx);
2476 return ERR_PTR(err);
2479 static void __init vmx_check_processor_compat(void *rtn)
2481 struct vmcs_config vmcs_conf;
2484 if (setup_vmcs_config(&vmcs_conf) < 0)
2486 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2487 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2488 smp_processor_id());
2493 static struct kvm_x86_ops vmx_x86_ops = {
2494 .cpu_has_kvm_support = cpu_has_kvm_support,
2495 .disabled_by_bios = vmx_disabled_by_bios,
2496 .hardware_setup = hardware_setup,
2497 .hardware_unsetup = hardware_unsetup,
2498 .check_processor_compatibility = vmx_check_processor_compat,
2499 .hardware_enable = hardware_enable,
2500 .hardware_disable = hardware_disable,
2502 .vcpu_create = vmx_create_vcpu,
2503 .vcpu_free = vmx_free_vcpu,
2504 .vcpu_reset = vmx_vcpu_reset,
2506 .prepare_guest_switch = vmx_save_host_state,
2507 .vcpu_load = vmx_vcpu_load,
2508 .vcpu_put = vmx_vcpu_put,
2509 .vcpu_decache = vmx_vcpu_decache,
2511 .set_guest_debug = set_guest_debug,
2512 .guest_debug_pre = kvm_guest_debug_pre,
2513 .get_msr = vmx_get_msr,
2514 .set_msr = vmx_set_msr,
2515 .get_segment_base = vmx_get_segment_base,
2516 .get_segment = vmx_get_segment,
2517 .set_segment = vmx_set_segment,
2518 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2519 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2520 .set_cr0 = vmx_set_cr0,
2521 .set_cr3 = vmx_set_cr3,
2522 .set_cr4 = vmx_set_cr4,
2523 #ifdef CONFIG_X86_64
2524 .set_efer = vmx_set_efer,
2526 .get_idt = vmx_get_idt,
2527 .set_idt = vmx_set_idt,
2528 .get_gdt = vmx_get_gdt,
2529 .set_gdt = vmx_set_gdt,
2530 .cache_regs = vcpu_load_rsp_rip,
2531 .decache_regs = vcpu_put_rsp_rip,
2532 .get_rflags = vmx_get_rflags,
2533 .set_rflags = vmx_set_rflags,
2535 .tlb_flush = vmx_flush_tlb,
2536 .inject_page_fault = vmx_inject_page_fault,
2538 .inject_gp = vmx_inject_gp,
2540 .run = vmx_vcpu_run,
2541 .handle_exit = kvm_handle_exit,
2542 .skip_emulated_instruction = skip_emulated_instruction,
2543 .patch_hypercall = vmx_patch_hypercall,
2544 .get_irq = vmx_get_irq,
2545 .set_irq = vmx_inject_irq,
2546 .inject_pending_irq = vmx_intr_assist,
2547 .inject_pending_vectors = do_interrupt_requests,
2550 static int __init vmx_init(void)
2555 vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2556 if (!vmx_io_bitmap_a)
2559 vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2560 if (!vmx_io_bitmap_b) {
2566 * Allow direct access to the PC debug port (it is often used for I/O
2567 * delays, but the vmexits simply slow things down).
2569 iova = kmap(vmx_io_bitmap_a);
2570 memset(iova, 0xff, PAGE_SIZE);
2571 clear_bit(0x80, iova);
2572 kunmap(vmx_io_bitmap_a);
2574 iova = kmap(vmx_io_bitmap_b);
2575 memset(iova, 0xff, PAGE_SIZE);
2576 kunmap(vmx_io_bitmap_b);
2578 r = kvm_init_x86(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2582 if (bypass_guest_pf)
2583 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2588 __free_page(vmx_io_bitmap_b);
2590 __free_page(vmx_io_bitmap_a);
2594 static void __exit vmx_exit(void)
2596 __free_page(vmx_io_bitmap_b);
2597 __free_page(vmx_io_bitmap_a);
2602 module_init(vmx_init)
2603 module_exit(vmx_exit)