drivers/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "kvm.h"
  19 #include "x86.h"
  20 #include "x86_emulate.h"
  21 #include "irq.h"
  22 #include "vmx.h"
  23 #include "segment_descriptor.h"
  24
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31
  32 #include <asm/io.h>
  33 #include <asm/desc.h>
  34
  35 MODULE_AUTHOR("Qumranet");
  36 MODULE_LICENSE("GPL");
  37
  38 static int bypass_guest_pf = 1;
  39 module_param(bypass_guest_pf, bool, 0);
  40
  41 struct vmcs {
  42         u32 revision_id;
  43         u32 abort;
  44         char data[0];
  45 };
  46
  47 struct vcpu_vmx {
  48         struct kvm_vcpu       vcpu;
  49         int                   launched;
  50         u8                    fail;
  51         u32                   idt_vectoring_info;
  52         struct kvm_msr_entry *guest_msrs;
  53         struct kvm_msr_entry *host_msrs;
  54         int                   nmsrs;
  55         int                   save_nmsrs;
  56         int                   msr_offset_efer;
  57 #ifdef CONFIG_X86_64
  58         int                   msr_offset_kernel_gs_base;
  59 #endif
  60         struct vmcs          *vmcs;
  61         struct {
  62                 int           loaded;
  63                 u16           fs_sel, gs_sel, ldt_sel;
  64                 int           gs_ldt_reload_needed;
  65                 int           fs_reload_needed;
  66                 int           guest_efer_loaded;
  67         } host_state;
  68         struct {
  69                 struct {
  70                         bool pending;
  71                         u8 vector;
  72                         unsigned rip;
  73                 } irq;
  74         } rmode;
  75 };
  76
  77 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
  78 {
  79         return container_of(vcpu, struct vcpu_vmx, vcpu);
  80 }
  81
  82 static int init_rmode_tss(struct kvm *kvm);
  83
  84 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
  85 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
  86
  87 static struct page *vmx_io_bitmap_a;
  88 static struct page *vmx_io_bitmap_b;
  89
  90 static struct vmcs_config {
  91         int size;
  92         int order;
  93         u32 revision_id;
  94         u32 pin_based_exec_ctrl;
  95         u32 cpu_based_exec_ctrl;
  96         u32 cpu_based_2nd_exec_ctrl;
  97         u32 vmexit_ctrl;
  98         u32 vmentry_ctrl;
  99 } vmcs_config;
 100
 101 #define VMX_SEGMENT_FIELD(seg)                                  \
 102         [VCPU_SREG_##seg] = {                                   \
 103                 .selector = GUEST_##seg##_SELECTOR,             \
 104                 .base = GUEST_##seg##_BASE,                     \
 105                 .limit = GUEST_##seg##_LIMIT,                   \
 106                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 107         }
 108
 109 static struct kvm_vmx_segment_field {
 110         unsigned selector;
 111         unsigned base;
 112         unsigned limit;
 113         unsigned ar_bytes;
 114 } kvm_vmx_segment_fields[] = {
 115         VMX_SEGMENT_FIELD(CS),
 116         VMX_SEGMENT_FIELD(DS),
 117         VMX_SEGMENT_FIELD(ES),
 118         VMX_SEGMENT_FIELD(FS),
 119         VMX_SEGMENT_FIELD(GS),
 120         VMX_SEGMENT_FIELD(SS),
 121         VMX_SEGMENT_FIELD(TR),
 122         VMX_SEGMENT_FIELD(LDTR),
 123 };
 124
 125 /*
 126  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 127  * away by decrementing the array size.
 128  */
 129 static const u32 vmx_msr_index[] = {
 130 #ifdef CONFIG_X86_64
 131         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
 132 #endif
 133         MSR_EFER, MSR_K6_STAR,
 134 };
 135 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 136
 137 static void load_msrs(struct kvm_msr_entry *e, int n)
 138 {
 139         int i;
 140
 141         for (i = 0; i < n; ++i)
 142                 wrmsrl(e[i].index, e[i].data);
 143 }
 144
 145 static void save_msrs(struct kvm_msr_entry *e, int n)
 146 {
 147         int i;
 148
 149         for (i = 0; i < n; ++i)
 150                 rdmsrl(e[i].index, e[i].data);
 151 }
 152
 153 static inline int is_page_fault(u32 intr_info)
 154 {
 155         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 156                              INTR_INFO_VALID_MASK)) ==
 157                 (INTR_TYPE_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 158 }
 159
 160 static inline int is_no_device(u32 intr_info)
 161 {
 162         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 163                              INTR_INFO_VALID_MASK)) ==
 164                 (INTR_TYPE_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 165 }
 166
 167 static inline int is_invalid_opcode(u32 intr_info)
 168 {
 169         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 170                              INTR_INFO_VALID_MASK)) ==
 171                 (INTR_TYPE_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 172 }
 173
 174 static inline int is_external_interrupt(u32 intr_info)
 175 {
 176         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 177                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 178 }
 179
 180 static inline int cpu_has_vmx_tpr_shadow(void)
 181 {
 182         return (vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW);
 183 }
 184
 185 static inline int vm_need_tpr_shadow(struct kvm *kvm)
 186 {
 187         return ((cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm)));
 188 }
 189
 190 static inline int cpu_has_secondary_exec_ctrls(void)
 191 {
 192         return (vmcs_config.cpu_based_exec_ctrl &
 193                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS);
 194 }
 195
 196 static inline int vm_need_secondary_exec_ctrls(struct kvm *kvm)
 197 {
 198         return ((cpu_has_secondary_exec_ctrls()) && (irqchip_in_kernel(kvm)));
 199 }
 200
 201 static inline int cpu_has_vmx_virtualize_apic_accesses(void)
 202 {
 203         return (vmcs_config.cpu_based_2nd_exec_ctrl &
 204                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
 205 }
 206
 207 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
 208 {
 209         return ((cpu_has_vmx_virtualize_apic_accesses()) &&
 210                 (irqchip_in_kernel(kvm)));
 211 }
 212
 213 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 214 {
 215         int i;
 216
 217         for (i = 0; i < vmx->nmsrs; ++i)
 218                 if (vmx->guest_msrs[i].index == msr)
 219                         return i;
 220         return -1;
 221 }
 222
 223 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 224 {
 225         int i;
 226
 227         i = __find_msr_index(vmx, msr);
 228         if (i >= 0)
 229                 return &vmx->guest_msrs[i];
 230         return NULL;
 231 }
 232
 233 static void vmcs_clear(struct vmcs *vmcs)
 234 {
 235         u64 phys_addr = __pa(vmcs);
 236         u8 error;
 237
 238         asm volatile (ASM_VMX_VMCLEAR_RAX "; setna %0"
 239                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 240                       : "cc", "memory");
 241         if (error)
 242                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 243                        vmcs, phys_addr);
 244 }
 245
 246 static void __vcpu_clear(void *arg)
 247 {
 248         struct vcpu_vmx *vmx = arg;
 249         int cpu = raw_smp_processor_id();
 250
 251         if (vmx->vcpu.cpu == cpu)
 252                 vmcs_clear(vmx->vmcs);
 253         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 254                 per_cpu(current_vmcs, cpu) = NULL;
 255         rdtscll(vmx->vcpu.host_tsc);
 256 }
 257
 258 static void vcpu_clear(struct vcpu_vmx *vmx)
 259 {
 260         if (vmx->vcpu.cpu == -1)
 261                 return;
 262         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 0, 1);
 263         vmx->launched = 0;
 264 }
 265
 266 static unsigned long vmcs_readl(unsigned long field)
 267 {
 268         unsigned long value;
 269
 270         asm volatile (ASM_VMX_VMREAD_RDX_RAX
 271                       : "=a"(value) : "d"(field) : "cc");
 272         return value;
 273 }
 274
 275 static u16 vmcs_read16(unsigned long field)
 276 {
 277         return vmcs_readl(field);
 278 }
 279
 280 static u32 vmcs_read32(unsigned long field)
 281 {
 282         return vmcs_readl(field);
 283 }
 284
 285 static u64 vmcs_read64(unsigned long field)
 286 {
 287 #ifdef CONFIG_X86_64
 288         return vmcs_readl(field);
 289 #else
 290         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 291 #endif
 292 }
 293
 294 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 295 {
 296         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 297                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 298         dump_stack();
 299 }
 300
 301 static void vmcs_writel(unsigned long field, unsigned long value)
 302 {
 303         u8 error;
 304
 305         asm volatile (ASM_VMX_VMWRITE_RAX_RDX "; setna %0"
 306                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 307         if (unlikely(error))
 308                 vmwrite_error(field, value);
 309 }
 310
 311 static void vmcs_write16(unsigned long field, u16 value)
 312 {
 313         vmcs_writel(field, value);
 314 }
 315
 316 static void vmcs_write32(unsigned long field, u32 value)
 317 {
 318         vmcs_writel(field, value);
 319 }
 320
 321 static void vmcs_write64(unsigned long field, u64 value)
 322 {
 323 #ifdef CONFIG_X86_64
 324         vmcs_writel(field, value);
 325 #else
 326         vmcs_writel(field, value);
 327         asm volatile ("");
 328         vmcs_writel(field+1, value >> 32);
 329 #endif
 330 }
 331
 332 static void vmcs_clear_bits(unsigned long field, u32 mask)
 333 {
 334         vmcs_writel(field, vmcs_readl(field) & ~mask);
 335 }
 336
 337 static void vmcs_set_bits(unsigned long field, u32 mask)
 338 {
 339         vmcs_writel(field, vmcs_readl(field) | mask);
 340 }
 341
 342 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 343 {
 344         u32 eb;
 345
 346         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR);
 347         if (!vcpu->fpu_active)
 348                 eb |= 1u << NM_VECTOR;
 349         if (vcpu->guest_debug.enabled)
 350                 eb |= 1u << 1;
 351         if (vcpu->rmode.active)
 352                 eb = ~0;
 353         vmcs_write32(EXCEPTION_BITMAP, eb);
 354 }
 355
 356 static void reload_tss(void)
 357 {
 358 #ifndef CONFIG_X86_64
 359
 360         /*
 361          * VT restores TR but not its size.  Useless.
 362          */
 363         struct descriptor_table gdt;
 364         struct segment_descriptor *descs;
 365
 366         get_gdt(&gdt);
 367         descs = (void *)gdt.base;
 368         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 369         load_TR_desc();
 370 #endif
 371 }
 372
 373 static void load_transition_efer(struct vcpu_vmx *vmx)
 374 {
 375         int efer_offset = vmx->msr_offset_efer;
 376         u64 host_efer = vmx->host_msrs[efer_offset].data;
 377         u64 guest_efer = vmx->guest_msrs[efer_offset].data;
 378         u64 ignore_bits;
 379
 380         if (efer_offset < 0)
 381                 return;
 382         /*
 383          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 384          * outside long mode
 385          */
 386         ignore_bits = EFER_NX | EFER_SCE;
 387 #ifdef CONFIG_X86_64
 388         ignore_bits |= EFER_LMA | EFER_LME;
 389         /* SCE is meaningful only in long mode on Intel */
 390         if (guest_efer & EFER_LMA)
 391                 ignore_bits &= ~(u64)EFER_SCE;
 392 #endif
 393         if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
 394                 return;
 395
 396         vmx->host_state.guest_efer_loaded = 1;
 397         guest_efer &= ~ignore_bits;
 398         guest_efer |= host_efer & ignore_bits;
 399         wrmsrl(MSR_EFER, guest_efer);
 400         vmx->vcpu.stat.efer_reload++;
 401 }
 402
 403 static void reload_host_efer(struct vcpu_vmx *vmx)
 404 {
 405         if (vmx->host_state.guest_efer_loaded) {
 406                 vmx->host_state.guest_efer_loaded = 0;
 407                 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
 408         }
 409 }
 410
 411 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 412 {
 413         struct vcpu_vmx *vmx = to_vmx(vcpu);
 414
 415         if (vmx->host_state.loaded)
 416                 return;
 417
 418         vmx->host_state.loaded = 1;
 419         /*
 420          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 421          * allow segment selectors with cpl > 0 or ti == 1.
 422          */
 423         vmx->host_state.ldt_sel = read_ldt();
 424         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 425         vmx->host_state.fs_sel = read_fs();
 426         if (!(vmx->host_state.fs_sel & 7)) {
 427                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 428                 vmx->host_state.fs_reload_needed = 0;
 429         } else {
 430                 vmcs_write16(HOST_FS_SELECTOR, 0);
 431                 vmx->host_state.fs_reload_needed = 1;
 432         }
 433         vmx->host_state.gs_sel = read_gs();
 434         if (!(vmx->host_state.gs_sel & 7))
 435                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 436         else {
 437                 vmcs_write16(HOST_GS_SELECTOR, 0);
 438                 vmx->host_state.gs_ldt_reload_needed = 1;
 439         }
 440
 441 #ifdef CONFIG_X86_64
 442         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 443         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 444 #else
 445         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 446         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 447 #endif
 448
 449 #ifdef CONFIG_X86_64
 450         if (is_long_mode(&vmx->vcpu))
 451                 save_msrs(vmx->host_msrs +
 452                           vmx->msr_offset_kernel_gs_base, 1);
 453
 454 #endif
 455         load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 456         load_transition_efer(vmx);
 457 }
 458
 459 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 460 {
 461         unsigned long flags;
 462
 463         if (!vmx->host_state.loaded)
 464                 return;
 465
 466         ++vmx->vcpu.stat.host_state_reload;
 467         vmx->host_state.loaded = 0;
 468         if (vmx->host_state.fs_reload_needed)
 469                 load_fs(vmx->host_state.fs_sel);
 470         if (vmx->host_state.gs_ldt_reload_needed) {
 471                 load_ldt(vmx->host_state.ldt_sel);
 472                 /*
 473                  * If we have to reload gs, we must take care to
 474                  * preserve our gs base.
 475                  */
 476                 local_irq_save(flags);
 477                 load_gs(vmx->host_state.gs_sel);
 478 #ifdef CONFIG_X86_64
 479                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 480 #endif
 481                 local_irq_restore(flags);
 482         }
 483         reload_tss();
 484         save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 485         load_msrs(vmx->host_msrs, vmx->save_nmsrs);
 486         reload_host_efer(vmx);
 487 }
 488
 489 /*
 490  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 491  * vcpu mutex is already taken.
 492  */
 493 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 494 {
 495         struct vcpu_vmx *vmx = to_vmx(vcpu);
 496         u64 phys_addr = __pa(vmx->vmcs);
 497         u64 tsc_this, delta;
 498
 499         if (vcpu->cpu != cpu) {
 500                 vcpu_clear(vmx);
 501                 kvm_migrate_apic_timer(vcpu);
 502         }
 503
 504         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 505                 u8 error;
 506
 507                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 508                 asm volatile (ASM_VMX_VMPTRLD_RAX "; setna %0"
 509                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 510                               : "cc");
 511                 if (error)
 512                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 513                                vmx->vmcs, phys_addr);
 514         }
 515
 516         if (vcpu->cpu != cpu) {
 517                 struct descriptor_table dt;
 518                 unsigned long sysenter_esp;
 519
 520                 vcpu->cpu = cpu;
 521                 /*
 522                  * Linux uses per-cpu TSS and GDT, so set these when switching
 523                  * processors.
 524                  */
 525                 vmcs_writel(HOST_TR_BASE, read_tr_base()); /* 22.2.4 */
 526                 get_gdt(&dt);
 527                 vmcs_writel(HOST_GDTR_BASE, dt.base);   /* 22.2.4 */
 528
 529                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 530                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 531
 532                 /*
 533                  * Make sure the time stamp counter is monotonous.
 534                  */
 535                 rdtscll(tsc_this);
 536                 delta = vcpu->host_tsc - tsc_this;
 537                 vmcs_write64(TSC_OFFSET, vmcs_read64(TSC_OFFSET) + delta);
 538         }
 539 }
 540
 541 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 542 {
 543         vmx_load_host_state(to_vmx(vcpu));
 544 }
 545
 546 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 547 {
 548         if (vcpu->fpu_active)
 549                 return;
 550         vcpu->fpu_active = 1;
 551         vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
 552         if (vcpu->cr0 & X86_CR0_TS)
 553                 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 554         update_exception_bitmap(vcpu);
 555 }
 556
 557 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 558 {
 559         if (!vcpu->fpu_active)
 560                 return;
 561         vcpu->fpu_active = 0;
 562         vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
 563         update_exception_bitmap(vcpu);
 564 }
 565
 566 static void vmx_vcpu_decache(struct kvm_vcpu *vcpu)
 567 {
 568         vcpu_clear(to_vmx(vcpu));
 569 }
 570
 571 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 572 {
 573         return vmcs_readl(GUEST_RFLAGS);
 574 }
 575
 576 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 577 {
 578         if (vcpu->rmode.active)
 579                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 580         vmcs_writel(GUEST_RFLAGS, rflags);
 581 }
 582
 583 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 584 {
 585         unsigned long rip;
 586         u32 interruptibility;
 587
 588         rip = vmcs_readl(GUEST_RIP);
 589         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 590         vmcs_writel(GUEST_RIP, rip);
 591
 592         /*
 593          * We emulated an instruction, so temporary interrupt blocking
 594          * should be removed, if set.
 595          */
 596         interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 597         if (interruptibility & 3)
 598                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
 599                              interruptibility & ~3);
 600         vcpu->interrupt_window_open = 1;
 601 }
 602
 603 static void vmx_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 604 {
 605         printk(KERN_DEBUG "inject_general_protection: rip 0x%lx\n",
 606                vmcs_readl(GUEST_RIP));
 607         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 608         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 609                      GP_VECTOR |
 610                      INTR_TYPE_EXCEPTION |
 611                      INTR_INFO_DELIEVER_CODE_MASK |
 612                      INTR_INFO_VALID_MASK);
 613 }
 614
 615 static void vmx_inject_ud(struct kvm_vcpu *vcpu)
 616 {
 617         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
 618                      UD_VECTOR |
 619                      INTR_TYPE_EXCEPTION |
 620                      INTR_INFO_VALID_MASK);
 621 }
 622
 623 /*
 624  * Swap MSR entry in host/guest MSR entry array.
 625  */
 626 #ifdef CONFIG_X86_64
 627 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
 628 {
 629         struct kvm_msr_entry tmp;
 630
 631         tmp = vmx->guest_msrs[to];
 632         vmx->guest_msrs[to] = vmx->guest_msrs[from];
 633         vmx->guest_msrs[from] = tmp;
 634         tmp = vmx->host_msrs[to];
 635         vmx->host_msrs[to] = vmx->host_msrs[from];
 636         vmx->host_msrs[from] = tmp;
 637 }
 638 #endif
 639
 640 /*
 641  * Set up the vmcs to automatically save and restore system
 642  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
 643  * mode, as fiddling with msrs is very expensive.
 644  */
 645 static void setup_msrs(struct vcpu_vmx *vmx)
 646 {
 647         int save_nmsrs;
 648
 649         save_nmsrs = 0;
 650 #ifdef CONFIG_X86_64
 651         if (is_long_mode(&vmx->vcpu)) {
 652                 int index;
 653
 654                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
 655                 if (index >= 0)
 656                         move_msr_up(vmx, index, save_nmsrs++);
 657                 index = __find_msr_index(vmx, MSR_LSTAR);
 658                 if (index >= 0)
 659                         move_msr_up(vmx, index, save_nmsrs++);
 660                 index = __find_msr_index(vmx, MSR_CSTAR);
 661                 if (index >= 0)
 662                         move_msr_up(vmx, index, save_nmsrs++);
 663                 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 664                 if (index >= 0)
 665                         move_msr_up(vmx, index, save_nmsrs++);
 666                 /*
 667                  * MSR_K6_STAR is only needed on long mode guests, and only
 668                  * if efer.sce is enabled.
 669                  */
 670                 index = __find_msr_index(vmx, MSR_K6_STAR);
 671                 if ((index >= 0) && (vmx->vcpu.shadow_efer & EFER_SCE))
 672                         move_msr_up(vmx, index, save_nmsrs++);
 673         }
 674 #endif
 675         vmx->save_nmsrs = save_nmsrs;
 676
 677 #ifdef CONFIG_X86_64
 678         vmx->msr_offset_kernel_gs_base =
 679                 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
 680 #endif
 681         vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
 682 }
 683
 684 /*
 685  * reads and returns guest's timestamp counter "register"
 686  * guest_tsc = host_tsc + tsc_offset    -- 21.3
 687  */
 688 static u64 guest_read_tsc(void)
 689 {
 690         u64 host_tsc, tsc_offset;
 691
 692         rdtscll(host_tsc);
 693         tsc_offset = vmcs_read64(TSC_OFFSET);
 694         return host_tsc + tsc_offset;
 695 }
 696
 697 /*
 698  * writes 'guest_tsc' into guest's timestamp counter "register"
 699  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
 700  */
 701 static void guest_write_tsc(u64 guest_tsc)
 702 {
 703         u64 host_tsc;
 704
 705         rdtscll(host_tsc);
 706         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
 707 }
 708
 709 /*
 710  * Reads an msr value (of 'msr_index') into 'pdata'.
 711  * Returns 0 on success, non-0 otherwise.
 712  * Assumes vcpu_load() was already called.
 713  */
 714 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
 715 {
 716         u64 data;
 717         struct kvm_msr_entry *msr;
 718
 719         if (!pdata) {
 720                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
 721                 return -EINVAL;
 722         }
 723
 724         switch (msr_index) {
 725 #ifdef CONFIG_X86_64
 726         case MSR_FS_BASE:
 727                 data = vmcs_readl(GUEST_FS_BASE);
 728                 break;
 729         case MSR_GS_BASE:
 730                 data = vmcs_readl(GUEST_GS_BASE);
 731                 break;
 732         case MSR_EFER:
 733                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 734 #endif
 735         case MSR_IA32_TIME_STAMP_COUNTER:
 736                 data = guest_read_tsc();
 737                 break;
 738         case MSR_IA32_SYSENTER_CS:
 739                 data = vmcs_read32(GUEST_SYSENTER_CS);
 740                 break;
 741         case MSR_IA32_SYSENTER_EIP:
 742                 data = vmcs_readl(GUEST_SYSENTER_EIP);
 743                 break;
 744         case MSR_IA32_SYSENTER_ESP:
 745                 data = vmcs_readl(GUEST_SYSENTER_ESP);
 746                 break;
 747         default:
 748                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
 749                 if (msr) {
 750                         data = msr->data;
 751                         break;
 752                 }
 753                 return kvm_get_msr_common(vcpu, msr_index, pdata);
 754         }
 755
 756         *pdata = data;
 757         return 0;
 758 }
 759
 760 /*
 761  * Writes msr value into into the appropriate "register".
 762  * Returns 0 on success, non-0 otherwise.
 763  * Assumes vcpu_load() was already called.
 764  */
 765 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
 766 {
 767         struct vcpu_vmx *vmx = to_vmx(vcpu);
 768         struct kvm_msr_entry *msr;
 769         int ret = 0;
 770
 771         switch (msr_index) {
 772 #ifdef CONFIG_X86_64
 773         case MSR_EFER:
 774                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 775                 if (vmx->host_state.loaded) {
 776                         reload_host_efer(vmx);
 777                         load_transition_efer(vmx);
 778                 }
 779                 break;
 780         case MSR_FS_BASE:
 781                 vmcs_writel(GUEST_FS_BASE, data);
 782                 break;
 783         case MSR_GS_BASE:
 784                 vmcs_writel(GUEST_GS_BASE, data);
 785                 break;
 786 #endif
 787         case MSR_IA32_SYSENTER_CS:
 788                 vmcs_write32(GUEST_SYSENTER_CS, data);
 789                 break;
 790         case MSR_IA32_SYSENTER_EIP:
 791                 vmcs_writel(GUEST_SYSENTER_EIP, data);
 792                 break;
 793         case MSR_IA32_SYSENTER_ESP:
 794                 vmcs_writel(GUEST_SYSENTER_ESP, data);
 795                 break;
 796         case MSR_IA32_TIME_STAMP_COUNTER:
 797                 guest_write_tsc(data);
 798                 break;
 799         default:
 800                 msr = find_msr_entry(vmx, msr_index);
 801                 if (msr) {
 802                         msr->data = data;
 803                         if (vmx->host_state.loaded)
 804                                 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
 805                         break;
 806                 }
 807                 ret = kvm_set_msr_common(vcpu, msr_index, data);
 808         }
 809
 810         return ret;
 811 }
 812
 813 /*
 814  * Sync the rsp and rip registers into the vcpu structure.  This allows
 815  * registers to be accessed by indexing vcpu->regs.
 816  */
 817 static void vcpu_load_rsp_rip(struct kvm_vcpu *vcpu)
 818 {
 819         vcpu->regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
 820         vcpu->rip = vmcs_readl(GUEST_RIP);
 821 }
 822
 823 /*
 824  * Syncs rsp and rip back into the vmcs.  Should be called after possible
 825  * modification.
 826  */
 827 static void vcpu_put_rsp_rip(struct kvm_vcpu *vcpu)
 828 {
 829         vmcs_writel(GUEST_RSP, vcpu->regs[VCPU_REGS_RSP]);
 830         vmcs_writel(GUEST_RIP, vcpu->rip);
 831 }
 832
 833 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 834 {
 835         unsigned long dr7 = 0x400;
 836         int old_singlestep;
 837
 838         old_singlestep = vcpu->guest_debug.singlestep;
 839
 840         vcpu->guest_debug.enabled = dbg->enabled;
 841         if (vcpu->guest_debug.enabled) {
 842                 int i;
 843
 844                 dr7 |= 0x200;  /* exact */
 845                 for (i = 0; i < 4; ++i) {
 846                         if (!dbg->breakpoints[i].enabled)
 847                                 continue;
 848                         vcpu->guest_debug.bp[i] = dbg->breakpoints[i].address;
 849                         dr7 |= 2 << (i*2);    /* global enable */
 850                         dr7 |= 0 << (i*4+16); /* execution breakpoint */
 851                 }
 852
 853                 vcpu->guest_debug.singlestep = dbg->singlestep;
 854         } else
 855                 vcpu->guest_debug.singlestep = 0;
 856
 857         if (old_singlestep && !vcpu->guest_debug.singlestep) {
 858                 unsigned long flags;
 859
 860                 flags = vmcs_readl(GUEST_RFLAGS);
 861                 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
 862                 vmcs_writel(GUEST_RFLAGS, flags);
 863         }
 864
 865         update_exception_bitmap(vcpu);
 866         vmcs_writel(GUEST_DR7, dr7);
 867
 868         return 0;
 869 }
 870
 871 static int vmx_get_irq(struct kvm_vcpu *vcpu)
 872 {
 873         struct vcpu_vmx *vmx = to_vmx(vcpu);
 874         u32 idtv_info_field;
 875
 876         idtv_info_field = vmx->idt_vectoring_info;
 877         if (idtv_info_field & INTR_INFO_VALID_MASK) {
 878                 if (is_external_interrupt(idtv_info_field))
 879                         return idtv_info_field & VECTORING_INFO_VECTOR_MASK;
 880                 else
 881                         printk(KERN_DEBUG "pending exception: not handled yet\n");
 882         }
 883         return -1;
 884 }
 885
 886 static __init int cpu_has_kvm_support(void)
 887 {
 888         unsigned long ecx = cpuid_ecx(1);
 889         return test_bit(5, &ecx); /* CPUID.1:ECX.VMX[bit 5] -> VT */
 890 }
 891
 892 static __init int vmx_disabled_by_bios(void)
 893 {
 894         u64 msr;
 895
 896         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 897         return (msr & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 898                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 899             == MSR_IA32_FEATURE_CONTROL_LOCKED;
 900         /* locked but not enabled */
 901 }
 902
 903 static void hardware_enable(void *garbage)
 904 {
 905         int cpu = raw_smp_processor_id();
 906         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
 907         u64 old;
 908
 909         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
 910         if ((old & (MSR_IA32_FEATURE_CONTROL_LOCKED |
 911                     MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 912             != (MSR_IA32_FEATURE_CONTROL_LOCKED |
 913                 MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED))
 914                 /* enable and lock */
 915                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
 916                        MSR_IA32_FEATURE_CONTROL_LOCKED |
 917                        MSR_IA32_FEATURE_CONTROL_VMXON_ENABLED);
 918         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
 919         asm volatile (ASM_VMX_VMXON_RAX : : "a"(&phys_addr), "m"(phys_addr)
 920                       : "memory", "cc");
 921 }
 922
 923 static void hardware_disable(void *garbage)
 924 {
 925         asm volatile (ASM_VMX_VMXOFF : : : "cc");
 926 }
 927
 928 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
 929                                       u32 msr, u32 *result)
 930 {
 931         u32 vmx_msr_low, vmx_msr_high;
 932         u32 ctl = ctl_min | ctl_opt;
 933
 934         rdmsr(msr, vmx_msr_low, vmx_msr_high);
 935
 936         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
 937         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
 938
 939         /* Ensure minimum (required) set of control bits are supported. */
 940         if (ctl_min & ~ctl)
 941                 return -EIO;
 942
 943         *result = ctl;
 944         return 0;
 945 }
 946
 947 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
 948 {
 949         u32 vmx_msr_low, vmx_msr_high;
 950         u32 min, opt;
 951         u32 _pin_based_exec_control = 0;
 952         u32 _cpu_based_exec_control = 0;
 953         u32 _cpu_based_2nd_exec_control = 0;
 954         u32 _vmexit_control = 0;
 955         u32 _vmentry_control = 0;
 956
 957         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
 958         opt = 0;
 959         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
 960                                 &_pin_based_exec_control) < 0)
 961                 return -EIO;
 962
 963         min = CPU_BASED_HLT_EXITING |
 964 #ifdef CONFIG_X86_64
 965               CPU_BASED_CR8_LOAD_EXITING |
 966               CPU_BASED_CR8_STORE_EXITING |
 967 #endif
 968               CPU_BASED_USE_IO_BITMAPS |
 969               CPU_BASED_MOV_DR_EXITING |
 970               CPU_BASED_USE_TSC_OFFSETING;
 971         opt = CPU_BASED_TPR_SHADOW |
 972               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 973         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
 974                                 &_cpu_based_exec_control) < 0)
 975                 return -EIO;
 976 #ifdef CONFIG_X86_64
 977         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
 978                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
 979                                            ~CPU_BASED_CR8_STORE_EXITING;
 980 #endif
 981         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
 982                 min = 0;
 983                 opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
 984                         SECONDARY_EXEC_WBINVD_EXITING;
 985                 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS2,
 986                                         &_cpu_based_2nd_exec_control) < 0)
 987                         return -EIO;
 988         }
 989 #ifndef CONFIG_X86_64
 990         if (!(_cpu_based_2nd_exec_control &
 991                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
 992                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
 993 #endif
 994
 995         min = 0;
 996 #ifdef CONFIG_X86_64
 997         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
 998 #endif
 999         opt = 0;
1000         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1001                                 &_vmexit_control) < 0)
1002                 return -EIO;
1003
1004         min = opt = 0;
1005         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1006                                 &_vmentry_control) < 0)
1007                 return -EIO;
1008
1009         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1010
1011         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1012         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1013                 return -EIO;
1014
1015 #ifdef CONFIG_X86_64
1016         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1017         if (vmx_msr_high & (1u<<16))
1018                 return -EIO;
1019 #endif
1020
1021         /* Require Write-Back (WB) memory type for VMCS accesses. */
1022         if (((vmx_msr_high >> 18) & 15) != 6)
1023                 return -EIO;
1024
1025         vmcs_conf->size = vmx_msr_high & 0x1fff;
1026         vmcs_conf->order = get_order(vmcs_config.size);
1027         vmcs_conf->revision_id = vmx_msr_low;
1028
1029         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1030         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1031         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1032         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1033         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1034
1035         return 0;
1036 }
1037
1038 static struct vmcs *alloc_vmcs_cpu(int cpu)
1039 {
1040         int node = cpu_to_node(cpu);
1041         struct page *pages;
1042         struct vmcs *vmcs;
1043
1044         pages = alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
1045         if (!pages)
1046                 return NULL;
1047         vmcs = page_address(pages);
1048         memset(vmcs, 0, vmcs_config.size);
1049         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1050         return vmcs;
1051 }
1052
1053 static struct vmcs *alloc_vmcs(void)
1054 {
1055         return alloc_vmcs_cpu(raw_smp_processor_id());
1056 }
1057
1058 static void free_vmcs(struct vmcs *vmcs)
1059 {
1060         free_pages((unsigned long)vmcs, vmcs_config.order);
1061 }
1062
1063 static void free_kvm_area(void)
1064 {
1065         int cpu;
1066
1067         for_each_online_cpu(cpu)
1068                 free_vmcs(per_cpu(vmxarea, cpu));
1069 }
1070
1071 static __init int alloc_kvm_area(void)
1072 {
1073         int cpu;
1074
1075         for_each_online_cpu(cpu) {
1076                 struct vmcs *vmcs;
1077
1078                 vmcs = alloc_vmcs_cpu(cpu);
1079                 if (!vmcs) {
1080                         free_kvm_area();
1081                         return -ENOMEM;
1082                 }
1083
1084                 per_cpu(vmxarea, cpu) = vmcs;
1085         }
1086         return 0;
1087 }
1088
1089 static __init int hardware_setup(void)
1090 {
1091         if (setup_vmcs_config(&vmcs_config) < 0)
1092                 return -EIO;
1093         return alloc_kvm_area();
1094 }
1095
1096 static __exit void hardware_unsetup(void)
1097 {
1098         free_kvm_area();
1099 }
1100
1101 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1102 {
1103         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1104
1105         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1106                 vmcs_write16(sf->selector, save->selector);
1107                 vmcs_writel(sf->base, save->base);
1108                 vmcs_write32(sf->limit, save->limit);
1109                 vmcs_write32(sf->ar_bytes, save->ar);
1110         } else {
1111                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1112                         << AR_DPL_SHIFT;
1113                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1114         }
1115 }
1116
1117 static void enter_pmode(struct kvm_vcpu *vcpu)
1118 {
1119         unsigned long flags;
1120
1121         vcpu->rmode.active = 0;
1122
1123         vmcs_writel(GUEST_TR_BASE, vcpu->rmode.tr.base);
1124         vmcs_write32(GUEST_TR_LIMIT, vcpu->rmode.tr.limit);
1125         vmcs_write32(GUEST_TR_AR_BYTES, vcpu->rmode.tr.ar);
1126
1127         flags = vmcs_readl(GUEST_RFLAGS);
1128         flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1129         flags |= (vcpu->rmode.save_iopl << IOPL_SHIFT);
1130         vmcs_writel(GUEST_RFLAGS, flags);
1131
1132         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1133                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1134
1135         update_exception_bitmap(vcpu);
1136
1137         fix_pmode_dataseg(VCPU_SREG_ES, &vcpu->rmode.es);
1138         fix_pmode_dataseg(VCPU_SREG_DS, &vcpu->rmode.ds);
1139         fix_pmode_dataseg(VCPU_SREG_GS, &vcpu->rmode.gs);
1140         fix_pmode_dataseg(VCPU_SREG_FS, &vcpu->rmode.fs);
1141
1142         vmcs_write16(GUEST_SS_SELECTOR, 0);
1143         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1144
1145         vmcs_write16(GUEST_CS_SELECTOR,
1146                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1147         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1148 }
1149
1150 static gva_t rmode_tss_base(struct kvm *kvm)
1151 {
1152         if (!kvm->tss_addr) {
1153                 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1154                                  kvm->memslots[0].npages - 3;
1155                 return base_gfn << PAGE_SHIFT;
1156         }
1157         return kvm->tss_addr;
1158 }
1159
1160 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1161 {
1162         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1163
1164         save->selector = vmcs_read16(sf->selector);
1165         save->base = vmcs_readl(sf->base);
1166         save->limit = vmcs_read32(sf->limit);
1167         save->ar = vmcs_read32(sf->ar_bytes);
1168         vmcs_write16(sf->selector, vmcs_readl(sf->base) >> 4);
1169         vmcs_write32(sf->limit, 0xffff);
1170         vmcs_write32(sf->ar_bytes, 0xf3);
1171 }
1172
1173 static void enter_rmode(struct kvm_vcpu *vcpu)
1174 {
1175         unsigned long flags;
1176
1177         vcpu->rmode.active = 1;
1178
1179         vcpu->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1180         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1181
1182         vcpu->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1183         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1184
1185         vcpu->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1186         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1187
1188         flags = vmcs_readl(GUEST_RFLAGS);
1189         vcpu->rmode.save_iopl = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1190
1191         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1192
1193         vmcs_writel(GUEST_RFLAGS, flags);
1194         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1195         update_exception_bitmap(vcpu);
1196
1197         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1198         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1199         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1200
1201         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1202         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1203         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1204                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1205         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1206
1207         fix_rmode_seg(VCPU_SREG_ES, &vcpu->rmode.es);
1208         fix_rmode_seg(VCPU_SREG_DS, &vcpu->rmode.ds);
1209         fix_rmode_seg(VCPU_SREG_GS, &vcpu->rmode.gs);
1210         fix_rmode_seg(VCPU_SREG_FS, &vcpu->rmode.fs);
1211
1212         kvm_mmu_reset_context(vcpu);
1213         init_rmode_tss(vcpu->kvm);
1214 }
1215
1216 #ifdef CONFIG_X86_64
1217
1218 static void enter_lmode(struct kvm_vcpu *vcpu)
1219 {
1220         u32 guest_tr_ar;
1221
1222         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1223         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1224                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1225                        __FUNCTION__);
1226                 vmcs_write32(GUEST_TR_AR_BYTES,
1227                              (guest_tr_ar & ~AR_TYPE_MASK)
1228                              | AR_TYPE_BUSY_64_TSS);
1229         }
1230
1231         vcpu->shadow_efer |= EFER_LMA;
1232
1233         find_msr_entry(to_vmx(vcpu), MSR_EFER)->data |= EFER_LMA | EFER_LME;
1234         vmcs_write32(VM_ENTRY_CONTROLS,
1235                      vmcs_read32(VM_ENTRY_CONTROLS)
1236                      | VM_ENTRY_IA32E_MODE);
1237 }
1238
1239 static void exit_lmode(struct kvm_vcpu *vcpu)
1240 {
1241         vcpu->shadow_efer &= ~EFER_LMA;
1242
1243         vmcs_write32(VM_ENTRY_CONTROLS,
1244                      vmcs_read32(VM_ENTRY_CONTROLS)
1245                      & ~VM_ENTRY_IA32E_MODE);
1246 }
1247
1248 #endif
1249
1250 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1251 {
1252         vcpu->cr4 &= KVM_GUEST_CR4_MASK;
1253         vcpu->cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1254 }
1255
1256 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1257 {
1258         vmx_fpu_deactivate(vcpu);
1259
1260         if (vcpu->rmode.active && (cr0 & X86_CR0_PE))
1261                 enter_pmode(vcpu);
1262
1263         if (!vcpu->rmode.active && !(cr0 & X86_CR0_PE))
1264                 enter_rmode(vcpu);
1265
1266 #ifdef CONFIG_X86_64
1267         if (vcpu->shadow_efer & EFER_LME) {
1268                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1269                         enter_lmode(vcpu);
1270                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1271                         exit_lmode(vcpu);
1272         }
1273 #endif
1274
1275         vmcs_writel(CR0_READ_SHADOW, cr0);
1276         vmcs_writel(GUEST_CR0,
1277                     (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON);
1278         vcpu->cr0 = cr0;
1279
1280         if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1281                 vmx_fpu_activate(vcpu);
1282 }
1283
1284 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1285 {
1286         vmcs_writel(GUEST_CR3, cr3);
1287         if (vcpu->cr0 & X86_CR0_PE)
1288                 vmx_fpu_deactivate(vcpu);
1289 }
1290
1291 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1292 {
1293         vmcs_writel(CR4_READ_SHADOW, cr4);
1294         vmcs_writel(GUEST_CR4, cr4 | (vcpu->rmode.active ?
1295                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON));
1296         vcpu->cr4 = cr4;
1297 }
1298
1299 #ifdef CONFIG_X86_64
1300
1301 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1302 {
1303         struct vcpu_vmx *vmx = to_vmx(vcpu);
1304         struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1305
1306         vcpu->shadow_efer = efer;
1307         if (efer & EFER_LMA) {
1308                 vmcs_write32(VM_ENTRY_CONTROLS,
1309                                      vmcs_read32(VM_ENTRY_CONTROLS) |
1310                                      VM_ENTRY_IA32E_MODE);
1311                 msr->data = efer;
1312
1313         } else {
1314                 vmcs_write32(VM_ENTRY_CONTROLS,
1315                                      vmcs_read32(VM_ENTRY_CONTROLS) &
1316                                      ~VM_ENTRY_IA32E_MODE);
1317
1318                 msr->data = efer & ~EFER_LME;
1319         }
1320         setup_msrs(vmx);
1321 }
1322
1323 #endif
1324
1325 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1326 {
1327         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1328
1329         return vmcs_readl(sf->base);
1330 }
1331
1332 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1333                             struct kvm_segment *var, int seg)
1334 {
1335         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1336         u32 ar;
1337
1338         var->base = vmcs_readl(sf->base);
1339         var->limit = vmcs_read32(sf->limit);
1340         var->selector = vmcs_read16(sf->selector);
1341         ar = vmcs_read32(sf->ar_bytes);
1342         if (ar & AR_UNUSABLE_MASK)
1343                 ar = 0;
1344         var->type = ar & 15;
1345         var->s = (ar >> 4) & 1;
1346         var->dpl = (ar >> 5) & 3;
1347         var->present = (ar >> 7) & 1;
1348         var->avl = (ar >> 12) & 1;
1349         var->l = (ar >> 13) & 1;
1350         var->db = (ar >> 14) & 1;
1351         var->g = (ar >> 15) & 1;
1352         var->unusable = (ar >> 16) & 1;
1353 }
1354
1355 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1356 {
1357         u32 ar;
1358
1359         if (var->unusable)
1360                 ar = 1 << 16;
1361         else {
1362                 ar = var->type & 15;
1363                 ar |= (var->s & 1) << 4;
1364                 ar |= (var->dpl & 3) << 5;
1365                 ar |= (var->present & 1) << 7;
1366                 ar |= (var->avl & 1) << 12;
1367                 ar |= (var->l & 1) << 13;
1368                 ar |= (var->db & 1) << 14;
1369                 ar |= (var->g & 1) << 15;
1370         }
1371         if (ar == 0) /* a 0 value means unusable */
1372                 ar = AR_UNUSABLE_MASK;
1373
1374         return ar;
1375 }
1376
1377 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1378                             struct kvm_segment *var, int seg)
1379 {
1380         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1381         u32 ar;
1382
1383         if (vcpu->rmode.active && seg == VCPU_SREG_TR) {
1384                 vcpu->rmode.tr.selector = var->selector;
1385                 vcpu->rmode.tr.base = var->base;
1386                 vcpu->rmode.tr.limit = var->limit;
1387                 vcpu->rmode.tr.ar = vmx_segment_access_rights(var);
1388                 return;
1389         }
1390         vmcs_writel(sf->base, var->base);
1391         vmcs_write32(sf->limit, var->limit);
1392         vmcs_write16(sf->selector, var->selector);
1393         if (vcpu->rmode.active && var->s) {
1394                 /*
1395                  * Hack real-mode segments into vm86 compatibility.
1396                  */
1397                 if (var->base == 0xffff0000 && var->selector == 0xf000)
1398                         vmcs_writel(sf->base, 0xf0000);
1399                 ar = 0xf3;
1400         } else
1401                 ar = vmx_segment_access_rights(var);
1402         vmcs_write32(sf->ar_bytes, ar);
1403 }
1404
1405 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1406 {
1407         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1408
1409         *db = (ar >> 14) & 1;
1410         *l = (ar >> 13) & 1;
1411 }
1412
1413 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1414 {
1415         dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1416         dt->base = vmcs_readl(GUEST_IDTR_BASE);
1417 }
1418
1419 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1420 {
1421         vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1422         vmcs_writel(GUEST_IDTR_BASE, dt->base);
1423 }
1424
1425 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1426 {
1427         dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1428         dt->base = vmcs_readl(GUEST_GDTR_BASE);
1429 }
1430
1431 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1432 {
1433         vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1434         vmcs_writel(GUEST_GDTR_BASE, dt->base);
1435 }
1436
1437 static int init_rmode_tss(struct kvm *kvm)
1438 {
1439         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
1440         u16 data = 0;
1441         int r;
1442
1443         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1444         if (r < 0)
1445                 return 0;
1446         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
1447         r = kvm_write_guest_page(kvm, fn++, &data, 0x66, sizeof(u16));
1448         if (r < 0)
1449                 return 0;
1450         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
1451         if (r < 0)
1452                 return 0;
1453         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
1454         if (r < 0)
1455                 return 0;
1456         data = ~0;
1457         r = kvm_write_guest_page(kvm, fn, &data, RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
1458                         sizeof(u8));
1459         if (r < 0)
1460                 return 0;
1461         return 1;
1462 }
1463
1464 static void seg_setup(int seg)
1465 {
1466         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1467
1468         vmcs_write16(sf->selector, 0);
1469         vmcs_writel(sf->base, 0);
1470         vmcs_write32(sf->limit, 0xffff);
1471         vmcs_write32(sf->ar_bytes, 0x93);
1472 }
1473
1474 static int alloc_apic_access_page(struct kvm *kvm)
1475 {
1476         struct kvm_userspace_memory_region kvm_userspace_mem;
1477         int r = 0;
1478
1479         mutex_lock(&kvm->lock);
1480         if (kvm->apic_access_page)
1481                 goto out;
1482         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
1483         kvm_userspace_mem.flags = 0;
1484         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
1485         kvm_userspace_mem.memory_size = PAGE_SIZE;
1486         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
1487         if (r)
1488                 goto out;
1489         kvm->apic_access_page = gfn_to_page(kvm, 0xfee00);
1490 out:
1491         mutex_unlock(&kvm->lock);
1492         return r;
1493 }
1494
1495 /*
1496  * Sets up the vmcs for emulated real mode.
1497  */
1498 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
1499 {
1500         u32 host_sysenter_cs;
1501         u32 junk;
1502         unsigned long a;
1503         struct descriptor_table dt;
1504         int i;
1505         unsigned long kvm_vmx_return;
1506         u32 exec_control;
1507
1508         /* I/O */
1509         vmcs_write64(IO_BITMAP_A, page_to_phys(vmx_io_bitmap_a));
1510         vmcs_write64(IO_BITMAP_B, page_to_phys(vmx_io_bitmap_b));
1511
1512         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
1513
1514         /* Control */
1515         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
1516                 vmcs_config.pin_based_exec_ctrl);
1517
1518         exec_control = vmcs_config.cpu_based_exec_ctrl;
1519         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
1520                 exec_control &= ~CPU_BASED_TPR_SHADOW;
1521 #ifdef CONFIG_X86_64
1522                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
1523                                 CPU_BASED_CR8_LOAD_EXITING;
1524 #endif
1525         }
1526         if (!vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1527                 exec_control &= ~CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1528         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
1529
1530         if (vm_need_secondary_exec_ctrls(vmx->vcpu.kvm))
1531                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
1532                              vmcs_config.cpu_based_2nd_exec_ctrl);
1533
1534         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
1535         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
1536         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
1537
1538         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
1539         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
1540         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
1541
1542         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
1543         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1544         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1545         vmcs_write16(HOST_FS_SELECTOR, read_fs());    /* 22.2.4 */
1546         vmcs_write16(HOST_GS_SELECTOR, read_gs());    /* 22.2.4 */
1547         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
1548 #ifdef CONFIG_X86_64
1549         rdmsrl(MSR_FS_BASE, a);
1550         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
1551         rdmsrl(MSR_GS_BASE, a);
1552         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
1553 #else
1554         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
1555         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
1556 #endif
1557
1558         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
1559
1560         get_idt(&dt);
1561         vmcs_writel(HOST_IDTR_BASE, dt.base);   /* 22.2.4 */
1562
1563         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
1564         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
1565         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
1566         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
1567         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
1568
1569         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
1570         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
1571         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
1572         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
1573         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
1574         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
1575
1576         for (i = 0; i < NR_VMX_MSR; ++i) {
1577                 u32 index = vmx_msr_index[i];
1578                 u32 data_low, data_high;
1579                 u64 data;
1580                 int j = vmx->nmsrs;
1581
1582                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
1583                         continue;
1584                 if (wrmsr_safe(index, data_low, data_high) < 0)
1585                         continue;
1586                 data = data_low | ((u64)data_high << 32);
1587                 vmx->host_msrs[j].index = index;
1588                 vmx->host_msrs[j].reserved = 0;
1589                 vmx->host_msrs[j].data = data;
1590                 vmx->guest_msrs[j] = vmx->host_msrs[j];
1591                 ++vmx->nmsrs;
1592         }
1593
1594         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
1595
1596         /* 22.2.1, 20.8.1 */
1597         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
1598
1599         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
1600         vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
1601
1602         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1603                 if (alloc_apic_access_page(vmx->vcpu.kvm) != 0)
1604                         return -ENOMEM;
1605
1606         return 0;
1607 }
1608
1609 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
1610 {
1611         struct vcpu_vmx *vmx = to_vmx(vcpu);
1612         u64 msr;
1613         int ret;
1614
1615         if (!init_rmode_tss(vmx->vcpu.kvm)) {
1616                 ret = -ENOMEM;
1617                 goto out;
1618         }
1619
1620         vmx->vcpu.rmode.active = 0;
1621
1622         vmx->vcpu.regs[VCPU_REGS_RDX] = get_rdx_init_val();
1623         set_cr8(&vmx->vcpu, 0);
1624         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1625         if (vmx->vcpu.vcpu_id == 0)
1626                 msr |= MSR_IA32_APICBASE_BSP;
1627         kvm_set_apic_base(&vmx->vcpu, msr);
1628
1629         fx_init(&vmx->vcpu);
1630
1631         /*
1632          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
1633          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
1634          */
1635         if (vmx->vcpu.vcpu_id == 0) {
1636                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
1637                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
1638         } else {
1639                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.sipi_vector << 8);
1640                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.sipi_vector << 12);
1641         }
1642         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1643         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1644
1645         seg_setup(VCPU_SREG_DS);
1646         seg_setup(VCPU_SREG_ES);
1647         seg_setup(VCPU_SREG_FS);
1648         seg_setup(VCPU_SREG_GS);
1649         seg_setup(VCPU_SREG_SS);
1650
1651         vmcs_write16(GUEST_TR_SELECTOR, 0);
1652         vmcs_writel(GUEST_TR_BASE, 0);
1653         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
1654         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1655
1656         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
1657         vmcs_writel(GUEST_LDTR_BASE, 0);
1658         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
1659         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
1660
1661         vmcs_write32(GUEST_SYSENTER_CS, 0);
1662         vmcs_writel(GUEST_SYSENTER_ESP, 0);
1663         vmcs_writel(GUEST_SYSENTER_EIP, 0);
1664
1665         vmcs_writel(GUEST_RFLAGS, 0x02);
1666         if (vmx->vcpu.vcpu_id == 0)
1667                 vmcs_writel(GUEST_RIP, 0xfff0);
1668         else
1669                 vmcs_writel(GUEST_RIP, 0);
1670         vmcs_writel(GUEST_RSP, 0);
1671
1672         /* todo: dr0 = dr1 = dr2 = dr3 = 0; dr6 = 0xffff0ff0 */
1673         vmcs_writel(GUEST_DR7, 0x400);
1674
1675         vmcs_writel(GUEST_GDTR_BASE, 0);
1676         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
1677
1678         vmcs_writel(GUEST_IDTR_BASE, 0);
1679         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
1680
1681         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
1682         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
1683         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
1684
1685         guest_write_tsc(0);
1686
1687         /* Special registers */
1688         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
1689
1690         setup_msrs(vmx);
1691
1692         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
1693
1694         if (cpu_has_vmx_tpr_shadow()) {
1695                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
1696                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
1697                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
1698                                      page_to_phys(vmx->vcpu.apic->regs_page));
1699                 vmcs_write32(TPR_THRESHOLD, 0);
1700         }
1701
1702         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
1703                 vmcs_write64(APIC_ACCESS_ADDR,
1704                              page_to_phys(vmx->vcpu.kvm->apic_access_page));
1705
1706         vmx->vcpu.cr0 = 0x60000010;
1707         vmx_set_cr0(&vmx->vcpu, vmx->vcpu.cr0); /* enter rmode */
1708         vmx_set_cr4(&vmx->vcpu, 0);
1709 #ifdef CONFIG_X86_64
1710         vmx_set_efer(&vmx->vcpu, 0);
1711 #endif
1712         vmx_fpu_activate(&vmx->vcpu);
1713         update_exception_bitmap(&vmx->vcpu);
1714
1715         return 0;
1716
1717 out:
1718         return ret;
1719 }
1720
1721 static void vmx_inject_irq(struct kvm_vcpu *vcpu, int irq)
1722 {
1723         struct vcpu_vmx *vmx = to_vmx(vcpu);
1724
1725         if (vcpu->rmode.active) {
1726                 vmx->rmode.irq.pending = true;
1727                 vmx->rmode.irq.vector = irq;
1728                 vmx->rmode.irq.rip = vmcs_readl(GUEST_RIP);
1729                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1730                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
1731                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1732                 vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip - 1);
1733                 return;
1734         }
1735         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
1736                         irq | INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1737 }
1738
1739 static void kvm_do_inject_irq(struct kvm_vcpu *vcpu)
1740 {
1741         int word_index = __ffs(vcpu->irq_summary);
1742         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1743         int irq = word_index * BITS_PER_LONG + bit_index;
1744
1745         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1746         if (!vcpu->irq_pending[word_index])
1747                 clear_bit(word_index, &vcpu->irq_summary);
1748         vmx_inject_irq(vcpu, irq);
1749 }
1750
1751
1752 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1753                                        struct kvm_run *kvm_run)
1754 {
1755         u32 cpu_based_vm_exec_control;
1756
1757         vcpu->interrupt_window_open =
1758                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
1759                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
1760
1761         if (vcpu->interrupt_window_open &&
1762             vcpu->irq_summary &&
1763             !(vmcs_read32(VM_ENTRY_INTR_INFO_FIELD) & INTR_INFO_VALID_MASK))
1764                 /*
1765                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1766                  */
1767                 kvm_do_inject_irq(vcpu);
1768
1769         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
1770         if (!vcpu->interrupt_window_open &&
1771             (vcpu->irq_summary || kvm_run->request_interrupt_window))
1772                 /*
1773                  * Interrupts blocked.  Wait for unblock.
1774                  */
1775                 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
1776         else
1777                 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
1778         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
1779 }
1780
1781 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
1782 {
1783         int ret;
1784         struct kvm_userspace_memory_region tss_mem = {
1785                 .slot = 8,
1786                 .guest_phys_addr = addr,
1787                 .memory_size = PAGE_SIZE * 3,
1788                 .flags = 0,
1789         };
1790
1791         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
1792         if (ret)
1793                 return ret;
1794         kvm->tss_addr = addr;
1795         return 0;
1796 }
1797
1798 static void kvm_guest_debug_pre(struct kvm_vcpu *vcpu)
1799 {
1800         struct kvm_guest_debug *dbg = &vcpu->guest_debug;
1801
1802         set_debugreg(dbg->bp[0], 0);
1803         set_debugreg(dbg->bp[1], 1);
1804         set_debugreg(dbg->bp[2], 2);
1805         set_debugreg(dbg->bp[3], 3);
1806
1807         if (dbg->singlestep) {
1808                 unsigned long flags;
1809
1810                 flags = vmcs_readl(GUEST_RFLAGS);
1811                 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1812                 vmcs_writel(GUEST_RFLAGS, flags);
1813         }
1814 }
1815
1816 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
1817                                   int vec, u32 err_code)
1818 {
1819         if (!vcpu->rmode.active)
1820                 return 0;
1821
1822         /*
1823          * Instruction with address size override prefix opcode 0x67
1824          * Cause the #SS fault with 0 error code in VM86 mode.
1825          */
1826         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
1827                 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
1828                         return 1;
1829         return 0;
1830 }
1831
1832 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1833 {
1834         struct vcpu_vmx *vmx = to_vmx(vcpu);
1835         u32 intr_info, error_code;
1836         unsigned long cr2, rip;
1837         u32 vect_info;
1838         enum emulation_result er;
1839
1840         vect_info = vmx->idt_vectoring_info;
1841         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
1842
1843         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
1844                                                 !is_page_fault(intr_info))
1845                 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
1846                        "intr info 0x%x\n", __FUNCTION__, vect_info, intr_info);
1847
1848         if (!irqchip_in_kernel(vcpu->kvm) && is_external_interrupt(vect_info)) {
1849                 int irq = vect_info & VECTORING_INFO_VECTOR_MASK;
1850                 set_bit(irq, vcpu->irq_pending);
1851                 set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
1852         }
1853
1854         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
1855                 return 1;  /* already handled by vmx_vcpu_run() */
1856
1857         if (is_no_device(intr_info)) {
1858                 vmx_fpu_activate(vcpu);
1859                 return 1;
1860         }
1861
1862         if (is_invalid_opcode(intr_info)) {
1863                 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
1864                 if (er != EMULATE_DONE)
1865                         vmx_inject_ud(vcpu);
1866
1867                 return 1;
1868         }
1869
1870         error_code = 0;
1871         rip = vmcs_readl(GUEST_RIP);
1872         if (intr_info & INTR_INFO_DELIEVER_CODE_MASK)
1873                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
1874         if (is_page_fault(intr_info)) {
1875                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1876                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
1877         }
1878
1879         if (vcpu->rmode.active &&
1880             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
1881                                                                 error_code)) {
1882                 if (vcpu->halt_request) {
1883                         vcpu->halt_request = 0;
1884                         return kvm_emulate_halt(vcpu);
1885                 }
1886                 return 1;
1887         }
1888
1889         if ((intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK)) ==
1890             (INTR_TYPE_EXCEPTION | 1)) {
1891                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1892                 return 0;
1893         }
1894         kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
1895         kvm_run->ex.exception = intr_info & INTR_INFO_VECTOR_MASK;
1896         kvm_run->ex.error_code = error_code;
1897         return 0;
1898 }
1899
1900 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
1901                                      struct kvm_run *kvm_run)
1902 {
1903         ++vcpu->stat.irq_exits;
1904         return 1;
1905 }
1906
1907 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1908 {
1909         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1910         return 0;
1911 }
1912
1913 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1914 {
1915         unsigned long exit_qualification;
1916         int size, down, in, string, rep;
1917         unsigned port;
1918
1919         ++vcpu->stat.io_exits;
1920         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1921         string = (exit_qualification & 16) != 0;
1922
1923         if (string) {
1924                 if (emulate_instruction(vcpu,
1925                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1926                         return 0;
1927                 return 1;
1928         }
1929
1930         size = (exit_qualification & 7) + 1;
1931         in = (exit_qualification & 8) != 0;
1932         down = (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_DF) != 0;
1933         rep = (exit_qualification & 32) != 0;
1934         port = exit_qualification >> 16;
1935
1936         return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
1937 }
1938
1939 static void
1940 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1941 {
1942         /*
1943          * Patch in the VMCALL instruction:
1944          */
1945         hypercall[0] = 0x0f;
1946         hypercall[1] = 0x01;
1947         hypercall[2] = 0xc1;
1948 }
1949
1950 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1951 {
1952         unsigned long exit_qualification;
1953         int cr;
1954         int reg;
1955
1956         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1957         cr = exit_qualification & 15;
1958         reg = (exit_qualification >> 8) & 15;
1959         switch ((exit_qualification >> 4) & 3) {
1960         case 0: /* mov to cr */
1961                 switch (cr) {
1962                 case 0:
1963                         vcpu_load_rsp_rip(vcpu);
1964                         set_cr0(vcpu, vcpu->regs[reg]);
1965                         skip_emulated_instruction(vcpu);
1966                         return 1;
1967                 case 3:
1968                         vcpu_load_rsp_rip(vcpu);
1969                         set_cr3(vcpu, vcpu->regs[reg]);
1970                         skip_emulated_instruction(vcpu);
1971                         return 1;
1972                 case 4:
1973                         vcpu_load_rsp_rip(vcpu);
1974                         set_cr4(vcpu, vcpu->regs[reg]);
1975                         skip_emulated_instruction(vcpu);
1976                         return 1;
1977                 case 8:
1978                         vcpu_load_rsp_rip(vcpu);
1979                         set_cr8(vcpu, vcpu->regs[reg]);
1980                         skip_emulated_instruction(vcpu);
1981                         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1982                         return 0;
1983                 };
1984                 break;
1985         case 2: /* clts */
1986                 vcpu_load_rsp_rip(vcpu);
1987                 vmx_fpu_deactivate(vcpu);
1988                 vcpu->cr0 &= ~X86_CR0_TS;
1989                 vmcs_writel(CR0_READ_SHADOW, vcpu->cr0);
1990                 vmx_fpu_activate(vcpu);
1991                 skip_emulated_instruction(vcpu);
1992                 return 1;
1993         case 1: /*mov from cr*/
1994                 switch (cr) {
1995                 case 3:
1996                         vcpu_load_rsp_rip(vcpu);
1997                         vcpu->regs[reg] = vcpu->cr3;
1998                         vcpu_put_rsp_rip(vcpu);
1999                         skip_emulated_instruction(vcpu);
2000                         return 1;
2001                 case 8:
2002                         vcpu_load_rsp_rip(vcpu);
2003                         vcpu->regs[reg] = get_cr8(vcpu);
2004                         vcpu_put_rsp_rip(vcpu);
2005                         skip_emulated_instruction(vcpu);
2006                         return 1;
2007                 }
2008                 break;
2009         case 3: /* lmsw */
2010                 lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2011
2012                 skip_emulated_instruction(vcpu);
2013                 return 1;
2014         default:
2015                 break;
2016         }
2017         kvm_run->exit_reason = 0;
2018         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2019                (int)(exit_qualification >> 4) & 3, cr);
2020         return 0;
2021 }
2022
2023 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2024 {
2025         unsigned long exit_qualification;
2026         unsigned long val;
2027         int dr, reg;
2028
2029         /*
2030          * FIXME: this code assumes the host is debugging the guest.
2031          *        need to deal with guest debugging itself too.
2032          */
2033         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2034         dr = exit_qualification & 7;
2035         reg = (exit_qualification >> 8) & 15;
2036         vcpu_load_rsp_rip(vcpu);
2037         if (exit_qualification & 16) {
2038                 /* mov from dr */
2039                 switch (dr) {
2040                 case 6:
2041                         val = 0xffff0ff0;
2042                         break;
2043                 case 7:
2044                         val = 0x400;
2045                         break;
2046                 default:
2047                         val = 0;
2048                 }
2049                 vcpu->regs[reg] = val;
2050         } else {
2051                 /* mov to dr */
2052         }
2053         vcpu_put_rsp_rip(vcpu);
2054         skip_emulated_instruction(vcpu);
2055         return 1;
2056 }
2057
2058 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2059 {
2060         kvm_emulate_cpuid(vcpu);
2061         return 1;
2062 }
2063
2064 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2065 {
2066         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2067         u64 data;
2068
2069         if (vmx_get_msr(vcpu, ecx, &data)) {
2070                 vmx_inject_gp(vcpu, 0);
2071                 return 1;
2072         }
2073
2074         /* FIXME: handling of bits 32:63 of rax, rdx */
2075         vcpu->regs[VCPU_REGS_RAX] = data & -1u;
2076         vcpu->regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
2077         skip_emulated_instruction(vcpu);
2078         return 1;
2079 }
2080
2081 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2082 {
2083         u32 ecx = vcpu->regs[VCPU_REGS_RCX];
2084         u64 data = (vcpu->regs[VCPU_REGS_RAX] & -1u)
2085                 | ((u64)(vcpu->regs[VCPU_REGS_RDX] & -1u) << 32);
2086
2087         if (vmx_set_msr(vcpu, ecx, data) != 0) {
2088                 vmx_inject_gp(vcpu, 0);
2089                 return 1;
2090         }
2091
2092         skip_emulated_instruction(vcpu);
2093         return 1;
2094 }
2095
2096 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
2097                                       struct kvm_run *kvm_run)
2098 {
2099         return 1;
2100 }
2101
2102 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
2103                                    struct kvm_run *kvm_run)
2104 {
2105         u32 cpu_based_vm_exec_control;
2106
2107         /* clear pending irq */
2108         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2109         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
2110         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2111         /*
2112          * If the user space waits to inject interrupts, exit as soon as
2113          * possible
2114          */
2115         if (kvm_run->request_interrupt_window &&
2116             !vcpu->irq_summary) {
2117                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2118                 ++vcpu->stat.irq_window_exits;
2119                 return 0;
2120         }
2121         return 1;
2122 }
2123
2124 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2125 {
2126         skip_emulated_instruction(vcpu);
2127         return kvm_emulate_halt(vcpu);
2128 }
2129
2130 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2131 {
2132         skip_emulated_instruction(vcpu);
2133         kvm_emulate_hypercall(vcpu);
2134         return 1;
2135 }
2136
2137 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2138 {
2139         skip_emulated_instruction(vcpu);
2140         /* TODO: Add support for VT-d/pass-through device */
2141         return 1;
2142 }
2143
2144 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2145 {
2146         u64 exit_qualification;
2147         enum emulation_result er;
2148         unsigned long offset;
2149
2150         exit_qualification = vmcs_read64(EXIT_QUALIFICATION);
2151         offset = exit_qualification & 0xffful;
2152
2153         er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
2154
2155         if (er !=  EMULATE_DONE) {
2156                 printk(KERN_ERR
2157                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
2158                        offset);
2159                 return -ENOTSUPP;
2160         }
2161         return 1;
2162 }
2163
2164 /*
2165  * The exit handlers return 1 if the exit was handled fully and guest execution
2166  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
2167  * to be done to userspace and return 0.
2168  */
2169 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
2170                                       struct kvm_run *kvm_run) = {
2171         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
2172         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
2173         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
2174         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
2175         [EXIT_REASON_CR_ACCESS]               = handle_cr,
2176         [EXIT_REASON_DR_ACCESS]               = handle_dr,
2177         [EXIT_REASON_CPUID]                   = handle_cpuid,
2178         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
2179         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
2180         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
2181         [EXIT_REASON_HLT]                     = handle_halt,
2182         [EXIT_REASON_VMCALL]                  = handle_vmcall,
2183         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
2184         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
2185         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
2186 };
2187
2188 static const int kvm_vmx_max_exit_handlers =
2189         ARRAY_SIZE(kvm_vmx_exit_handlers);
2190
2191 /*
2192  * The guest has exited.  See if we can fix it or if we need userspace
2193  * assistance.
2194  */
2195 static int kvm_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2196 {
2197         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
2198         struct vcpu_vmx *vmx = to_vmx(vcpu);
2199         u32 vectoring_info = vmx->idt_vectoring_info;
2200
2201         if (unlikely(vmx->fail)) {
2202                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2203                 kvm_run->fail_entry.hardware_entry_failure_reason
2204                         = vmcs_read32(VM_INSTRUCTION_ERROR);
2205                 return 0;
2206         }
2207
2208         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
2209                                 exit_reason != EXIT_REASON_EXCEPTION_NMI)
2210                 printk(KERN_WARNING "%s: unexpected, valid vectoring info and "
2211                        "exit reason is 0x%x\n", __FUNCTION__, exit_reason);
2212         if (exit_reason < kvm_vmx_max_exit_handlers
2213             && kvm_vmx_exit_handlers[exit_reason])
2214                 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
2215         else {
2216                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2217                 kvm_run->hw.hardware_exit_reason = exit_reason;
2218         }
2219         return 0;
2220 }
2221
2222 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2223 {
2224 }
2225
2226 static void update_tpr_threshold(struct kvm_vcpu *vcpu)
2227 {
2228         int max_irr, tpr;
2229
2230         if (!vm_need_tpr_shadow(vcpu->kvm))
2231                 return;
2232
2233         if (!kvm_lapic_enabled(vcpu) ||
2234             ((max_irr = kvm_lapic_find_highest_irr(vcpu)) == -1)) {
2235                 vmcs_write32(TPR_THRESHOLD, 0);
2236                 return;
2237         }
2238
2239         tpr = (kvm_lapic_get_cr8(vcpu) & 0x0f) << 4;
2240         vmcs_write32(TPR_THRESHOLD, (max_irr > tpr) ? tpr >> 4 : max_irr >> 4);
2241 }
2242
2243 static void enable_irq_window(struct kvm_vcpu *vcpu)
2244 {
2245         u32 cpu_based_vm_exec_control;
2246
2247         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2248         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2249         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2250 }
2251
2252 static void vmx_intr_assist(struct kvm_vcpu *vcpu)
2253 {
2254         struct vcpu_vmx *vmx = to_vmx(vcpu);
2255         u32 idtv_info_field, intr_info_field;
2256         int has_ext_irq, interrupt_window_open;
2257         int vector;
2258
2259         update_tpr_threshold(vcpu);
2260
2261         has_ext_irq = kvm_cpu_has_interrupt(vcpu);
2262         intr_info_field = vmcs_read32(VM_ENTRY_INTR_INFO_FIELD);
2263         idtv_info_field = vmx->idt_vectoring_info;
2264         if (intr_info_field & INTR_INFO_VALID_MASK) {
2265                 if (idtv_info_field & INTR_INFO_VALID_MASK) {
2266                         /* TODO: fault when IDT_Vectoring */
2267                         printk(KERN_ERR "Fault when IDT_Vectoring\n");
2268                 }
2269                 if (has_ext_irq)
2270                         enable_irq_window(vcpu);
2271                 return;
2272         }
2273         if (unlikely(idtv_info_field & INTR_INFO_VALID_MASK)) {
2274                 if ((idtv_info_field & VECTORING_INFO_TYPE_MASK)
2275                     == INTR_TYPE_EXT_INTR
2276                     && vcpu->rmode.active) {
2277                         u8 vect = idtv_info_field & VECTORING_INFO_VECTOR_MASK;
2278
2279                         vmx_inject_irq(vcpu, vect);
2280                         if (unlikely(has_ext_irq))
2281                                 enable_irq_window(vcpu);
2282                         return;
2283                 }
2284
2285                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, idtv_info_field);
2286                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2287                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
2288
2289                 if (unlikely(idtv_info_field & INTR_INFO_DELIEVER_CODE_MASK))
2290                         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
2291                                 vmcs_read32(IDT_VECTORING_ERROR_CODE));
2292                 if (unlikely(has_ext_irq))
2293                         enable_irq_window(vcpu);
2294                 return;
2295         }
2296         if (!has_ext_irq)
2297                 return;
2298         interrupt_window_open =
2299                 ((vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2300                  (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0);
2301         if (interrupt_window_open) {
2302                 vector = kvm_cpu_get_interrupt(vcpu);
2303                 vmx_inject_irq(vcpu, vector);
2304                 kvm_timer_intr_post(vcpu, vector);
2305         } else
2306                 enable_irq_window(vcpu);
2307 }
2308
2309 /*
2310  * Failure to inject an interrupt should give us the information
2311  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
2312  * when fetching the interrupt redirection bitmap in the real-mode
2313  * tss, this doesn't happen.  So we do it ourselves.
2314  */
2315 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
2316 {
2317         vmx->rmode.irq.pending = 0;
2318         if (vmcs_readl(GUEST_RIP) + 1 != vmx->rmode.irq.rip)
2319                 return;
2320         vmcs_writel(GUEST_RIP, vmx->rmode.irq.rip);
2321         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
2322                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
2323                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
2324                 return;
2325         }
2326         vmx->idt_vectoring_info =
2327                 VECTORING_INFO_VALID_MASK
2328                 | INTR_TYPE_EXT_INTR
2329                 | vmx->rmode.irq.vector;
2330 }
2331
2332 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2333 {
2334         struct vcpu_vmx *vmx = to_vmx(vcpu);
2335         u32 intr_info;
2336
2337         /*
2338          * Loading guest fpu may have cleared host cr0.ts
2339          */
2340         vmcs_writel(HOST_CR0, read_cr0());
2341
2342         asm(
2343                 /* Store host registers */
2344 #ifdef CONFIG_X86_64
2345                 "push %%rdx; push %%rbp;"
2346                 "push %%rcx \n\t"
2347 #else
2348                 "push %%edx; push %%ebp;"
2349                 "push %%ecx \n\t"
2350 #endif
2351                 ASM_VMX_VMWRITE_RSP_RDX "\n\t"
2352                 /* Check if vmlaunch of vmresume is needed */
2353                 "cmpl $0, %c[launched](%0) \n\t"
2354                 /* Load guest registers.  Don't clobber flags. */
2355 #ifdef CONFIG_X86_64
2356                 "mov %c[cr2](%0), %%rax \n\t"
2357                 "mov %%rax, %%cr2 \n\t"
2358                 "mov %c[rax](%0), %%rax \n\t"
2359                 "mov %c[rbx](%0), %%rbx \n\t"
2360                 "mov %c[rdx](%0), %%rdx \n\t"
2361                 "mov %c[rsi](%0), %%rsi \n\t"
2362                 "mov %c[rdi](%0), %%rdi \n\t"
2363                 "mov %c[rbp](%0), %%rbp \n\t"
2364                 "mov %c[r8](%0),  %%r8  \n\t"
2365                 "mov %c[r9](%0),  %%r9  \n\t"
2366                 "mov %c[r10](%0), %%r10 \n\t"
2367                 "mov %c[r11](%0), %%r11 \n\t"
2368                 "mov %c[r12](%0), %%r12 \n\t"
2369                 "mov %c[r13](%0), %%r13 \n\t"
2370                 "mov %c[r14](%0), %%r14 \n\t"
2371                 "mov %c[r15](%0), %%r15 \n\t"
2372                 "mov %c[rcx](%0), %%rcx \n\t" /* kills %0 (rcx) */
2373 #else
2374                 "mov %c[cr2](%0), %%eax \n\t"
2375                 "mov %%eax,   %%cr2 \n\t"
2376                 "mov %c[rax](%0), %%eax \n\t"
2377                 "mov %c[rbx](%0), %%ebx \n\t"
2378                 "mov %c[rdx](%0), %%edx \n\t"
2379                 "mov %c[rsi](%0), %%esi \n\t"
2380                 "mov %c[rdi](%0), %%edi \n\t"
2381                 "mov %c[rbp](%0), %%ebp \n\t"
2382                 "mov %c[rcx](%0), %%ecx \n\t" /* kills %0 (ecx) */
2383 #endif
2384                 /* Enter guest mode */
2385                 "jne .Llaunched \n\t"
2386                 ASM_VMX_VMLAUNCH "\n\t"
2387                 "jmp .Lkvm_vmx_return \n\t"
2388                 ".Llaunched: " ASM_VMX_VMRESUME "\n\t"
2389                 ".Lkvm_vmx_return: "
2390                 /* Save guest registers, load host registers, keep flags */
2391 #ifdef CONFIG_X86_64
2392                 "xchg %0,     (%%rsp) \n\t"
2393                 "mov %%rax, %c[rax](%0) \n\t"
2394                 "mov %%rbx, %c[rbx](%0) \n\t"
2395                 "pushq (%%rsp); popq %c[rcx](%0) \n\t"
2396                 "mov %%rdx, %c[rdx](%0) \n\t"
2397                 "mov %%rsi, %c[rsi](%0) \n\t"
2398                 "mov %%rdi, %c[rdi](%0) \n\t"
2399                 "mov %%rbp, %c[rbp](%0) \n\t"
2400                 "mov %%r8,  %c[r8](%0) \n\t"
2401                 "mov %%r9,  %c[r9](%0) \n\t"
2402                 "mov %%r10, %c[r10](%0) \n\t"
2403                 "mov %%r11, %c[r11](%0) \n\t"
2404                 "mov %%r12, %c[r12](%0) \n\t"
2405                 "mov %%r13, %c[r13](%0) \n\t"
2406                 "mov %%r14, %c[r14](%0) \n\t"
2407                 "mov %%r15, %c[r15](%0) \n\t"
2408                 "mov %%cr2, %%rax   \n\t"
2409                 "mov %%rax, %c[cr2](%0) \n\t"
2410
2411                 "pop  %%rbp; pop  %%rbp; pop  %%rdx \n\t"
2412 #else
2413                 "xchg %0, (%%esp) \n\t"
2414                 "mov %%eax, %c[rax](%0) \n\t"
2415                 "mov %%ebx, %c[rbx](%0) \n\t"
2416                 "pushl (%%esp); popl %c[rcx](%0) \n\t"
2417                 "mov %%edx, %c[rdx](%0) \n\t"
2418                 "mov %%esi, %c[rsi](%0) \n\t"
2419                 "mov %%edi, %c[rdi](%0) \n\t"
2420                 "mov %%ebp, %c[rbp](%0) \n\t"
2421                 "mov %%cr2, %%eax  \n\t"
2422                 "mov %%eax, %c[cr2](%0) \n\t"
2423
2424                 "pop %%ebp; pop %%ebp; pop %%edx \n\t"
2425 #endif
2426                 "setbe %c[fail](%0) \n\t"
2427               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
2428                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
2429                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
2430                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RAX])),
2431                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBX])),
2432                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RCX])),
2433                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDX])),
2434                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RSI])),
2435                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RDI])),
2436                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_RBP])),
2437 #ifdef CONFIG_X86_64
2438                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R8])),
2439                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R9])),
2440                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R10])),
2441                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R11])),
2442                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R12])),
2443                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R13])),
2444                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R14])),
2445                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.regs[VCPU_REGS_R15])),
2446 #endif
2447                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.cr2))
2448               : "cc", "memory"
2449 #ifdef CONFIG_X86_64
2450                 , "rbx", "rdi", "rsi"
2451                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
2452 #else
2453                 , "ebx", "edi", "rsi"
2454 #endif
2455               );
2456
2457         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
2458         if (vmx->rmode.irq.pending)
2459                 fixup_rmode_irq(vmx);
2460
2461         vcpu->interrupt_window_open =
2462                 (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & 3) == 0;
2463
2464         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
2465         vmx->launched = 1;
2466
2467         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2468
2469         /* We need to handle NMIs before interrupts are enabled */
2470         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == 0x200) /* nmi */
2471                 asm("int $2");
2472 }
2473
2474 static void vmx_inject_page_fault(struct kvm_vcpu *vcpu,
2475                                   unsigned long addr,
2476                                   u32 err_code)
2477 {
2478         struct vcpu_vmx *vmx = to_vmx(vcpu);
2479         u32 vect_info = vmx->idt_vectoring_info;
2480
2481         ++vcpu->stat.pf_guest;
2482
2483         if (is_page_fault(vect_info)) {
2484                 printk(KERN_DEBUG "inject_page_fault: "
2485                        "double fault 0x%lx @ 0x%lx\n",
2486                        addr, vmcs_readl(GUEST_RIP));
2487                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, 0);
2488                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2489                              DF_VECTOR |
2490                              INTR_TYPE_EXCEPTION |
2491                              INTR_INFO_DELIEVER_CODE_MASK |
2492                              INTR_INFO_VALID_MASK);
2493                 return;
2494         }
2495         vcpu->cr2 = addr;
2496         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, err_code);
2497         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2498                      PF_VECTOR |
2499                      INTR_TYPE_EXCEPTION |
2500                      INTR_INFO_DELIEVER_CODE_MASK |
2501                      INTR_INFO_VALID_MASK);
2502
2503 }
2504
2505 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
2506 {
2507         struct vcpu_vmx *vmx = to_vmx(vcpu);
2508
2509         if (vmx->vmcs) {
2510                 on_each_cpu(__vcpu_clear, vmx, 0, 1);
2511                 free_vmcs(vmx->vmcs);
2512                 vmx->vmcs = NULL;
2513         }
2514 }
2515
2516 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
2517 {
2518         struct vcpu_vmx *vmx = to_vmx(vcpu);
2519
2520         vmx_free_vmcs(vcpu);
2521         kfree(vmx->host_msrs);
2522         kfree(vmx->guest_msrs);
2523         kvm_vcpu_uninit(vcpu);
2524         kmem_cache_free(kvm_vcpu_cache, vmx);
2525 }
2526
2527 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
2528 {
2529         int err;
2530         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
2531         int cpu;
2532
2533         if (!vmx)
2534                 return ERR_PTR(-ENOMEM);
2535
2536         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
2537         if (err)
2538                 goto free_vcpu;
2539
2540         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2541         if (!vmx->guest_msrs) {
2542                 err = -ENOMEM;
2543                 goto uninit_vcpu;
2544         }
2545
2546         vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
2547         if (!vmx->host_msrs)
2548                 goto free_guest_msrs;
2549
2550         vmx->vmcs = alloc_vmcs();
2551         if (!vmx->vmcs)
2552                 goto free_msrs;
2553
2554         vmcs_clear(vmx->vmcs);
2555
2556         cpu = get_cpu();
2557         vmx_vcpu_load(&vmx->vcpu, cpu);
2558         err = vmx_vcpu_setup(vmx);
2559         vmx_vcpu_put(&vmx->vcpu);
2560         put_cpu();
2561         if (err)
2562                 goto free_vmcs;
2563
2564         return &vmx->vcpu;
2565
2566 free_vmcs:
2567         free_vmcs(vmx->vmcs);
2568 free_msrs:
2569         kfree(vmx->host_msrs);
2570 free_guest_msrs:
2571         kfree(vmx->guest_msrs);
2572 uninit_vcpu:
2573         kvm_vcpu_uninit(&vmx->vcpu);
2574 free_vcpu:
2575         kmem_cache_free(kvm_vcpu_cache, vmx);
2576         return ERR_PTR(err);
2577 }
2578
2579 static void __init vmx_check_processor_compat(void *rtn)
2580 {
2581         struct vmcs_config vmcs_conf;
2582
2583         *(int *)rtn = 0;
2584         if (setup_vmcs_config(&vmcs_conf) < 0)
2585                 *(int *)rtn = -EIO;
2586         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
2587                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
2588                                 smp_processor_id());
2589                 *(int *)rtn = -EIO;
2590         }
2591 }
2592
2593 static struct kvm_x86_ops vmx_x86_ops = {
2594         .cpu_has_kvm_support = cpu_has_kvm_support,
2595         .disabled_by_bios = vmx_disabled_by_bios,
2596         .hardware_setup = hardware_setup,
2597         .hardware_unsetup = hardware_unsetup,
2598         .check_processor_compatibility = vmx_check_processor_compat,
2599         .hardware_enable = hardware_enable,
2600         .hardware_disable = hardware_disable,
2601
2602         .vcpu_create = vmx_create_vcpu,
2603         .vcpu_free = vmx_free_vcpu,
2604         .vcpu_reset = vmx_vcpu_reset,
2605
2606         .prepare_guest_switch = vmx_save_host_state,
2607         .vcpu_load = vmx_vcpu_load,
2608         .vcpu_put = vmx_vcpu_put,
2609         .vcpu_decache = vmx_vcpu_decache,
2610
2611         .set_guest_debug = set_guest_debug,
2612         .guest_debug_pre = kvm_guest_debug_pre,
2613         .get_msr = vmx_get_msr,
2614         .set_msr = vmx_set_msr,
2615         .get_segment_base = vmx_get_segment_base,
2616         .get_segment = vmx_get_segment,
2617         .set_segment = vmx_set_segment,
2618         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
2619         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
2620         .set_cr0 = vmx_set_cr0,
2621         .set_cr3 = vmx_set_cr3,
2622         .set_cr4 = vmx_set_cr4,
2623 #ifdef CONFIG_X86_64
2624         .set_efer = vmx_set_efer,
2625 #endif
2626         .get_idt = vmx_get_idt,
2627         .set_idt = vmx_set_idt,
2628         .get_gdt = vmx_get_gdt,
2629         .set_gdt = vmx_set_gdt,
2630         .cache_regs = vcpu_load_rsp_rip,
2631         .decache_regs = vcpu_put_rsp_rip,
2632         .get_rflags = vmx_get_rflags,
2633         .set_rflags = vmx_set_rflags,
2634
2635         .tlb_flush = vmx_flush_tlb,
2636         .inject_page_fault = vmx_inject_page_fault,
2637
2638         .inject_gp = vmx_inject_gp,
2639
2640         .run = vmx_vcpu_run,
2641         .handle_exit = kvm_handle_exit,
2642         .skip_emulated_instruction = skip_emulated_instruction,
2643         .patch_hypercall = vmx_patch_hypercall,
2644         .get_irq = vmx_get_irq,
2645         .set_irq = vmx_inject_irq,
2646         .inject_pending_irq = vmx_intr_assist,
2647         .inject_pending_vectors = do_interrupt_requests,
2648
2649         .set_tss_addr = vmx_set_tss_addr,
2650 };
2651
2652 static int __init vmx_init(void)
2653 {
2654         void *iova;
2655         int r;
2656
2657         vmx_io_bitmap_a = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2658         if (!vmx_io_bitmap_a)
2659                 return -ENOMEM;
2660
2661         vmx_io_bitmap_b = alloc_page(GFP_KERNEL | __GFP_HIGHMEM);
2662         if (!vmx_io_bitmap_b) {
2663                 r = -ENOMEM;
2664                 goto out;
2665         }
2666
2667         /*
2668          * Allow direct access to the PC debug port (it is often used for I/O
2669          * delays, but the vmexits simply slow things down).
2670          */
2671         iova = kmap(vmx_io_bitmap_a);
2672         memset(iova, 0xff, PAGE_SIZE);
2673         clear_bit(0x80, iova);
2674         kunmap(vmx_io_bitmap_a);
2675
2676         iova = kmap(vmx_io_bitmap_b);
2677         memset(iova, 0xff, PAGE_SIZE);
2678         kunmap(vmx_io_bitmap_b);
2679
2680         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
2681         if (r)
2682                 goto out1;
2683
2684         if (bypass_guest_pf)
2685                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
2686
2687         return 0;
2688
2689 out1:
2690         __free_page(vmx_io_bitmap_b);
2691 out:
2692         __free_page(vmx_io_bitmap_a);
2693         return r;
2694 }
2695
2696 static void __exit vmx_exit(void)
2697 {
2698         __free_page(vmx_io_bitmap_b);
2699         __free_page(vmx_io_bitmap_a);
2700
2701         kvm_exit();
2702 }
2703
2704 module_init(vmx_init)
2705 module_exit(vmx_exit)