drivers/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16
  17 #include "kvm_svm.h"
  18 #include "x86_emulate.h"
  19 #include "irq.h"
  20
  21 #include <linux/module.h>
  22 #include <linux/kernel.h>
  23 #include <linux/vmalloc.h>
  24 #include <linux/highmem.h>
  25 #include <linux/sched.h>
  26
  27 #include <asm/desc.h>
  28
  29 MODULE_AUTHOR("Qumranet");
  30 MODULE_LICENSE("GPL");
  31
  32 #define IOPM_ALLOC_ORDER 2
  33 #define MSRPM_ALLOC_ORDER 1
  34
  35 #define DB_VECTOR 1
  36 #define UD_VECTOR 6
  37 #define GP_VECTOR 13
  38
  39 #define DR7_GD_MASK (1 << 13)
  40 #define DR6_BD_MASK (1 << 13)
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define KVM_EFER_LMA (1 << 10)
  46 #define KVM_EFER_LME (1 << 8)
  47
  48 #define SVM_FEATURE_NPT  (1 << 0)
  49 #define SVM_FEATURE_LBRV (1 << 1)
  50 #define SVM_DEATURE_SVML (1 << 2)
  51
  52 static void kvm_reput_irq(struct vcpu_svm *svm);
  53
  54 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  55 {
  56         return container_of(vcpu, struct vcpu_svm, vcpu);
  57 }
  58
  59 unsigned long iopm_base;
  60 unsigned long msrpm_base;
  61
  62 struct kvm_ldttss_desc {
  63         u16 limit0;
  64         u16 base0;
  65         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  66         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  67         u32 base3;
  68         u32 zero1;
  69 } __attribute__((packed));
  70
  71 struct svm_cpu_data {
  72         int cpu;
  73
  74         u64 asid_generation;
  75         u32 max_asid;
  76         u32 next_asid;
  77         struct kvm_ldttss_desc *tss_desc;
  78
  79         struct page *save_area;
  80 };
  81
  82 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  83 static uint32_t svm_features;
  84
  85 struct svm_init_data {
  86         int cpu;
  87         int r;
  88 };
  89
  90 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  91
  92 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  93 #define MSRS_RANGE_SIZE 2048
  94 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  95
  96 #define MAX_INST_SIZE 15
  97
  98 static inline u32 svm_has(u32 feat)
  99 {
 100         return svm_features & feat;
 101 }
 102
 103 static inline u8 pop_irq(struct kvm_vcpu *vcpu)
 104 {
 105         int word_index = __ffs(vcpu->irq_summary);
 106         int bit_index = __ffs(vcpu->irq_pending[word_index]);
 107         int irq = word_index * BITS_PER_LONG + bit_index;
 108
 109         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
 110         if (!vcpu->irq_pending[word_index])
 111                 clear_bit(word_index, &vcpu->irq_summary);
 112         return irq;
 113 }
 114
 115 static inline void push_irq(struct kvm_vcpu *vcpu, u8 irq)
 116 {
 117         set_bit(irq, vcpu->irq_pending);
 118         set_bit(irq / BITS_PER_LONG, &vcpu->irq_summary);
 119 }
 120
 121 static inline void clgi(void)
 122 {
 123         asm volatile (SVM_CLGI);
 124 }
 125
 126 static inline void stgi(void)
 127 {
 128         asm volatile (SVM_STGI);
 129 }
 130
 131 static inline void invlpga(unsigned long addr, u32 asid)
 132 {
 133         asm volatile (SVM_INVLPGA :: "a"(addr), "c"(asid));
 134 }
 135
 136 static inline unsigned long kvm_read_cr2(void)
 137 {
 138         unsigned long cr2;
 139
 140         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 141         return cr2;
 142 }
 143
 144 static inline void kvm_write_cr2(unsigned long val)
 145 {
 146         asm volatile ("mov %0, %%cr2" :: "r" (val));
 147 }
 148
 149 static inline unsigned long read_dr6(void)
 150 {
 151         unsigned long dr6;
 152
 153         asm volatile ("mov %%dr6, %0" : "=r" (dr6));
 154         return dr6;
 155 }
 156
 157 static inline void write_dr6(unsigned long val)
 158 {
 159         asm volatile ("mov %0, %%dr6" :: "r" (val));
 160 }
 161
 162 static inline unsigned long read_dr7(void)
 163 {
 164         unsigned long dr7;
 165
 166         asm volatile ("mov %%dr7, %0" : "=r" (dr7));
 167         return dr7;
 168 }
 169
 170 static inline void write_dr7(unsigned long val)
 171 {
 172         asm volatile ("mov %0, %%dr7" :: "r" (val));
 173 }
 174
 175 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 176 {
 177         to_svm(vcpu)->asid_generation--;
 178 }
 179
 180 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 181 {
 182         force_new_asid(vcpu);
 183 }
 184
 185 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 186 {
 187         if (!(efer & KVM_EFER_LMA))
 188                 efer &= ~KVM_EFER_LME;
 189
 190         to_svm(vcpu)->vmcb->save.efer = efer | MSR_EFER_SVME_MASK;
 191         vcpu->shadow_efer = efer;
 192 }
 193
 194 static void svm_inject_gp(struct kvm_vcpu *vcpu, unsigned error_code)
 195 {
 196         struct vcpu_svm *svm = to_svm(vcpu);
 197
 198         svm->vmcb->control.event_inj =          SVM_EVTINJ_VALID |
 199                                                 SVM_EVTINJ_VALID_ERR |
 200                                                 SVM_EVTINJ_TYPE_EXEPT |
 201                                                 GP_VECTOR;
 202         svm->vmcb->control.event_inj_err = error_code;
 203 }
 204
 205 static void inject_ud(struct kvm_vcpu *vcpu)
 206 {
 207         to_svm(vcpu)->vmcb->control.event_inj = SVM_EVTINJ_VALID |
 208                                                 SVM_EVTINJ_TYPE_EXEPT |
 209                                                 UD_VECTOR;
 210 }
 211
 212 static int is_page_fault(uint32_t info)
 213 {
 214         info &= SVM_EVTINJ_VEC_MASK | SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 215         return info == (PF_VECTOR | SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_EXEPT);
 216 }
 217
 218 static int is_external_interrupt(u32 info)
 219 {
 220         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 221         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 222 }
 223
 224 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 225 {
 226         struct vcpu_svm *svm = to_svm(vcpu);
 227
 228         if (!svm->next_rip) {
 229                 printk(KERN_DEBUG "%s: NOP\n", __FUNCTION__);
 230                 return;
 231         }
 232         if (svm->next_rip - svm->vmcb->save.rip > MAX_INST_SIZE) {
 233                 printk(KERN_ERR "%s: ip 0x%llx next 0x%llx\n",
 234                        __FUNCTION__,
 235                        svm->vmcb->save.rip,
 236                        svm->next_rip);
 237         }
 238
 239         vcpu->rip = svm->vmcb->save.rip = svm->next_rip;
 240         svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 241
 242         vcpu->interrupt_window_open = 1;
 243 }
 244
 245 static int has_svm(void)
 246 {
 247         uint32_t eax, ebx, ecx, edx;
 248
 249         if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) {
 250                 printk(KERN_INFO "has_svm: not amd\n");
 251                 return 0;
 252         }
 253
 254         cpuid(0x80000000, &eax, &ebx, &ecx, &edx);
 255         if (eax < SVM_CPUID_FUNC) {
 256                 printk(KERN_INFO "has_svm: can't execute cpuid_8000000a\n");
 257                 return 0;
 258         }
 259
 260         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
 261         if (!(ecx & (1 << SVM_CPUID_FEATURE_SHIFT))) {
 262                 printk(KERN_DEBUG "has_svm: svm not available\n");
 263                 return 0;
 264         }
 265         return 1;
 266 }
 267
 268 static void svm_hardware_disable(void *garbage)
 269 {
 270         struct svm_cpu_data *svm_data
 271                 = per_cpu(svm_data, raw_smp_processor_id());
 272
 273         if (svm_data) {
 274                 uint64_t efer;
 275
 276                 wrmsrl(MSR_VM_HSAVE_PA, 0);
 277                 rdmsrl(MSR_EFER, efer);
 278                 wrmsrl(MSR_EFER, efer & ~MSR_EFER_SVME_MASK);
 279                 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 280                 __free_page(svm_data->save_area);
 281                 kfree(svm_data);
 282         }
 283 }
 284
 285 static void svm_hardware_enable(void *garbage)
 286 {
 287
 288         struct svm_cpu_data *svm_data;
 289         uint64_t efer;
 290 #ifdef CONFIG_X86_64
 291         struct desc_ptr gdt_descr;
 292 #else
 293         struct desc_ptr gdt_descr;
 294 #endif
 295         struct desc_struct *gdt;
 296         int me = raw_smp_processor_id();
 297
 298         if (!has_svm()) {
 299                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 300                 return;
 301         }
 302         svm_data = per_cpu(svm_data, me);
 303
 304         if (!svm_data) {
 305                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 306                        me);
 307                 return;
 308         }
 309
 310         svm_data->asid_generation = 1;
 311         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 312         svm_data->next_asid = svm_data->max_asid + 1;
 313         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 314
 315         asm volatile ( "sgdt %0" : "=m"(gdt_descr) );
 316         gdt = (struct desc_struct *)gdt_descr.address;
 317         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 318
 319         rdmsrl(MSR_EFER, efer);
 320         wrmsrl(MSR_EFER, efer | MSR_EFER_SVME_MASK);
 321
 322         wrmsrl(MSR_VM_HSAVE_PA,
 323                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 324 }
 325
 326 static int svm_cpu_init(int cpu)
 327 {
 328         struct svm_cpu_data *svm_data;
 329         int r;
 330
 331         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 332         if (!svm_data)
 333                 return -ENOMEM;
 334         svm_data->cpu = cpu;
 335         svm_data->save_area = alloc_page(GFP_KERNEL);
 336         r = -ENOMEM;
 337         if (!svm_data->save_area)
 338                 goto err_1;
 339
 340         per_cpu(svm_data, cpu) = svm_data;
 341
 342         return 0;
 343
 344 err_1:
 345         kfree(svm_data);
 346         return r;
 347
 348 }
 349
 350 static void set_msr_interception(u32 *msrpm, unsigned msr,
 351                                  int read, int write)
 352 {
 353         int i;
 354
 355         for (i = 0; i < NUM_MSR_MAPS; i++) {
 356                 if (msr >= msrpm_ranges[i] &&
 357                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 358                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 359                                           msrpm_ranges[i]) * 2;
 360
 361                         u32 *base = msrpm + (msr_offset / 32);
 362                         u32 msr_shift = msr_offset % 32;
 363                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 364                         *base = (*base & ~(0x3 << msr_shift)) |
 365                                 (mask << msr_shift);
 366                         return;
 367                 }
 368         }
 369         BUG();
 370 }
 371
 372 static __init int svm_hardware_setup(void)
 373 {
 374         int cpu;
 375         struct page *iopm_pages;
 376         struct page *msrpm_pages;
 377         void *iopm_va, *msrpm_va;
 378         int r;
 379
 380         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 381
 382         if (!iopm_pages)
 383                 return -ENOMEM;
 384
 385         iopm_va = page_address(iopm_pages);
 386         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 387         clear_bit(0x80, iopm_va); /* allow direct access to PC debug port */
 388         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 389
 390
 391         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 392
 393         r = -ENOMEM;
 394         if (!msrpm_pages)
 395                 goto err_1;
 396
 397         msrpm_va = page_address(msrpm_pages);
 398         memset(msrpm_va, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 399         msrpm_base = page_to_pfn(msrpm_pages) << PAGE_SHIFT;
 400
 401 #ifdef CONFIG_X86_64
 402         set_msr_interception(msrpm_va, MSR_GS_BASE, 1, 1);
 403         set_msr_interception(msrpm_va, MSR_FS_BASE, 1, 1);
 404         set_msr_interception(msrpm_va, MSR_KERNEL_GS_BASE, 1, 1);
 405         set_msr_interception(msrpm_va, MSR_LSTAR, 1, 1);
 406         set_msr_interception(msrpm_va, MSR_CSTAR, 1, 1);
 407         set_msr_interception(msrpm_va, MSR_SYSCALL_MASK, 1, 1);
 408 #endif
 409         set_msr_interception(msrpm_va, MSR_K6_STAR, 1, 1);
 410         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_CS, 1, 1);
 411         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_ESP, 1, 1);
 412         set_msr_interception(msrpm_va, MSR_IA32_SYSENTER_EIP, 1, 1);
 413
 414         for_each_online_cpu(cpu) {
 415                 r = svm_cpu_init(cpu);
 416                 if (r)
 417                         goto err_2;
 418         }
 419         return 0;
 420
 421 err_2:
 422         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 423         msrpm_base = 0;
 424 err_1:
 425         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 426         iopm_base = 0;
 427         return r;
 428 }
 429
 430 static __exit void svm_hardware_unsetup(void)
 431 {
 432         __free_pages(pfn_to_page(msrpm_base >> PAGE_SHIFT), MSRPM_ALLOC_ORDER);
 433         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 434         iopm_base = msrpm_base = 0;
 435 }
 436
 437 static void init_seg(struct vmcb_seg *seg)
 438 {
 439         seg->selector = 0;
 440         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 441                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 442         seg->limit = 0xffff;
 443         seg->base = 0;
 444 }
 445
 446 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 447 {
 448         seg->selector = 0;
 449         seg->attrib = SVM_SELECTOR_P_MASK | type;
 450         seg->limit = 0xffff;
 451         seg->base = 0;
 452 }
 453
 454 static void init_vmcb(struct vmcb *vmcb)
 455 {
 456         struct vmcb_control_area *control = &vmcb->control;
 457         struct vmcb_save_area *save = &vmcb->save;
 458
 459         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 460                                         INTERCEPT_CR3_MASK |
 461                                         INTERCEPT_CR4_MASK;
 462
 463         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 464                                         INTERCEPT_CR3_MASK |
 465                                         INTERCEPT_CR4_MASK;
 466
 467         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 468                                         INTERCEPT_DR1_MASK |
 469                                         INTERCEPT_DR2_MASK |
 470                                         INTERCEPT_DR3_MASK;
 471
 472         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 473                                         INTERCEPT_DR1_MASK |
 474                                         INTERCEPT_DR2_MASK |
 475                                         INTERCEPT_DR3_MASK |
 476                                         INTERCEPT_DR5_MASK |
 477                                         INTERCEPT_DR7_MASK;
 478
 479         control->intercept_exceptions = (1 << PF_VECTOR) |
 480                                         (1 << UD_VECTOR);
 481
 482
 483         control->intercept =    (1ULL << INTERCEPT_INTR) |
 484                                 (1ULL << INTERCEPT_NMI) |
 485                                 (1ULL << INTERCEPT_SMI) |
 486                 /*
 487                  * selective cr0 intercept bug?
 488                  *      0:   0f 22 d8                mov    %eax,%cr3
 489                  *      3:   0f 20 c0                mov    %cr0,%eax
 490                  *      6:   0d 00 00 00 80          or     $0x80000000,%eax
 491                  *      b:   0f 22 c0                mov    %eax,%cr0
 492                  * set cr3 ->interception
 493                  * get cr0 ->interception
 494                  * set cr0 -> no interception
 495                  */
 496                 /*              (1ULL << INTERCEPT_SELECTIVE_CR0) | */
 497                                 (1ULL << INTERCEPT_CPUID) |
 498                                 (1ULL << INTERCEPT_INVD) |
 499                                 (1ULL << INTERCEPT_HLT) |
 500                                 (1ULL << INTERCEPT_INVLPGA) |
 501                                 (1ULL << INTERCEPT_IOIO_PROT) |
 502                                 (1ULL << INTERCEPT_MSR_PROT) |
 503                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 504                                 (1ULL << INTERCEPT_SHUTDOWN) |
 505                                 (1ULL << INTERCEPT_VMRUN) |
 506                                 (1ULL << INTERCEPT_VMMCALL) |
 507                                 (1ULL << INTERCEPT_VMLOAD) |
 508                                 (1ULL << INTERCEPT_VMSAVE) |
 509                                 (1ULL << INTERCEPT_STGI) |
 510                                 (1ULL << INTERCEPT_CLGI) |
 511                                 (1ULL << INTERCEPT_SKINIT) |
 512                                 (1ULL << INTERCEPT_WBINVD) |
 513                                 (1ULL << INTERCEPT_MONITOR) |
 514                                 (1ULL << INTERCEPT_MWAIT);
 515
 516         control->iopm_base_pa = iopm_base;
 517         control->msrpm_base_pa = msrpm_base;
 518         control->tsc_offset = 0;
 519         control->int_ctl = V_INTR_MASKING_MASK;
 520
 521         init_seg(&save->es);
 522         init_seg(&save->ss);
 523         init_seg(&save->ds);
 524         init_seg(&save->fs);
 525         init_seg(&save->gs);
 526
 527         save->cs.selector = 0xf000;
 528         /* Executable/Readable Code Segment */
 529         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 530                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 531         save->cs.limit = 0xffff;
 532         /*
 533          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 534          * be consistent with it.
 535          *
 536          * Replace when we have real mode working for vmx.
 537          */
 538         save->cs.base = 0xf0000;
 539
 540         save->gdtr.limit = 0xffff;
 541         save->idtr.limit = 0xffff;
 542
 543         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 544         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 545
 546         save->efer = MSR_EFER_SVME_MASK;
 547
 548         save->dr6 = 0xffff0ff0;
 549         save->dr7 = 0x400;
 550         save->rflags = 2;
 551         save->rip = 0x0000fff0;
 552
 553         /*
 554          * cr0 val on cpu init should be 0x60000010, we enable cpu
 555          * cache by default. the orderly way is to enable cache in bios.
 556          */
 557         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 558         save->cr4 = X86_CR4_PAE;
 559         /* rdx = ?? */
 560 }
 561
 562 static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
 563 {
 564         struct vcpu_svm *svm = to_svm(vcpu);
 565
 566         init_vmcb(svm->vmcb);
 567
 568         if (vcpu->vcpu_id != 0) {
 569                 svm->vmcb->save.rip = 0;
 570                 svm->vmcb->save.cs.base = svm->vcpu.sipi_vector << 12;
 571                 svm->vmcb->save.cs.selector = svm->vcpu.sipi_vector << 8;
 572         }
 573 }
 574
 575 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 576 {
 577         struct vcpu_svm *svm;
 578         struct page *page;
 579         int err;
 580
 581         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 582         if (!svm) {
 583                 err = -ENOMEM;
 584                 goto out;
 585         }
 586
 587         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 588         if (err)
 589                 goto free_svm;
 590
 591         if (irqchip_in_kernel(kvm)) {
 592                 err = kvm_create_lapic(&svm->vcpu);
 593                 if (err < 0)
 594                         goto free_svm;
 595         }
 596
 597         page = alloc_page(GFP_KERNEL);
 598         if (!page) {
 599                 err = -ENOMEM;
 600                 goto uninit;
 601         }
 602
 603         svm->vmcb = page_address(page);
 604         clear_page(svm->vmcb);
 605         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 606         svm->asid_generation = 0;
 607         memset(svm->db_regs, 0, sizeof(svm->db_regs));
 608         init_vmcb(svm->vmcb);
 609
 610         fx_init(&svm->vcpu);
 611         svm->vcpu.fpu_active = 1;
 612         svm->vcpu.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 613         if (svm->vcpu.vcpu_id == 0)
 614                 svm->vcpu.apic_base |= MSR_IA32_APICBASE_BSP;
 615
 616         return &svm->vcpu;
 617
 618 uninit:
 619         kvm_vcpu_uninit(&svm->vcpu);
 620 free_svm:
 621         kmem_cache_free(kvm_vcpu_cache, svm);
 622 out:
 623         return ERR_PTR(err);
 624 }
 625
 626 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 627 {
 628         struct vcpu_svm *svm = to_svm(vcpu);
 629
 630         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 631         kvm_vcpu_uninit(vcpu);
 632         kmem_cache_free(kvm_vcpu_cache, svm);
 633 }
 634
 635 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 636 {
 637         struct vcpu_svm *svm = to_svm(vcpu);
 638         int i;
 639
 640         if (unlikely(cpu != vcpu->cpu)) {
 641                 u64 tsc_this, delta;
 642
 643                 /*
 644                  * Make sure that the guest sees a monotonically
 645                  * increasing TSC.
 646                  */
 647                 rdtscll(tsc_this);
 648                 delta = vcpu->host_tsc - tsc_this;
 649                 svm->vmcb->control.tsc_offset += delta;
 650                 vcpu->cpu = cpu;
 651                 kvm_migrate_apic_timer(vcpu);
 652         }
 653
 654         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 655                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 656 }
 657
 658 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 659 {
 660         struct vcpu_svm *svm = to_svm(vcpu);
 661         int i;
 662
 663         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 664                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 665
 666         rdtscll(vcpu->host_tsc);
 667         kvm_put_guest_fpu(vcpu);
 668 }
 669
 670 static void svm_vcpu_decache(struct kvm_vcpu *vcpu)
 671 {
 672 }
 673
 674 static void svm_cache_regs(struct kvm_vcpu *vcpu)
 675 {
 676         struct vcpu_svm *svm = to_svm(vcpu);
 677
 678         vcpu->regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
 679         vcpu->regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
 680         vcpu->rip = svm->vmcb->save.rip;
 681 }
 682
 683 static void svm_decache_regs(struct kvm_vcpu *vcpu)
 684 {
 685         struct vcpu_svm *svm = to_svm(vcpu);
 686         svm->vmcb->save.rax = vcpu->regs[VCPU_REGS_RAX];
 687         svm->vmcb->save.rsp = vcpu->regs[VCPU_REGS_RSP];
 688         svm->vmcb->save.rip = vcpu->rip;
 689 }
 690
 691 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 692 {
 693         return to_svm(vcpu)->vmcb->save.rflags;
 694 }
 695
 696 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 697 {
 698         to_svm(vcpu)->vmcb->save.rflags = rflags;
 699 }
 700
 701 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 702 {
 703         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 704
 705         switch (seg) {
 706         case VCPU_SREG_CS: return &save->cs;
 707         case VCPU_SREG_DS: return &save->ds;
 708         case VCPU_SREG_ES: return &save->es;
 709         case VCPU_SREG_FS: return &save->fs;
 710         case VCPU_SREG_GS: return &save->gs;
 711         case VCPU_SREG_SS: return &save->ss;
 712         case VCPU_SREG_TR: return &save->tr;
 713         case VCPU_SREG_LDTR: return &save->ldtr;
 714         }
 715         BUG();
 716         return NULL;
 717 }
 718
 719 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 720 {
 721         struct vmcb_seg *s = svm_seg(vcpu, seg);
 722
 723         return s->base;
 724 }
 725
 726 static void svm_get_segment(struct kvm_vcpu *vcpu,
 727                             struct kvm_segment *var, int seg)
 728 {
 729         struct vmcb_seg *s = svm_seg(vcpu, seg);
 730
 731         var->base = s->base;
 732         var->limit = s->limit;
 733         var->selector = s->selector;
 734         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 735         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 736         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 737         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 738         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 739         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 740         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 741         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 742         var->unusable = !var->present;
 743 }
 744
 745 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 746 {
 747         struct vcpu_svm *svm = to_svm(vcpu);
 748
 749         dt->limit = svm->vmcb->save.idtr.limit;
 750         dt->base = svm->vmcb->save.idtr.base;
 751 }
 752
 753 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 754 {
 755         struct vcpu_svm *svm = to_svm(vcpu);
 756
 757         svm->vmcb->save.idtr.limit = dt->limit;
 758         svm->vmcb->save.idtr.base = dt->base ;
 759 }
 760
 761 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 762 {
 763         struct vcpu_svm *svm = to_svm(vcpu);
 764
 765         dt->limit = svm->vmcb->save.gdtr.limit;
 766         dt->base = svm->vmcb->save.gdtr.base;
 767 }
 768
 769 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 770 {
 771         struct vcpu_svm *svm = to_svm(vcpu);
 772
 773         svm->vmcb->save.gdtr.limit = dt->limit;
 774         svm->vmcb->save.gdtr.base = dt->base ;
 775 }
 776
 777 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 778 {
 779 }
 780
 781 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 782 {
 783         struct vcpu_svm *svm = to_svm(vcpu);
 784
 785 #ifdef CONFIG_X86_64
 786         if (vcpu->shadow_efer & KVM_EFER_LME) {
 787                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 788                         vcpu->shadow_efer |= KVM_EFER_LMA;
 789                         svm->vmcb->save.efer |= KVM_EFER_LMA | KVM_EFER_LME;
 790                 }
 791
 792                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG) ) {
 793                         vcpu->shadow_efer &= ~KVM_EFER_LMA;
 794                         svm->vmcb->save.efer &= ~(KVM_EFER_LMA | KVM_EFER_LME);
 795                 }
 796         }
 797 #endif
 798         if ((vcpu->cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 799                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 800                 vcpu->fpu_active = 1;
 801         }
 802
 803         vcpu->cr0 = cr0;
 804         cr0 |= X86_CR0_PG | X86_CR0_WP;
 805         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 806         svm->vmcb->save.cr0 = cr0;
 807 }
 808
 809 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 810 {
 811        vcpu->cr4 = cr4;
 812        to_svm(vcpu)->vmcb->save.cr4 = cr4 | X86_CR4_PAE;
 813 }
 814
 815 static void svm_set_segment(struct kvm_vcpu *vcpu,
 816                             struct kvm_segment *var, int seg)
 817 {
 818         struct vcpu_svm *svm = to_svm(vcpu);
 819         struct vmcb_seg *s = svm_seg(vcpu, seg);
 820
 821         s->base = var->base;
 822         s->limit = var->limit;
 823         s->selector = var->selector;
 824         if (var->unusable)
 825                 s->attrib = 0;
 826         else {
 827                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 828                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 829                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 830                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 831                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 832                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 833                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 834                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 835         }
 836         if (seg == VCPU_SREG_CS)
 837                 svm->vmcb->save.cpl
 838                         = (svm->vmcb->save.cs.attrib
 839                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 840
 841 }
 842
 843 /* FIXME:
 844
 845         svm(vcpu)->vmcb->control.int_ctl &= ~V_TPR_MASK;
 846         svm(vcpu)->vmcb->control.int_ctl |= (sregs->cr8 & V_TPR_MASK);
 847
 848 */
 849
 850 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_debug_guest *dbg)
 851 {
 852         return -EOPNOTSUPP;
 853 }
 854
 855 static int svm_get_irq(struct kvm_vcpu *vcpu)
 856 {
 857         struct vcpu_svm *svm = to_svm(vcpu);
 858         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 859
 860         if (is_external_interrupt(exit_int_info))
 861                 return exit_int_info & SVM_EVTINJ_VEC_MASK;
 862         return -1;
 863 }
 864
 865 static void load_host_msrs(struct kvm_vcpu *vcpu)
 866 {
 867 #ifdef CONFIG_X86_64
 868         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 869 #endif
 870 }
 871
 872 static void save_host_msrs(struct kvm_vcpu *vcpu)
 873 {
 874 #ifdef CONFIG_X86_64
 875         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
 876 #endif
 877 }
 878
 879 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
 880 {
 881         if (svm_data->next_asid > svm_data->max_asid) {
 882                 ++svm_data->asid_generation;
 883                 svm_data->next_asid = 1;
 884                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
 885         }
 886
 887         svm->vcpu.cpu = svm_data->cpu;
 888         svm->asid_generation = svm_data->asid_generation;
 889         svm->vmcb->control.asid = svm_data->next_asid++;
 890 }
 891
 892 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
 893 {
 894         return to_svm(vcpu)->db_regs[dr];
 895 }
 896
 897 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
 898                        int *exception)
 899 {
 900         struct vcpu_svm *svm = to_svm(vcpu);
 901
 902         *exception = 0;
 903
 904         if (svm->vmcb->save.dr7 & DR7_GD_MASK) {
 905                 svm->vmcb->save.dr7 &= ~DR7_GD_MASK;
 906                 svm->vmcb->save.dr6 |= DR6_BD_MASK;
 907                 *exception = DB_VECTOR;
 908                 return;
 909         }
 910
 911         switch (dr) {
 912         case 0 ... 3:
 913                 svm->db_regs[dr] = value;
 914                 return;
 915         case 4 ... 5:
 916                 if (vcpu->cr4 & X86_CR4_DE) {
 917                         *exception = UD_VECTOR;
 918                         return;
 919                 }
 920         case 7: {
 921                 if (value & ~((1ULL << 32) - 1)) {
 922                         *exception = GP_VECTOR;
 923                         return;
 924                 }
 925                 svm->vmcb->save.dr7 = value;
 926                 return;
 927         }
 928         default:
 929                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
 930                        __FUNCTION__, dr);
 931                 *exception = UD_VECTOR;
 932                 return;
 933         }
 934 }
 935
 936 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 937 {
 938         u32 exit_int_info = svm->vmcb->control.exit_int_info;
 939         struct kvm *kvm = svm->vcpu.kvm;
 940         u64 fault_address;
 941         u32 error_code;
 942         enum emulation_result er;
 943         int r;
 944
 945         if (!irqchip_in_kernel(kvm) &&
 946                 is_external_interrupt(exit_int_info))
 947                 push_irq(&svm->vcpu, exit_int_info & SVM_EVTINJ_VEC_MASK);
 948
 949         mutex_lock(&kvm->lock);
 950
 951         fault_address  = svm->vmcb->control.exit_info_2;
 952         error_code = svm->vmcb->control.exit_info_1;
 953         r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
 954         if (r < 0) {
 955                 mutex_unlock(&kvm->lock);
 956                 return r;
 957         }
 958         if (!r) {
 959                 mutex_unlock(&kvm->lock);
 960                 return 1;
 961         }
 962         er = emulate_instruction(&svm->vcpu, kvm_run, fault_address,
 963                                  error_code, 0);
 964         mutex_unlock(&kvm->lock);
 965
 966         switch (er) {
 967         case EMULATE_DONE:
 968                 return 1;
 969         case EMULATE_DO_MMIO:
 970                 ++svm->vcpu.stat.mmio_exits;
 971                 return 0;
 972         case EMULATE_FAIL:
 973                 kvm_report_emulation_failure(&svm->vcpu, "pagetable");
 974                 break;
 975         default:
 976                 BUG();
 977         }
 978
 979         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
 980         return 0;
 981 }
 982
 983 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 984 {
 985         int er;
 986
 987         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0);
 988         if (er != EMULATE_DONE)
 989                 inject_ud(&svm->vcpu);
 990
 991         return 1;
 992 }
 993
 994 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
 995 {
 996         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 997         if (!(svm->vcpu.cr0 & X86_CR0_TS))
 998                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
 999         svm->vcpu.fpu_active = 1;
1000
1001         return 1;
1002 }
1003
1004 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1005 {
1006         /*
1007          * VMCB is undefined after a SHUTDOWN intercept
1008          * so reinitialize it.
1009          */
1010         clear_page(svm->vmcb);
1011         init_vmcb(svm->vmcb);
1012
1013         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1014         return 0;
1015 }
1016
1017 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1018 {
1019         u32 io_info = svm->vmcb->control.exit_info_1; //address size bug?
1020         int size, down, in, string, rep;
1021         unsigned port;
1022
1023         ++svm->vcpu.stat.io_exits;
1024
1025         svm->next_rip = svm->vmcb->control.exit_info_2;
1026
1027         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1028
1029         if (string) {
1030                 if (emulate_instruction(&svm->vcpu,
1031                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1032                         return 0;
1033                 return 1;
1034         }
1035
1036         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1037         port = io_info >> 16;
1038         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1039         rep = (io_info & SVM_IOIO_REP_MASK) != 0;
1040         down = (svm->vmcb->save.rflags & X86_EFLAGS_DF) != 0;
1041
1042         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1043 }
1044
1045 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1046 {
1047         return 1;
1048 }
1049
1050 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1051 {
1052         svm->next_rip = svm->vmcb->save.rip + 1;
1053         skip_emulated_instruction(&svm->vcpu);
1054         return kvm_emulate_halt(&svm->vcpu);
1055 }
1056
1057 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1058 {
1059         svm->next_rip = svm->vmcb->save.rip + 3;
1060         skip_emulated_instruction(&svm->vcpu);
1061         kvm_emulate_hypercall(&svm->vcpu);
1062         return 1;
1063 }
1064
1065 static int invalid_op_interception(struct vcpu_svm *svm,
1066                                    struct kvm_run *kvm_run)
1067 {
1068         inject_ud(&svm->vcpu);
1069         return 1;
1070 }
1071
1072 static int task_switch_interception(struct vcpu_svm *svm,
1073                                     struct kvm_run *kvm_run)
1074 {
1075         pr_unimpl(&svm->vcpu, "%s: task switch is unsupported\n", __FUNCTION__);
1076         kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1077         return 0;
1078 }
1079
1080 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1081 {
1082         svm->next_rip = svm->vmcb->save.rip + 2;
1083         kvm_emulate_cpuid(&svm->vcpu);
1084         return 1;
1085 }
1086
1087 static int emulate_on_interception(struct vcpu_svm *svm,
1088                                    struct kvm_run *kvm_run)
1089 {
1090         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1091                 pr_unimpl(&svm->vcpu, "%s: failed\n", __FUNCTION__);
1092         return 1;
1093 }
1094
1095 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1096 {
1097         struct vcpu_svm *svm = to_svm(vcpu);
1098
1099         switch (ecx) {
1100         case MSR_IA32_TIME_STAMP_COUNTER: {
1101                 u64 tsc;
1102
1103                 rdtscll(tsc);
1104                 *data = svm->vmcb->control.tsc_offset + tsc;
1105                 break;
1106         }
1107         case MSR_K6_STAR:
1108                 *data = svm->vmcb->save.star;
1109                 break;
1110 #ifdef CONFIG_X86_64
1111         case MSR_LSTAR:
1112                 *data = svm->vmcb->save.lstar;
1113                 break;
1114         case MSR_CSTAR:
1115                 *data = svm->vmcb->save.cstar;
1116                 break;
1117         case MSR_KERNEL_GS_BASE:
1118                 *data = svm->vmcb->save.kernel_gs_base;
1119                 break;
1120         case MSR_SYSCALL_MASK:
1121                 *data = svm->vmcb->save.sfmask;
1122                 break;
1123 #endif
1124         case MSR_IA32_SYSENTER_CS:
1125                 *data = svm->vmcb->save.sysenter_cs;
1126                 break;
1127         case MSR_IA32_SYSENTER_EIP:
1128                 *data = svm->vmcb->save.sysenter_eip;
1129                 break;
1130         case MSR_IA32_SYSENTER_ESP:
1131                 *data = svm->vmcb->save.sysenter_esp;
1132                 break;
1133         default:
1134                 return kvm_get_msr_common(vcpu, ecx, data);
1135         }
1136         return 0;
1137 }
1138
1139 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1140 {
1141         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1142         u64 data;
1143
1144         if (svm_get_msr(&svm->vcpu, ecx, &data))
1145                 svm_inject_gp(&svm->vcpu, 0);
1146         else {
1147                 svm->vmcb->save.rax = data & 0xffffffff;
1148                 svm->vcpu.regs[VCPU_REGS_RDX] = data >> 32;
1149                 svm->next_rip = svm->vmcb->save.rip + 2;
1150                 skip_emulated_instruction(&svm->vcpu);
1151         }
1152         return 1;
1153 }
1154
1155 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
1156 {
1157         struct vcpu_svm *svm = to_svm(vcpu);
1158
1159         switch (ecx) {
1160         case MSR_IA32_TIME_STAMP_COUNTER: {
1161                 u64 tsc;
1162
1163                 rdtscll(tsc);
1164                 svm->vmcb->control.tsc_offset = data - tsc;
1165                 break;
1166         }
1167         case MSR_K6_STAR:
1168                 svm->vmcb->save.star = data;
1169                 break;
1170 #ifdef CONFIG_X86_64
1171         case MSR_LSTAR:
1172                 svm->vmcb->save.lstar = data;
1173                 break;
1174         case MSR_CSTAR:
1175                 svm->vmcb->save.cstar = data;
1176                 break;
1177         case MSR_KERNEL_GS_BASE:
1178                 svm->vmcb->save.kernel_gs_base = data;
1179                 break;
1180         case MSR_SYSCALL_MASK:
1181                 svm->vmcb->save.sfmask = data;
1182                 break;
1183 #endif
1184         case MSR_IA32_SYSENTER_CS:
1185                 svm->vmcb->save.sysenter_cs = data;
1186                 break;
1187         case MSR_IA32_SYSENTER_EIP:
1188                 svm->vmcb->save.sysenter_eip = data;
1189                 break;
1190         case MSR_IA32_SYSENTER_ESP:
1191                 svm->vmcb->save.sysenter_esp = data;
1192                 break;
1193         default:
1194                 return kvm_set_msr_common(vcpu, ecx, data);
1195         }
1196         return 0;
1197 }
1198
1199 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1200 {
1201         u32 ecx = svm->vcpu.regs[VCPU_REGS_RCX];
1202         u64 data = (svm->vmcb->save.rax & -1u)
1203                 | ((u64)(svm->vcpu.regs[VCPU_REGS_RDX] & -1u) << 32);
1204         svm->next_rip = svm->vmcb->save.rip + 2;
1205         if (svm_set_msr(&svm->vcpu, ecx, data))
1206                 svm_inject_gp(&svm->vcpu, 0);
1207         else
1208                 skip_emulated_instruction(&svm->vcpu);
1209         return 1;
1210 }
1211
1212 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1213 {
1214         if (svm->vmcb->control.exit_info_1)
1215                 return wrmsr_interception(svm, kvm_run);
1216         else
1217                 return rdmsr_interception(svm, kvm_run);
1218 }
1219
1220 static int interrupt_window_interception(struct vcpu_svm *svm,
1221                                    struct kvm_run *kvm_run)
1222 {
1223         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
1224         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1225         /*
1226          * If the user space waits to inject interrupts, exit as soon as
1227          * possible
1228          */
1229         if (kvm_run->request_interrupt_window &&
1230             !svm->vcpu.irq_summary) {
1231                 ++svm->vcpu.stat.irq_window_exits;
1232                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
1233                 return 0;
1234         }
1235
1236         return 1;
1237 }
1238
1239 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
1240                                       struct kvm_run *kvm_run) = {
1241         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
1242         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
1243         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
1244         /* for now: */
1245         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
1246         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
1247         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
1248         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
1249         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
1250         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
1251         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
1252         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
1253         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
1254         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
1255         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
1256         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
1257         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
1258         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
1259         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
1260         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
1261         [SVM_EXIT_INTR]                         = nop_on_interception,
1262         [SVM_EXIT_NMI]                          = nop_on_interception,
1263         [SVM_EXIT_SMI]                          = nop_on_interception,
1264         [SVM_EXIT_INIT]                         = nop_on_interception,
1265         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
1266         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
1267         [SVM_EXIT_CPUID]                        = cpuid_interception,
1268         [SVM_EXIT_INVD]                         = emulate_on_interception,
1269         [SVM_EXIT_HLT]                          = halt_interception,
1270         [SVM_EXIT_INVLPG]                       = emulate_on_interception,
1271         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
1272         [SVM_EXIT_IOIO]                         = io_interception,
1273         [SVM_EXIT_MSR]                          = msr_interception,
1274         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
1275         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
1276         [SVM_EXIT_VMRUN]                        = invalid_op_interception,
1277         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
1278         [SVM_EXIT_VMLOAD]                       = invalid_op_interception,
1279         [SVM_EXIT_VMSAVE]                       = invalid_op_interception,
1280         [SVM_EXIT_STGI]                         = invalid_op_interception,
1281         [SVM_EXIT_CLGI]                         = invalid_op_interception,
1282         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
1283         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
1284         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
1285         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
1286 };
1287
1288
1289 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
1290 {
1291         struct vcpu_svm *svm = to_svm(vcpu);
1292         u32 exit_code = svm->vmcb->control.exit_code;
1293
1294         kvm_reput_irq(svm);
1295
1296         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
1297                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
1298                 kvm_run->fail_entry.hardware_entry_failure_reason
1299                         = svm->vmcb->control.exit_code;
1300                 return 0;
1301         }
1302
1303         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
1304             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR)
1305                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
1306                        "exit_code 0x%x\n",
1307                        __FUNCTION__, svm->vmcb->control.exit_int_info,
1308                        exit_code);
1309
1310         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
1311             || svm_exit_handlers[exit_code] == 0) {
1312                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
1313                 kvm_run->hw.hardware_exit_reason = exit_code;
1314                 return 0;
1315         }
1316
1317         return svm_exit_handlers[exit_code](svm, kvm_run);
1318 }
1319
1320 static void reload_tss(struct kvm_vcpu *vcpu)
1321 {
1322         int cpu = raw_smp_processor_id();
1323
1324         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1325         svm_data->tss_desc->type = 9; //available 32/64-bit TSS
1326         load_TR_desc();
1327 }
1328
1329 static void pre_svm_run(struct vcpu_svm *svm)
1330 {
1331         int cpu = raw_smp_processor_id();
1332
1333         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
1334
1335         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
1336         if (svm->vcpu.cpu != cpu ||
1337             svm->asid_generation != svm_data->asid_generation)
1338                 new_asid(svm, svm_data);
1339 }
1340
1341
1342 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
1343 {
1344         struct vmcb_control_area *control;
1345
1346         control = &svm->vmcb->control;
1347         control->int_vector = irq;
1348         control->int_ctl &= ~V_INTR_PRIO_MASK;
1349         control->int_ctl |= V_IRQ_MASK |
1350                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1351 }
1352
1353 static void svm_set_irq(struct kvm_vcpu *vcpu, int irq)
1354 {
1355         struct vcpu_svm *svm = to_svm(vcpu);
1356
1357         svm_inject_irq(svm, irq);
1358 }
1359
1360 static void svm_intr_assist(struct kvm_vcpu *vcpu)
1361 {
1362         struct vcpu_svm *svm = to_svm(vcpu);
1363         struct vmcb *vmcb = svm->vmcb;
1364         int intr_vector = -1;
1365
1366         kvm_inject_pending_timer_irqs(vcpu);
1367         if ((vmcb->control.exit_int_info & SVM_EVTINJ_VALID) &&
1368             ((vmcb->control.exit_int_info & SVM_EVTINJ_TYPE_MASK) == 0)) {
1369                 intr_vector = vmcb->control.exit_int_info &
1370                               SVM_EVTINJ_VEC_MASK;
1371                 vmcb->control.exit_int_info = 0;
1372                 svm_inject_irq(svm, intr_vector);
1373                 return;
1374         }
1375
1376         if (vmcb->control.int_ctl & V_IRQ_MASK)
1377                 return;
1378
1379         if (!kvm_cpu_has_interrupt(vcpu))
1380                 return;
1381
1382         if (!(vmcb->save.rflags & X86_EFLAGS_IF) ||
1383             (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
1384             (vmcb->control.event_inj & SVM_EVTINJ_VALID)) {
1385                 /* unable to deliver irq, set pending irq */
1386                 vmcb->control.intercept |= (1ULL << INTERCEPT_VINTR);
1387                 svm_inject_irq(svm, 0x0);
1388                 return;
1389         }
1390         /* Okay, we can deliver the interrupt: grab it and update PIC state. */
1391         intr_vector = kvm_cpu_get_interrupt(vcpu);
1392         svm_inject_irq(svm, intr_vector);
1393         kvm_timer_intr_post(vcpu, intr_vector);
1394 }
1395
1396 static void kvm_reput_irq(struct vcpu_svm *svm)
1397 {
1398         struct vmcb_control_area *control = &svm->vmcb->control;
1399
1400         if ((control->int_ctl & V_IRQ_MASK)
1401             && !irqchip_in_kernel(svm->vcpu.kvm)) {
1402                 control->int_ctl &= ~V_IRQ_MASK;
1403                 push_irq(&svm->vcpu, control->int_vector);
1404         }
1405
1406         svm->vcpu.interrupt_window_open =
1407                 !(control->int_state & SVM_INTERRUPT_SHADOW_MASK);
1408 }
1409
1410 static void svm_do_inject_vector(struct vcpu_svm *svm)
1411 {
1412         struct kvm_vcpu *vcpu = &svm->vcpu;
1413         int word_index = __ffs(vcpu->irq_summary);
1414         int bit_index = __ffs(vcpu->irq_pending[word_index]);
1415         int irq = word_index * BITS_PER_LONG + bit_index;
1416
1417         clear_bit(bit_index, &vcpu->irq_pending[word_index]);
1418         if (!vcpu->irq_pending[word_index])
1419                 clear_bit(word_index, &vcpu->irq_summary);
1420         svm_inject_irq(svm, irq);
1421 }
1422
1423 static void do_interrupt_requests(struct kvm_vcpu *vcpu,
1424                                        struct kvm_run *kvm_run)
1425 {
1426         struct vcpu_svm *svm = to_svm(vcpu);
1427         struct vmcb_control_area *control = &svm->vmcb->control;
1428
1429         svm->vcpu.interrupt_window_open =
1430                 (!(control->int_state & SVM_INTERRUPT_SHADOW_MASK) &&
1431                  (svm->vmcb->save.rflags & X86_EFLAGS_IF));
1432
1433         if (svm->vcpu.interrupt_window_open && svm->vcpu.irq_summary)
1434                 /*
1435                  * If interrupts enabled, and not blocked by sti or mov ss. Good.
1436                  */
1437                 svm_do_inject_vector(svm);
1438
1439         /*
1440          * Interrupts blocked.  Wait for unblock.
1441          */
1442         if (!svm->vcpu.interrupt_window_open &&
1443             (svm->vcpu.irq_summary || kvm_run->request_interrupt_window)) {
1444                 control->intercept |= 1ULL << INTERCEPT_VINTR;
1445         } else
1446                 control->intercept &= ~(1ULL << INTERCEPT_VINTR);
1447 }
1448
1449 static void save_db_regs(unsigned long *db_regs)
1450 {
1451         asm volatile ("mov %%dr0, %0" : "=r"(db_regs[0]));
1452         asm volatile ("mov %%dr1, %0" : "=r"(db_regs[1]));
1453         asm volatile ("mov %%dr2, %0" : "=r"(db_regs[2]));
1454         asm volatile ("mov %%dr3, %0" : "=r"(db_regs[3]));
1455 }
1456
1457 static void load_db_regs(unsigned long *db_regs)
1458 {
1459         asm volatile ("mov %0, %%dr0" : : "r"(db_regs[0]));
1460         asm volatile ("mov %0, %%dr1" : : "r"(db_regs[1]));
1461         asm volatile ("mov %0, %%dr2" : : "r"(db_regs[2]));
1462         asm volatile ("mov %0, %%dr3" : : "r"(db_regs[3]));
1463 }
1464
1465 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
1466 {
1467         force_new_asid(vcpu);
1468 }
1469
1470 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1471 {
1472 }
1473
1474 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
1475 {
1476         struct vcpu_svm *svm = to_svm(vcpu);
1477         u16 fs_selector;
1478         u16 gs_selector;
1479         u16 ldt_selector;
1480
1481         pre_svm_run(svm);
1482
1483         save_host_msrs(vcpu);
1484         fs_selector = read_fs();
1485         gs_selector = read_gs();
1486         ldt_selector = read_ldt();
1487         svm->host_cr2 = kvm_read_cr2();
1488         svm->host_dr6 = read_dr6();
1489         svm->host_dr7 = read_dr7();
1490         svm->vmcb->save.cr2 = vcpu->cr2;
1491
1492         if (svm->vmcb->save.dr7 & 0xff) {
1493                 write_dr7(0);
1494                 save_db_regs(svm->host_db_regs);
1495                 load_db_regs(svm->db_regs);
1496         }
1497
1498         clgi();
1499
1500         local_irq_enable();
1501
1502         asm volatile (
1503 #ifdef CONFIG_X86_64
1504                 "push %%rbx; push %%rcx; push %%rdx;"
1505                 "push %%rsi; push %%rdi; push %%rbp;"
1506                 "push %%r8;  push %%r9;  push %%r10; push %%r11;"
1507                 "push %%r12; push %%r13; push %%r14; push %%r15;"
1508 #else
1509                 "push %%ebx; push %%ecx; push %%edx;"
1510                 "push %%esi; push %%edi; push %%ebp;"
1511 #endif
1512
1513 #ifdef CONFIG_X86_64
1514                 "mov %c[rbx](%[svm]), %%rbx \n\t"
1515                 "mov %c[rcx](%[svm]), %%rcx \n\t"
1516                 "mov %c[rdx](%[svm]), %%rdx \n\t"
1517                 "mov %c[rsi](%[svm]), %%rsi \n\t"
1518                 "mov %c[rdi](%[svm]), %%rdi \n\t"
1519                 "mov %c[rbp](%[svm]), %%rbp \n\t"
1520                 "mov %c[r8](%[svm]),  %%r8  \n\t"
1521                 "mov %c[r9](%[svm]),  %%r9  \n\t"
1522                 "mov %c[r10](%[svm]), %%r10 \n\t"
1523                 "mov %c[r11](%[svm]), %%r11 \n\t"
1524                 "mov %c[r12](%[svm]), %%r12 \n\t"
1525                 "mov %c[r13](%[svm]), %%r13 \n\t"
1526                 "mov %c[r14](%[svm]), %%r14 \n\t"
1527                 "mov %c[r15](%[svm]), %%r15 \n\t"
1528 #else
1529                 "mov %c[rbx](%[svm]), %%ebx \n\t"
1530                 "mov %c[rcx](%[svm]), %%ecx \n\t"
1531                 "mov %c[rdx](%[svm]), %%edx \n\t"
1532                 "mov %c[rsi](%[svm]), %%esi \n\t"
1533                 "mov %c[rdi](%[svm]), %%edi \n\t"
1534                 "mov %c[rbp](%[svm]), %%ebp \n\t"
1535 #endif
1536
1537 #ifdef CONFIG_X86_64
1538                 /* Enter guest mode */
1539                 "push %%rax \n\t"
1540                 "mov %c[vmcb](%[svm]), %%rax \n\t"
1541                 SVM_VMLOAD "\n\t"
1542                 SVM_VMRUN "\n\t"
1543                 SVM_VMSAVE "\n\t"
1544                 "pop %%rax \n\t"
1545 #else
1546                 /* Enter guest mode */
1547                 "push %%eax \n\t"
1548                 "mov %c[vmcb](%[svm]), %%eax \n\t"
1549                 SVM_VMLOAD "\n\t"
1550                 SVM_VMRUN "\n\t"
1551                 SVM_VMSAVE "\n\t"
1552                 "pop %%eax \n\t"
1553 #endif
1554
1555                 /* Save guest registers, load host registers */
1556 #ifdef CONFIG_X86_64
1557                 "mov %%rbx, %c[rbx](%[svm]) \n\t"
1558                 "mov %%rcx, %c[rcx](%[svm]) \n\t"
1559                 "mov %%rdx, %c[rdx](%[svm]) \n\t"
1560                 "mov %%rsi, %c[rsi](%[svm]) \n\t"
1561                 "mov %%rdi, %c[rdi](%[svm]) \n\t"
1562                 "mov %%rbp, %c[rbp](%[svm]) \n\t"
1563                 "mov %%r8,  %c[r8](%[svm]) \n\t"
1564                 "mov %%r9,  %c[r9](%[svm]) \n\t"
1565                 "mov %%r10, %c[r10](%[svm]) \n\t"
1566                 "mov %%r11, %c[r11](%[svm]) \n\t"
1567                 "mov %%r12, %c[r12](%[svm]) \n\t"
1568                 "mov %%r13, %c[r13](%[svm]) \n\t"
1569                 "mov %%r14, %c[r14](%[svm]) \n\t"
1570                 "mov %%r15, %c[r15](%[svm]) \n\t"
1571
1572                 "pop  %%r15; pop  %%r14; pop  %%r13; pop  %%r12;"
1573                 "pop  %%r11; pop  %%r10; pop  %%r9;  pop  %%r8;"
1574                 "pop  %%rbp; pop  %%rdi; pop  %%rsi;"
1575                 "pop  %%rdx; pop  %%rcx; pop  %%rbx; \n\t"
1576 #else
1577                 "mov %%ebx, %c[rbx](%[svm]) \n\t"
1578                 "mov %%ecx, %c[rcx](%[svm]) \n\t"
1579                 "mov %%edx, %c[rdx](%[svm]) \n\t"
1580                 "mov %%esi, %c[rsi](%[svm]) \n\t"
1581                 "mov %%edi, %c[rdi](%[svm]) \n\t"
1582                 "mov %%ebp, %c[rbp](%[svm]) \n\t"
1583
1584                 "pop  %%ebp; pop  %%edi; pop  %%esi;"
1585                 "pop  %%edx; pop  %%ecx; pop  %%ebx; \n\t"
1586 #endif
1587                 :
1588                 : [svm]"a"(svm),
1589                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
1590                   [rbx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBX])),
1591                   [rcx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RCX])),
1592                   [rdx]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDX])),
1593                   [rsi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RSI])),
1594                   [rdi]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RDI])),
1595                   [rbp]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_RBP]))
1596 #ifdef CONFIG_X86_64
1597                   ,[r8 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R8])),
1598                   [r9 ]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R9 ])),
1599                   [r10]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R10])),
1600                   [r11]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R11])),
1601                   [r12]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R12])),
1602                   [r13]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R13])),
1603                   [r14]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R14])),
1604                   [r15]"i"(offsetof(struct vcpu_svm,vcpu.regs[VCPU_REGS_R15]))
1605 #endif
1606                 : "cc", "memory" );
1607
1608         if ((svm->vmcb->save.dr7 & 0xff))
1609                 load_db_regs(svm->host_db_regs);
1610
1611         vcpu->cr2 = svm->vmcb->save.cr2;
1612
1613         write_dr6(svm->host_dr6);
1614         write_dr7(svm->host_dr7);
1615         kvm_write_cr2(svm->host_cr2);
1616
1617         load_fs(fs_selector);
1618         load_gs(gs_selector);
1619         load_ldt(ldt_selector);
1620         load_host_msrs(vcpu);
1621
1622         reload_tss(vcpu);
1623
1624         local_irq_disable();
1625
1626         stgi();
1627
1628         svm->next_rip = 0;
1629 }
1630
1631 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
1632 {
1633         struct vcpu_svm *svm = to_svm(vcpu);
1634
1635         svm->vmcb->save.cr3 = root;
1636         force_new_asid(vcpu);
1637
1638         if (vcpu->fpu_active) {
1639                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
1640                 svm->vmcb->save.cr0 |= X86_CR0_TS;
1641                 vcpu->fpu_active = 0;
1642         }
1643 }
1644
1645 static void svm_inject_page_fault(struct kvm_vcpu *vcpu,
1646                                   unsigned long  addr,
1647                                   uint32_t err_code)
1648 {
1649         struct vcpu_svm *svm = to_svm(vcpu);
1650         uint32_t exit_int_info = svm->vmcb->control.exit_int_info;
1651
1652         ++vcpu->stat.pf_guest;
1653
1654         if (is_page_fault(exit_int_info)) {
1655
1656                 svm->vmcb->control.event_inj_err = 0;
1657                 svm->vmcb->control.event_inj =  SVM_EVTINJ_VALID |
1658                                                 SVM_EVTINJ_VALID_ERR |
1659                                                 SVM_EVTINJ_TYPE_EXEPT |
1660                                                 DF_VECTOR;
1661                 return;
1662         }
1663         vcpu->cr2 = addr;
1664         svm->vmcb->save.cr2 = addr;
1665         svm->vmcb->control.event_inj =  SVM_EVTINJ_VALID |
1666                                         SVM_EVTINJ_VALID_ERR |
1667                                         SVM_EVTINJ_TYPE_EXEPT |
1668                                         PF_VECTOR;
1669         svm->vmcb->control.event_inj_err = err_code;
1670 }
1671
1672
1673 static int is_disabled(void)
1674 {
1675         u64 vm_cr;
1676
1677         rdmsrl(MSR_VM_CR, vm_cr);
1678         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
1679                 return 1;
1680
1681         return 0;
1682 }
1683
1684 static void
1685 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
1686 {
1687         /*
1688          * Patch in the VMMCALL instruction:
1689          */
1690         hypercall[0] = 0x0f;
1691         hypercall[1] = 0x01;
1692         hypercall[2] = 0xd9;
1693 }
1694
1695 static void svm_check_processor_compat(void *rtn)
1696 {
1697         *(int *)rtn = 0;
1698 }
1699
1700 static struct kvm_x86_ops svm_x86_ops = {
1701         .cpu_has_kvm_support = has_svm,
1702         .disabled_by_bios = is_disabled,
1703         .hardware_setup = svm_hardware_setup,
1704         .hardware_unsetup = svm_hardware_unsetup,
1705         .check_processor_compatibility = svm_check_processor_compat,
1706         .hardware_enable = svm_hardware_enable,
1707         .hardware_disable = svm_hardware_disable,
1708
1709         .vcpu_create = svm_create_vcpu,
1710         .vcpu_free = svm_free_vcpu,
1711         .vcpu_reset = svm_vcpu_reset,
1712
1713         .prepare_guest_switch = svm_prepare_guest_switch,
1714         .vcpu_load = svm_vcpu_load,
1715         .vcpu_put = svm_vcpu_put,
1716         .vcpu_decache = svm_vcpu_decache,
1717
1718         .set_guest_debug = svm_guest_debug,
1719         .get_msr = svm_get_msr,
1720         .set_msr = svm_set_msr,
1721         .get_segment_base = svm_get_segment_base,
1722         .get_segment = svm_get_segment,
1723         .set_segment = svm_set_segment,
1724         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
1725         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
1726         .set_cr0 = svm_set_cr0,
1727         .set_cr3 = svm_set_cr3,
1728         .set_cr4 = svm_set_cr4,
1729         .set_efer = svm_set_efer,
1730         .get_idt = svm_get_idt,
1731         .set_idt = svm_set_idt,
1732         .get_gdt = svm_get_gdt,
1733         .set_gdt = svm_set_gdt,
1734         .get_dr = svm_get_dr,
1735         .set_dr = svm_set_dr,
1736         .cache_regs = svm_cache_regs,
1737         .decache_regs = svm_decache_regs,
1738         .get_rflags = svm_get_rflags,
1739         .set_rflags = svm_set_rflags,
1740
1741         .tlb_flush = svm_flush_tlb,
1742         .inject_page_fault = svm_inject_page_fault,
1743
1744         .inject_gp = svm_inject_gp,
1745
1746         .run = svm_vcpu_run,
1747         .handle_exit = handle_exit,
1748         .skip_emulated_instruction = skip_emulated_instruction,
1749         .patch_hypercall = svm_patch_hypercall,
1750         .get_irq = svm_get_irq,
1751         .set_irq = svm_set_irq,
1752         .inject_pending_irq = svm_intr_assist,
1753         .inject_pending_vectors = do_interrupt_requests,
1754 };
1755
1756 static int __init svm_init(void)
1757 {
1758         return kvm_init_x86(&svm_x86_ops, sizeof(struct vcpu_svm),
1759                               THIS_MODULE);
1760 }
1761
1762 static void __exit svm_exit(void)
1763 {
1764         kvm_exit_x86();
1765 }
1766
1767 module_init(svm_init)
1768 module_exit(svm_exit)