drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PKEY_INDEX            |
 387                                          IB_QP_PATH_MIG_STATE),
 388                                 [RC]  = (IB_QP_CUR_STATE             |
 389                                          IB_QP_ALT_PATH              |
 390                                          IB_QP_ACCESS_FLAGS          |
 391                                          IB_QP_PKEY_INDEX            |
 392                                          IB_QP_MIN_RNR_TIMER         |
 393                                          IB_QP_PATH_MIG_STATE),
 394                                 [MLX] = (IB_QP_CUR_STATE             |
 395                                          IB_QP_QKEY),
 396                         }
 397                 }
 398         },
 399         [IB_QPS_RTS]   = {
 400                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 401                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 402                 [IB_QPS_RTS]   = {
 403                         .trans = MTHCA_TRANS_RTS2RTS,
 404                         .opt_param = {
 405                                 [UD]  = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 408                                          IB_QP_ALT_PATH              |
 409                                          IB_QP_PATH_MIG_STATE),
 410                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_PATH_MIG_STATE        |
 413                                          IB_QP_MIN_RNR_TIMER),
 414                                 [MLX] = (IB_QP_CUR_STATE             |
 415                                          IB_QP_QKEY),
 416                         }
 417                 },
 418                 [IB_QPS_SQD]   = {
 419                         .trans = MTHCA_TRANS_RTS2SQD,
 420                 },
 421         },
 422         [IB_QPS_SQD]   = {
 423                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 424                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 425                 [IB_QPS_RTS]   = {
 426                         .trans = MTHCA_TRANS_SQD2RTS,
 427                         .opt_param = {
 428                                 [UD]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                                 [UC]  = (IB_QP_CUR_STATE             |
 431                                          IB_QP_ALT_PATH              |
 432                                          IB_QP_ACCESS_FLAGS          |
 433                                          IB_QP_PATH_MIG_STATE),
 434                                 [RC]  = (IB_QP_CUR_STATE             |
 435                                          IB_QP_ALT_PATH              |
 436                                          IB_QP_ACCESS_FLAGS          |
 437                                          IB_QP_MIN_RNR_TIMER         |
 438                                          IB_QP_PATH_MIG_STATE),
 439                                 [MLX] = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                         }
 442                 },
 443                 [IB_QPS_SQD]   = {
 444                         .trans = MTHCA_TRANS_SQD2SQD,
 445                         .opt_param = {
 446                                 [UD]  = (IB_QP_PKEY_INDEX            |
 447                                          IB_QP_QKEY),
 448                                 [UC]  = (IB_QP_AV                    |
 449                                          IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_PKEY_INDEX            |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [RC]  = (IB_QP_AV                    |
 455                                          IB_QP_TIMEOUT               |
 456                                          IB_QP_RETRY_CNT             |
 457                                          IB_QP_RNR_RETRY             |
 458                                          IB_QP_MAX_QP_RD_ATOMIC      |
 459                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 460                                          IB_QP_CUR_STATE             |
 461                                          IB_QP_ALT_PATH              |
 462                                          IB_QP_ACCESS_FLAGS          |
 463                                          IB_QP_PKEY_INDEX            |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_PKEY_INDEX            |
 467                                          IB_QP_QKEY),
 468                         }
 469                 }
 470         },
 471         [IB_QPS_SQE]   = {
 472                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 473                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 474                 [IB_QPS_RTS]   = {
 475                         .trans = MTHCA_TRANS_SQERR2RTS,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_QKEY),
 479                                 [UC]  = IB_QP_CUR_STATE,
 480                                 [RC]  = (IB_QP_CUR_STATE             |
 481                                          IB_QP_MIN_RNR_TIMER),
 482                                 [MLX] = (IB_QP_CUR_STATE             |
 483                                          IB_QP_QKEY),
 484                         }
 485                 }
 486         },
 487         [IB_QPS_ERR] = {
 488                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 489                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 490         }
 491 };
 492
 493 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 494                         int attr_mask)
 495 {
 496         if (attr_mask & IB_QP_PKEY_INDEX)
 497                 sqp->pkey_index = attr->pkey_index;
 498         if (attr_mask & IB_QP_QKEY)
 499                 sqp->qkey = attr->qkey;
 500         if (attr_mask & IB_QP_SQ_PSN)
 501                 sqp->send_psn = attr->sq_psn;
 502 }
 503
 504 static void init_port(struct mthca_dev *dev, int port)
 505 {
 506         int err;
 507         u8 status;
 508         struct mthca_init_ib_param param;
 509
 510         memset(&param, 0, sizeof param);
 511
 512         param.port_width = dev->limits.port_width_cap;
 513         param.vl_cap     = dev->limits.vl_cap;
 514         param.mtu_cap    = dev->limits.mtu_cap;
 515         param.gid_cap    = dev->limits.gid_table_len;
 516         param.pkey_cap   = dev->limits.pkey_table_len;
 517
 518         err = mthca_INIT_IB(dev, &param, port, &status);
 519         if (err)
 520                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 521         if (status)
 522                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 523 }
 524
 525 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 526 {
 527         struct mthca_dev *dev = to_mdev(ibqp->device);
 528         struct mthca_qp *qp = to_mqp(ibqp);
 529         enum ib_qp_state cur_state, new_state;
 530         struct mthca_mailbox *mailbox;
 531         struct mthca_qp_param *qp_param;
 532         struct mthca_qp_context *qp_context;
 533         u32 req_param, opt_param;
 534         u8 status;
 535         int err;
 536
 537         if (attr_mask & IB_QP_CUR_STATE) {
 538                 if (attr->cur_qp_state != IB_QPS_RTR &&
 539                     attr->cur_qp_state != IB_QPS_RTS &&
 540                     attr->cur_qp_state != IB_QPS_SQD &&
 541                     attr->cur_qp_state != IB_QPS_SQE)
 542                         return -EINVAL;
 543                 else
 544                         cur_state = attr->cur_qp_state;
 545         } else {
 546                 spin_lock_irq(&qp->sq.lock);
 547                 spin_lock(&qp->rq.lock);
 548                 cur_state = qp->state;
 549                 spin_unlock(&qp->rq.lock);
 550                 spin_unlock_irq(&qp->sq.lock);
 551         }
 552
 553         if (attr_mask & IB_QP_STATE) {
 554                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 555                         return -EINVAL;
 556                 new_state = attr->qp_state;
 557         } else
 558                 new_state = cur_state;
 559
 560         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 561                 mthca_dbg(dev, "Illegal QP transition "
 562                           "%d->%d\n", cur_state, new_state);
 563                 return -EINVAL;
 564         }
 565
 566         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 567         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 568
 569         if ((req_param & attr_mask) != req_param) {
 570                 mthca_dbg(dev, "QP transition "
 571                           "%d->%d missing req attr 0x%08x\n",
 572                           cur_state, new_state,
 573                           req_param & ~attr_mask);
 574                 return -EINVAL;
 575         }
 576
 577         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 578                 mthca_dbg(dev, "QP transition (transport %d) "
 579                           "%d->%d has extra attr 0x%08x\n",
 580                           qp->transport,
 581                           cur_state, new_state,
 582                           attr_mask & ~(req_param | opt_param |
 583                                                  IB_QP_STATE));
 584                 return -EINVAL;
 585         }
 586
 587         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 588              attr->pkey_index >= dev->limits.pkey_table_len) {
 589                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 590                           attr->pkey_index,dev->limits.pkey_table_len-1);
 591                 return -EINVAL;
 592         }
 593
 594         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 595             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 596                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 597                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 598                 return -EINVAL;
 599         }
 600
 601         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 602             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 603                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 604                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 605                 return -EINVAL;
 606         }
 607
 608         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 609         if (IS_ERR(mailbox))
 610                 return PTR_ERR(mailbox);
 611         qp_param = mailbox->buf;
 612         qp_context = &qp_param->context;
 613         memset(qp_param, 0, sizeof *qp_param);
 614
 615         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 616                                              (to_mthca_st(qp->transport) << 16));
 617         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 618         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 619                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 620         else {
 621                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 622                 switch (attr->path_mig_state) {
 623                 case IB_MIG_MIGRATED:
 624                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 625                         break;
 626                 case IB_MIG_REARM:
 627                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 628                         break;
 629                 case IB_MIG_ARMED:
 630                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 631                         break;
 632                 }
 633         }
 634
 635         /* leave tavor_sched_queue as 0 */
 636
 637         if (qp->transport == MLX || qp->transport == UD)
 638                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 639         else if (attr_mask & IB_QP_PATH_MTU)
 640                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 641
 642         if (mthca_is_memfree(dev)) {
 643                 if (qp->rq.max)
 644                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 645                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 646
 647                 if (qp->sq.max)
 648                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 649                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 650         }
 651
 652         /* leave arbel_sched_queue as 0 */
 653
 654         if (qp->ibqp.uobject)
 655                 qp_context->usr_page =
 656                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 657         else
 658                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 659         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 660         if (attr_mask & IB_QP_DEST_QPN) {
 661                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 662         }
 663
 664         if (qp->transport == MLX)
 665                 qp_context->pri_path.port_pkey |=
 666                         cpu_to_be32(to_msqp(qp)->port << 24);
 667         else {
 668                 if (attr_mask & IB_QP_PORT) {
 669                         qp_context->pri_path.port_pkey |=
 670                                 cpu_to_be32(attr->port_num << 24);
 671                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 672                 }
 673         }
 674
 675         if (attr_mask & IB_QP_PKEY_INDEX) {
 676                 qp_context->pri_path.port_pkey |=
 677                         cpu_to_be32(attr->pkey_index);
 678                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 679         }
 680
 681         if (attr_mask & IB_QP_RNR_RETRY) {
 682                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 683                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 684         }
 685
 686         if (attr_mask & IB_QP_AV) {
 687                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 688                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 689                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 690                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 691                         qp_context->pri_path.g_mylmc |= 1 << 7;
 692                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 693                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 694                         qp_context->pri_path.sl_tclass_flowlabel =
 695                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 696                                             (attr->ah_attr.grh.traffic_class << 20) |
 697                                             (attr->ah_attr.grh.flow_label));
 698                         memcpy(qp_context->pri_path.rgid,
 699                                attr->ah_attr.grh.dgid.raw, 16);
 700                 } else {
 701                         qp_context->pri_path.sl_tclass_flowlabel =
 702                                 cpu_to_be32(attr->ah_attr.sl << 28);
 703                 }
 704                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 705         }
 706
 707         if (attr_mask & IB_QP_TIMEOUT) {
 708                 qp_context->pri_path.ackto = attr->timeout << 3;
 709                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 710         }
 711
 712         /* XXX alt_path */
 713
 714         /* leave rdd as 0 */
 715         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 716         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 717         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 718         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 719                                              (MTHCA_FLIGHT_LIMIT << 24) |
 720                                              MTHCA_QP_BIT_SRE           |
 721                                              MTHCA_QP_BIT_SWE           |
 722                                              MTHCA_QP_BIT_SAE);
 723         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 724                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 725         if (attr_mask & IB_QP_RETRY_CNT) {
 726                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 727                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 728         }
 729
 730         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 731                 if (attr->max_rd_atomic)
 732                         qp_context->params1 |=
 733                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 734                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 735         }
 736
 737         if (attr_mask & IB_QP_SQ_PSN)
 738                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 739         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 740
 741         if (mthca_is_memfree(dev)) {
 742                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 743                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 744         }
 745
 746         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 747                 qp_context->params2 |=
 748                         cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 749                                     MTHCA_QP_BIT_RWE : 0);
 750
 751                 /*
 752                  * Only enable RDMA reads and atomics if we have
 753                  * responder resources set to a non-zero value.
 754                  */
 755                 if (qp->resp_depth) {
 756                         qp_context->params2 |=
 757                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 758                                             MTHCA_QP_BIT_RRE : 0);
 759                         qp_context->params2 |=
 760                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 761                                             MTHCA_QP_BIT_RAE : 0);
 762                 }
 763
 764                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 765                                                         MTHCA_QP_OPTPAR_RRE |
 766                                                         MTHCA_QP_OPTPAR_RAE);
 767
 768                 qp->atomic_rd_en = attr->qp_access_flags;
 769         }
 770
 771         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 772                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 773                         /*
 774                          * Lowering our responder resources to zero.
 775                          * Turn off reads RDMA and atomics as responder.
 776                          * (RRE/RAE in params2 already zero)
 777                          */
 778                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRE |
 779                                                                 MTHCA_QP_OPTPAR_RAE);
 780                 }
 781
 782                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 783                         /*
 784                          * Increasing our responder resources from
 785                          * zero.  Turn on RDMA reads and atomics as
 786                          * appropriate.
 787                          */
 788                         qp_context->params2 |=
 789                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 790                                             MTHCA_QP_BIT_RRE : 0);
 791                         qp_context->params2 |=
 792                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 793                                             MTHCA_QP_BIT_RAE : 0);
 794
 795                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRE |
 796                                                                 MTHCA_QP_OPTPAR_RAE);
 797                 }
 798
 799                 if (attr->max_dest_rd_atomic)
 800                         qp_context->params2 |=
 801                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 802
 803                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 804
 805                 qp->resp_depth = attr->max_dest_rd_atomic;
 806         }
 807
 808         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 809
 810         if (ibqp->srq)
 811                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 812
 813         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 814                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 815                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 816         }
 817         if (attr_mask & IB_QP_RQ_PSN)
 818                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 819
 820         qp_context->ra_buff_indx =
 821                 cpu_to_be32(dev->qp_table.rdb_base +
 822                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 823                              dev->qp_table.rdb_shift));
 824
 825         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 826
 827         if (mthca_is_memfree(dev))
 828                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 829
 830         if (attr_mask & IB_QP_QKEY) {
 831                 qp_context->qkey = cpu_to_be32(attr->qkey);
 832                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 833         }
 834
 835         if (ibqp->srq)
 836                 qp_context->srqn = cpu_to_be32(1 << 24 |
 837                                                to_msrq(ibqp->srq)->srqn);
 838
 839         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 840                               qp->qpn, 0, mailbox, 0, &status);
 841         if (status) {
 842                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 843                            state_table[cur_state][new_state].trans, status);
 844                 err = -EINVAL;
 845         }
 846
 847         if (!err)
 848                 qp->state = new_state;
 849
 850         mthca_free_mailbox(dev, mailbox);
 851
 852         if (is_sqp(dev, qp))
 853                 store_attrs(to_msqp(qp), attr, attr_mask);
 854
 855         /*
 856          * If we moved QP0 to RTR, bring the IB link up; if we moved
 857          * QP0 to RESET or ERROR, bring the link back down.
 858          */
 859         if (is_qp0(dev, qp)) {
 860                 if (cur_state != IB_QPS_RTR &&
 861                     new_state == IB_QPS_RTR)
 862                         init_port(dev, to_msqp(qp)->port);
 863
 864                 if (cur_state != IB_QPS_RESET &&
 865                     cur_state != IB_QPS_ERR &&
 866                     (new_state == IB_QPS_RESET ||
 867                      new_state == IB_QPS_ERR))
 868                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 869         }
 870
 871         /*
 872          * If we moved a kernel QP to RESET, clean up all old CQ
 873          * entries and reinitialize the QP.
 874          */
 875         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 876                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 877                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 878                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 879                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 880                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 881
 882                 mthca_wq_init(&qp->sq);
 883                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 884
 885                 mthca_wq_init(&qp->rq);
 886                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 887
 888                 if (mthca_is_memfree(dev)) {
 889                         *qp->sq.db = 0;
 890                         *qp->rq.db = 0;
 891                 }
 892         }
 893
 894         return err;
 895 }
 896
 897 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 898                                  struct mthca_pd *pd,
 899                                  struct mthca_qp *qp)
 900 {
 901         int max_data_size;
 902
 903         /*
 904          * Calculate the maximum size of WQE s/g segments, excluding
 905          * the next segment and other non-data segments.
 906          */
 907         max_data_size = min(dev->limits.max_desc_sz, 1 << qp->sq.wqe_shift) -
 908                 sizeof (struct mthca_next_seg);
 909
 910         switch (qp->transport) {
 911         case MLX:
 912                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 913                 break;
 914
 915         case UD:
 916                 if (mthca_is_memfree(dev))
 917                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 918                 else
 919                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 920                 break;
 921
 922         default:
 923                 max_data_size -= sizeof (struct mthca_raddr_seg);
 924                 break;
 925         }
 926
 927         /* We don't support inline data for kernel QPs (yet). */
 928         if (!pd->ibpd.uobject)
 929                 qp->max_inline_data = 0;
 930         else
 931                 qp->max_inline_data = max_data_size - MTHCA_INLINE_HEADER_SIZE;
 932
 933         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 934                               max_data_size / sizeof (struct mthca_data_seg));
 935         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 936                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 937                                 sizeof (struct mthca_next_seg)) /
 938                                sizeof (struct mthca_data_seg));
 939 }
 940
 941 /*
 942  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 943  * rq.max_gs and sq.max_gs must all be assigned.
 944  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 945  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 946  * queue)
 947  */
 948 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 949                                struct mthca_pd *pd,
 950                                struct mthca_qp *qp)
 951 {
 952         int size;
 953         int err = -ENOMEM;
 954
 955         size = sizeof (struct mthca_next_seg) +
 956                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 957
 958         if (size > dev->limits.max_desc_sz)
 959                 return -EINVAL;
 960
 961         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 962              qp->rq.wqe_shift++)
 963                 ; /* nothing */
 964
 965         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 966         switch (qp->transport) {
 967         case MLX:
 968                 size += 2 * sizeof (struct mthca_data_seg);
 969                 break;
 970
 971         case UD:
 972                 size += mthca_is_memfree(dev) ?
 973                         sizeof (struct mthca_arbel_ud_seg) :
 974                         sizeof (struct mthca_tavor_ud_seg);
 975                 break;
 976
 977         case UC:
 978                 size += sizeof (struct mthca_raddr_seg);
 979                 break;
 980
 981         case RC:
 982                 size += sizeof (struct mthca_raddr_seg);
 983                 /*
 984                  * An atomic op will require an atomic segment, a
 985                  * remote address segment and one scatter entry.
 986                  */
 987                 size = max_t(int, size,
 988                              sizeof (struct mthca_atomic_seg) +
 989                              sizeof (struct mthca_raddr_seg) +
 990                              sizeof (struct mthca_data_seg));
 991                 break;
 992
 993         default:
 994                 break;
 995         }
 996
 997         /* Make sure that we have enough space for a bind request */
 998         size = max_t(int, size, sizeof (struct mthca_bind_seg));
 999
1000         size += sizeof (struct mthca_next_seg);
1001
1002         if (size > dev->limits.max_desc_sz)
1003                 return -EINVAL;
1004
1005         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1006              qp->sq.wqe_shift++)
1007                 ; /* nothing */
1008
1009         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1010                                     1 << qp->sq.wqe_shift);
1011
1012         /*
1013          * If this is a userspace QP, we don't actually have to
1014          * allocate anything.  All we need is to calculate the WQE
1015          * sizes and the send_wqe_offset, so we're done now.
1016          */
1017         if (pd->ibpd.uobject)
1018                 return 0;
1019
1020         size = PAGE_ALIGN(qp->send_wqe_offset +
1021                           (qp->sq.max << qp->sq.wqe_shift));
1022
1023         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1024                            GFP_KERNEL);
1025         if (!qp->wrid)
1026                 goto err_out;
1027
1028         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1029                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1030         if (err)
1031                 goto err_out;
1032
1033         return 0;
1034
1035 err_out:
1036         kfree(qp->wrid);
1037         return err;
1038 }
1039
1040 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1041                                struct mthca_qp *qp)
1042 {
1043         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1044                                        (qp->sq.max << qp->sq.wqe_shift)),
1045                        &qp->queue, qp->is_direct, &qp->mr);
1046         kfree(qp->wrid);
1047 }
1048
1049 static int mthca_map_memfree(struct mthca_dev *dev,
1050                              struct mthca_qp *qp)
1051 {
1052         int ret;
1053
1054         if (mthca_is_memfree(dev)) {
1055                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1056                 if (ret)
1057                         return ret;
1058
1059                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1060                 if (ret)
1061                         goto err_qpc;
1062
1063                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1064                                       qp->qpn << dev->qp_table.rdb_shift);
1065                 if (ret)
1066                         goto err_eqpc;
1067
1068         }
1069
1070         return 0;
1071
1072 err_eqpc:
1073         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1074
1075 err_qpc:
1076         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1077
1078         return ret;
1079 }
1080
1081 static void mthca_unmap_memfree(struct mthca_dev *dev,
1082                                 struct mthca_qp *qp)
1083 {
1084         mthca_table_put(dev, dev->qp_table.rdb_table,
1085                         qp->qpn << dev->qp_table.rdb_shift);
1086         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1087         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1088 }
1089
1090 static int mthca_alloc_memfree(struct mthca_dev *dev,
1091                                struct mthca_qp *qp)
1092 {
1093         int ret = 0;
1094
1095         if (mthca_is_memfree(dev)) {
1096                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1097                                                  qp->qpn, &qp->rq.db);
1098                 if (qp->rq.db_index < 0)
1099                         return ret;
1100
1101                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1102                                                  qp->qpn, &qp->sq.db);
1103                 if (qp->sq.db_index < 0)
1104                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1105         }
1106
1107         return ret;
1108 }
1109
1110 static void mthca_free_memfree(struct mthca_dev *dev,
1111                                struct mthca_qp *qp)
1112 {
1113         if (mthca_is_memfree(dev)) {
1114                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1115                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1116         }
1117 }
1118
1119 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1120                                  struct mthca_pd *pd,
1121                                  struct mthca_cq *send_cq,
1122                                  struct mthca_cq *recv_cq,
1123                                  enum ib_sig_type send_policy,
1124                                  struct mthca_qp *qp)
1125 {
1126         int ret;
1127         int i;
1128
1129         atomic_set(&qp->refcount, 1);
1130         init_waitqueue_head(&qp->wait);
1131         qp->state        = IB_QPS_RESET;
1132         qp->atomic_rd_en = 0;
1133         qp->resp_depth   = 0;
1134         qp->sq_policy    = send_policy;
1135         mthca_wq_init(&qp->sq);
1136         mthca_wq_init(&qp->rq);
1137
1138         ret = mthca_map_memfree(dev, qp);
1139         if (ret)
1140                 return ret;
1141
1142         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1143         if (ret) {
1144                 mthca_unmap_memfree(dev, qp);
1145                 return ret;
1146         }
1147
1148         mthca_adjust_qp_caps(dev, pd, qp);
1149
1150         /*
1151          * If this is a userspace QP, we're done now.  The doorbells
1152          * will be allocated and buffers will be initialized in
1153          * userspace.
1154          */
1155         if (pd->ibpd.uobject)
1156                 return 0;
1157
1158         ret = mthca_alloc_memfree(dev, qp);
1159         if (ret) {
1160                 mthca_free_wqe_buf(dev, qp);
1161                 mthca_unmap_memfree(dev, qp);
1162                 return ret;
1163         }
1164
1165         if (mthca_is_memfree(dev)) {
1166                 struct mthca_next_seg *next;
1167                 struct mthca_data_seg *scatter;
1168                 int size = (sizeof (struct mthca_next_seg) +
1169                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1170
1171                 for (i = 0; i < qp->rq.max; ++i) {
1172                         next = get_recv_wqe(qp, i);
1173                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1174                                                    qp->rq.wqe_shift);
1175                         next->ee_nds = cpu_to_be32(size);
1176
1177                         for (scatter = (void *) (next + 1);
1178                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1179                              ++scatter)
1180                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1181                 }
1182
1183                 for (i = 0; i < qp->sq.max; ++i) {
1184                         next = get_send_wqe(qp, i);
1185                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1186                                                     qp->sq.wqe_shift) +
1187                                                    qp->send_wqe_offset);
1188                 }
1189         }
1190
1191         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1192         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1193
1194         return 0;
1195 }
1196
1197 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1198                              struct mthca_qp *qp)
1199 {
1200         /* Sanity check QP size before proceeding */
1201         if (cap->max_send_wr  > dev->limits.max_wqes ||
1202             cap->max_recv_wr  > dev->limits.max_wqes ||
1203             cap->max_send_sge > dev->limits.max_sg   ||
1204             cap->max_recv_sge > dev->limits.max_sg)
1205                 return -EINVAL;
1206
1207         if (mthca_is_memfree(dev)) {
1208                 qp->rq.max = cap->max_recv_wr ?
1209                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1210                 qp->sq.max = cap->max_send_wr ?
1211                         roundup_pow_of_two(cap->max_send_wr) : 0;
1212         } else {
1213                 qp->rq.max = cap->max_recv_wr;
1214                 qp->sq.max = cap->max_send_wr;
1215         }
1216
1217         qp->rq.max_gs = cap->max_recv_sge;
1218         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1219                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1220                                     MTHCA_INLINE_CHUNK_SIZE) /
1221                               sizeof (struct mthca_data_seg));
1222
1223         /*
1224          * For MLX transport we need 2 extra S/G entries:
1225          * one for the header and one for the checksum at the end
1226          */
1227         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1228             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1229                 return -EINVAL;
1230
1231         return 0;
1232 }
1233
1234 int mthca_alloc_qp(struct mthca_dev *dev,
1235                    struct mthca_pd *pd,
1236                    struct mthca_cq *send_cq,
1237                    struct mthca_cq *recv_cq,
1238                    enum ib_qp_type type,
1239                    enum ib_sig_type send_policy,
1240                    struct ib_qp_cap *cap,
1241                    struct mthca_qp *qp)
1242 {
1243         int err;
1244
1245         err = mthca_set_qp_size(dev, cap, qp);
1246         if (err)
1247                 return err;
1248
1249         switch (type) {
1250         case IB_QPT_RC: qp->transport = RC; break;
1251         case IB_QPT_UC: qp->transport = UC; break;
1252         case IB_QPT_UD: qp->transport = UD; break;
1253         default: return -EINVAL;
1254         }
1255
1256         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1257         if (qp->qpn == -1)
1258                 return -ENOMEM;
1259
1260         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1261                                     send_policy, qp);
1262         if (err) {
1263                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1264                 return err;
1265         }
1266
1267         spin_lock_irq(&dev->qp_table.lock);
1268         mthca_array_set(&dev->qp_table.qp,
1269                         qp->qpn & (dev->limits.num_qps - 1), qp);
1270         spin_unlock_irq(&dev->qp_table.lock);
1271
1272         return 0;
1273 }
1274
1275 int mthca_alloc_sqp(struct mthca_dev *dev,
1276                     struct mthca_pd *pd,
1277                     struct mthca_cq *send_cq,
1278                     struct mthca_cq *recv_cq,
1279                     enum ib_sig_type send_policy,
1280                     struct ib_qp_cap *cap,
1281                     int qpn,
1282                     int port,
1283                     struct mthca_sqp *sqp)
1284 {
1285         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1286         int err;
1287
1288         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1289         if (err)
1290                 return err;
1291
1292         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1293         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1294                                              &sqp->header_dma, GFP_KERNEL);
1295         if (!sqp->header_buf)
1296                 return -ENOMEM;
1297
1298         spin_lock_irq(&dev->qp_table.lock);
1299         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1300                 err = -EBUSY;
1301         else
1302                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1303         spin_unlock_irq(&dev->qp_table.lock);
1304
1305         if (err)
1306                 goto err_out;
1307
1308         sqp->port = port;
1309         sqp->qp.qpn       = mqpn;
1310         sqp->qp.transport = MLX;
1311
1312         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1313                                     send_policy, &sqp->qp);
1314         if (err)
1315                 goto err_out_free;
1316
1317         atomic_inc(&pd->sqp_count);
1318
1319         return 0;
1320
1321  err_out_free:
1322         /*
1323          * Lock CQs here, so that CQ polling code can do QP lookup
1324          * without taking a lock.
1325          */
1326         spin_lock_irq(&send_cq->lock);
1327         if (send_cq != recv_cq)
1328                 spin_lock(&recv_cq->lock);
1329
1330         spin_lock(&dev->qp_table.lock);
1331         mthca_array_clear(&dev->qp_table.qp, mqpn);
1332         spin_unlock(&dev->qp_table.lock);
1333
1334         if (send_cq != recv_cq)
1335                 spin_unlock(&recv_cq->lock);
1336         spin_unlock_irq(&send_cq->lock);
1337
1338  err_out:
1339         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1340                           sqp->header_buf, sqp->header_dma);
1341
1342         return err;
1343 }
1344
1345 void mthca_free_qp(struct mthca_dev *dev,
1346                    struct mthca_qp *qp)
1347 {
1348         u8 status;
1349         struct mthca_cq *send_cq;
1350         struct mthca_cq *recv_cq;
1351
1352         send_cq = to_mcq(qp->ibqp.send_cq);
1353         recv_cq = to_mcq(qp->ibqp.recv_cq);
1354
1355         /*
1356          * Lock CQs here, so that CQ polling code can do QP lookup
1357          * without taking a lock.
1358          */
1359         spin_lock_irq(&send_cq->lock);
1360         if (send_cq != recv_cq)
1361                 spin_lock(&recv_cq->lock);
1362
1363         spin_lock(&dev->qp_table.lock);
1364         mthca_array_clear(&dev->qp_table.qp,
1365                           qp->qpn & (dev->limits.num_qps - 1));
1366         spin_unlock(&dev->qp_table.lock);
1367
1368         if (send_cq != recv_cq)
1369                 spin_unlock(&recv_cq->lock);
1370         spin_unlock_irq(&send_cq->lock);
1371
1372         atomic_dec(&qp->refcount);
1373         wait_event(qp->wait, !atomic_read(&qp->refcount));
1374
1375         if (qp->state != IB_QPS_RESET)
1376                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1377
1378         /*
1379          * If this is a userspace QP, the buffers, MR, CQs and so on
1380          * will be cleaned up in userspace, so all we have to do is
1381          * unref the mem-free tables and free the QPN in our table.
1382          */
1383         if (!qp->ibqp.uobject) {
1384                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1385                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1386                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1387                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1388                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1389
1390                 mthca_free_memfree(dev, qp);
1391                 mthca_free_wqe_buf(dev, qp);
1392         }
1393
1394         mthca_unmap_memfree(dev, qp);
1395
1396         if (is_sqp(dev, qp)) {
1397                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1398                 dma_free_coherent(&dev->pdev->dev,
1399                                   to_msqp(qp)->header_buf_size,
1400                                   to_msqp(qp)->header_buf,
1401                                   to_msqp(qp)->header_dma);
1402         } else
1403                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1404 }
1405
1406 /* Create UD header for an MLX send and build a data segment for it */
1407 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1408                             int ind, struct ib_send_wr *wr,
1409                             struct mthca_mlx_seg *mlx,
1410                             struct mthca_data_seg *data)
1411 {
1412         int header_size;
1413         int err;
1414         u16 pkey;
1415
1416         ib_ud_header_init(256, /* assume a MAD */
1417                           sqp->ud_header.grh_present,
1418                           &sqp->ud_header);
1419
1420         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1421         if (err)
1422                 return err;
1423         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1424         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1425                                   (sqp->ud_header.lrh.destination_lid ==
1426                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1427                                   (sqp->ud_header.lrh.service_level << 8));
1428         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1429         mlx->vcrc = 0;
1430
1431         switch (wr->opcode) {
1432         case IB_WR_SEND:
1433                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1434                 sqp->ud_header.immediate_present = 0;
1435                 break;
1436         case IB_WR_SEND_WITH_IMM:
1437                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1438                 sqp->ud_header.immediate_present = 1;
1439                 sqp->ud_header.immediate_data = wr->imm_data;
1440                 break;
1441         default:
1442                 return -EINVAL;
1443         }
1444
1445         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1446         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1447                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1448         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1449         if (!sqp->qp.ibqp.qp_num)
1450                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1451                                    sqp->pkey_index, &pkey);
1452         else
1453                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1454                                    wr->wr.ud.pkey_index, &pkey);
1455         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1456         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1457         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1458         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1459                                                sqp->qkey : wr->wr.ud.remote_qkey);
1460         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1461
1462         header_size = ib_ud_header_pack(&sqp->ud_header,
1463                                         sqp->header_buf +
1464                                         ind * MTHCA_UD_HEADER_SIZE);
1465
1466         data->byte_count = cpu_to_be32(header_size);
1467         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1468         data->addr       = cpu_to_be64(sqp->header_dma +
1469                                        ind * MTHCA_UD_HEADER_SIZE);
1470
1471         return 0;
1472 }
1473
1474 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1475                                     struct ib_cq *ib_cq)
1476 {
1477         unsigned cur;
1478         struct mthca_cq *cq;
1479
1480         cur = wq->head - wq->tail;
1481         if (likely(cur + nreq < wq->max))
1482                 return 0;
1483
1484         cq = to_mcq(ib_cq);
1485         spin_lock(&cq->lock);
1486         cur = wq->head - wq->tail;
1487         spin_unlock(&cq->lock);
1488
1489         return cur + nreq >= wq->max;
1490 }
1491
1492 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1493                           struct ib_send_wr **bad_wr)
1494 {
1495         struct mthca_dev *dev = to_mdev(ibqp->device);
1496         struct mthca_qp *qp = to_mqp(ibqp);
1497         void *wqe;
1498         void *prev_wqe;
1499         unsigned long flags;
1500         int err = 0;
1501         int nreq;
1502         int i;
1503         int size;
1504         int size0 = 0;
1505         u32 f0 = 0;
1506         int ind;
1507         u8 op0 = 0;
1508
1509         spin_lock_irqsave(&qp->sq.lock, flags);
1510
1511         /* XXX check that state is OK to post send */
1512
1513         ind = qp->sq.next_ind;
1514
1515         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1516                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1517                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1518                                         " %d max, %d nreq)\n", qp->qpn,
1519                                         qp->sq.head, qp->sq.tail,
1520                                         qp->sq.max, nreq);
1521                         err = -ENOMEM;
1522                         *bad_wr = wr;
1523                         goto out;
1524                 }
1525
1526                 wqe = get_send_wqe(qp, ind);
1527                 prev_wqe = qp->sq.last;
1528                 qp->sq.last = wqe;
1529
1530                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1531                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1532                 ((struct mthca_next_seg *) wqe)->flags =
1533                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1534                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1535                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1536                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1537                         cpu_to_be32(1);
1538                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1539                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1540                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1541
1542                 wqe += sizeof (struct mthca_next_seg);
1543                 size = sizeof (struct mthca_next_seg) / 16;
1544
1545                 switch (qp->transport) {
1546                 case RC:
1547                         switch (wr->opcode) {
1548                         case IB_WR_ATOMIC_CMP_AND_SWP:
1549                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1550                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1551                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1552                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1553                                         cpu_to_be32(wr->wr.atomic.rkey);
1554                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1555
1556                                 wqe += sizeof (struct mthca_raddr_seg);
1557
1558                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1559                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1560                                                 cpu_to_be64(wr->wr.atomic.swap);
1561                                         ((struct mthca_atomic_seg *) wqe)->compare =
1562                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1563                                 } else {
1564                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1565                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1566                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1567                                 }
1568
1569                                 wqe += sizeof (struct mthca_atomic_seg);
1570                                 size += (sizeof (struct mthca_raddr_seg) +
1571                                          sizeof (struct mthca_atomic_seg)) / 16;
1572                                 break;
1573
1574                         case IB_WR_RDMA_WRITE:
1575                         case IB_WR_RDMA_WRITE_WITH_IMM:
1576                         case IB_WR_RDMA_READ:
1577                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1578                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1579                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1580                                         cpu_to_be32(wr->wr.rdma.rkey);
1581                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1582                                 wqe += sizeof (struct mthca_raddr_seg);
1583                                 size += sizeof (struct mthca_raddr_seg) / 16;
1584                                 break;
1585
1586                         default:
1587                                 /* No extra segments required for sends */
1588                                 break;
1589                         }
1590
1591                         break;
1592
1593                 case UC:
1594                         switch (wr->opcode) {
1595                         case IB_WR_RDMA_WRITE:
1596                         case IB_WR_RDMA_WRITE_WITH_IMM:
1597                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1598                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1599                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1600                                         cpu_to_be32(wr->wr.rdma.rkey);
1601                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1602                                 wqe += sizeof (struct mthca_raddr_seg);
1603                                 size += sizeof (struct mthca_raddr_seg) / 16;
1604                                 break;
1605
1606                         default:
1607                                 /* No extra segments required for sends */
1608                                 break;
1609                         }
1610
1611                         break;
1612
1613                 case UD:
1614                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1615                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1616                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1617                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1618                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1619                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1620                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1621                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1622
1623                         wqe += sizeof (struct mthca_tavor_ud_seg);
1624                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1625                         break;
1626
1627                 case MLX:
1628                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1629                                                wqe - sizeof (struct mthca_next_seg),
1630                                                wqe);
1631                         if (err) {
1632                                 *bad_wr = wr;
1633                                 goto out;
1634                         }
1635                         wqe += sizeof (struct mthca_data_seg);
1636                         size += sizeof (struct mthca_data_seg) / 16;
1637                         break;
1638                 }
1639
1640                 if (wr->num_sge > qp->sq.max_gs) {
1641                         mthca_err(dev, "too many gathers\n");
1642                         err = -EINVAL;
1643                         *bad_wr = wr;
1644                         goto out;
1645                 }
1646
1647                 for (i = 0; i < wr->num_sge; ++i) {
1648                         ((struct mthca_data_seg *) wqe)->byte_count =
1649                                 cpu_to_be32(wr->sg_list[i].length);
1650                         ((struct mthca_data_seg *) wqe)->lkey =
1651                                 cpu_to_be32(wr->sg_list[i].lkey);
1652                         ((struct mthca_data_seg *) wqe)->addr =
1653                                 cpu_to_be64(wr->sg_list[i].addr);
1654                         wqe += sizeof (struct mthca_data_seg);
1655                         size += sizeof (struct mthca_data_seg) / 16;
1656                 }
1657
1658                 /* Add one more inline data segment for ICRC */
1659                 if (qp->transport == MLX) {
1660                         ((struct mthca_data_seg *) wqe)->byte_count =
1661                                 cpu_to_be32((1 << 31) | 4);
1662                         ((u32 *) wqe)[1] = 0;
1663                         wqe += sizeof (struct mthca_data_seg);
1664                         size += sizeof (struct mthca_data_seg) / 16;
1665                 }
1666
1667                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1668
1669                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1670                         mthca_err(dev, "opcode invalid\n");
1671                         err = -EINVAL;
1672                         *bad_wr = wr;
1673                         goto out;
1674                 }
1675
1676                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1677                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1678                                      qp->send_wqe_offset) |
1679                                     mthca_opcode[wr->opcode]);
1680                 wmb();
1681                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1682                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1683
1684                 if (!size0) {
1685                         size0 = size;
1686                         op0   = mthca_opcode[wr->opcode];
1687                 }
1688
1689                 ++ind;
1690                 if (unlikely(ind >= qp->sq.max))
1691                         ind -= qp->sq.max;
1692         }
1693
1694 out:
1695         if (likely(nreq)) {
1696                 __be32 doorbell[2];
1697
1698                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1699                                            qp->send_wqe_offset) | f0 | op0);
1700                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1701
1702                 wmb();
1703
1704                 mthca_write64(doorbell,
1705                               dev->kar + MTHCA_SEND_DOORBELL,
1706                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1707         }
1708
1709         qp->sq.next_ind = ind;
1710         qp->sq.head    += nreq;
1711
1712         spin_unlock_irqrestore(&qp->sq.lock, flags);
1713         return err;
1714 }
1715
1716 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1717                              struct ib_recv_wr **bad_wr)
1718 {
1719         struct mthca_dev *dev = to_mdev(ibqp->device);
1720         struct mthca_qp *qp = to_mqp(ibqp);
1721         __be32 doorbell[2];
1722         unsigned long flags;
1723         int err = 0;
1724         int nreq;
1725         int i;
1726         int size;
1727         int size0 = 0;
1728         int ind;
1729         void *wqe;
1730         void *prev_wqe;
1731
1732         spin_lock_irqsave(&qp->rq.lock, flags);
1733
1734         /* XXX check that state is OK to post receive */
1735
1736         ind = qp->rq.next_ind;
1737
1738         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1739                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1740                         nreq = 0;
1741
1742                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1743                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1744
1745                         wmb();
1746
1747                         mthca_write64(doorbell,
1748                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1749                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1750
1751                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1752                         size0 = 0;
1753                 }
1754
1755                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1756                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1757                                         " %d max, %d nreq)\n", qp->qpn,
1758                                         qp->rq.head, qp->rq.tail,
1759                                         qp->rq.max, nreq);
1760                         err = -ENOMEM;
1761                         *bad_wr = wr;
1762                         goto out;
1763                 }
1764
1765                 wqe = get_recv_wqe(qp, ind);
1766                 prev_wqe = qp->rq.last;
1767                 qp->rq.last = wqe;
1768
1769                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1770                 ((struct mthca_next_seg *) wqe)->ee_nds =
1771                         cpu_to_be32(MTHCA_NEXT_DBD);
1772                 ((struct mthca_next_seg *) wqe)->flags = 0;
1773
1774                 wqe += sizeof (struct mthca_next_seg);
1775                 size = sizeof (struct mthca_next_seg) / 16;
1776
1777                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1778                         err = -EINVAL;
1779                         *bad_wr = wr;
1780                         goto out;
1781                 }
1782
1783                 for (i = 0; i < wr->num_sge; ++i) {
1784                         ((struct mthca_data_seg *) wqe)->byte_count =
1785                                 cpu_to_be32(wr->sg_list[i].length);
1786                         ((struct mthca_data_seg *) wqe)->lkey =
1787                                 cpu_to_be32(wr->sg_list[i].lkey);
1788                         ((struct mthca_data_seg *) wqe)->addr =
1789                                 cpu_to_be64(wr->sg_list[i].addr);
1790                         wqe += sizeof (struct mthca_data_seg);
1791                         size += sizeof (struct mthca_data_seg) / 16;
1792                 }
1793
1794                 qp->wrid[ind] = wr->wr_id;
1795
1796                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1797                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1798                 wmb();
1799                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1800                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1801
1802                 if (!size0)
1803                         size0 = size;
1804
1805                 ++ind;
1806                 if (unlikely(ind >= qp->rq.max))
1807                         ind -= qp->rq.max;
1808         }
1809
1810 out:
1811         if (likely(nreq)) {
1812                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1813                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1814
1815                 wmb();
1816
1817                 mthca_write64(doorbell,
1818                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1819                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1820         }
1821
1822         qp->rq.next_ind = ind;
1823         qp->rq.head    += nreq;
1824
1825         spin_unlock_irqrestore(&qp->rq.lock, flags);
1826         return err;
1827 }
1828
1829 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1830                           struct ib_send_wr **bad_wr)
1831 {
1832         struct mthca_dev *dev = to_mdev(ibqp->device);
1833         struct mthca_qp *qp = to_mqp(ibqp);
1834         __be32 doorbell[2];
1835         void *wqe;
1836         void *prev_wqe;
1837         unsigned long flags;
1838         int err = 0;
1839         int nreq;
1840         int i;
1841         int size;
1842         int size0 = 0;
1843         u32 f0 = 0;
1844         int ind;
1845         u8 op0 = 0;
1846
1847         spin_lock_irqsave(&qp->sq.lock, flags);
1848
1849         /* XXX check that state is OK to post send */
1850
1851         ind = qp->sq.head & (qp->sq.max - 1);
1852
1853         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1854                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1855                         nreq = 0;
1856
1857                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1858                                                   ((qp->sq.head & 0xffff) << 8) |
1859                                                   f0 | op0);
1860                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1861
1862                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1863                         size0 = 0;
1864
1865                         /*
1866                          * Make sure that descriptors are written before
1867                          * doorbell record.
1868                          */
1869                         wmb();
1870                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1871
1872                         /*
1873                          * Make sure doorbell record is written before we
1874                          * write MMIO send doorbell.
1875                          */
1876                         wmb();
1877                         mthca_write64(doorbell,
1878                                       dev->kar + MTHCA_SEND_DOORBELL,
1879                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1880                 }
1881
1882                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1883                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1884                                         " %d max, %d nreq)\n", qp->qpn,
1885                                         qp->sq.head, qp->sq.tail,
1886                                         qp->sq.max, nreq);
1887                         err = -ENOMEM;
1888                         *bad_wr = wr;
1889                         goto out;
1890                 }
1891
1892                 wqe = get_send_wqe(qp, ind);
1893                 prev_wqe = qp->sq.last;
1894                 qp->sq.last = wqe;
1895
1896                 ((struct mthca_next_seg *) wqe)->flags =
1897                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1898                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1899                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1900                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1901                         cpu_to_be32(1);
1902                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1903                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1904                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1905
1906                 wqe += sizeof (struct mthca_next_seg);
1907                 size = sizeof (struct mthca_next_seg) / 16;
1908
1909                 switch (qp->transport) {
1910                 case RC:
1911                         switch (wr->opcode) {
1912                         case IB_WR_ATOMIC_CMP_AND_SWP:
1913                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1914                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1915                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1916                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1917                                         cpu_to_be32(wr->wr.atomic.rkey);
1918                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1919
1920                                 wqe += sizeof (struct mthca_raddr_seg);
1921
1922                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1923                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1924                                                 cpu_to_be64(wr->wr.atomic.swap);
1925                                         ((struct mthca_atomic_seg *) wqe)->compare =
1926                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1927                                 } else {
1928                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1929                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1930                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1931                                 }
1932
1933                                 wqe += sizeof (struct mthca_atomic_seg);
1934                                 size += (sizeof (struct mthca_raddr_seg) +
1935                                          sizeof (struct mthca_atomic_seg)) / 16;
1936                                 break;
1937
1938                         case IB_WR_RDMA_READ:
1939                         case IB_WR_RDMA_WRITE:
1940                         case IB_WR_RDMA_WRITE_WITH_IMM:
1941                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1942                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1943                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1944                                         cpu_to_be32(wr->wr.rdma.rkey);
1945                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1946                                 wqe += sizeof (struct mthca_raddr_seg);
1947                                 size += sizeof (struct mthca_raddr_seg) / 16;
1948                                 break;
1949
1950                         default:
1951                                 /* No extra segments required for sends */
1952                                 break;
1953                         }
1954
1955                         break;
1956
1957                 case UC:
1958                         switch (wr->opcode) {
1959                         case IB_WR_RDMA_WRITE:
1960                         case IB_WR_RDMA_WRITE_WITH_IMM:
1961                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1962                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1963                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1964                                         cpu_to_be32(wr->wr.rdma.rkey);
1965                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1966                                 wqe += sizeof (struct mthca_raddr_seg);
1967                                 size += sizeof (struct mthca_raddr_seg) / 16;
1968                                 break;
1969
1970                         default:
1971                                 /* No extra segments required for sends */
1972                                 break;
1973                         }
1974
1975                         break;
1976
1977                 case UD:
1978                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1979                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1980                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1981                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1982                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1983                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1984
1985                         wqe += sizeof (struct mthca_arbel_ud_seg);
1986                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1987                         break;
1988
1989                 case MLX:
1990                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1991                                                wqe - sizeof (struct mthca_next_seg),
1992                                                wqe);
1993                         if (err) {
1994                                 *bad_wr = wr;
1995                                 goto out;
1996                         }
1997                         wqe += sizeof (struct mthca_data_seg);
1998                         size += sizeof (struct mthca_data_seg) / 16;
1999                         break;
2000                 }
2001
2002                 if (wr->num_sge > qp->sq.max_gs) {
2003                         mthca_err(dev, "too many gathers\n");
2004                         err = -EINVAL;
2005                         *bad_wr = wr;
2006                         goto out;
2007                 }
2008
2009                 for (i = 0; i < wr->num_sge; ++i) {
2010                         ((struct mthca_data_seg *) wqe)->byte_count =
2011                                 cpu_to_be32(wr->sg_list[i].length);
2012                         ((struct mthca_data_seg *) wqe)->lkey =
2013                                 cpu_to_be32(wr->sg_list[i].lkey);
2014                         ((struct mthca_data_seg *) wqe)->addr =
2015                                 cpu_to_be64(wr->sg_list[i].addr);
2016                         wqe += sizeof (struct mthca_data_seg);
2017                         size += sizeof (struct mthca_data_seg) / 16;
2018                 }
2019
2020                 /* Add one more inline data segment for ICRC */
2021                 if (qp->transport == MLX) {
2022                         ((struct mthca_data_seg *) wqe)->byte_count =
2023                                 cpu_to_be32((1 << 31) | 4);
2024                         ((u32 *) wqe)[1] = 0;
2025                         wqe += sizeof (struct mthca_data_seg);
2026                         size += sizeof (struct mthca_data_seg) / 16;
2027                 }
2028
2029                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2030
2031                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2032                         mthca_err(dev, "opcode invalid\n");
2033                         err = -EINVAL;
2034                         *bad_wr = wr;
2035                         goto out;
2036                 }
2037
2038                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2039                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2040                                      qp->send_wqe_offset) |
2041                                     mthca_opcode[wr->opcode]);
2042                 wmb();
2043                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2044                         cpu_to_be32(MTHCA_NEXT_DBD | size);
2045
2046                 if (!size0) {
2047                         size0 = size;
2048                         op0   = mthca_opcode[wr->opcode];
2049                 }
2050
2051                 ++ind;
2052                 if (unlikely(ind >= qp->sq.max))
2053                         ind -= qp->sq.max;
2054         }
2055
2056 out:
2057         if (likely(nreq)) {
2058                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2059                                           ((qp->sq.head & 0xffff) << 8) |
2060                                           f0 | op0);
2061                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2062
2063                 qp->sq.head += nreq;
2064
2065                 /*
2066                  * Make sure that descriptors are written before
2067                  * doorbell record.
2068                  */
2069                 wmb();
2070                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2071
2072                 /*
2073                  * Make sure doorbell record is written before we
2074                  * write MMIO send doorbell.
2075                  */
2076                 wmb();
2077                 mthca_write64(doorbell,
2078                               dev->kar + MTHCA_SEND_DOORBELL,
2079                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2080         }
2081
2082         spin_unlock_irqrestore(&qp->sq.lock, flags);
2083         return err;
2084 }
2085
2086 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2087                              struct ib_recv_wr **bad_wr)
2088 {
2089         struct mthca_dev *dev = to_mdev(ibqp->device);
2090         struct mthca_qp *qp = to_mqp(ibqp);
2091         unsigned long flags;
2092         int err = 0;
2093         int nreq;
2094         int ind;
2095         int i;
2096         void *wqe;
2097
2098         spin_lock_irqsave(&qp->rq.lock, flags);
2099
2100         /* XXX check that state is OK to post receive */
2101
2102         ind = qp->rq.head & (qp->rq.max - 1);
2103
2104         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2105                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2106                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2107                                         " %d max, %d nreq)\n", qp->qpn,
2108                                         qp->rq.head, qp->rq.tail,
2109                                         qp->rq.max, nreq);
2110                         err = -ENOMEM;
2111                         *bad_wr = wr;
2112                         goto out;
2113                 }
2114
2115                 wqe = get_recv_wqe(qp, ind);
2116
2117                 ((struct mthca_next_seg *) wqe)->flags = 0;
2118
2119                 wqe += sizeof (struct mthca_next_seg);
2120
2121                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2122                         err = -EINVAL;
2123                         *bad_wr = wr;
2124                         goto out;
2125                 }
2126
2127                 for (i = 0; i < wr->num_sge; ++i) {
2128                         ((struct mthca_data_seg *) wqe)->byte_count =
2129                                 cpu_to_be32(wr->sg_list[i].length);
2130                         ((struct mthca_data_seg *) wqe)->lkey =
2131                                 cpu_to_be32(wr->sg_list[i].lkey);
2132                         ((struct mthca_data_seg *) wqe)->addr =
2133                                 cpu_to_be64(wr->sg_list[i].addr);
2134                         wqe += sizeof (struct mthca_data_seg);
2135                 }
2136
2137                 if (i < qp->rq.max_gs) {
2138                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2139                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2140                         ((struct mthca_data_seg *) wqe)->addr = 0;
2141                 }
2142
2143                 qp->wrid[ind] = wr->wr_id;
2144
2145                 ++ind;
2146                 if (unlikely(ind >= qp->rq.max))
2147                         ind -= qp->rq.max;
2148         }
2149 out:
2150         if (likely(nreq)) {
2151                 qp->rq.head += nreq;
2152
2153                 /*
2154                  * Make sure that descriptors are written before
2155                  * doorbell record.
2156                  */
2157                 wmb();
2158                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2159         }
2160
2161         spin_unlock_irqrestore(&qp->rq.lock, flags);
2162         return err;
2163 }
2164
2165 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2166                        int index, int *dbd, __be32 *new_wqe)
2167 {
2168         struct mthca_next_seg *next;
2169
2170         /*
2171          * For SRQs, all WQEs generate a CQE, so we're always at the
2172          * end of the doorbell chain.
2173          */
2174         if (qp->ibqp.srq) {
2175                 *new_wqe = 0;
2176                 return 0;
2177         }
2178
2179         if (is_send)
2180                 next = get_send_wqe(qp, index);
2181         else
2182                 next = get_recv_wqe(qp, index);
2183
2184         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2185         if (next->ee_nds & cpu_to_be32(0x3f))
2186                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2187                         (next->ee_nds & cpu_to_be32(0x3f));
2188         else
2189                 *new_wqe = 0;
2190
2191         return 0;
2192 }
2193
2194 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2195 {
2196         int err;
2197         u8 status;
2198         int i;
2199
2200         spin_lock_init(&dev->qp_table.lock);
2201
2202         /*
2203          * We reserve 2 extra QPs per port for the special QPs.  The
2204          * special QP for port 1 has to be even, so round up.
2205          */
2206         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2207         err = mthca_alloc_init(&dev->qp_table.alloc,
2208                                dev->limits.num_qps,
2209                                (1 << 24) - 1,
2210                                dev->qp_table.sqp_start +
2211                                MTHCA_MAX_PORTS * 2);
2212         if (err)
2213                 return err;
2214
2215         err = mthca_array_init(&dev->qp_table.qp,
2216                                dev->limits.num_qps);
2217         if (err) {
2218                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2219                 return err;
2220         }
2221
2222         for (i = 0; i < 2; ++i) {
2223                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2224                                             dev->qp_table.sqp_start + i * 2,
2225                                             &status);
2226                 if (err)
2227                         goto err_out;
2228                 if (status) {
2229                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2230                                    "status %02x, aborting.\n",
2231                                    status);
2232                         err = -EINVAL;
2233                         goto err_out;
2234                 }
2235         }
2236         return 0;
2237
2238  err_out:
2239         for (i = 0; i < 2; ++i)
2240                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2241
2242         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2243         mthca_alloc_cleanup(&dev->qp_table.alloc);
2244
2245         return err;
2246 }
2247
2248 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2249 {
2250         int i;
2251         u8 status;
2252
2253         for (i = 0; i < 2; ++i)
2254                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2255
2256         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2257         mthca_alloc_cleanup(&dev->qp_table.alloc);
2258 }