drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39
  40 #include <rdma/ib_verbs.h>
  41 #include <rdma/ib_cache.h>
  42 #include <rdma/ib_pack.h>
  43
  44 #include "mthca_dev.h"
  45 #include "mthca_cmd.h"
  46 #include "mthca_memfree.h"
  47 #include "mthca_wqe.h"
  48
  49 enum {
  50         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  51         MTHCA_ACK_REQ_FREQ       = 10,
  52         MTHCA_FLIGHT_LIMIT       = 9,
  53         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  54         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  55         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  56 };
  57
  58 enum {
  59         MTHCA_QP_STATE_RST  = 0,
  60         MTHCA_QP_STATE_INIT = 1,
  61         MTHCA_QP_STATE_RTR  = 2,
  62         MTHCA_QP_STATE_RTS  = 3,
  63         MTHCA_QP_STATE_SQE  = 4,
  64         MTHCA_QP_STATE_SQD  = 5,
  65         MTHCA_QP_STATE_ERR  = 6,
  66         MTHCA_QP_STATE_DRAINING = 7
  67 };
  68
  69 enum {
  70         MTHCA_QP_ST_RC  = 0x0,
  71         MTHCA_QP_ST_UC  = 0x1,
  72         MTHCA_QP_ST_RD  = 0x2,
  73         MTHCA_QP_ST_UD  = 0x3,
  74         MTHCA_QP_ST_MLX = 0x7
  75 };
  76
  77 enum {
  78         MTHCA_QP_PM_MIGRATED = 0x3,
  79         MTHCA_QP_PM_ARMED    = 0x0,
  80         MTHCA_QP_PM_REARM    = 0x1
  81 };
  82
  83 enum {
  84         /* qp_context flags */
  85         MTHCA_QP_BIT_DE  = 1 <<  8,
  86         /* params1 */
  87         MTHCA_QP_BIT_SRE = 1 << 15,
  88         MTHCA_QP_BIT_SWE = 1 << 14,
  89         MTHCA_QP_BIT_SAE = 1 << 13,
  90         MTHCA_QP_BIT_SIC = 1 <<  4,
  91         MTHCA_QP_BIT_SSC = 1 <<  3,
  92         /* params2 */
  93         MTHCA_QP_BIT_RRE = 1 << 15,
  94         MTHCA_QP_BIT_RWE = 1 << 14,
  95         MTHCA_QP_BIT_RAE = 1 << 13,
  96         MTHCA_QP_BIT_RIC = 1 <<  4,
  97         MTHCA_QP_BIT_RSC = 1 <<  3
  98 };
  99
 100 struct mthca_qp_path {
 101         __be32 port_pkey;
 102         u8     rnr_retry;
 103         u8     g_mylmc;
 104         __be16 rlid;
 105         u8     ackto;
 106         u8     mgid_index;
 107         u8     static_rate;
 108         u8     hop_limit;
 109         __be32 sl_tclass_flowlabel;
 110         u8     rgid[16];
 111 } __attribute__((packed));
 112
 113 struct mthca_qp_context {
 114         __be32 flags;
 115         __be32 tavor_sched_queue; /* Reserved on Arbel */
 116         u8     mtu_msgmax;
 117         u8     rq_size_stride;  /* Reserved on Tavor */
 118         u8     sq_size_stride;  /* Reserved on Tavor */
 119         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 120         __be32 usr_page;
 121         __be32 local_qpn;
 122         __be32 remote_qpn;
 123         u32    reserved1[2];
 124         struct mthca_qp_path pri_path;
 125         struct mthca_qp_path alt_path;
 126         __be32 rdd;
 127         __be32 pd;
 128         __be32 wqe_base;
 129         __be32 wqe_lkey;
 130         __be32 params1;
 131         __be32 reserved2;
 132         __be32 next_send_psn;
 133         __be32 cqn_snd;
 134         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 135         __be32 snd_db_index;    /* (debugging only entries) */
 136         __be32 last_acked_psn;
 137         __be32 ssn;
 138         __be32 params2;
 139         __be32 rnr_nextrecvpsn;
 140         __be32 ra_buff_indx;
 141         __be32 cqn_rcv;
 142         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 143         __be32 rcv_db_index;    /* (debugging only entries) */
 144         __be32 qkey;
 145         __be32 srqn;
 146         __be32 rmsn;
 147         __be16 rq_wqe_counter;  /* reserved on Tavor */
 148         __be16 sq_wqe_counter;  /* reserved on Tavor */
 149         u32    reserved3[18];
 150 } __attribute__((packed));
 151
 152 struct mthca_qp_param {
 153         __be32 opt_param_mask;
 154         u32    reserved1;
 155         struct mthca_qp_context context;
 156         u32    reserved2[62];
 157 } __attribute__((packed));
 158
 159 enum {
 160         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 161         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 162         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 163         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 164         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 165         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 166         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 167         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 168         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 169         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 170         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 171         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 172         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 173         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 174         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 175         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 176         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 177 };
 178
 179 static const u8 mthca_opcode[] = {
 180         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 181         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 182         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 183         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 184         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 185         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 186         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 187 };
 188
 189 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 190 {
 191         return qp->qpn >= dev->qp_table.sqp_start &&
 192                 qp->qpn <= dev->qp_table.sqp_start + 3;
 193 }
 194
 195 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 196 {
 197         return qp->qpn >= dev->qp_table.sqp_start &&
 198                 qp->qpn <= dev->qp_table.sqp_start + 1;
 199 }
 200
 201 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 202 {
 203         if (qp->is_direct)
 204                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 205         else
 206                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 207                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 208 }
 209
 210 static void *get_send_wqe(struct mthca_qp *qp, int n)
 211 {
 212         if (qp->is_direct)
 213                 return qp->queue.direct.buf + qp->send_wqe_offset +
 214                         (n << qp->sq.wqe_shift);
 215         else
 216                 return qp->queue.page_list[(qp->send_wqe_offset +
 217                                             (n << qp->sq.wqe_shift)) >>
 218                                            PAGE_SHIFT].buf +
 219                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 220                          (PAGE_SIZE - 1));
 221 }
 222
 223 static void mthca_wq_init(struct mthca_wq *wq)
 224 {
 225         spin_lock_init(&wq->lock);
 226         wq->next_ind  = 0;
 227         wq->last_comp = wq->max - 1;
 228         wq->head      = 0;
 229         wq->tail      = 0;
 230 }
 231
 232 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 233                     enum ib_event_type event_type)
 234 {
 235         struct mthca_qp *qp;
 236         struct ib_event event;
 237
 238         spin_lock(&dev->qp_table.lock);
 239         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 240         if (qp)
 241                 atomic_inc(&qp->refcount);
 242         spin_unlock(&dev->qp_table.lock);
 243
 244         if (!qp) {
 245                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 246                 return;
 247         }
 248
 249         event.device      = &dev->ib_dev;
 250         event.event       = event_type;
 251         event.element.qp  = &qp->ibqp;
 252         if (qp->ibqp.event_handler)
 253                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 254
 255         if (atomic_dec_and_test(&qp->refcount))
 256                 wake_up(&qp->wait);
 257 }
 258
 259 static int to_mthca_state(enum ib_qp_state ib_state)
 260 {
 261         switch (ib_state) {
 262         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 263         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 264         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 265         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 266         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 267         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 268         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 269         default:                return -1;
 270         }
 271 }
 272
 273 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 274
 275 static int to_mthca_st(int transport)
 276 {
 277         switch (transport) {
 278         case RC:  return MTHCA_QP_ST_RC;
 279         case UC:  return MTHCA_QP_ST_UC;
 280         case UD:  return MTHCA_QP_ST_UD;
 281         case RD:  return MTHCA_QP_ST_RD;
 282         case MLX: return MTHCA_QP_ST_MLX;
 283         default:  return -1;
 284         }
 285 }
 286
 287 static const struct {
 288         int trans;
 289         u32 req_param[NUM_TRANS];
 290         u32 opt_param[NUM_TRANS];
 291 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 292         [IB_QPS_RESET] = {
 293                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 294                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 295                 [IB_QPS_INIT]  = {
 296                         .trans = MTHCA_TRANS_RST2INIT,
 297                         .req_param = {
 298                                 [UD]  = (IB_QP_PKEY_INDEX |
 299                                          IB_QP_PORT       |
 300                                          IB_QP_QKEY),
 301                                 [UC]  = (IB_QP_PKEY_INDEX |
 302                                          IB_QP_PORT       |
 303                                          IB_QP_ACCESS_FLAGS),
 304                                 [RC]  = (IB_QP_PKEY_INDEX |
 305                                          IB_QP_PORT       |
 306                                          IB_QP_ACCESS_FLAGS),
 307                                 [MLX] = (IB_QP_PKEY_INDEX |
 308                                          IB_QP_QKEY),
 309                         },
 310                         /* bug-for-bug compatibility with VAPI: */
 311                         .opt_param = {
 312                                 [MLX] = IB_QP_PORT
 313                         }
 314                 },
 315         },
 316         [IB_QPS_INIT]  = {
 317                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 318                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 319                 [IB_QPS_INIT]  = {
 320                         .trans = MTHCA_TRANS_INIT2INIT,
 321                         .opt_param = {
 322                                 [UD]  = (IB_QP_PKEY_INDEX |
 323                                          IB_QP_PORT       |
 324                                          IB_QP_QKEY),
 325                                 [UC]  = (IB_QP_PKEY_INDEX |
 326                                          IB_QP_PORT       |
 327                                          IB_QP_ACCESS_FLAGS),
 328                                 [RC]  = (IB_QP_PKEY_INDEX |
 329                                          IB_QP_PORT       |
 330                                          IB_QP_ACCESS_FLAGS),
 331                                 [MLX] = (IB_QP_PKEY_INDEX |
 332                                          IB_QP_QKEY),
 333                         }
 334                 },
 335                 [IB_QPS_RTR]   = {
 336                         .trans = MTHCA_TRANS_INIT2RTR,
 337                         .req_param = {
 338                                 [UC]  = (IB_QP_AV                  |
 339                                          IB_QP_PATH_MTU            |
 340                                          IB_QP_DEST_QPN            |
 341                                          IB_QP_RQ_PSN),
 342                                 [RC]  = (IB_QP_AV                  |
 343                                          IB_QP_PATH_MTU            |
 344                                          IB_QP_DEST_QPN            |
 345                                          IB_QP_RQ_PSN              |
 346                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 347                                          IB_QP_MIN_RNR_TIMER),
 348                         },
 349                         .opt_param = {
 350                                 [UD]  = (IB_QP_PKEY_INDEX |
 351                                          IB_QP_QKEY),
 352                                 [UC]  = (IB_QP_ALT_PATH     |
 353                                          IB_QP_ACCESS_FLAGS |
 354                                          IB_QP_PKEY_INDEX),
 355                                 [RC]  = (IB_QP_ALT_PATH     |
 356                                          IB_QP_ACCESS_FLAGS |
 357                                          IB_QP_PKEY_INDEX),
 358                                 [MLX] = (IB_QP_PKEY_INDEX |
 359                                          IB_QP_QKEY),
 360                         }
 361                 }
 362         },
 363         [IB_QPS_RTR]   = {
 364                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 365                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 366                 [IB_QPS_RTS]   = {
 367                         .trans = MTHCA_TRANS_RTR2RTS,
 368                         .req_param = {
 369                                 [UD]  = IB_QP_SQ_PSN,
 370                                 [UC]  = IB_QP_SQ_PSN,
 371                                 [RC]  = (IB_QP_TIMEOUT           |
 372                                          IB_QP_RETRY_CNT         |
 373                                          IB_QP_RNR_RETRY         |
 374                                          IB_QP_SQ_PSN            |
 375                                          IB_QP_MAX_QP_RD_ATOMIC),
 376                                 [MLX] = IB_QP_SQ_PSN,
 377                         },
 378                         .opt_param = {
 379                                 [UD]  = (IB_QP_CUR_STATE             |
 380                                          IB_QP_QKEY),
 381                                 [UC]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_ALT_PATH              |
 383                                          IB_QP_ACCESS_FLAGS          |
 384                                          IB_QP_PKEY_INDEX            |
 385                                          IB_QP_PATH_MIG_STATE),
 386                                 [RC]  = (IB_QP_CUR_STATE             |
 387                                          IB_QP_ALT_PATH              |
 388                                          IB_QP_ACCESS_FLAGS          |
 389                                          IB_QP_PKEY_INDEX            |
 390                                          IB_QP_MIN_RNR_TIMER         |
 391                                          IB_QP_PATH_MIG_STATE),
 392                                 [MLX] = (IB_QP_CUR_STATE             |
 393                                          IB_QP_QKEY),
 394                         }
 395                 }
 396         },
 397         [IB_QPS_RTS]   = {
 398                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 399                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 400                 [IB_QPS_RTS]   = {
 401                         .trans = MTHCA_TRANS_RTS2RTS,
 402                         .opt_param = {
 403                                 [UD]  = (IB_QP_CUR_STATE             |
 404                                          IB_QP_QKEY),
 405                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 406                                          IB_QP_ALT_PATH              |
 407                                          IB_QP_PATH_MIG_STATE),
 408                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 409                                          IB_QP_ALT_PATH              |
 410                                          IB_QP_PATH_MIG_STATE        |
 411                                          IB_QP_MIN_RNR_TIMER),
 412                                 [MLX] = (IB_QP_CUR_STATE             |
 413                                          IB_QP_QKEY),
 414                         }
 415                 },
 416                 [IB_QPS_SQD]   = {
 417                         .trans = MTHCA_TRANS_RTS2SQD,
 418                 },
 419         },
 420         [IB_QPS_SQD]   = {
 421                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 422                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 423                 [IB_QPS_RTS]   = {
 424                         .trans = MTHCA_TRANS_SQD2RTS,
 425                         .opt_param = {
 426                                 [UD]  = (IB_QP_CUR_STATE             |
 427                                          IB_QP_QKEY),
 428                                 [UC]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_ALT_PATH              |
 430                                          IB_QP_ACCESS_FLAGS          |
 431                                          IB_QP_PATH_MIG_STATE),
 432                                 [RC]  = (IB_QP_CUR_STATE             |
 433                                          IB_QP_ALT_PATH              |
 434                                          IB_QP_ACCESS_FLAGS          |
 435                                          IB_QP_MIN_RNR_TIMER         |
 436                                          IB_QP_PATH_MIG_STATE),
 437                                 [MLX] = (IB_QP_CUR_STATE             |
 438                                          IB_QP_QKEY),
 439                         }
 440                 },
 441                 [IB_QPS_SQD]   = {
 442                         .trans = MTHCA_TRANS_SQD2SQD,
 443                         .opt_param = {
 444                                 [UD]  = (IB_QP_PKEY_INDEX            |
 445                                          IB_QP_QKEY),
 446                                 [UC]  = (IB_QP_AV                    |
 447                                          IB_QP_CUR_STATE             |
 448                                          IB_QP_ALT_PATH              |
 449                                          IB_QP_ACCESS_FLAGS          |
 450                                          IB_QP_PKEY_INDEX            |
 451                                          IB_QP_PATH_MIG_STATE),
 452                                 [RC]  = (IB_QP_AV                    |
 453                                          IB_QP_TIMEOUT               |
 454                                          IB_QP_RETRY_CNT             |
 455                                          IB_QP_RNR_RETRY             |
 456                                          IB_QP_MAX_QP_RD_ATOMIC      |
 457                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 458                                          IB_QP_CUR_STATE             |
 459                                          IB_QP_ALT_PATH              |
 460                                          IB_QP_ACCESS_FLAGS          |
 461                                          IB_QP_PKEY_INDEX            |
 462                                          IB_QP_MIN_RNR_TIMER         |
 463                                          IB_QP_PATH_MIG_STATE),
 464                                 [MLX] = (IB_QP_PKEY_INDEX            |
 465                                          IB_QP_QKEY),
 466                         }
 467                 }
 468         },
 469         [IB_QPS_SQE]   = {
 470                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 471                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 472                 [IB_QPS_RTS]   = {
 473                         .trans = MTHCA_TRANS_SQERR2RTS,
 474                         .opt_param = {
 475                                 [UD]  = (IB_QP_CUR_STATE             |
 476                                          IB_QP_QKEY),
 477                                 [UC]  = IB_QP_CUR_STATE,
 478                                 [RC]  = (IB_QP_CUR_STATE             |
 479                                          IB_QP_MIN_RNR_TIMER),
 480                                 [MLX] = (IB_QP_CUR_STATE             |
 481                                          IB_QP_QKEY),
 482                         }
 483                 }
 484         },
 485         [IB_QPS_ERR] = {
 486                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 487                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 488         }
 489 };
 490
 491 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 492                         int attr_mask)
 493 {
 494         if (attr_mask & IB_QP_PKEY_INDEX)
 495                 sqp->pkey_index = attr->pkey_index;
 496         if (attr_mask & IB_QP_QKEY)
 497                 sqp->qkey = attr->qkey;
 498         if (attr_mask & IB_QP_SQ_PSN)
 499                 sqp->send_psn = attr->sq_psn;
 500 }
 501
 502 static void init_port(struct mthca_dev *dev, int port)
 503 {
 504         int err;
 505         u8 status;
 506         struct mthca_init_ib_param param;
 507
 508         memset(&param, 0, sizeof param);
 509
 510         param.port_width = dev->limits.port_width_cap;
 511         param.vl_cap     = dev->limits.vl_cap;
 512         param.mtu_cap    = dev->limits.mtu_cap;
 513         param.gid_cap    = dev->limits.gid_table_len;
 514         param.pkey_cap   = dev->limits.pkey_table_len;
 515
 516         err = mthca_INIT_IB(dev, &param, port, &status);
 517         if (err)
 518                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 519         if (status)
 520                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 521 }
 522
 523 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 524 {
 525         struct mthca_dev *dev = to_mdev(ibqp->device);
 526         struct mthca_qp *qp = to_mqp(ibqp);
 527         enum ib_qp_state cur_state, new_state;
 528         struct mthca_mailbox *mailbox;
 529         struct mthca_qp_param *qp_param;
 530         struct mthca_qp_context *qp_context;
 531         u32 req_param, opt_param;
 532         u8 status;
 533         int err;
 534
 535         if (attr_mask & IB_QP_CUR_STATE) {
 536                 if (attr->cur_qp_state != IB_QPS_RTR &&
 537                     attr->cur_qp_state != IB_QPS_RTS &&
 538                     attr->cur_qp_state != IB_QPS_SQD &&
 539                     attr->cur_qp_state != IB_QPS_SQE)
 540                         return -EINVAL;
 541                 else
 542                         cur_state = attr->cur_qp_state;
 543         } else {
 544                 spin_lock_irq(&qp->sq.lock);
 545                 spin_lock(&qp->rq.lock);
 546                 cur_state = qp->state;
 547                 spin_unlock(&qp->rq.lock);
 548                 spin_unlock_irq(&qp->sq.lock);
 549         }
 550
 551         if (attr_mask & IB_QP_STATE) {
 552                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 553                         return -EINVAL;
 554                 new_state = attr->qp_state;
 555         } else
 556                 new_state = cur_state;
 557
 558         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 559                 mthca_dbg(dev, "Illegal QP transition "
 560                           "%d->%d\n", cur_state, new_state);
 561                 return -EINVAL;
 562         }
 563
 564         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 565         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 566
 567         if ((req_param & attr_mask) != req_param) {
 568                 mthca_dbg(dev, "QP transition "
 569                           "%d->%d missing req attr 0x%08x\n",
 570                           cur_state, new_state,
 571                           req_param & ~attr_mask);
 572                 return -EINVAL;
 573         }
 574
 575         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 576                 mthca_dbg(dev, "QP transition (transport %d) "
 577                           "%d->%d has extra attr 0x%08x\n",
 578                           qp->transport,
 579                           cur_state, new_state,
 580                           attr_mask & ~(req_param | opt_param |
 581                                                  IB_QP_STATE));
 582                 return -EINVAL;
 583         }
 584
 585         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 586         if (IS_ERR(mailbox))
 587                 return PTR_ERR(mailbox);
 588         qp_param = mailbox->buf;
 589         qp_context = &qp_param->context;
 590         memset(qp_param, 0, sizeof *qp_param);
 591
 592         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 593                                              (to_mthca_st(qp->transport) << 16));
 594         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 595         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 596                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 597         else {
 598                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 599                 switch (attr->path_mig_state) {
 600                 case IB_MIG_MIGRATED:
 601                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 602                         break;
 603                 case IB_MIG_REARM:
 604                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 605                         break;
 606                 case IB_MIG_ARMED:
 607                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 608                         break;
 609                 }
 610         }
 611
 612         /* leave tavor_sched_queue as 0 */
 613
 614         if (qp->transport == MLX || qp->transport == UD)
 615                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 616         else if (attr_mask & IB_QP_PATH_MTU)
 617                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 618
 619         if (mthca_is_memfree(dev)) {
 620                 if (qp->rq.max)
 621                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 622                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 623
 624                 if (qp->sq.max)
 625                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 626                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 627         }
 628
 629         /* leave arbel_sched_queue as 0 */
 630
 631         if (qp->ibqp.uobject)
 632                 qp_context->usr_page =
 633                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 634         else
 635                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 636         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 637         if (attr_mask & IB_QP_DEST_QPN) {
 638                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 639         }
 640
 641         if (qp->transport == MLX)
 642                 qp_context->pri_path.port_pkey |=
 643                         cpu_to_be32(to_msqp(qp)->port << 24);
 644         else {
 645                 if (attr_mask & IB_QP_PORT) {
 646                         qp_context->pri_path.port_pkey |=
 647                                 cpu_to_be32(attr->port_num << 24);
 648                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 649                 }
 650         }
 651
 652         if (attr_mask & IB_QP_PKEY_INDEX) {
 653                 qp_context->pri_path.port_pkey |=
 654                         cpu_to_be32(attr->pkey_index);
 655                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 656         }
 657
 658         if (attr_mask & IB_QP_RNR_RETRY) {
 659                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 660                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 661         }
 662
 663         if (attr_mask & IB_QP_AV) {
 664                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 665                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 666                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 667                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 668                         qp_context->pri_path.g_mylmc |= 1 << 7;
 669                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 670                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 671                         qp_context->pri_path.sl_tclass_flowlabel =
 672                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 673                                             (attr->ah_attr.grh.traffic_class << 20) |
 674                                             (attr->ah_attr.grh.flow_label));
 675                         memcpy(qp_context->pri_path.rgid,
 676                                attr->ah_attr.grh.dgid.raw, 16);
 677                 } else {
 678                         qp_context->pri_path.sl_tclass_flowlabel =
 679                                 cpu_to_be32(attr->ah_attr.sl << 28);
 680                 }
 681                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 682         }
 683
 684         if (attr_mask & IB_QP_TIMEOUT) {
 685                 qp_context->pri_path.ackto = attr->timeout << 3;
 686                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 687         }
 688
 689         /* XXX alt_path */
 690
 691         /* leave rdd as 0 */
 692         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 693         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 694         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 695         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 696                                              (MTHCA_FLIGHT_LIMIT << 24) |
 697                                              MTHCA_QP_BIT_SRE           |
 698                                              MTHCA_QP_BIT_SWE           |
 699                                              MTHCA_QP_BIT_SAE);
 700         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 701                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 702         if (attr_mask & IB_QP_RETRY_CNT) {
 703                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 704                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 705         }
 706
 707         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 708                 qp_context->params1 |= cpu_to_be32(min(attr->max_rd_atomic ?
 709                                                        ffs(attr->max_rd_atomic) - 1 : 0,
 710                                                        7) << 21);
 711                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 712         }
 713
 714         if (attr_mask & IB_QP_SQ_PSN)
 715                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 716         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 717
 718         if (mthca_is_memfree(dev)) {
 719                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 720                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 721         }
 722
 723         if (attr_mask & IB_QP_ACCESS_FLAGS) {
 724                 /*
 725                  * Only enable RDMA/atomics if we have responder
 726                  * resources set to a non-zero value.
 727                  */
 728                 if (qp->resp_depth) {
 729                         qp_context->params2 |=
 730                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE ?
 731                                             MTHCA_QP_BIT_RWE : 0);
 732                         qp_context->params2 |=
 733                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_READ ?
 734                                             MTHCA_QP_BIT_RRE : 0);
 735                         qp_context->params2 |=
 736                                 cpu_to_be32(attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC ?
 737                                             MTHCA_QP_BIT_RAE : 0);
 738                 }
 739
 740                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 741                                                         MTHCA_QP_OPTPAR_RRE |
 742                                                         MTHCA_QP_OPTPAR_RAE);
 743
 744                 qp->atomic_rd_en = attr->qp_access_flags;
 745         }
 746
 747         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 748                 u8 rra_max;
 749
 750                 if (qp->resp_depth && !attr->max_dest_rd_atomic) {
 751                         /*
 752                          * Lowering our responder resources to zero.
 753                          * Turn off RDMA/atomics as responder.
 754                          * (RWE/RRE/RAE in params2 already zero)
 755                          */
 756                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 757                                                                 MTHCA_QP_OPTPAR_RRE |
 758                                                                 MTHCA_QP_OPTPAR_RAE);
 759                 }
 760
 761                 if (!qp->resp_depth && attr->max_dest_rd_atomic) {
 762                         /*
 763                          * Increasing our responder resources from
 764                          * zero.  Turn on RDMA/atomics as appropriate.
 765                          */
 766                         qp_context->params2 |=
 767                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_WRITE ?
 768                                             MTHCA_QP_BIT_RWE : 0);
 769                         qp_context->params2 |=
 770                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_READ ?
 771                                             MTHCA_QP_BIT_RRE : 0);
 772                         qp_context->params2 |=
 773                                 cpu_to_be32(qp->atomic_rd_en & IB_ACCESS_REMOTE_ATOMIC ?
 774                                             MTHCA_QP_BIT_RAE : 0);
 775
 776                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 777                                                                 MTHCA_QP_OPTPAR_RRE |
 778                                                                 MTHCA_QP_OPTPAR_RAE);
 779                 }
 780
 781                 for (rra_max = 0;
 782                      1 << rra_max < attr->max_dest_rd_atomic &&
 783                              rra_max < dev->qp_table.rdb_shift;
 784                      ++rra_max)
 785                         ; /* nothing */
 786
 787                 qp_context->params2      |= cpu_to_be32(rra_max << 21);
 788                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 789
 790                 qp->resp_depth = attr->max_dest_rd_atomic;
 791         }
 792
 793         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 794
 795         if (ibqp->srq)
 796                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 797
 798         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 799                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 800                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 801         }
 802         if (attr_mask & IB_QP_RQ_PSN)
 803                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 804
 805         qp_context->ra_buff_indx =
 806                 cpu_to_be32(dev->qp_table.rdb_base +
 807                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 808                              dev->qp_table.rdb_shift));
 809
 810         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 811
 812         if (mthca_is_memfree(dev))
 813                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 814
 815         if (attr_mask & IB_QP_QKEY) {
 816                 qp_context->qkey = cpu_to_be32(attr->qkey);
 817                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 818         }
 819
 820         if (ibqp->srq)
 821                 qp_context->srqn = cpu_to_be32(1 << 24 |
 822                                                to_msrq(ibqp->srq)->srqn);
 823
 824         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 825                               qp->qpn, 0, mailbox, 0, &status);
 826         if (status) {
 827                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 828                            state_table[cur_state][new_state].trans, status);
 829                 err = -EINVAL;
 830         }
 831
 832         if (!err)
 833                 qp->state = new_state;
 834
 835         mthca_free_mailbox(dev, mailbox);
 836
 837         if (is_sqp(dev, qp))
 838                 store_attrs(to_msqp(qp), attr, attr_mask);
 839
 840         /*
 841          * If we moved QP0 to RTR, bring the IB link up; if we moved
 842          * QP0 to RESET or ERROR, bring the link back down.
 843          */
 844         if (is_qp0(dev, qp)) {
 845                 if (cur_state != IB_QPS_RTR &&
 846                     new_state == IB_QPS_RTR)
 847                         init_port(dev, to_msqp(qp)->port);
 848
 849                 if (cur_state != IB_QPS_RESET &&
 850                     cur_state != IB_QPS_ERR &&
 851                     (new_state == IB_QPS_RESET ||
 852                      new_state == IB_QPS_ERR))
 853                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 854         }
 855
 856         /*
 857          * If we moved a kernel QP to RESET, clean up all old CQ
 858          * entries and reinitialize the QP.
 859          */
 860         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 861                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 862                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 863                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 864                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 865                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 866
 867                 mthca_wq_init(&qp->sq);
 868                 mthca_wq_init(&qp->rq);
 869
 870                 if (mthca_is_memfree(dev)) {
 871                         *qp->sq.db = 0;
 872                         *qp->rq.db = 0;
 873                 }
 874         }
 875
 876         return err;
 877 }
 878
 879 /*
 880  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 881  * rq.max_gs and sq.max_gs must all be assigned.
 882  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 883  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 884  * queue)
 885  */
 886 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 887                                struct mthca_pd *pd,
 888                                struct mthca_qp *qp)
 889 {
 890         int size;
 891         int err = -ENOMEM;
 892
 893         size = sizeof (struct mthca_next_seg) +
 894                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 895
 896         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 897              qp->rq.wqe_shift++)
 898                 ; /* nothing */
 899
 900         size = sizeof (struct mthca_next_seg) +
 901                 qp->sq.max_gs * sizeof (struct mthca_data_seg);
 902         switch (qp->transport) {
 903         case MLX:
 904                 size += 2 * sizeof (struct mthca_data_seg);
 905                 break;
 906         case UD:
 907                 if (mthca_is_memfree(dev))
 908                         size += sizeof (struct mthca_arbel_ud_seg);
 909                 else
 910                         size += sizeof (struct mthca_tavor_ud_seg);
 911                 break;
 912         default:
 913                 /* bind seg is as big as atomic + raddr segs */
 914                 size += sizeof (struct mthca_bind_seg);
 915         }
 916
 917         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
 918              qp->sq.wqe_shift++)
 919                 ; /* nothing */
 920
 921         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
 922                                     1 << qp->sq.wqe_shift);
 923
 924         /*
 925          * If this is a userspace QP, we don't actually have to
 926          * allocate anything.  All we need is to calculate the WQE
 927          * sizes and the send_wqe_offset, so we're done now.
 928          */
 929         if (pd->ibpd.uobject)
 930                 return 0;
 931
 932         size = PAGE_ALIGN(qp->send_wqe_offset +
 933                           (qp->sq.max << qp->sq.wqe_shift));
 934
 935         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
 936                            GFP_KERNEL);
 937         if (!qp->wrid)
 938                 goto err_out;
 939
 940         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
 941                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
 942         if (err)
 943                 goto err_out;
 944
 945         return 0;
 946
 947 err_out:
 948         kfree(qp->wrid);
 949         return err;
 950 }
 951
 952 static void mthca_free_wqe_buf(struct mthca_dev *dev,
 953                                struct mthca_qp *qp)
 954 {
 955         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
 956                                        (qp->sq.max << qp->sq.wqe_shift)),
 957                        &qp->queue, qp->is_direct, &qp->mr);
 958         kfree(qp->wrid);
 959 }
 960
 961 static int mthca_map_memfree(struct mthca_dev *dev,
 962                              struct mthca_qp *qp)
 963 {
 964         int ret;
 965
 966         if (mthca_is_memfree(dev)) {
 967                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
 968                 if (ret)
 969                         return ret;
 970
 971                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
 972                 if (ret)
 973                         goto err_qpc;
 974
 975                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
 976                                       qp->qpn << dev->qp_table.rdb_shift);
 977                 if (ret)
 978                         goto err_eqpc;
 979
 980         }
 981
 982         return 0;
 983
 984 err_eqpc:
 985         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
 986
 987 err_qpc:
 988         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
 989
 990         return ret;
 991 }
 992
 993 static void mthca_unmap_memfree(struct mthca_dev *dev,
 994                                 struct mthca_qp *qp)
 995 {
 996         mthca_table_put(dev, dev->qp_table.rdb_table,
 997                         qp->qpn << dev->qp_table.rdb_shift);
 998         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
 999         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1000 }
1001
1002 static int mthca_alloc_memfree(struct mthca_dev *dev,
1003                                struct mthca_qp *qp)
1004 {
1005         int ret = 0;
1006
1007         if (mthca_is_memfree(dev)) {
1008                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1009                                                  qp->qpn, &qp->rq.db);
1010                 if (qp->rq.db_index < 0)
1011                         return ret;
1012
1013                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1014                                                  qp->qpn, &qp->sq.db);
1015                 if (qp->sq.db_index < 0)
1016                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1017         }
1018
1019         return ret;
1020 }
1021
1022 static void mthca_free_memfree(struct mthca_dev *dev,
1023                                struct mthca_qp *qp)
1024 {
1025         if (mthca_is_memfree(dev)) {
1026                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1027                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1028         }
1029 }
1030
1031 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1032                                  struct mthca_pd *pd,
1033                                  struct mthca_cq *send_cq,
1034                                  struct mthca_cq *recv_cq,
1035                                  enum ib_sig_type send_policy,
1036                                  struct mthca_qp *qp)
1037 {
1038         int ret;
1039         int i;
1040
1041         atomic_set(&qp->refcount, 1);
1042         init_waitqueue_head(&qp->wait);
1043         qp->state        = IB_QPS_RESET;
1044         qp->atomic_rd_en = 0;
1045         qp->resp_depth   = 0;
1046         qp->sq_policy    = send_policy;
1047         mthca_wq_init(&qp->sq);
1048         mthca_wq_init(&qp->rq);
1049
1050         ret = mthca_map_memfree(dev, qp);
1051         if (ret)
1052                 return ret;
1053
1054         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1055         if (ret) {
1056                 mthca_unmap_memfree(dev, qp);
1057                 return ret;
1058         }
1059
1060         /*
1061          * If this is a userspace QP, we're done now.  The doorbells
1062          * will be allocated and buffers will be initialized in
1063          * userspace.
1064          */
1065         if (pd->ibpd.uobject)
1066                 return 0;
1067
1068         ret = mthca_alloc_memfree(dev, qp);
1069         if (ret) {
1070                 mthca_free_wqe_buf(dev, qp);
1071                 mthca_unmap_memfree(dev, qp);
1072                 return ret;
1073         }
1074
1075         if (mthca_is_memfree(dev)) {
1076                 struct mthca_next_seg *next;
1077                 struct mthca_data_seg *scatter;
1078                 int size = (sizeof (struct mthca_next_seg) +
1079                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1080
1081                 for (i = 0; i < qp->rq.max; ++i) {
1082                         next = get_recv_wqe(qp, i);
1083                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1084                                                    qp->rq.wqe_shift);
1085                         next->ee_nds = cpu_to_be32(size);
1086
1087                         for (scatter = (void *) (next + 1);
1088                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1089                              ++scatter)
1090                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1091                 }
1092
1093                 for (i = 0; i < qp->sq.max; ++i) {
1094                         next = get_send_wqe(qp, i);
1095                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1096                                                     qp->sq.wqe_shift) +
1097                                                    qp->send_wqe_offset);
1098                 }
1099         }
1100
1101         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1102         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1103
1104         return 0;
1105 }
1106
1107 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1108                              struct mthca_qp *qp)
1109 {
1110         /* Sanity check QP size before proceeding */
1111         if (cap->max_send_wr  > dev->limits.max_wqes ||
1112             cap->max_recv_wr  > dev->limits.max_wqes ||
1113             cap->max_send_sge > dev->limits.max_sg   ||
1114             cap->max_recv_sge > dev->limits.max_sg)
1115                 return -EINVAL;
1116
1117         if (mthca_is_memfree(dev)) {
1118                 qp->rq.max = cap->max_recv_wr ?
1119                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1120                 qp->sq.max = cap->max_send_wr ?
1121                         roundup_pow_of_two(cap->max_send_wr) : 0;
1122         } else {
1123                 qp->rq.max = cap->max_recv_wr;
1124                 qp->sq.max = cap->max_send_wr;
1125         }
1126
1127         qp->rq.max_gs = cap->max_recv_sge;
1128         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1129                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1130                                     MTHCA_INLINE_CHUNK_SIZE) /
1131                               sizeof (struct mthca_data_seg));
1132
1133         /*
1134          * For MLX transport we need 2 extra S/G entries:
1135          * one for the header and one for the checksum at the end
1136          */
1137         if ((qp->transport == MLX && qp->sq.max_gs + 2 > dev->limits.max_sg) ||
1138             qp->sq.max_gs > dev->limits.max_sg || qp->rq.max_gs > dev->limits.max_sg)
1139                 return -EINVAL;
1140
1141         return 0;
1142 }
1143
1144 int mthca_alloc_qp(struct mthca_dev *dev,
1145                    struct mthca_pd *pd,
1146                    struct mthca_cq *send_cq,
1147                    struct mthca_cq *recv_cq,
1148                    enum ib_qp_type type,
1149                    enum ib_sig_type send_policy,
1150                    struct ib_qp_cap *cap,
1151                    struct mthca_qp *qp)
1152 {
1153         int err;
1154
1155         err = mthca_set_qp_size(dev, cap, qp);
1156         if (err)
1157                 return err;
1158
1159         switch (type) {
1160         case IB_QPT_RC: qp->transport = RC; break;
1161         case IB_QPT_UC: qp->transport = UC; break;
1162         case IB_QPT_UD: qp->transport = UD; break;
1163         default: return -EINVAL;
1164         }
1165
1166         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1167         if (qp->qpn == -1)
1168                 return -ENOMEM;
1169
1170         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1171                                     send_policy, qp);
1172         if (err) {
1173                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1174                 return err;
1175         }
1176
1177         spin_lock_irq(&dev->qp_table.lock);
1178         mthca_array_set(&dev->qp_table.qp,
1179                         qp->qpn & (dev->limits.num_qps - 1), qp);
1180         spin_unlock_irq(&dev->qp_table.lock);
1181
1182         return 0;
1183 }
1184
1185 int mthca_alloc_sqp(struct mthca_dev *dev,
1186                     struct mthca_pd *pd,
1187                     struct mthca_cq *send_cq,
1188                     struct mthca_cq *recv_cq,
1189                     enum ib_sig_type send_policy,
1190                     struct ib_qp_cap *cap,
1191                     int qpn,
1192                     int port,
1193                     struct mthca_sqp *sqp)
1194 {
1195         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1196         int err;
1197
1198         err = mthca_set_qp_size(dev, cap, &sqp->qp);
1199         if (err)
1200                 return err;
1201
1202         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1203         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1204                                              &sqp->header_dma, GFP_KERNEL);
1205         if (!sqp->header_buf)
1206                 return -ENOMEM;
1207
1208         spin_lock_irq(&dev->qp_table.lock);
1209         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1210                 err = -EBUSY;
1211         else
1212                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1213         spin_unlock_irq(&dev->qp_table.lock);
1214
1215         if (err)
1216                 goto err_out;
1217
1218         sqp->port = port;
1219         sqp->qp.qpn       = mqpn;
1220         sqp->qp.transport = MLX;
1221
1222         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1223                                     send_policy, &sqp->qp);
1224         if (err)
1225                 goto err_out_free;
1226
1227         atomic_inc(&pd->sqp_count);
1228
1229         return 0;
1230
1231  err_out_free:
1232         /*
1233          * Lock CQs here, so that CQ polling code can do QP lookup
1234          * without taking a lock.
1235          */
1236         spin_lock_irq(&send_cq->lock);
1237         if (send_cq != recv_cq)
1238                 spin_lock(&recv_cq->lock);
1239
1240         spin_lock(&dev->qp_table.lock);
1241         mthca_array_clear(&dev->qp_table.qp, mqpn);
1242         spin_unlock(&dev->qp_table.lock);
1243
1244         if (send_cq != recv_cq)
1245                 spin_unlock(&recv_cq->lock);
1246         spin_unlock_irq(&send_cq->lock);
1247
1248  err_out:
1249         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1250                           sqp->header_buf, sqp->header_dma);
1251
1252         return err;
1253 }
1254
1255 void mthca_free_qp(struct mthca_dev *dev,
1256                    struct mthca_qp *qp)
1257 {
1258         u8 status;
1259         struct mthca_cq *send_cq;
1260         struct mthca_cq *recv_cq;
1261
1262         send_cq = to_mcq(qp->ibqp.send_cq);
1263         recv_cq = to_mcq(qp->ibqp.recv_cq);
1264
1265         /*
1266          * Lock CQs here, so that CQ polling code can do QP lookup
1267          * without taking a lock.
1268          */
1269         spin_lock_irq(&send_cq->lock);
1270         if (send_cq != recv_cq)
1271                 spin_lock(&recv_cq->lock);
1272
1273         spin_lock(&dev->qp_table.lock);
1274         mthca_array_clear(&dev->qp_table.qp,
1275                           qp->qpn & (dev->limits.num_qps - 1));
1276         spin_unlock(&dev->qp_table.lock);
1277
1278         if (send_cq != recv_cq)
1279                 spin_unlock(&recv_cq->lock);
1280         spin_unlock_irq(&send_cq->lock);
1281
1282         atomic_dec(&qp->refcount);
1283         wait_event(qp->wait, !atomic_read(&qp->refcount));
1284
1285         if (qp->state != IB_QPS_RESET)
1286                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1287
1288         /*
1289          * If this is a userspace QP, the buffers, MR, CQs and so on
1290          * will be cleaned up in userspace, so all we have to do is
1291          * unref the mem-free tables and free the QPN in our table.
1292          */
1293         if (!qp->ibqp.uobject) {
1294                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1295                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1296                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1297                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1298                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1299
1300                 mthca_free_memfree(dev, qp);
1301                 mthca_free_wqe_buf(dev, qp);
1302         }
1303
1304         mthca_unmap_memfree(dev, qp);
1305
1306         if (is_sqp(dev, qp)) {
1307                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1308                 dma_free_coherent(&dev->pdev->dev,
1309                                   to_msqp(qp)->header_buf_size,
1310                                   to_msqp(qp)->header_buf,
1311                                   to_msqp(qp)->header_dma);
1312         } else
1313                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1314 }
1315
1316 /* Create UD header for an MLX send and build a data segment for it */
1317 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1318                             int ind, struct ib_send_wr *wr,
1319                             struct mthca_mlx_seg *mlx,
1320                             struct mthca_data_seg *data)
1321 {
1322         int header_size;
1323         int err;
1324         u16 pkey;
1325
1326         ib_ud_header_init(256, /* assume a MAD */
1327                           sqp->ud_header.grh_present,
1328                           &sqp->ud_header);
1329
1330         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1331         if (err)
1332                 return err;
1333         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1334         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1335                                   (sqp->ud_header.lrh.destination_lid ==
1336                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1337                                   (sqp->ud_header.lrh.service_level << 8));
1338         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1339         mlx->vcrc = 0;
1340
1341         switch (wr->opcode) {
1342         case IB_WR_SEND:
1343                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1344                 sqp->ud_header.immediate_present = 0;
1345                 break;
1346         case IB_WR_SEND_WITH_IMM:
1347                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1348                 sqp->ud_header.immediate_present = 1;
1349                 sqp->ud_header.immediate_data = wr->imm_data;
1350                 break;
1351         default:
1352                 return -EINVAL;
1353         }
1354
1355         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1356         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1357                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1358         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1359         if (!sqp->qp.ibqp.qp_num)
1360                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1361                                    sqp->pkey_index, &pkey);
1362         else
1363                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1364                                    wr->wr.ud.pkey_index, &pkey);
1365         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1366         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1367         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1368         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1369                                                sqp->qkey : wr->wr.ud.remote_qkey);
1370         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1371
1372         header_size = ib_ud_header_pack(&sqp->ud_header,
1373                                         sqp->header_buf +
1374                                         ind * MTHCA_UD_HEADER_SIZE);
1375
1376         data->byte_count = cpu_to_be32(header_size);
1377         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1378         data->addr       = cpu_to_be64(sqp->header_dma +
1379                                        ind * MTHCA_UD_HEADER_SIZE);
1380
1381         return 0;
1382 }
1383
1384 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1385                                     struct ib_cq *ib_cq)
1386 {
1387         unsigned cur;
1388         struct mthca_cq *cq;
1389
1390         cur = wq->head - wq->tail;
1391         if (likely(cur + nreq < wq->max))
1392                 return 0;
1393
1394         cq = to_mcq(ib_cq);
1395         spin_lock(&cq->lock);
1396         cur = wq->head - wq->tail;
1397         spin_unlock(&cq->lock);
1398
1399         return cur + nreq >= wq->max;
1400 }
1401
1402 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1403                           struct ib_send_wr **bad_wr)
1404 {
1405         struct mthca_dev *dev = to_mdev(ibqp->device);
1406         struct mthca_qp *qp = to_mqp(ibqp);
1407         void *wqe;
1408         void *prev_wqe;
1409         unsigned long flags;
1410         int err = 0;
1411         int nreq;
1412         int i;
1413         int size;
1414         int size0 = 0;
1415         u32 f0 = 0;
1416         int ind;
1417         u8 op0 = 0;
1418
1419         spin_lock_irqsave(&qp->sq.lock, flags);
1420
1421         /* XXX check that state is OK to post send */
1422
1423         ind = qp->sq.next_ind;
1424
1425         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1426                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1427                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1428                                         " %d max, %d nreq)\n", qp->qpn,
1429                                         qp->sq.head, qp->sq.tail,
1430                                         qp->sq.max, nreq);
1431                         err = -ENOMEM;
1432                         *bad_wr = wr;
1433                         goto out;
1434                 }
1435
1436                 wqe = get_send_wqe(qp, ind);
1437                 prev_wqe = qp->sq.last;
1438                 qp->sq.last = wqe;
1439
1440                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1441                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1442                 ((struct mthca_next_seg *) wqe)->flags =
1443                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1444                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1445                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1446                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1447                         cpu_to_be32(1);
1448                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1449                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1450                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1451
1452                 wqe += sizeof (struct mthca_next_seg);
1453                 size = sizeof (struct mthca_next_seg) / 16;
1454
1455                 switch (qp->transport) {
1456                 case RC:
1457                         switch (wr->opcode) {
1458                         case IB_WR_ATOMIC_CMP_AND_SWP:
1459                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1460                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1461                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1462                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1463                                         cpu_to_be32(wr->wr.atomic.rkey);
1464                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1465
1466                                 wqe += sizeof (struct mthca_raddr_seg);
1467
1468                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1469                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1470                                                 cpu_to_be64(wr->wr.atomic.swap);
1471                                         ((struct mthca_atomic_seg *) wqe)->compare =
1472                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1473                                 } else {
1474                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1475                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1476                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1477                                 }
1478
1479                                 wqe += sizeof (struct mthca_atomic_seg);
1480                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1481                                         sizeof (struct mthca_atomic_seg);
1482                                 break;
1483
1484                         case IB_WR_RDMA_WRITE:
1485                         case IB_WR_RDMA_WRITE_WITH_IMM:
1486                         case IB_WR_RDMA_READ:
1487                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1488                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1489                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1490                                         cpu_to_be32(wr->wr.rdma.rkey);
1491                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1492                                 wqe += sizeof (struct mthca_raddr_seg);
1493                                 size += sizeof (struct mthca_raddr_seg) / 16;
1494                                 break;
1495
1496                         default:
1497                                 /* No extra segments required for sends */
1498                                 break;
1499                         }
1500
1501                         break;
1502
1503                 case UC:
1504                         switch (wr->opcode) {
1505                         case IB_WR_RDMA_WRITE:
1506                         case IB_WR_RDMA_WRITE_WITH_IMM:
1507                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1508                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1509                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1510                                         cpu_to_be32(wr->wr.rdma.rkey);
1511                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1512                                 wqe += sizeof (struct mthca_raddr_seg);
1513                                 size += sizeof (struct mthca_raddr_seg) / 16;
1514                                 break;
1515
1516                         default:
1517                                 /* No extra segments required for sends */
1518                                 break;
1519                         }
1520
1521                         break;
1522
1523                 case UD:
1524                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1525                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1526                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1527                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1528                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1529                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1530                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1531                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1532
1533                         wqe += sizeof (struct mthca_tavor_ud_seg);
1534                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1535                         break;
1536
1537                 case MLX:
1538                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1539                                                wqe - sizeof (struct mthca_next_seg),
1540                                                wqe);
1541                         if (err) {
1542                                 *bad_wr = wr;
1543                                 goto out;
1544                         }
1545                         wqe += sizeof (struct mthca_data_seg);
1546                         size += sizeof (struct mthca_data_seg) / 16;
1547                         break;
1548                 }
1549
1550                 if (wr->num_sge > qp->sq.max_gs) {
1551                         mthca_err(dev, "too many gathers\n");
1552                         err = -EINVAL;
1553                         *bad_wr = wr;
1554                         goto out;
1555                 }
1556
1557                 for (i = 0; i < wr->num_sge; ++i) {
1558                         ((struct mthca_data_seg *) wqe)->byte_count =
1559                                 cpu_to_be32(wr->sg_list[i].length);
1560                         ((struct mthca_data_seg *) wqe)->lkey =
1561                                 cpu_to_be32(wr->sg_list[i].lkey);
1562                         ((struct mthca_data_seg *) wqe)->addr =
1563                                 cpu_to_be64(wr->sg_list[i].addr);
1564                         wqe += sizeof (struct mthca_data_seg);
1565                         size += sizeof (struct mthca_data_seg) / 16;
1566                 }
1567
1568                 /* Add one more inline data segment for ICRC */
1569                 if (qp->transport == MLX) {
1570                         ((struct mthca_data_seg *) wqe)->byte_count =
1571                                 cpu_to_be32((1 << 31) | 4);
1572                         ((u32 *) wqe)[1] = 0;
1573                         wqe += sizeof (struct mthca_data_seg);
1574                         size += sizeof (struct mthca_data_seg) / 16;
1575                 }
1576
1577                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1578
1579                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1580                         mthca_err(dev, "opcode invalid\n");
1581                         err = -EINVAL;
1582                         *bad_wr = wr;
1583                         goto out;
1584                 }
1585
1586                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1587                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1588                                      qp->send_wqe_offset) |
1589                                     mthca_opcode[wr->opcode]);
1590                 wmb();
1591                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1592                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1593
1594                 if (!size0) {
1595                         size0 = size;
1596                         op0   = mthca_opcode[wr->opcode];
1597                 }
1598
1599                 ++ind;
1600                 if (unlikely(ind >= qp->sq.max))
1601                         ind -= qp->sq.max;
1602         }
1603
1604 out:
1605         if (likely(nreq)) {
1606                 __be32 doorbell[2];
1607
1608                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1609                                            qp->send_wqe_offset) | f0 | op0);
1610                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1611
1612                 wmb();
1613
1614                 mthca_write64(doorbell,
1615                               dev->kar + MTHCA_SEND_DOORBELL,
1616                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1617         }
1618
1619         qp->sq.next_ind = ind;
1620         qp->sq.head    += nreq;
1621
1622         spin_unlock_irqrestore(&qp->sq.lock, flags);
1623         return err;
1624 }
1625
1626 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1627                              struct ib_recv_wr **bad_wr)
1628 {
1629         struct mthca_dev *dev = to_mdev(ibqp->device);
1630         struct mthca_qp *qp = to_mqp(ibqp);
1631         unsigned long flags;
1632         int err = 0;
1633         int nreq;
1634         int i;
1635         int size;
1636         int size0 = 0;
1637         int ind;
1638         void *wqe;
1639         void *prev_wqe;
1640
1641         spin_lock_irqsave(&qp->rq.lock, flags);
1642
1643         /* XXX check that state is OK to post receive */
1644
1645         ind = qp->rq.next_ind;
1646
1647         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1648                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1649                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1650                                         " %d max, %d nreq)\n", qp->qpn,
1651                                         qp->rq.head, qp->rq.tail,
1652                                         qp->rq.max, nreq);
1653                         err = -ENOMEM;
1654                         *bad_wr = wr;
1655                         goto out;
1656                 }
1657
1658                 wqe = get_recv_wqe(qp, ind);
1659                 prev_wqe = qp->rq.last;
1660                 qp->rq.last = wqe;
1661
1662                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1663                 ((struct mthca_next_seg *) wqe)->ee_nds =
1664                         cpu_to_be32(MTHCA_NEXT_DBD);
1665                 ((struct mthca_next_seg *) wqe)->flags = 0;
1666
1667                 wqe += sizeof (struct mthca_next_seg);
1668                 size = sizeof (struct mthca_next_seg) / 16;
1669
1670                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1671                         err = -EINVAL;
1672                         *bad_wr = wr;
1673                         goto out;
1674                 }
1675
1676                 for (i = 0; i < wr->num_sge; ++i) {
1677                         ((struct mthca_data_seg *) wqe)->byte_count =
1678                                 cpu_to_be32(wr->sg_list[i].length);
1679                         ((struct mthca_data_seg *) wqe)->lkey =
1680                                 cpu_to_be32(wr->sg_list[i].lkey);
1681                         ((struct mthca_data_seg *) wqe)->addr =
1682                                 cpu_to_be64(wr->sg_list[i].addr);
1683                         wqe += sizeof (struct mthca_data_seg);
1684                         size += sizeof (struct mthca_data_seg) / 16;
1685                 }
1686
1687                 qp->wrid[ind] = wr->wr_id;
1688
1689                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1690                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1691                 wmb();
1692                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1693                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1694
1695                 if (!size0)
1696                         size0 = size;
1697
1698                 ++ind;
1699                 if (unlikely(ind >= qp->rq.max))
1700                         ind -= qp->rq.max;
1701         }
1702
1703 out:
1704         if (likely(nreq)) {
1705                 __be32 doorbell[2];
1706
1707                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1708                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1709
1710                 wmb();
1711
1712                 mthca_write64(doorbell,
1713                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1714                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1715         }
1716
1717         qp->rq.next_ind = ind;
1718         qp->rq.head    += nreq;
1719
1720         spin_unlock_irqrestore(&qp->rq.lock, flags);
1721         return err;
1722 }
1723
1724 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1725                           struct ib_send_wr **bad_wr)
1726 {
1727         struct mthca_dev *dev = to_mdev(ibqp->device);
1728         struct mthca_qp *qp = to_mqp(ibqp);
1729         void *wqe;
1730         void *prev_wqe;
1731         unsigned long flags;
1732         int err = 0;
1733         int nreq;
1734         int i;
1735         int size;
1736         int size0 = 0;
1737         u32 f0 = 0;
1738         int ind;
1739         u8 op0 = 0;
1740
1741         spin_lock_irqsave(&qp->sq.lock, flags);
1742
1743         /* XXX check that state is OK to post send */
1744
1745         ind = qp->sq.head & (qp->sq.max - 1);
1746
1747         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1748                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1749                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1750                                         " %d max, %d nreq)\n", qp->qpn,
1751                                         qp->sq.head, qp->sq.tail,
1752                                         qp->sq.max, nreq);
1753                         err = -ENOMEM;
1754                         *bad_wr = wr;
1755                         goto out;
1756                 }
1757
1758                 wqe = get_send_wqe(qp, ind);
1759                 prev_wqe = qp->sq.last;
1760                 qp->sq.last = wqe;
1761
1762                 ((struct mthca_next_seg *) wqe)->flags =
1763                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1764                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1765                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1766                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1767                         cpu_to_be32(1);
1768                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1769                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1770                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1771
1772                 wqe += sizeof (struct mthca_next_seg);
1773                 size = sizeof (struct mthca_next_seg) / 16;
1774
1775                 switch (qp->transport) {
1776                 case RC:
1777                         switch (wr->opcode) {
1778                         case IB_WR_ATOMIC_CMP_AND_SWP:
1779                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1780                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1781                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1782                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1783                                         cpu_to_be32(wr->wr.atomic.rkey);
1784                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1785
1786                                 wqe += sizeof (struct mthca_raddr_seg);
1787
1788                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1789                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1790                                                 cpu_to_be64(wr->wr.atomic.swap);
1791                                         ((struct mthca_atomic_seg *) wqe)->compare =
1792                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1793                                 } else {
1794                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1795                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1796                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1797                                 }
1798
1799                                 wqe += sizeof (struct mthca_atomic_seg);
1800                                 size += sizeof (struct mthca_raddr_seg) / 16 +
1801                                         sizeof (struct mthca_atomic_seg);
1802                                 break;
1803
1804                         case IB_WR_RDMA_READ:
1805                         case IB_WR_RDMA_WRITE:
1806                         case IB_WR_RDMA_WRITE_WITH_IMM:
1807                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1808                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1809                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1810                                         cpu_to_be32(wr->wr.rdma.rkey);
1811                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1812                                 wqe += sizeof (struct mthca_raddr_seg);
1813                                 size += sizeof (struct mthca_raddr_seg) / 16;
1814                                 break;
1815
1816                         default:
1817                                 /* No extra segments required for sends */
1818                                 break;
1819                         }
1820
1821                         break;
1822
1823                 case UC:
1824                         switch (wr->opcode) {
1825                         case IB_WR_RDMA_WRITE:
1826                         case IB_WR_RDMA_WRITE_WITH_IMM:
1827                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1828                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1829                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1830                                         cpu_to_be32(wr->wr.rdma.rkey);
1831                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1832                                 wqe += sizeof (struct mthca_raddr_seg);
1833                                 size += sizeof (struct mthca_raddr_seg) / 16;
1834                                 break;
1835
1836                         default:
1837                                 /* No extra segments required for sends */
1838                                 break;
1839                         }
1840
1841                         break;
1842
1843                 case UD:
1844                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1845                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1846                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1847                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1848                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1849                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1850
1851                         wqe += sizeof (struct mthca_arbel_ud_seg);
1852                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1853                         break;
1854
1855                 case MLX:
1856                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1857                                                wqe - sizeof (struct mthca_next_seg),
1858                                                wqe);
1859                         if (err) {
1860                                 *bad_wr = wr;
1861                                 goto out;
1862                         }
1863                         wqe += sizeof (struct mthca_data_seg);
1864                         size += sizeof (struct mthca_data_seg) / 16;
1865                         break;
1866                 }
1867
1868                 if (wr->num_sge > qp->sq.max_gs) {
1869                         mthca_err(dev, "too many gathers\n");
1870                         err = -EINVAL;
1871                         *bad_wr = wr;
1872                         goto out;
1873                 }
1874
1875                 for (i = 0; i < wr->num_sge; ++i) {
1876                         ((struct mthca_data_seg *) wqe)->byte_count =
1877                                 cpu_to_be32(wr->sg_list[i].length);
1878                         ((struct mthca_data_seg *) wqe)->lkey =
1879                                 cpu_to_be32(wr->sg_list[i].lkey);
1880                         ((struct mthca_data_seg *) wqe)->addr =
1881                                 cpu_to_be64(wr->sg_list[i].addr);
1882                         wqe += sizeof (struct mthca_data_seg);
1883                         size += sizeof (struct mthca_data_seg) / 16;
1884                 }
1885
1886                 /* Add one more inline data segment for ICRC */
1887                 if (qp->transport == MLX) {
1888                         ((struct mthca_data_seg *) wqe)->byte_count =
1889                                 cpu_to_be32((1 << 31) | 4);
1890                         ((u32 *) wqe)[1] = 0;
1891                         wqe += sizeof (struct mthca_data_seg);
1892                         size += sizeof (struct mthca_data_seg) / 16;
1893                 }
1894
1895                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1896
1897                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1898                         mthca_err(dev, "opcode invalid\n");
1899                         err = -EINVAL;
1900                         *bad_wr = wr;
1901                         goto out;
1902                 }
1903
1904                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1905                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1906                                      qp->send_wqe_offset) |
1907                                     mthca_opcode[wr->opcode]);
1908                 wmb();
1909                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1910                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1911
1912                 if (!size0) {
1913                         size0 = size;
1914                         op0   = mthca_opcode[wr->opcode];
1915                 }
1916
1917                 ++ind;
1918                 if (unlikely(ind >= qp->sq.max))
1919                         ind -= qp->sq.max;
1920         }
1921
1922 out:
1923         if (likely(nreq)) {
1924                 __be32 doorbell[2];
1925
1926                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
1927                                           ((qp->sq.head & 0xffff) << 8) |
1928                                           f0 | op0);
1929                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1930
1931                 qp->sq.head += nreq;
1932
1933                 /*
1934                  * Make sure that descriptors are written before
1935                  * doorbell record.
1936                  */
1937                 wmb();
1938                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1939
1940                 /*
1941                  * Make sure doorbell record is written before we
1942                  * write MMIO send doorbell.
1943                  */
1944                 wmb();
1945                 mthca_write64(doorbell,
1946                               dev->kar + MTHCA_SEND_DOORBELL,
1947                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1948         }
1949
1950         spin_unlock_irqrestore(&qp->sq.lock, flags);
1951         return err;
1952 }
1953
1954 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1955                              struct ib_recv_wr **bad_wr)
1956 {
1957         struct mthca_dev *dev = to_mdev(ibqp->device);
1958         struct mthca_qp *qp = to_mqp(ibqp);
1959         unsigned long flags;
1960         int err = 0;
1961         int nreq;
1962         int ind;
1963         int i;
1964         void *wqe;
1965
1966         spin_lock_irqsave(&qp->rq.lock, flags);
1967
1968         /* XXX check that state is OK to post receive */
1969
1970         ind = qp->rq.head & (qp->rq.max - 1);
1971
1972         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1973                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1974                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1975                                         " %d max, %d nreq)\n", qp->qpn,
1976                                         qp->rq.head, qp->rq.tail,
1977                                         qp->rq.max, nreq);
1978                         err = -ENOMEM;
1979                         *bad_wr = wr;
1980                         goto out;
1981                 }
1982
1983                 wqe = get_recv_wqe(qp, ind);
1984
1985                 ((struct mthca_next_seg *) wqe)->flags = 0;
1986
1987                 wqe += sizeof (struct mthca_next_seg);
1988
1989                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1990                         err = -EINVAL;
1991                         *bad_wr = wr;
1992                         goto out;
1993                 }
1994
1995                 for (i = 0; i < wr->num_sge; ++i) {
1996                         ((struct mthca_data_seg *) wqe)->byte_count =
1997                                 cpu_to_be32(wr->sg_list[i].length);
1998                         ((struct mthca_data_seg *) wqe)->lkey =
1999                                 cpu_to_be32(wr->sg_list[i].lkey);
2000                         ((struct mthca_data_seg *) wqe)->addr =
2001                                 cpu_to_be64(wr->sg_list[i].addr);
2002                         wqe += sizeof (struct mthca_data_seg);
2003                 }
2004
2005                 if (i < qp->rq.max_gs) {
2006                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2007                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2008                         ((struct mthca_data_seg *) wqe)->addr = 0;
2009                 }
2010
2011                 qp->wrid[ind] = wr->wr_id;
2012
2013                 ++ind;
2014                 if (unlikely(ind >= qp->rq.max))
2015                         ind -= qp->rq.max;
2016         }
2017 out:
2018         if (likely(nreq)) {
2019                 qp->rq.head += nreq;
2020
2021                 /*
2022                  * Make sure that descriptors are written before
2023                  * doorbell record.
2024                  */
2025                 wmb();
2026                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2027         }
2028
2029         spin_unlock_irqrestore(&qp->rq.lock, flags);
2030         return err;
2031 }
2032
2033 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2034                        int index, int *dbd, __be32 *new_wqe)
2035 {
2036         struct mthca_next_seg *next;
2037
2038         /*
2039          * For SRQs, all WQEs generate a CQE, so we're always at the
2040          * end of the doorbell chain.
2041          */
2042         if (qp->ibqp.srq) {
2043                 *new_wqe = 0;
2044                 return 0;
2045         }
2046
2047         if (is_send)
2048                 next = get_send_wqe(qp, index);
2049         else
2050                 next = get_recv_wqe(qp, index);
2051
2052         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2053         if (next->ee_nds & cpu_to_be32(0x3f))
2054                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2055                         (next->ee_nds & cpu_to_be32(0x3f));
2056         else
2057                 *new_wqe = 0;
2058
2059         return 0;
2060 }
2061
2062 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2063 {
2064         int err;
2065         u8 status;
2066         int i;
2067
2068         spin_lock_init(&dev->qp_table.lock);
2069
2070         /*
2071          * We reserve 2 extra QPs per port for the special QPs.  The
2072          * special QP for port 1 has to be even, so round up.
2073          */
2074         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2075         err = mthca_alloc_init(&dev->qp_table.alloc,
2076                                dev->limits.num_qps,
2077                                (1 << 24) - 1,
2078                                dev->qp_table.sqp_start +
2079                                MTHCA_MAX_PORTS * 2);
2080         if (err)
2081                 return err;
2082
2083         err = mthca_array_init(&dev->qp_table.qp,
2084                                dev->limits.num_qps);
2085         if (err) {
2086                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2087                 return err;
2088         }
2089
2090         for (i = 0; i < 2; ++i) {
2091                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2092                                             dev->qp_table.sqp_start + i * 2,
2093                                             &status);
2094                 if (err)
2095                         goto err_out;
2096                 if (status) {
2097                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2098                                    "status %02x, aborting.\n",
2099                                    status);
2100                         err = -EINVAL;
2101                         goto err_out;
2102                 }
2103         }
2104         return 0;
2105
2106  err_out:
2107         for (i = 0; i < 2; ++i)
2108                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2109
2110         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2111         mthca_alloc_cleanup(&dev->qp_table.alloc);
2112
2113         return err;
2114 }
2115
2116 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2117 {
2118         int i;
2119         u8 status;
2120
2121         for (i = 0; i < 2; ++i)
2122                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2123
2124         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2125         mthca_alloc_cleanup(&dev->qp_table.alloc);
2126 }