drivers/infiniband/hw/mthca/mthca_qp.c

   1 /*
   2  * Copyright (c) 2004 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Cisco Systems. All rights reserved.
   4  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   5  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   6  *
   7  * This software is available to you under a choice of one of two
   8  * licenses.  You may choose to be licensed under the terms of the GNU
   9  * General Public License (GPL) Version 2, available from the file
  10  * COPYING in the main directory of this source tree, or the
  11  * OpenIB.org BSD license below:
  12  *
  13  *     Redistribution and use in source and binary forms, with or
  14  *     without modification, are permitted provided that the following
  15  *     conditions are met:
  16  *
  17  *      - Redistributions of source code must retain the above
  18  *        copyright notice, this list of conditions and the following
  19  *        disclaimer.
  20  *
  21  *      - Redistributions in binary form must reproduce the above
  22  *        copyright notice, this list of conditions and the following
  23  *        disclaimer in the documentation and/or other materials
  24  *        provided with the distribution.
  25  *
  26  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33  * SOFTWARE.
  34  *
  35  * $Id: mthca_qp.c 1355 2004-12-17 15:23:43Z roland $
  36  */
  37
  38 #include <linux/init.h>
  39 #include <linux/string.h>
  40 #include <linux/slab.h>
  41
  42 #include <rdma/ib_verbs.h>
  43 #include <rdma/ib_cache.h>
  44 #include <rdma/ib_pack.h>
  45
  46 #include "mthca_dev.h"
  47 #include "mthca_cmd.h"
  48 #include "mthca_memfree.h"
  49 #include "mthca_wqe.h"
  50
  51 enum {
  52         MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
  53         MTHCA_ACK_REQ_FREQ       = 10,
  54         MTHCA_FLIGHT_LIMIT       = 9,
  55         MTHCA_UD_HEADER_SIZE     = 72, /* largest UD header possible */
  56         MTHCA_INLINE_HEADER_SIZE = 4,  /* data segment overhead for inline */
  57         MTHCA_INLINE_CHUNK_SIZE  = 16  /* inline data segment chunk */
  58 };
  59
  60 enum {
  61         MTHCA_QP_STATE_RST  = 0,
  62         MTHCA_QP_STATE_INIT = 1,
  63         MTHCA_QP_STATE_RTR  = 2,
  64         MTHCA_QP_STATE_RTS  = 3,
  65         MTHCA_QP_STATE_SQE  = 4,
  66         MTHCA_QP_STATE_SQD  = 5,
  67         MTHCA_QP_STATE_ERR  = 6,
  68         MTHCA_QP_STATE_DRAINING = 7
  69 };
  70
  71 enum {
  72         MTHCA_QP_ST_RC  = 0x0,
  73         MTHCA_QP_ST_UC  = 0x1,
  74         MTHCA_QP_ST_RD  = 0x2,
  75         MTHCA_QP_ST_UD  = 0x3,
  76         MTHCA_QP_ST_MLX = 0x7
  77 };
  78
  79 enum {
  80         MTHCA_QP_PM_MIGRATED = 0x3,
  81         MTHCA_QP_PM_ARMED    = 0x0,
  82         MTHCA_QP_PM_REARM    = 0x1
  83 };
  84
  85 enum {
  86         /* qp_context flags */
  87         MTHCA_QP_BIT_DE  = 1 <<  8,
  88         /* params1 */
  89         MTHCA_QP_BIT_SRE = 1 << 15,
  90         MTHCA_QP_BIT_SWE = 1 << 14,
  91         MTHCA_QP_BIT_SAE = 1 << 13,
  92         MTHCA_QP_BIT_SIC = 1 <<  4,
  93         MTHCA_QP_BIT_SSC = 1 <<  3,
  94         /* params2 */
  95         MTHCA_QP_BIT_RRE = 1 << 15,
  96         MTHCA_QP_BIT_RWE = 1 << 14,
  97         MTHCA_QP_BIT_RAE = 1 << 13,
  98         MTHCA_QP_BIT_RIC = 1 <<  4,
  99         MTHCA_QP_BIT_RSC = 1 <<  3
 100 };
 101
 102 struct mthca_qp_path {
 103         __be32 port_pkey;
 104         u8     rnr_retry;
 105         u8     g_mylmc;
 106         __be16 rlid;
 107         u8     ackto;
 108         u8     mgid_index;
 109         u8     static_rate;
 110         u8     hop_limit;
 111         __be32 sl_tclass_flowlabel;
 112         u8     rgid[16];
 113 } __attribute__((packed));
 114
 115 struct mthca_qp_context {
 116         __be32 flags;
 117         __be32 tavor_sched_queue; /* Reserved on Arbel */
 118         u8     mtu_msgmax;
 119         u8     rq_size_stride;  /* Reserved on Tavor */
 120         u8     sq_size_stride;  /* Reserved on Tavor */
 121         u8     rlkey_arbel_sched_queue; /* Reserved on Tavor */
 122         __be32 usr_page;
 123         __be32 local_qpn;
 124         __be32 remote_qpn;
 125         u32    reserved1[2];
 126         struct mthca_qp_path pri_path;
 127         struct mthca_qp_path alt_path;
 128         __be32 rdd;
 129         __be32 pd;
 130         __be32 wqe_base;
 131         __be32 wqe_lkey;
 132         __be32 params1;
 133         __be32 reserved2;
 134         __be32 next_send_psn;
 135         __be32 cqn_snd;
 136         __be32 snd_wqe_base_l;  /* Next send WQE on Tavor */
 137         __be32 snd_db_index;    /* (debugging only entries) */
 138         __be32 last_acked_psn;
 139         __be32 ssn;
 140         __be32 params2;
 141         __be32 rnr_nextrecvpsn;
 142         __be32 ra_buff_indx;
 143         __be32 cqn_rcv;
 144         __be32 rcv_wqe_base_l;  /* Next recv WQE on Tavor */
 145         __be32 rcv_db_index;    /* (debugging only entries) */
 146         __be32 qkey;
 147         __be32 srqn;
 148         __be32 rmsn;
 149         __be16 rq_wqe_counter;  /* reserved on Tavor */
 150         __be16 sq_wqe_counter;  /* reserved on Tavor */
 151         u32    reserved3[18];
 152 } __attribute__((packed));
 153
 154 struct mthca_qp_param {
 155         __be32 opt_param_mask;
 156         u32    reserved1;
 157         struct mthca_qp_context context;
 158         u32    reserved2[62];
 159 } __attribute__((packed));
 160
 161 enum {
 162         MTHCA_QP_OPTPAR_ALT_ADDR_PATH     = 1 << 0,
 163         MTHCA_QP_OPTPAR_RRE               = 1 << 1,
 164         MTHCA_QP_OPTPAR_RAE               = 1 << 2,
 165         MTHCA_QP_OPTPAR_RWE               = 1 << 3,
 166         MTHCA_QP_OPTPAR_PKEY_INDEX        = 1 << 4,
 167         MTHCA_QP_OPTPAR_Q_KEY             = 1 << 5,
 168         MTHCA_QP_OPTPAR_RNR_TIMEOUT       = 1 << 6,
 169         MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
 170         MTHCA_QP_OPTPAR_SRA_MAX           = 1 << 8,
 171         MTHCA_QP_OPTPAR_RRA_MAX           = 1 << 9,
 172         MTHCA_QP_OPTPAR_PM_STATE          = 1 << 10,
 173         MTHCA_QP_OPTPAR_PORT_NUM          = 1 << 11,
 174         MTHCA_QP_OPTPAR_RETRY_COUNT       = 1 << 12,
 175         MTHCA_QP_OPTPAR_ALT_RNR_RETRY     = 1 << 13,
 176         MTHCA_QP_OPTPAR_ACK_TIMEOUT       = 1 << 14,
 177         MTHCA_QP_OPTPAR_RNR_RETRY         = 1 << 15,
 178         MTHCA_QP_OPTPAR_SCHED_QUEUE       = 1 << 16
 179 };
 180
 181 static const u8 mthca_opcode[] = {
 182         [IB_WR_SEND]                 = MTHCA_OPCODE_SEND,
 183         [IB_WR_SEND_WITH_IMM]        = MTHCA_OPCODE_SEND_IMM,
 184         [IB_WR_RDMA_WRITE]           = MTHCA_OPCODE_RDMA_WRITE,
 185         [IB_WR_RDMA_WRITE_WITH_IMM]  = MTHCA_OPCODE_RDMA_WRITE_IMM,
 186         [IB_WR_RDMA_READ]            = MTHCA_OPCODE_RDMA_READ,
 187         [IB_WR_ATOMIC_CMP_AND_SWP]   = MTHCA_OPCODE_ATOMIC_CS,
 188         [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
 189 };
 190
 191 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
 192 {
 193         return qp->qpn >= dev->qp_table.sqp_start &&
 194                 qp->qpn <= dev->qp_table.sqp_start + 3;
 195 }
 196
 197 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
 198 {
 199         return qp->qpn >= dev->qp_table.sqp_start &&
 200                 qp->qpn <= dev->qp_table.sqp_start + 1;
 201 }
 202
 203 static void *get_recv_wqe(struct mthca_qp *qp, int n)
 204 {
 205         if (qp->is_direct)
 206                 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
 207         else
 208                 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
 209                         ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
 210 }
 211
 212 static void *get_send_wqe(struct mthca_qp *qp, int n)
 213 {
 214         if (qp->is_direct)
 215                 return qp->queue.direct.buf + qp->send_wqe_offset +
 216                         (n << qp->sq.wqe_shift);
 217         else
 218                 return qp->queue.page_list[(qp->send_wqe_offset +
 219                                             (n << qp->sq.wqe_shift)) >>
 220                                            PAGE_SHIFT].buf +
 221                         ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
 222                          (PAGE_SIZE - 1));
 223 }
 224
 225 static void mthca_wq_init(struct mthca_wq *wq)
 226 {
 227         spin_lock_init(&wq->lock);
 228         wq->next_ind  = 0;
 229         wq->last_comp = wq->max - 1;
 230         wq->head      = 0;
 231         wq->tail      = 0;
 232 }
 233
 234 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
 235                     enum ib_event_type event_type)
 236 {
 237         struct mthca_qp *qp;
 238         struct ib_event event;
 239
 240         spin_lock(&dev->qp_table.lock);
 241         qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
 242         if (qp)
 243                 atomic_inc(&qp->refcount);
 244         spin_unlock(&dev->qp_table.lock);
 245
 246         if (!qp) {
 247                 mthca_warn(dev, "Async event for bogus QP %08x\n", qpn);
 248                 return;
 249         }
 250
 251         event.device      = &dev->ib_dev;
 252         event.event       = event_type;
 253         event.element.qp  = &qp->ibqp;
 254         if (qp->ibqp.event_handler)
 255                 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
 256
 257         if (atomic_dec_and_test(&qp->refcount))
 258                 wake_up(&qp->wait);
 259 }
 260
 261 static int to_mthca_state(enum ib_qp_state ib_state)
 262 {
 263         switch (ib_state) {
 264         case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
 265         case IB_QPS_INIT:  return MTHCA_QP_STATE_INIT;
 266         case IB_QPS_RTR:   return MTHCA_QP_STATE_RTR;
 267         case IB_QPS_RTS:   return MTHCA_QP_STATE_RTS;
 268         case IB_QPS_SQD:   return MTHCA_QP_STATE_SQD;
 269         case IB_QPS_SQE:   return MTHCA_QP_STATE_SQE;
 270         case IB_QPS_ERR:   return MTHCA_QP_STATE_ERR;
 271         default:                return -1;
 272         }
 273 }
 274
 275 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
 276
 277 static int to_mthca_st(int transport)
 278 {
 279         switch (transport) {
 280         case RC:  return MTHCA_QP_ST_RC;
 281         case UC:  return MTHCA_QP_ST_UC;
 282         case UD:  return MTHCA_QP_ST_UD;
 283         case RD:  return MTHCA_QP_ST_RD;
 284         case MLX: return MTHCA_QP_ST_MLX;
 285         default:  return -1;
 286         }
 287 }
 288
 289 static const struct {
 290         int trans;
 291         u32 req_param[NUM_TRANS];
 292         u32 opt_param[NUM_TRANS];
 293 } state_table[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = {
 294         [IB_QPS_RESET] = {
 295                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 296                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 297                 [IB_QPS_INIT]  = {
 298                         .trans = MTHCA_TRANS_RST2INIT,
 299                         .req_param = {
 300                                 [UD]  = (IB_QP_PKEY_INDEX |
 301                                          IB_QP_PORT       |
 302                                          IB_QP_QKEY),
 303                                 [UC]  = (IB_QP_PKEY_INDEX |
 304                                          IB_QP_PORT       |
 305                                          IB_QP_ACCESS_FLAGS),
 306                                 [RC]  = (IB_QP_PKEY_INDEX |
 307                                          IB_QP_PORT       |
 308                                          IB_QP_ACCESS_FLAGS),
 309                                 [MLX] = (IB_QP_PKEY_INDEX |
 310                                          IB_QP_QKEY),
 311                         },
 312                         /* bug-for-bug compatibility with VAPI: */
 313                         .opt_param = {
 314                                 [MLX] = IB_QP_PORT
 315                         }
 316                 },
 317         },
 318         [IB_QPS_INIT]  = {
 319                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 320                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 321                 [IB_QPS_INIT]  = {
 322                         .trans = MTHCA_TRANS_INIT2INIT,
 323                         .opt_param = {
 324                                 [UD]  = (IB_QP_PKEY_INDEX |
 325                                          IB_QP_PORT       |
 326                                          IB_QP_QKEY),
 327                                 [UC]  = (IB_QP_PKEY_INDEX |
 328                                          IB_QP_PORT       |
 329                                          IB_QP_ACCESS_FLAGS),
 330                                 [RC]  = (IB_QP_PKEY_INDEX |
 331                                          IB_QP_PORT       |
 332                                          IB_QP_ACCESS_FLAGS),
 333                                 [MLX] = (IB_QP_PKEY_INDEX |
 334                                          IB_QP_QKEY),
 335                         }
 336                 },
 337                 [IB_QPS_RTR]   = {
 338                         .trans = MTHCA_TRANS_INIT2RTR,
 339                         .req_param = {
 340                                 [UC]  = (IB_QP_AV                  |
 341                                          IB_QP_PATH_MTU            |
 342                                          IB_QP_DEST_QPN            |
 343                                          IB_QP_RQ_PSN),
 344                                 [RC]  = (IB_QP_AV                  |
 345                                          IB_QP_PATH_MTU            |
 346                                          IB_QP_DEST_QPN            |
 347                                          IB_QP_RQ_PSN              |
 348                                          IB_QP_MAX_DEST_RD_ATOMIC  |
 349                                          IB_QP_MIN_RNR_TIMER),
 350                         },
 351                         .opt_param = {
 352                                 [UD]  = (IB_QP_PKEY_INDEX |
 353                                          IB_QP_QKEY),
 354                                 [UC]  = (IB_QP_ALT_PATH     |
 355                                          IB_QP_ACCESS_FLAGS |
 356                                          IB_QP_PKEY_INDEX),
 357                                 [RC]  = (IB_QP_ALT_PATH     |
 358                                          IB_QP_ACCESS_FLAGS |
 359                                          IB_QP_PKEY_INDEX),
 360                                 [MLX] = (IB_QP_PKEY_INDEX |
 361                                          IB_QP_QKEY),
 362                         }
 363                 }
 364         },
 365         [IB_QPS_RTR]   = {
 366                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 367                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 368                 [IB_QPS_RTS]   = {
 369                         .trans = MTHCA_TRANS_RTR2RTS,
 370                         .req_param = {
 371                                 [UD]  = IB_QP_SQ_PSN,
 372                                 [UC]  = IB_QP_SQ_PSN,
 373                                 [RC]  = (IB_QP_TIMEOUT           |
 374                                          IB_QP_RETRY_CNT         |
 375                                          IB_QP_RNR_RETRY         |
 376                                          IB_QP_SQ_PSN            |
 377                                          IB_QP_MAX_QP_RD_ATOMIC),
 378                                 [MLX] = IB_QP_SQ_PSN,
 379                         },
 380                         .opt_param = {
 381                                 [UD]  = (IB_QP_CUR_STATE             |
 382                                          IB_QP_QKEY),
 383                                 [UC]  = (IB_QP_CUR_STATE             |
 384                                          IB_QP_ALT_PATH              |
 385                                          IB_QP_ACCESS_FLAGS          |
 386                                          IB_QP_PKEY_INDEX            |
 387                                          IB_QP_PATH_MIG_STATE),
 388                                 [RC]  = (IB_QP_CUR_STATE             |
 389                                          IB_QP_ALT_PATH              |
 390                                          IB_QP_ACCESS_FLAGS          |
 391                                          IB_QP_PKEY_INDEX            |
 392                                          IB_QP_MIN_RNR_TIMER         |
 393                                          IB_QP_PATH_MIG_STATE),
 394                                 [MLX] = (IB_QP_CUR_STATE             |
 395                                          IB_QP_QKEY),
 396                         }
 397                 }
 398         },
 399         [IB_QPS_RTS]   = {
 400                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 401                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 402                 [IB_QPS_RTS]   = {
 403                         .trans = MTHCA_TRANS_RTS2RTS,
 404                         .opt_param = {
 405                                 [UD]  = (IB_QP_CUR_STATE             |
 406                                          IB_QP_QKEY),
 407                                 [UC]  = (IB_QP_ACCESS_FLAGS          |
 408                                          IB_QP_ALT_PATH              |
 409                                          IB_QP_PATH_MIG_STATE),
 410                                 [RC]  = (IB_QP_ACCESS_FLAGS          |
 411                                          IB_QP_ALT_PATH              |
 412                                          IB_QP_PATH_MIG_STATE        |
 413                                          IB_QP_MIN_RNR_TIMER),
 414                                 [MLX] = (IB_QP_CUR_STATE             |
 415                                          IB_QP_QKEY),
 416                         }
 417                 },
 418                 [IB_QPS_SQD]   = {
 419                         .trans = MTHCA_TRANS_RTS2SQD,
 420                 },
 421         },
 422         [IB_QPS_SQD]   = {
 423                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 424                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 425                 [IB_QPS_RTS]   = {
 426                         .trans = MTHCA_TRANS_SQD2RTS,
 427                         .opt_param = {
 428                                 [UD]  = (IB_QP_CUR_STATE             |
 429                                          IB_QP_QKEY),
 430                                 [UC]  = (IB_QP_CUR_STATE             |
 431                                          IB_QP_ALT_PATH              |
 432                                          IB_QP_ACCESS_FLAGS          |
 433                                          IB_QP_PATH_MIG_STATE),
 434                                 [RC]  = (IB_QP_CUR_STATE             |
 435                                          IB_QP_ALT_PATH              |
 436                                          IB_QP_ACCESS_FLAGS          |
 437                                          IB_QP_MIN_RNR_TIMER         |
 438                                          IB_QP_PATH_MIG_STATE),
 439                                 [MLX] = (IB_QP_CUR_STATE             |
 440                                          IB_QP_QKEY),
 441                         }
 442                 },
 443                 [IB_QPS_SQD]   = {
 444                         .trans = MTHCA_TRANS_SQD2SQD,
 445                         .opt_param = {
 446                                 [UD]  = (IB_QP_PKEY_INDEX            |
 447                                          IB_QP_QKEY),
 448                                 [UC]  = (IB_QP_AV                    |
 449                                          IB_QP_CUR_STATE             |
 450                                          IB_QP_ALT_PATH              |
 451                                          IB_QP_ACCESS_FLAGS          |
 452                                          IB_QP_PKEY_INDEX            |
 453                                          IB_QP_PATH_MIG_STATE),
 454                                 [RC]  = (IB_QP_AV                    |
 455                                          IB_QP_TIMEOUT               |
 456                                          IB_QP_RETRY_CNT             |
 457                                          IB_QP_RNR_RETRY             |
 458                                          IB_QP_MAX_QP_RD_ATOMIC      |
 459                                          IB_QP_MAX_DEST_RD_ATOMIC    |
 460                                          IB_QP_CUR_STATE             |
 461                                          IB_QP_ALT_PATH              |
 462                                          IB_QP_ACCESS_FLAGS          |
 463                                          IB_QP_PKEY_INDEX            |
 464                                          IB_QP_MIN_RNR_TIMER         |
 465                                          IB_QP_PATH_MIG_STATE),
 466                                 [MLX] = (IB_QP_PKEY_INDEX            |
 467                                          IB_QP_QKEY),
 468                         }
 469                 }
 470         },
 471         [IB_QPS_SQE]   = {
 472                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 473                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR },
 474                 [IB_QPS_RTS]   = {
 475                         .trans = MTHCA_TRANS_SQERR2RTS,
 476                         .opt_param = {
 477                                 [UD]  = (IB_QP_CUR_STATE             |
 478                                          IB_QP_QKEY),
 479                                 [UC]  = (IB_QP_CUR_STATE             |
 480                                          IB_QP_ACCESS_FLAGS),
 481                                 [MLX] = (IB_QP_CUR_STATE             |
 482                                          IB_QP_QKEY),
 483                         }
 484                 }
 485         },
 486         [IB_QPS_ERR] = {
 487                 [IB_QPS_RESET] = { .trans = MTHCA_TRANS_ANY2RST },
 488                 [IB_QPS_ERR] = { .trans = MTHCA_TRANS_ANY2ERR }
 489         }
 490 };
 491
 492 static void store_attrs(struct mthca_sqp *sqp, struct ib_qp_attr *attr,
 493                         int attr_mask)
 494 {
 495         if (attr_mask & IB_QP_PKEY_INDEX)
 496                 sqp->pkey_index = attr->pkey_index;
 497         if (attr_mask & IB_QP_QKEY)
 498                 sqp->qkey = attr->qkey;
 499         if (attr_mask & IB_QP_SQ_PSN)
 500                 sqp->send_psn = attr->sq_psn;
 501 }
 502
 503 static void init_port(struct mthca_dev *dev, int port)
 504 {
 505         int err;
 506         u8 status;
 507         struct mthca_init_ib_param param;
 508
 509         memset(&param, 0, sizeof param);
 510
 511         param.port_width = dev->limits.port_width_cap;
 512         param.vl_cap     = dev->limits.vl_cap;
 513         param.mtu_cap    = dev->limits.mtu_cap;
 514         param.gid_cap    = dev->limits.gid_table_len;
 515         param.pkey_cap   = dev->limits.pkey_table_len;
 516
 517         err = mthca_INIT_IB(dev, &param, port, &status);
 518         if (err)
 519                 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
 520         if (status)
 521                 mthca_warn(dev, "INIT_IB returned status %02x.\n", status);
 522 }
 523
 524 static __be32 get_hw_access_flags(struct mthca_qp *qp, struct ib_qp_attr *attr,
 525                                   int attr_mask)
 526 {
 527         u8 dest_rd_atomic;
 528         u32 access_flags;
 529         u32 hw_access_flags = 0;
 530
 531         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 532                 dest_rd_atomic = attr->max_dest_rd_atomic;
 533         else
 534                 dest_rd_atomic = qp->resp_depth;
 535
 536         if (attr_mask & IB_QP_ACCESS_FLAGS)
 537                 access_flags = attr->qp_access_flags;
 538         else
 539                 access_flags = qp->atomic_rd_en;
 540
 541         if (!dest_rd_atomic)
 542                 access_flags &= IB_ACCESS_REMOTE_WRITE;
 543
 544         if (access_flags & IB_ACCESS_REMOTE_READ)
 545                 hw_access_flags |= MTHCA_QP_BIT_RRE;
 546         if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
 547                 hw_access_flags |= MTHCA_QP_BIT_RAE;
 548         if (access_flags & IB_ACCESS_REMOTE_WRITE)
 549                 hw_access_flags |= MTHCA_QP_BIT_RWE;
 550
 551         return cpu_to_be32(hw_access_flags);
 552 }
 553
 554 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask)
 555 {
 556         struct mthca_dev *dev = to_mdev(ibqp->device);
 557         struct mthca_qp *qp = to_mqp(ibqp);
 558         enum ib_qp_state cur_state, new_state;
 559         struct mthca_mailbox *mailbox;
 560         struct mthca_qp_param *qp_param;
 561         struct mthca_qp_context *qp_context;
 562         u32 req_param, opt_param;
 563         u8 status;
 564         int err;
 565
 566         if (attr_mask & IB_QP_CUR_STATE) {
 567                 if (attr->cur_qp_state != IB_QPS_RTR &&
 568                     attr->cur_qp_state != IB_QPS_RTS &&
 569                     attr->cur_qp_state != IB_QPS_SQD &&
 570                     attr->cur_qp_state != IB_QPS_SQE)
 571                         return -EINVAL;
 572                 else
 573                         cur_state = attr->cur_qp_state;
 574         } else {
 575                 spin_lock_irq(&qp->sq.lock);
 576                 spin_lock(&qp->rq.lock);
 577                 cur_state = qp->state;
 578                 spin_unlock(&qp->rq.lock);
 579                 spin_unlock_irq(&qp->sq.lock);
 580         }
 581
 582         if (attr_mask & IB_QP_STATE) {
 583                if (attr->qp_state < 0 || attr->qp_state > IB_QPS_ERR)
 584                         return -EINVAL;
 585                 new_state = attr->qp_state;
 586         } else
 587                 new_state = cur_state;
 588
 589         if (state_table[cur_state][new_state].trans == MTHCA_TRANS_INVALID) {
 590                 mthca_dbg(dev, "Illegal QP transition "
 591                           "%d->%d\n", cur_state, new_state);
 592                 return -EINVAL;
 593         }
 594
 595         req_param = state_table[cur_state][new_state].req_param[qp->transport];
 596         opt_param = state_table[cur_state][new_state].opt_param[qp->transport];
 597
 598         if ((req_param & attr_mask) != req_param) {
 599                 mthca_dbg(dev, "QP transition "
 600                           "%d->%d missing req attr 0x%08x\n",
 601                           cur_state, new_state,
 602                           req_param & ~attr_mask);
 603                 return -EINVAL;
 604         }
 605
 606         if (attr_mask & ~(req_param | opt_param | IB_QP_STATE)) {
 607                 mthca_dbg(dev, "QP transition (transport %d) "
 608                           "%d->%d has extra attr 0x%08x\n",
 609                           qp->transport,
 610                           cur_state, new_state,
 611                           attr_mask & ~(req_param | opt_param |
 612                                                  IB_QP_STATE));
 613                 return -EINVAL;
 614         }
 615
 616         if ((attr_mask & IB_QP_PKEY_INDEX) &&
 617              attr->pkey_index >= dev->limits.pkey_table_len) {
 618                 mthca_dbg(dev, "PKey index (%u) too large. max is %d\n",
 619                           attr->pkey_index,dev->limits.pkey_table_len-1);
 620                 return -EINVAL;
 621         }
 622
 623         if ((attr_mask & IB_QP_PORT) &&
 624             (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
 625                 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
 626                 return -EINVAL;
 627         }
 628
 629         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
 630             attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
 631                 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
 632                           attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
 633                 return -EINVAL;
 634         }
 635
 636         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
 637             attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
 638                 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
 639                           attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
 640                 return -EINVAL;
 641         }
 642
 643         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 644         if (IS_ERR(mailbox))
 645                 return PTR_ERR(mailbox);
 646         qp_param = mailbox->buf;
 647         qp_context = &qp_param->context;
 648         memset(qp_param, 0, sizeof *qp_param);
 649
 650         qp_context->flags      = cpu_to_be32((to_mthca_state(new_state) << 28) |
 651                                              (to_mthca_st(qp->transport) << 16));
 652         qp_context->flags     |= cpu_to_be32(MTHCA_QP_BIT_DE);
 653         if (!(attr_mask & IB_QP_PATH_MIG_STATE))
 654                 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 655         else {
 656                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
 657                 switch (attr->path_mig_state) {
 658                 case IB_MIG_MIGRATED:
 659                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
 660                         break;
 661                 case IB_MIG_REARM:
 662                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
 663                         break;
 664                 case IB_MIG_ARMED:
 665                         qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
 666                         break;
 667                 }
 668         }
 669
 670         /* leave tavor_sched_queue as 0 */
 671
 672         if (qp->transport == MLX || qp->transport == UD)
 673                 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
 674         else if (attr_mask & IB_QP_PATH_MTU)
 675                 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
 676
 677         if (mthca_is_memfree(dev)) {
 678                 if (qp->rq.max)
 679                         qp_context->rq_size_stride = long_log2(qp->rq.max) << 3;
 680                 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
 681
 682                 if (qp->sq.max)
 683                         qp_context->sq_size_stride = long_log2(qp->sq.max) << 3;
 684                 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
 685         }
 686
 687         /* leave arbel_sched_queue as 0 */
 688
 689         if (qp->ibqp.uobject)
 690                 qp_context->usr_page =
 691                         cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
 692         else
 693                 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
 694         qp_context->local_qpn  = cpu_to_be32(qp->qpn);
 695         if (attr_mask & IB_QP_DEST_QPN) {
 696                 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
 697         }
 698
 699         if (qp->transport == MLX)
 700                 qp_context->pri_path.port_pkey |=
 701                         cpu_to_be32(to_msqp(qp)->port << 24);
 702         else {
 703                 if (attr_mask & IB_QP_PORT) {
 704                         qp_context->pri_path.port_pkey |=
 705                                 cpu_to_be32(attr->port_num << 24);
 706                         qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
 707                 }
 708         }
 709
 710         if (attr_mask & IB_QP_PKEY_INDEX) {
 711                 qp_context->pri_path.port_pkey |=
 712                         cpu_to_be32(attr->pkey_index);
 713                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
 714         }
 715
 716         if (attr_mask & IB_QP_RNR_RETRY) {
 717                 qp_context->pri_path.rnr_retry = attr->rnr_retry << 5;
 718                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY);
 719         }
 720
 721         if (attr_mask & IB_QP_AV) {
 722                 qp_context->pri_path.g_mylmc     = attr->ah_attr.src_path_bits & 0x7f;
 723                 qp_context->pri_path.rlid        = cpu_to_be16(attr->ah_attr.dlid);
 724                 qp_context->pri_path.static_rate = !!attr->ah_attr.static_rate;
 725                 if (attr->ah_attr.ah_flags & IB_AH_GRH) {
 726                         qp_context->pri_path.g_mylmc |= 1 << 7;
 727                         qp_context->pri_path.mgid_index = attr->ah_attr.grh.sgid_index;
 728                         qp_context->pri_path.hop_limit = attr->ah_attr.grh.hop_limit;
 729                         qp_context->pri_path.sl_tclass_flowlabel =
 730                                 cpu_to_be32((attr->ah_attr.sl << 28)                |
 731                                             (attr->ah_attr.grh.traffic_class << 20) |
 732                                             (attr->ah_attr.grh.flow_label));
 733                         memcpy(qp_context->pri_path.rgid,
 734                                attr->ah_attr.grh.dgid.raw, 16);
 735                 } else {
 736                         qp_context->pri_path.sl_tclass_flowlabel =
 737                                 cpu_to_be32(attr->ah_attr.sl << 28);
 738                 }
 739                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
 740         }
 741
 742         if (attr_mask & IB_QP_TIMEOUT) {
 743                 qp_context->pri_path.ackto = attr->timeout << 3;
 744                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
 745         }
 746
 747         /* XXX alt_path */
 748
 749         /* leave rdd as 0 */
 750         qp_context->pd         = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
 751         /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
 752         qp_context->wqe_lkey   = cpu_to_be32(qp->mr.ibmr.lkey);
 753         qp_context->params1    = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
 754                                              (MTHCA_FLIGHT_LIMIT << 24) |
 755                                              MTHCA_QP_BIT_SWE);
 756         if (qp->sq_policy == IB_SIGNAL_ALL_WR)
 757                 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
 758         if (attr_mask & IB_QP_RETRY_CNT) {
 759                 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
 760                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
 761         }
 762
 763         if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
 764                 if (attr->max_rd_atomic) {
 765                         qp_context->params1 |=
 766                                 cpu_to_be32(MTHCA_QP_BIT_SRE |
 767                                             MTHCA_QP_BIT_SAE);
 768                         qp_context->params1 |=
 769                                 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
 770                 }
 771                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
 772         }
 773
 774         if (attr_mask & IB_QP_SQ_PSN)
 775                 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
 776         qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
 777
 778         if (mthca_is_memfree(dev)) {
 779                 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
 780                 qp_context->snd_db_index   = cpu_to_be32(qp->sq.db_index);
 781         }
 782
 783         if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
 784                 if (attr->max_dest_rd_atomic)
 785                         qp_context->params2 |=
 786                                 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
 787
 788                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
 789         }
 790
 791         if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
 792                 qp_context->params2      |= get_hw_access_flags(qp, attr, attr_mask);
 793                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
 794                                                         MTHCA_QP_OPTPAR_RRE |
 795                                                         MTHCA_QP_OPTPAR_RAE);
 796         }
 797
 798         qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
 799
 800         if (ibqp->srq)
 801                 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
 802
 803         if (attr_mask & IB_QP_MIN_RNR_TIMER) {
 804                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
 805                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
 806         }
 807         if (attr_mask & IB_QP_RQ_PSN)
 808                 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
 809
 810         qp_context->ra_buff_indx =
 811                 cpu_to_be32(dev->qp_table.rdb_base +
 812                             ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
 813                              dev->qp_table.rdb_shift));
 814
 815         qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
 816
 817         if (mthca_is_memfree(dev))
 818                 qp_context->rcv_db_index   = cpu_to_be32(qp->rq.db_index);
 819
 820         if (attr_mask & IB_QP_QKEY) {
 821                 qp_context->qkey = cpu_to_be32(attr->qkey);
 822                 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
 823         }
 824
 825         if (ibqp->srq)
 826                 qp_context->srqn = cpu_to_be32(1 << 24 |
 827                                                to_msrq(ibqp->srq)->srqn);
 828
 829         err = mthca_MODIFY_QP(dev, state_table[cur_state][new_state].trans,
 830                               qp->qpn, 0, mailbox, 0, &status);
 831         if (status) {
 832                 mthca_warn(dev, "modify QP %d returned status %02x.\n",
 833                            state_table[cur_state][new_state].trans, status);
 834                 err = -EINVAL;
 835         }
 836
 837         if (!err) {
 838                 qp->state = new_state;
 839                 if (attr_mask & IB_QP_ACCESS_FLAGS)
 840                         qp->atomic_rd_en = attr->qp_access_flags;
 841                 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
 842                         qp->resp_depth = attr->max_dest_rd_atomic;
 843         }
 844
 845         mthca_free_mailbox(dev, mailbox);
 846
 847         if (is_sqp(dev, qp))
 848                 store_attrs(to_msqp(qp), attr, attr_mask);
 849
 850         /*
 851          * If we moved QP0 to RTR, bring the IB link up; if we moved
 852          * QP0 to RESET or ERROR, bring the link back down.
 853          */
 854         if (is_qp0(dev, qp)) {
 855                 if (cur_state != IB_QPS_RTR &&
 856                     new_state == IB_QPS_RTR)
 857                         init_port(dev, to_msqp(qp)->port);
 858
 859                 if (cur_state != IB_QPS_RESET &&
 860                     cur_state != IB_QPS_ERR &&
 861                     (new_state == IB_QPS_RESET ||
 862                      new_state == IB_QPS_ERR))
 863                         mthca_CLOSE_IB(dev, to_msqp(qp)->port, &status);
 864         }
 865
 866         /*
 867          * If we moved a kernel QP to RESET, clean up all old CQ
 868          * entries and reinitialize the QP.
 869          */
 870         if (!err && new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
 871                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
 872                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 873                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
 874                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
 875                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
 876
 877                 mthca_wq_init(&qp->sq);
 878                 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
 879
 880                 mthca_wq_init(&qp->rq);
 881                 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
 882
 883                 if (mthca_is_memfree(dev)) {
 884                         *qp->sq.db = 0;
 885                         *qp->rq.db = 0;
 886                 }
 887         }
 888
 889         return err;
 890 }
 891
 892 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
 893 {
 894         /*
 895          * Calculate the maximum size of WQE s/g segments, excluding
 896          * the next segment and other non-data segments.
 897          */
 898         int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
 899
 900         switch (qp->transport) {
 901         case MLX:
 902                 max_data_size -= 2 * sizeof (struct mthca_data_seg);
 903                 break;
 904
 905         case UD:
 906                 if (mthca_is_memfree(dev))
 907                         max_data_size -= sizeof (struct mthca_arbel_ud_seg);
 908                 else
 909                         max_data_size -= sizeof (struct mthca_tavor_ud_seg);
 910                 break;
 911
 912         default:
 913                 max_data_size -= sizeof (struct mthca_raddr_seg);
 914                 break;
 915         }
 916
 917         return max_data_size;
 918 }
 919
 920 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
 921 {
 922         /* We don't support inline data for kernel QPs (yet). */
 923         return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
 924 }
 925
 926 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
 927                                  struct mthca_pd *pd,
 928                                  struct mthca_qp *qp)
 929 {
 930         int max_data_size = mthca_max_data_size(dev, qp,
 931                                                 min(dev->limits.max_desc_sz,
 932                                                     1 << qp->sq.wqe_shift));
 933
 934         qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
 935
 936         qp->sq.max_gs = min_t(int, dev->limits.max_sg,
 937                               max_data_size / sizeof (struct mthca_data_seg));
 938         qp->rq.max_gs = min_t(int, dev->limits.max_sg,
 939                                (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
 940                                 sizeof (struct mthca_next_seg)) /
 941                                sizeof (struct mthca_data_seg));
 942 }
 943
 944 /*
 945  * Allocate and register buffer for WQEs.  qp->rq.max, sq.max,
 946  * rq.max_gs and sq.max_gs must all be assigned.
 947  * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
 948  * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
 949  * queue)
 950  */
 951 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
 952                                struct mthca_pd *pd,
 953                                struct mthca_qp *qp)
 954 {
 955         int size;
 956         int err = -ENOMEM;
 957
 958         size = sizeof (struct mthca_next_seg) +
 959                 qp->rq.max_gs * sizeof (struct mthca_data_seg);
 960
 961         if (size > dev->limits.max_desc_sz)
 962                 return -EINVAL;
 963
 964         for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
 965              qp->rq.wqe_shift++)
 966                 ; /* nothing */
 967
 968         size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
 969         switch (qp->transport) {
 970         case MLX:
 971                 size += 2 * sizeof (struct mthca_data_seg);
 972                 break;
 973
 974         case UD:
 975                 size += mthca_is_memfree(dev) ?
 976                         sizeof (struct mthca_arbel_ud_seg) :
 977                         sizeof (struct mthca_tavor_ud_seg);
 978                 break;
 979
 980         case UC:
 981                 size += sizeof (struct mthca_raddr_seg);
 982                 break;
 983
 984         case RC:
 985                 size += sizeof (struct mthca_raddr_seg);
 986                 /*
 987                  * An atomic op will require an atomic segment, a
 988                  * remote address segment and one scatter entry.
 989                  */
 990                 size = max_t(int, size,
 991                              sizeof (struct mthca_atomic_seg) +
 992                              sizeof (struct mthca_raddr_seg) +
 993                              sizeof (struct mthca_data_seg));
 994                 break;
 995
 996         default:
 997                 break;
 998         }
 999
1000         /* Make sure that we have enough space for a bind request */
1001         size = max_t(int, size, sizeof (struct mthca_bind_seg));
1002
1003         size += sizeof (struct mthca_next_seg);
1004
1005         if (size > dev->limits.max_desc_sz)
1006                 return -EINVAL;
1007
1008         for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1009              qp->sq.wqe_shift++)
1010                 ; /* nothing */
1011
1012         qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1013                                     1 << qp->sq.wqe_shift);
1014
1015         /*
1016          * If this is a userspace QP, we don't actually have to
1017          * allocate anything.  All we need is to calculate the WQE
1018          * sizes and the send_wqe_offset, so we're done now.
1019          */
1020         if (pd->ibpd.uobject)
1021                 return 0;
1022
1023         size = PAGE_ALIGN(qp->send_wqe_offset +
1024                           (qp->sq.max << qp->sq.wqe_shift));
1025
1026         qp->wrid = kmalloc((qp->rq.max + qp->sq.max) * sizeof (u64),
1027                            GFP_KERNEL);
1028         if (!qp->wrid)
1029                 goto err_out;
1030
1031         err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1032                               &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1033         if (err)
1034                 goto err_out;
1035
1036         return 0;
1037
1038 err_out:
1039         kfree(qp->wrid);
1040         return err;
1041 }
1042
1043 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1044                                struct mthca_qp *qp)
1045 {
1046         mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1047                                        (qp->sq.max << qp->sq.wqe_shift)),
1048                        &qp->queue, qp->is_direct, &qp->mr);
1049         kfree(qp->wrid);
1050 }
1051
1052 static int mthca_map_memfree(struct mthca_dev *dev,
1053                              struct mthca_qp *qp)
1054 {
1055         int ret;
1056
1057         if (mthca_is_memfree(dev)) {
1058                 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1059                 if (ret)
1060                         return ret;
1061
1062                 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1063                 if (ret)
1064                         goto err_qpc;
1065
1066                 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1067                                       qp->qpn << dev->qp_table.rdb_shift);
1068                 if (ret)
1069                         goto err_eqpc;
1070
1071         }
1072
1073         return 0;
1074
1075 err_eqpc:
1076         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1077
1078 err_qpc:
1079         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1080
1081         return ret;
1082 }
1083
1084 static void mthca_unmap_memfree(struct mthca_dev *dev,
1085                                 struct mthca_qp *qp)
1086 {
1087         mthca_table_put(dev, dev->qp_table.rdb_table,
1088                         qp->qpn << dev->qp_table.rdb_shift);
1089         mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1090         mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1091 }
1092
1093 static int mthca_alloc_memfree(struct mthca_dev *dev,
1094                                struct mthca_qp *qp)
1095 {
1096         int ret = 0;
1097
1098         if (mthca_is_memfree(dev)) {
1099                 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1100                                                  qp->qpn, &qp->rq.db);
1101                 if (qp->rq.db_index < 0)
1102                         return ret;
1103
1104                 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1105                                                  qp->qpn, &qp->sq.db);
1106                 if (qp->sq.db_index < 0)
1107                         mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1108         }
1109
1110         return ret;
1111 }
1112
1113 static void mthca_free_memfree(struct mthca_dev *dev,
1114                                struct mthca_qp *qp)
1115 {
1116         if (mthca_is_memfree(dev)) {
1117                 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1118                 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1119         }
1120 }
1121
1122 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1123                                  struct mthca_pd *pd,
1124                                  struct mthca_cq *send_cq,
1125                                  struct mthca_cq *recv_cq,
1126                                  enum ib_sig_type send_policy,
1127                                  struct mthca_qp *qp)
1128 {
1129         int ret;
1130         int i;
1131
1132         atomic_set(&qp->refcount, 1);
1133         init_waitqueue_head(&qp->wait);
1134         qp->state        = IB_QPS_RESET;
1135         qp->atomic_rd_en = 0;
1136         qp->resp_depth   = 0;
1137         qp->sq_policy    = send_policy;
1138         mthca_wq_init(&qp->sq);
1139         mthca_wq_init(&qp->rq);
1140
1141         ret = mthca_map_memfree(dev, qp);
1142         if (ret)
1143                 return ret;
1144
1145         ret = mthca_alloc_wqe_buf(dev, pd, qp);
1146         if (ret) {
1147                 mthca_unmap_memfree(dev, qp);
1148                 return ret;
1149         }
1150
1151         mthca_adjust_qp_caps(dev, pd, qp);
1152
1153         /*
1154          * If this is a userspace QP, we're done now.  The doorbells
1155          * will be allocated and buffers will be initialized in
1156          * userspace.
1157          */
1158         if (pd->ibpd.uobject)
1159                 return 0;
1160
1161         ret = mthca_alloc_memfree(dev, qp);
1162         if (ret) {
1163                 mthca_free_wqe_buf(dev, qp);
1164                 mthca_unmap_memfree(dev, qp);
1165                 return ret;
1166         }
1167
1168         if (mthca_is_memfree(dev)) {
1169                 struct mthca_next_seg *next;
1170                 struct mthca_data_seg *scatter;
1171                 int size = (sizeof (struct mthca_next_seg) +
1172                             qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1173
1174                 for (i = 0; i < qp->rq.max; ++i) {
1175                         next = get_recv_wqe(qp, i);
1176                         next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1177                                                    qp->rq.wqe_shift);
1178                         next->ee_nds = cpu_to_be32(size);
1179
1180                         for (scatter = (void *) (next + 1);
1181                              (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1182                              ++scatter)
1183                                 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1184                 }
1185
1186                 for (i = 0; i < qp->sq.max; ++i) {
1187                         next = get_send_wqe(qp, i);
1188                         next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1189                                                     qp->sq.wqe_shift) +
1190                                                    qp->send_wqe_offset);
1191                 }
1192         }
1193
1194         qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1195         qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1196
1197         return 0;
1198 }
1199
1200 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1201                              struct mthca_pd *pd, struct mthca_qp *qp)
1202 {
1203         int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1204
1205         /* Sanity check QP size before proceeding */
1206         if (cap->max_send_wr     > dev->limits.max_wqes ||
1207             cap->max_recv_wr     > dev->limits.max_wqes ||
1208             cap->max_send_sge    > dev->limits.max_sg   ||
1209             cap->max_recv_sge    > dev->limits.max_sg   ||
1210             cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1211                 return -EINVAL;
1212
1213         /*
1214          * For MLX transport we need 2 extra S/G entries:
1215          * one for the header and one for the checksum at the end
1216          */
1217         if (qp->transport == MLX && cap->max_recv_sge + 2 > dev->limits.max_sg)
1218                 return -EINVAL;
1219
1220         if (mthca_is_memfree(dev)) {
1221                 qp->rq.max = cap->max_recv_wr ?
1222                         roundup_pow_of_two(cap->max_recv_wr) : 0;
1223                 qp->sq.max = cap->max_send_wr ?
1224                         roundup_pow_of_two(cap->max_send_wr) : 0;
1225         } else {
1226                 qp->rq.max = cap->max_recv_wr;
1227                 qp->sq.max = cap->max_send_wr;
1228         }
1229
1230         qp->rq.max_gs = cap->max_recv_sge;
1231         qp->sq.max_gs = max_t(int, cap->max_send_sge,
1232                               ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1233                                     MTHCA_INLINE_CHUNK_SIZE) /
1234                               sizeof (struct mthca_data_seg));
1235
1236         return 0;
1237 }
1238
1239 int mthca_alloc_qp(struct mthca_dev *dev,
1240                    struct mthca_pd *pd,
1241                    struct mthca_cq *send_cq,
1242                    struct mthca_cq *recv_cq,
1243                    enum ib_qp_type type,
1244                    enum ib_sig_type send_policy,
1245                    struct ib_qp_cap *cap,
1246                    struct mthca_qp *qp)
1247 {
1248         int err;
1249
1250         err = mthca_set_qp_size(dev, cap, pd, qp);
1251         if (err)
1252                 return err;
1253
1254         switch (type) {
1255         case IB_QPT_RC: qp->transport = RC; break;
1256         case IB_QPT_UC: qp->transport = UC; break;
1257         case IB_QPT_UD: qp->transport = UD; break;
1258         default: return -EINVAL;
1259         }
1260
1261         qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1262         if (qp->qpn == -1)
1263                 return -ENOMEM;
1264
1265         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1266                                     send_policy, qp);
1267         if (err) {
1268                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1269                 return err;
1270         }
1271
1272         spin_lock_irq(&dev->qp_table.lock);
1273         mthca_array_set(&dev->qp_table.qp,
1274                         qp->qpn & (dev->limits.num_qps - 1), qp);
1275         spin_unlock_irq(&dev->qp_table.lock);
1276
1277         return 0;
1278 }
1279
1280 int mthca_alloc_sqp(struct mthca_dev *dev,
1281                     struct mthca_pd *pd,
1282                     struct mthca_cq *send_cq,
1283                     struct mthca_cq *recv_cq,
1284                     enum ib_sig_type send_policy,
1285                     struct ib_qp_cap *cap,
1286                     int qpn,
1287                     int port,
1288                     struct mthca_sqp *sqp)
1289 {
1290         u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1291         int err;
1292
1293         err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1294         if (err)
1295                 return err;
1296
1297         sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1298         sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1299                                              &sqp->header_dma, GFP_KERNEL);
1300         if (!sqp->header_buf)
1301                 return -ENOMEM;
1302
1303         spin_lock_irq(&dev->qp_table.lock);
1304         if (mthca_array_get(&dev->qp_table.qp, mqpn))
1305                 err = -EBUSY;
1306         else
1307                 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1308         spin_unlock_irq(&dev->qp_table.lock);
1309
1310         if (err)
1311                 goto err_out;
1312
1313         sqp->port = port;
1314         sqp->qp.qpn       = mqpn;
1315         sqp->qp.transport = MLX;
1316
1317         err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1318                                     send_policy, &sqp->qp);
1319         if (err)
1320                 goto err_out_free;
1321
1322         atomic_inc(&pd->sqp_count);
1323
1324         return 0;
1325
1326  err_out_free:
1327         /*
1328          * Lock CQs here, so that CQ polling code can do QP lookup
1329          * without taking a lock.
1330          */
1331         spin_lock_irq(&send_cq->lock);
1332         if (send_cq != recv_cq)
1333                 spin_lock(&recv_cq->lock);
1334
1335         spin_lock(&dev->qp_table.lock);
1336         mthca_array_clear(&dev->qp_table.qp, mqpn);
1337         spin_unlock(&dev->qp_table.lock);
1338
1339         if (send_cq != recv_cq)
1340                 spin_unlock(&recv_cq->lock);
1341         spin_unlock_irq(&send_cq->lock);
1342
1343  err_out:
1344         dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1345                           sqp->header_buf, sqp->header_dma);
1346
1347         return err;
1348 }
1349
1350 void mthca_free_qp(struct mthca_dev *dev,
1351                    struct mthca_qp *qp)
1352 {
1353         u8 status;
1354         struct mthca_cq *send_cq;
1355         struct mthca_cq *recv_cq;
1356
1357         send_cq = to_mcq(qp->ibqp.send_cq);
1358         recv_cq = to_mcq(qp->ibqp.recv_cq);
1359
1360         /*
1361          * Lock CQs here, so that CQ polling code can do QP lookup
1362          * without taking a lock.
1363          */
1364         spin_lock_irq(&send_cq->lock);
1365         if (send_cq != recv_cq)
1366                 spin_lock(&recv_cq->lock);
1367
1368         spin_lock(&dev->qp_table.lock);
1369         mthca_array_clear(&dev->qp_table.qp,
1370                           qp->qpn & (dev->limits.num_qps - 1));
1371         spin_unlock(&dev->qp_table.lock);
1372
1373         if (send_cq != recv_cq)
1374                 spin_unlock(&recv_cq->lock);
1375         spin_unlock_irq(&send_cq->lock);
1376
1377         atomic_dec(&qp->refcount);
1378         wait_event(qp->wait, !atomic_read(&qp->refcount));
1379
1380         if (qp->state != IB_QPS_RESET)
1381                 mthca_MODIFY_QP(dev, MTHCA_TRANS_ANY2RST, qp->qpn, 0, NULL, 0, &status);
1382
1383         /*
1384          * If this is a userspace QP, the buffers, MR, CQs and so on
1385          * will be cleaned up in userspace, so all we have to do is
1386          * unref the mem-free tables and free the QPN in our table.
1387          */
1388         if (!qp->ibqp.uobject) {
1389                 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq)->cqn, qp->qpn,
1390                                qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1391                 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
1392                         mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq)->cqn, qp->qpn,
1393                                        qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1394
1395                 mthca_free_memfree(dev, qp);
1396                 mthca_free_wqe_buf(dev, qp);
1397         }
1398
1399         mthca_unmap_memfree(dev, qp);
1400
1401         if (is_sqp(dev, qp)) {
1402                 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1403                 dma_free_coherent(&dev->pdev->dev,
1404                                   to_msqp(qp)->header_buf_size,
1405                                   to_msqp(qp)->header_buf,
1406                                   to_msqp(qp)->header_dma);
1407         } else
1408                 mthca_free(&dev->qp_table.alloc, qp->qpn);
1409 }
1410
1411 /* Create UD header for an MLX send and build a data segment for it */
1412 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1413                             int ind, struct ib_send_wr *wr,
1414                             struct mthca_mlx_seg *mlx,
1415                             struct mthca_data_seg *data)
1416 {
1417         int header_size;
1418         int err;
1419         u16 pkey;
1420
1421         ib_ud_header_init(256, /* assume a MAD */
1422                           sqp->ud_header.grh_present,
1423                           &sqp->ud_header);
1424
1425         err = mthca_read_ah(dev, to_mah(wr->wr.ud.ah), &sqp->ud_header);
1426         if (err)
1427                 return err;
1428         mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1429         mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1430                                   (sqp->ud_header.lrh.destination_lid ==
1431                                    IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1432                                   (sqp->ud_header.lrh.service_level << 8));
1433         mlx->rlid = sqp->ud_header.lrh.destination_lid;
1434         mlx->vcrc = 0;
1435
1436         switch (wr->opcode) {
1437         case IB_WR_SEND:
1438                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1439                 sqp->ud_header.immediate_present = 0;
1440                 break;
1441         case IB_WR_SEND_WITH_IMM:
1442                 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1443                 sqp->ud_header.immediate_present = 1;
1444                 sqp->ud_header.immediate_data = wr->imm_data;
1445                 break;
1446         default:
1447                 return -EINVAL;
1448         }
1449
1450         sqp->ud_header.lrh.virtual_lane    = !sqp->qp.ibqp.qp_num ? 15 : 0;
1451         if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1452                 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1453         sqp->ud_header.bth.solicited_event = !!(wr->send_flags & IB_SEND_SOLICITED);
1454         if (!sqp->qp.ibqp.qp_num)
1455                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1456                                    sqp->pkey_index, &pkey);
1457         else
1458                 ib_get_cached_pkey(&dev->ib_dev, sqp->port,
1459                                    wr->wr.ud.pkey_index, &pkey);
1460         sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1461         sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->wr.ud.remote_qpn);
1462         sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1463         sqp->ud_header.deth.qkey = cpu_to_be32(wr->wr.ud.remote_qkey & 0x80000000 ?
1464                                                sqp->qkey : wr->wr.ud.remote_qkey);
1465         sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1466
1467         header_size = ib_ud_header_pack(&sqp->ud_header,
1468                                         sqp->header_buf +
1469                                         ind * MTHCA_UD_HEADER_SIZE);
1470
1471         data->byte_count = cpu_to_be32(header_size);
1472         data->lkey       = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1473         data->addr       = cpu_to_be64(sqp->header_dma +
1474                                        ind * MTHCA_UD_HEADER_SIZE);
1475
1476         return 0;
1477 }
1478
1479 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1480                                     struct ib_cq *ib_cq)
1481 {
1482         unsigned cur;
1483         struct mthca_cq *cq;
1484
1485         cur = wq->head - wq->tail;
1486         if (likely(cur + nreq < wq->max))
1487                 return 0;
1488
1489         cq = to_mcq(ib_cq);
1490         spin_lock(&cq->lock);
1491         cur = wq->head - wq->tail;
1492         spin_unlock(&cq->lock);
1493
1494         return cur + nreq >= wq->max;
1495 }
1496
1497 int mthca_tavor_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1498                           struct ib_send_wr **bad_wr)
1499 {
1500         struct mthca_dev *dev = to_mdev(ibqp->device);
1501         struct mthca_qp *qp = to_mqp(ibqp);
1502         void *wqe;
1503         void *prev_wqe;
1504         unsigned long flags;
1505         int err = 0;
1506         int nreq;
1507         int i;
1508         int size;
1509         int size0 = 0;
1510         u32 f0 = 0;
1511         int ind;
1512         u8 op0 = 0;
1513
1514         spin_lock_irqsave(&qp->sq.lock, flags);
1515
1516         /* XXX check that state is OK to post send */
1517
1518         ind = qp->sq.next_ind;
1519
1520         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1521                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1522                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1523                                         " %d max, %d nreq)\n", qp->qpn,
1524                                         qp->sq.head, qp->sq.tail,
1525                                         qp->sq.max, nreq);
1526                         err = -ENOMEM;
1527                         *bad_wr = wr;
1528                         goto out;
1529                 }
1530
1531                 wqe = get_send_wqe(qp, ind);
1532                 prev_wqe = qp->sq.last;
1533                 qp->sq.last = wqe;
1534
1535                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1536                 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1537                 ((struct mthca_next_seg *) wqe)->flags =
1538                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1539                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1540                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1541                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1542                         cpu_to_be32(1);
1543                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1544                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1545                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1546
1547                 wqe += sizeof (struct mthca_next_seg);
1548                 size = sizeof (struct mthca_next_seg) / 16;
1549
1550                 switch (qp->transport) {
1551                 case RC:
1552                         switch (wr->opcode) {
1553                         case IB_WR_ATOMIC_CMP_AND_SWP:
1554                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1555                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1556                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1557                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1558                                         cpu_to_be32(wr->wr.atomic.rkey);
1559                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1560
1561                                 wqe += sizeof (struct mthca_raddr_seg);
1562
1563                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1564                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1565                                                 cpu_to_be64(wr->wr.atomic.swap);
1566                                         ((struct mthca_atomic_seg *) wqe)->compare =
1567                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1568                                 } else {
1569                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1570                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1571                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1572                                 }
1573
1574                                 wqe += sizeof (struct mthca_atomic_seg);
1575                                 size += (sizeof (struct mthca_raddr_seg) +
1576                                          sizeof (struct mthca_atomic_seg)) / 16;
1577                                 break;
1578
1579                         case IB_WR_RDMA_WRITE:
1580                         case IB_WR_RDMA_WRITE_WITH_IMM:
1581                         case IB_WR_RDMA_READ:
1582                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1583                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1584                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1585                                         cpu_to_be32(wr->wr.rdma.rkey);
1586                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1587                                 wqe += sizeof (struct mthca_raddr_seg);
1588                                 size += sizeof (struct mthca_raddr_seg) / 16;
1589                                 break;
1590
1591                         default:
1592                                 /* No extra segments required for sends */
1593                                 break;
1594                         }
1595
1596                         break;
1597
1598                 case UC:
1599                         switch (wr->opcode) {
1600                         case IB_WR_RDMA_WRITE:
1601                         case IB_WR_RDMA_WRITE_WITH_IMM:
1602                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1603                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1604                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1605                                         cpu_to_be32(wr->wr.rdma.rkey);
1606                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1607                                 wqe += sizeof (struct mthca_raddr_seg);
1608                                 size += sizeof (struct mthca_raddr_seg) / 16;
1609                                 break;
1610
1611                         default:
1612                                 /* No extra segments required for sends */
1613                                 break;
1614                         }
1615
1616                         break;
1617
1618                 case UD:
1619                         ((struct mthca_tavor_ud_seg *) wqe)->lkey =
1620                                 cpu_to_be32(to_mah(wr->wr.ud.ah)->key);
1621                         ((struct mthca_tavor_ud_seg *) wqe)->av_addr =
1622                                 cpu_to_be64(to_mah(wr->wr.ud.ah)->avdma);
1623                         ((struct mthca_tavor_ud_seg *) wqe)->dqpn =
1624                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1625                         ((struct mthca_tavor_ud_seg *) wqe)->qkey =
1626                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1627
1628                         wqe += sizeof (struct mthca_tavor_ud_seg);
1629                         size += sizeof (struct mthca_tavor_ud_seg) / 16;
1630                         break;
1631
1632                 case MLX:
1633                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1634                                                wqe - sizeof (struct mthca_next_seg),
1635                                                wqe);
1636                         if (err) {
1637                                 *bad_wr = wr;
1638                                 goto out;
1639                         }
1640                         wqe += sizeof (struct mthca_data_seg);
1641                         size += sizeof (struct mthca_data_seg) / 16;
1642                         break;
1643                 }
1644
1645                 if (wr->num_sge > qp->sq.max_gs) {
1646                         mthca_err(dev, "too many gathers\n");
1647                         err = -EINVAL;
1648                         *bad_wr = wr;
1649                         goto out;
1650                 }
1651
1652                 for (i = 0; i < wr->num_sge; ++i) {
1653                         ((struct mthca_data_seg *) wqe)->byte_count =
1654                                 cpu_to_be32(wr->sg_list[i].length);
1655                         ((struct mthca_data_seg *) wqe)->lkey =
1656                                 cpu_to_be32(wr->sg_list[i].lkey);
1657                         ((struct mthca_data_seg *) wqe)->addr =
1658                                 cpu_to_be64(wr->sg_list[i].addr);
1659                         wqe += sizeof (struct mthca_data_seg);
1660                         size += sizeof (struct mthca_data_seg) / 16;
1661                 }
1662
1663                 /* Add one more inline data segment for ICRC */
1664                 if (qp->transport == MLX) {
1665                         ((struct mthca_data_seg *) wqe)->byte_count =
1666                                 cpu_to_be32((1 << 31) | 4);
1667                         ((u32 *) wqe)[1] = 0;
1668                         wqe += sizeof (struct mthca_data_seg);
1669                         size += sizeof (struct mthca_data_seg) / 16;
1670                 }
1671
1672                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1673
1674                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1675                         mthca_err(dev, "opcode invalid\n");
1676                         err = -EINVAL;
1677                         *bad_wr = wr;
1678                         goto out;
1679                 }
1680
1681                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1682                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
1683                                      qp->send_wqe_offset) |
1684                                     mthca_opcode[wr->opcode]);
1685                 wmb();
1686                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1687                         cpu_to_be32((size0 ? 0 : MTHCA_NEXT_DBD) | size);
1688
1689                 if (!size0) {
1690                         size0 = size;
1691                         op0   = mthca_opcode[wr->opcode];
1692                 }
1693
1694                 ++ind;
1695                 if (unlikely(ind >= qp->sq.max))
1696                         ind -= qp->sq.max;
1697         }
1698
1699 out:
1700         if (likely(nreq)) {
1701                 __be32 doorbell[2];
1702
1703                 doorbell[0] = cpu_to_be32(((qp->sq.next_ind << qp->sq.wqe_shift) +
1704                                            qp->send_wqe_offset) | f0 | op0);
1705                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1706
1707                 wmb();
1708
1709                 mthca_write64(doorbell,
1710                               dev->kar + MTHCA_SEND_DOORBELL,
1711                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1712         }
1713
1714         qp->sq.next_ind = ind;
1715         qp->sq.head    += nreq;
1716
1717         spin_unlock_irqrestore(&qp->sq.lock, flags);
1718         return err;
1719 }
1720
1721 int mthca_tavor_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
1722                              struct ib_recv_wr **bad_wr)
1723 {
1724         struct mthca_dev *dev = to_mdev(ibqp->device);
1725         struct mthca_qp *qp = to_mqp(ibqp);
1726         __be32 doorbell[2];
1727         unsigned long flags;
1728         int err = 0;
1729         int nreq;
1730         int i;
1731         int size;
1732         int size0 = 0;
1733         int ind;
1734         void *wqe;
1735         void *prev_wqe;
1736
1737         spin_lock_irqsave(&qp->rq.lock, flags);
1738
1739         /* XXX check that state is OK to post receive */
1740
1741         ind = qp->rq.next_ind;
1742
1743         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1744                 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1745                         nreq = 0;
1746
1747                         doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1748                         doorbell[1] = cpu_to_be32(qp->qpn << 8);
1749
1750                         wmb();
1751
1752                         mthca_write64(doorbell,
1753                                       dev->kar + MTHCA_RECEIVE_DOORBELL,
1754                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1755
1756                         qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1757                         size0 = 0;
1758                 }
1759
1760                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1761                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1762                                         " %d max, %d nreq)\n", qp->qpn,
1763                                         qp->rq.head, qp->rq.tail,
1764                                         qp->rq.max, nreq);
1765                         err = -ENOMEM;
1766                         *bad_wr = wr;
1767                         goto out;
1768                 }
1769
1770                 wqe = get_recv_wqe(qp, ind);
1771                 prev_wqe = qp->rq.last;
1772                 qp->rq.last = wqe;
1773
1774                 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1775                 ((struct mthca_next_seg *) wqe)->ee_nds =
1776                         cpu_to_be32(MTHCA_NEXT_DBD);
1777                 ((struct mthca_next_seg *) wqe)->flags = 0;
1778
1779                 wqe += sizeof (struct mthca_next_seg);
1780                 size = sizeof (struct mthca_next_seg) / 16;
1781
1782                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1783                         err = -EINVAL;
1784                         *bad_wr = wr;
1785                         goto out;
1786                 }
1787
1788                 for (i = 0; i < wr->num_sge; ++i) {
1789                         ((struct mthca_data_seg *) wqe)->byte_count =
1790                                 cpu_to_be32(wr->sg_list[i].length);
1791                         ((struct mthca_data_seg *) wqe)->lkey =
1792                                 cpu_to_be32(wr->sg_list[i].lkey);
1793                         ((struct mthca_data_seg *) wqe)->addr =
1794                                 cpu_to_be64(wr->sg_list[i].addr);
1795                         wqe += sizeof (struct mthca_data_seg);
1796                         size += sizeof (struct mthca_data_seg) / 16;
1797                 }
1798
1799                 qp->wrid[ind] = wr->wr_id;
1800
1801                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1802                         cpu_to_be32((ind << qp->rq.wqe_shift) | 1);
1803                 wmb();
1804                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1805                         cpu_to_be32(MTHCA_NEXT_DBD | size);
1806
1807                 if (!size0)
1808                         size0 = size;
1809
1810                 ++ind;
1811                 if (unlikely(ind >= qp->rq.max))
1812                         ind -= qp->rq.max;
1813         }
1814
1815 out:
1816         if (likely(nreq)) {
1817                 doorbell[0] = cpu_to_be32((qp->rq.next_ind << qp->rq.wqe_shift) | size0);
1818                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | nreq);
1819
1820                 wmb();
1821
1822                 mthca_write64(doorbell,
1823                               dev->kar + MTHCA_RECEIVE_DOORBELL,
1824                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1825         }
1826
1827         qp->rq.next_ind = ind;
1828         qp->rq.head    += nreq;
1829
1830         spin_unlock_irqrestore(&qp->rq.lock, flags);
1831         return err;
1832 }
1833
1834 int mthca_arbel_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
1835                           struct ib_send_wr **bad_wr)
1836 {
1837         struct mthca_dev *dev = to_mdev(ibqp->device);
1838         struct mthca_qp *qp = to_mqp(ibqp);
1839         __be32 doorbell[2];
1840         void *wqe;
1841         void *prev_wqe;
1842         unsigned long flags;
1843         int err = 0;
1844         int nreq;
1845         int i;
1846         int size;
1847         int size0 = 0;
1848         u32 f0 = 0;
1849         int ind;
1850         u8 op0 = 0;
1851
1852         spin_lock_irqsave(&qp->sq.lock, flags);
1853
1854         /* XXX check that state is OK to post send */
1855
1856         ind = qp->sq.head & (qp->sq.max - 1);
1857
1858         for (nreq = 0; wr; ++nreq, wr = wr->next) {
1859                 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1860                         nreq = 0;
1861
1862                         doorbell[0] = cpu_to_be32((MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1863                                                   ((qp->sq.head & 0xffff) << 8) |
1864                                                   f0 | op0);
1865                         doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
1866
1867                         qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1868                         size0 = 0;
1869
1870                         /*
1871                          * Make sure that descriptors are written before
1872                          * doorbell record.
1873                          */
1874                         wmb();
1875                         *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1876
1877                         /*
1878                          * Make sure doorbell record is written before we
1879                          * write MMIO send doorbell.
1880                          */
1881                         wmb();
1882                         mthca_write64(doorbell,
1883                                       dev->kar + MTHCA_SEND_DOORBELL,
1884                                       MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1885                 }
1886
1887                 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1888                         mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1889                                         " %d max, %d nreq)\n", qp->qpn,
1890                                         qp->sq.head, qp->sq.tail,
1891                                         qp->sq.max, nreq);
1892                         err = -ENOMEM;
1893                         *bad_wr = wr;
1894                         goto out;
1895                 }
1896
1897                 wqe = get_send_wqe(qp, ind);
1898                 prev_wqe = qp->sq.last;
1899                 qp->sq.last = wqe;
1900
1901                 ((struct mthca_next_seg *) wqe)->flags =
1902                         ((wr->send_flags & IB_SEND_SIGNALED) ?
1903                          cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1904                         ((wr->send_flags & IB_SEND_SOLICITED) ?
1905                          cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0)   |
1906                         cpu_to_be32(1);
1907                 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1908                     wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1909                         ((struct mthca_next_seg *) wqe)->imm = wr->imm_data;
1910
1911                 wqe += sizeof (struct mthca_next_seg);
1912                 size = sizeof (struct mthca_next_seg) / 16;
1913
1914                 switch (qp->transport) {
1915                 case RC:
1916                         switch (wr->opcode) {
1917                         case IB_WR_ATOMIC_CMP_AND_SWP:
1918                         case IB_WR_ATOMIC_FETCH_AND_ADD:
1919                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1920                                         cpu_to_be64(wr->wr.atomic.remote_addr);
1921                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1922                                         cpu_to_be32(wr->wr.atomic.rkey);
1923                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1924
1925                                 wqe += sizeof (struct mthca_raddr_seg);
1926
1927                                 if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1928                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1929                                                 cpu_to_be64(wr->wr.atomic.swap);
1930                                         ((struct mthca_atomic_seg *) wqe)->compare =
1931                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1932                                 } else {
1933                                         ((struct mthca_atomic_seg *) wqe)->swap_add =
1934                                                 cpu_to_be64(wr->wr.atomic.compare_add);
1935                                         ((struct mthca_atomic_seg *) wqe)->compare = 0;
1936                                 }
1937
1938                                 wqe += sizeof (struct mthca_atomic_seg);
1939                                 size += (sizeof (struct mthca_raddr_seg) +
1940                                          sizeof (struct mthca_atomic_seg)) / 16;
1941                                 break;
1942
1943                         case IB_WR_RDMA_READ:
1944                         case IB_WR_RDMA_WRITE:
1945                         case IB_WR_RDMA_WRITE_WITH_IMM:
1946                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1947                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1948                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1949                                         cpu_to_be32(wr->wr.rdma.rkey);
1950                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1951                                 wqe += sizeof (struct mthca_raddr_seg);
1952                                 size += sizeof (struct mthca_raddr_seg) / 16;
1953                                 break;
1954
1955                         default:
1956                                 /* No extra segments required for sends */
1957                                 break;
1958                         }
1959
1960                         break;
1961
1962                 case UC:
1963                         switch (wr->opcode) {
1964                         case IB_WR_RDMA_WRITE:
1965                         case IB_WR_RDMA_WRITE_WITH_IMM:
1966                                 ((struct mthca_raddr_seg *) wqe)->raddr =
1967                                         cpu_to_be64(wr->wr.rdma.remote_addr);
1968                                 ((struct mthca_raddr_seg *) wqe)->rkey =
1969                                         cpu_to_be32(wr->wr.rdma.rkey);
1970                                 ((struct mthca_raddr_seg *) wqe)->reserved = 0;
1971                                 wqe += sizeof (struct mthca_raddr_seg);
1972                                 size += sizeof (struct mthca_raddr_seg) / 16;
1973                                 break;
1974
1975                         default:
1976                                 /* No extra segments required for sends */
1977                                 break;
1978                         }
1979
1980                         break;
1981
1982                 case UD:
1983                         memcpy(((struct mthca_arbel_ud_seg *) wqe)->av,
1984                                to_mah(wr->wr.ud.ah)->av, MTHCA_AV_SIZE);
1985                         ((struct mthca_arbel_ud_seg *) wqe)->dqpn =
1986                                 cpu_to_be32(wr->wr.ud.remote_qpn);
1987                         ((struct mthca_arbel_ud_seg *) wqe)->qkey =
1988                                 cpu_to_be32(wr->wr.ud.remote_qkey);
1989
1990                         wqe += sizeof (struct mthca_arbel_ud_seg);
1991                         size += sizeof (struct mthca_arbel_ud_seg) / 16;
1992                         break;
1993
1994                 case MLX:
1995                         err = build_mlx_header(dev, to_msqp(qp), ind, wr,
1996                                                wqe - sizeof (struct mthca_next_seg),
1997                                                wqe);
1998                         if (err) {
1999                                 *bad_wr = wr;
2000                                 goto out;
2001                         }
2002                         wqe += sizeof (struct mthca_data_seg);
2003                         size += sizeof (struct mthca_data_seg) / 16;
2004                         break;
2005                 }
2006
2007                 if (wr->num_sge > qp->sq.max_gs) {
2008                         mthca_err(dev, "too many gathers\n");
2009                         err = -EINVAL;
2010                         *bad_wr = wr;
2011                         goto out;
2012                 }
2013
2014                 for (i = 0; i < wr->num_sge; ++i) {
2015                         ((struct mthca_data_seg *) wqe)->byte_count =
2016                                 cpu_to_be32(wr->sg_list[i].length);
2017                         ((struct mthca_data_seg *) wqe)->lkey =
2018                                 cpu_to_be32(wr->sg_list[i].lkey);
2019                         ((struct mthca_data_seg *) wqe)->addr =
2020                                 cpu_to_be64(wr->sg_list[i].addr);
2021                         wqe += sizeof (struct mthca_data_seg);
2022                         size += sizeof (struct mthca_data_seg) / 16;
2023                 }
2024
2025                 /* Add one more inline data segment for ICRC */
2026                 if (qp->transport == MLX) {
2027                         ((struct mthca_data_seg *) wqe)->byte_count =
2028                                 cpu_to_be32((1 << 31) | 4);
2029                         ((u32 *) wqe)[1] = 0;
2030                         wqe += sizeof (struct mthca_data_seg);
2031                         size += sizeof (struct mthca_data_seg) / 16;
2032                 }
2033
2034                 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2035
2036                 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2037                         mthca_err(dev, "opcode invalid\n");
2038                         err = -EINVAL;
2039                         *bad_wr = wr;
2040                         goto out;
2041                 }
2042
2043                 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2044                         cpu_to_be32(((ind << qp->sq.wqe_shift) +
2045                                      qp->send_wqe_offset) |
2046                                     mthca_opcode[wr->opcode]);
2047                 wmb();
2048                 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2049                         cpu_to_be32(MTHCA_NEXT_DBD | size);
2050
2051                 if (!size0) {
2052                         size0 = size;
2053                         op0   = mthca_opcode[wr->opcode];
2054                 }
2055
2056                 ++ind;
2057                 if (unlikely(ind >= qp->sq.max))
2058                         ind -= qp->sq.max;
2059         }
2060
2061 out:
2062         if (likely(nreq)) {
2063                 doorbell[0] = cpu_to_be32((nreq << 24)                  |
2064                                           ((qp->sq.head & 0xffff) << 8) |
2065                                           f0 | op0);
2066                 doorbell[1] = cpu_to_be32((qp->qpn << 8) | size0);
2067
2068                 qp->sq.head += nreq;
2069
2070                 /*
2071                  * Make sure that descriptors are written before
2072                  * doorbell record.
2073                  */
2074                 wmb();
2075                 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2076
2077                 /*
2078                  * Make sure doorbell record is written before we
2079                  * write MMIO send doorbell.
2080                  */
2081                 wmb();
2082                 mthca_write64(doorbell,
2083                               dev->kar + MTHCA_SEND_DOORBELL,
2084                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2085         }
2086
2087         spin_unlock_irqrestore(&qp->sq.lock, flags);
2088         return err;
2089 }
2090
2091 int mthca_arbel_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
2092                              struct ib_recv_wr **bad_wr)
2093 {
2094         struct mthca_dev *dev = to_mdev(ibqp->device);
2095         struct mthca_qp *qp = to_mqp(ibqp);
2096         unsigned long flags;
2097         int err = 0;
2098         int nreq;
2099         int ind;
2100         int i;
2101         void *wqe;
2102
2103         spin_lock_irqsave(&qp->rq.lock, flags);
2104
2105         /* XXX check that state is OK to post receive */
2106
2107         ind = qp->rq.head & (qp->rq.max - 1);
2108
2109         for (nreq = 0; wr; ++nreq, wr = wr->next) {
2110                 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2111                         mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2112                                         " %d max, %d nreq)\n", qp->qpn,
2113                                         qp->rq.head, qp->rq.tail,
2114                                         qp->rq.max, nreq);
2115                         err = -ENOMEM;
2116                         *bad_wr = wr;
2117                         goto out;
2118                 }
2119
2120                 wqe = get_recv_wqe(qp, ind);
2121
2122                 ((struct mthca_next_seg *) wqe)->flags = 0;
2123
2124                 wqe += sizeof (struct mthca_next_seg);
2125
2126                 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2127                         err = -EINVAL;
2128                         *bad_wr = wr;
2129                         goto out;
2130                 }
2131
2132                 for (i = 0; i < wr->num_sge; ++i) {
2133                         ((struct mthca_data_seg *) wqe)->byte_count =
2134                                 cpu_to_be32(wr->sg_list[i].length);
2135                         ((struct mthca_data_seg *) wqe)->lkey =
2136                                 cpu_to_be32(wr->sg_list[i].lkey);
2137                         ((struct mthca_data_seg *) wqe)->addr =
2138                                 cpu_to_be64(wr->sg_list[i].addr);
2139                         wqe += sizeof (struct mthca_data_seg);
2140                 }
2141
2142                 if (i < qp->rq.max_gs) {
2143                         ((struct mthca_data_seg *) wqe)->byte_count = 0;
2144                         ((struct mthca_data_seg *) wqe)->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
2145                         ((struct mthca_data_seg *) wqe)->addr = 0;
2146                 }
2147
2148                 qp->wrid[ind] = wr->wr_id;
2149
2150                 ++ind;
2151                 if (unlikely(ind >= qp->rq.max))
2152                         ind -= qp->rq.max;
2153         }
2154 out:
2155         if (likely(nreq)) {
2156                 qp->rq.head += nreq;
2157
2158                 /*
2159                  * Make sure that descriptors are written before
2160                  * doorbell record.
2161                  */
2162                 wmb();
2163                 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2164         }
2165
2166         spin_unlock_irqrestore(&qp->rq.lock, flags);
2167         return err;
2168 }
2169
2170 int mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2171                        int index, int *dbd, __be32 *new_wqe)
2172 {
2173         struct mthca_next_seg *next;
2174
2175         /*
2176          * For SRQs, all WQEs generate a CQE, so we're always at the
2177          * end of the doorbell chain.
2178          */
2179         if (qp->ibqp.srq) {
2180                 *new_wqe = 0;
2181                 return 0;
2182         }
2183
2184         if (is_send)
2185                 next = get_send_wqe(qp, index);
2186         else
2187                 next = get_recv_wqe(qp, index);
2188
2189         *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2190         if (next->ee_nds & cpu_to_be32(0x3f))
2191                 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2192                         (next->ee_nds & cpu_to_be32(0x3f));
2193         else
2194                 *new_wqe = 0;
2195
2196         return 0;
2197 }
2198
2199 int __devinit mthca_init_qp_table(struct mthca_dev *dev)
2200 {
2201         int err;
2202         u8 status;
2203         int i;
2204
2205         spin_lock_init(&dev->qp_table.lock);
2206
2207         /*
2208          * We reserve 2 extra QPs per port for the special QPs.  The
2209          * special QP for port 1 has to be even, so round up.
2210          */
2211         dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2212         err = mthca_alloc_init(&dev->qp_table.alloc,
2213                                dev->limits.num_qps,
2214                                (1 << 24) - 1,
2215                                dev->qp_table.sqp_start +
2216                                MTHCA_MAX_PORTS * 2);
2217         if (err)
2218                 return err;
2219
2220         err = mthca_array_init(&dev->qp_table.qp,
2221                                dev->limits.num_qps);
2222         if (err) {
2223                 mthca_alloc_cleanup(&dev->qp_table.alloc);
2224                 return err;
2225         }
2226
2227         for (i = 0; i < 2; ++i) {
2228                 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2229                                             dev->qp_table.sqp_start + i * 2,
2230                                             &status);
2231                 if (err)
2232                         goto err_out;
2233                 if (status) {
2234                         mthca_warn(dev, "CONF_SPECIAL_QP returned "
2235                                    "status %02x, aborting.\n",
2236                                    status);
2237                         err = -EINVAL;
2238                         goto err_out;
2239                 }
2240         }
2241         return 0;
2242
2243  err_out:
2244         for (i = 0; i < 2; ++i)
2245                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2246
2247         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2248         mthca_alloc_cleanup(&dev->qp_table.alloc);
2249
2250         return err;
2251 }
2252
2253 void __devexit mthca_cleanup_qp_table(struct mthca_dev *dev)
2254 {
2255         int i;
2256         u8 status;
2257
2258         for (i = 0; i < 2; ++i)
2259                 mthca_CONF_SPECIAL_QP(dev, i, 0, &status);
2260
2261         mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2262         mthca_alloc_cleanup(&dev->qp_table.alloc);
2263 }