2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/pci.h>
35 #include <linux/delay.h>
37 #include "ipath_kernel.h"
38 #include "ipath_verbs.h"
39 #include "ipath_common.h"
42 * clear (write) a pio buffer, to clear a parity error. This routine
43 * should only be called when in freeze mode, and the buffer should be
44 * canceled afterwards.
46 static void ipath_clrpiobuf(struct ipath_devdata *dd, u32 pnum)
49 u32 dwcnt; /* dword count to write */
50 if (pnum < dd->ipath_piobcnt2k) {
51 pbuf = (u32 __iomem *) (dd->ipath_pio2kbase + pnum *
53 dwcnt = dd->ipath_piosize2k >> 2;
56 pbuf = (u32 __iomem *) (dd->ipath_pio4kbase +
57 (pnum - dd->ipath_piobcnt2k) * dd->ipath_4kalign);
58 dwcnt = dd->ipath_piosize4k >> 2;
60 dev_info(&dd->pcidev->dev,
61 "Rewrite PIO buffer %u, to recover from parity error\n",
64 /* no flush required, since already in freeze */
65 writel(dwcnt + 1, pbuf);
71 * Called when we might have an error that is specific to a particular
72 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
73 * If rewrite is true, and bits are set in the sendbufferror registers,
74 * we'll write to the buffer, for error recovery on parity errors.
76 void ipath_disarm_senderrbufs(struct ipath_devdata *dd, int rewrite)
79 unsigned long sbuf[4];
81 * it's possible that sendbuffererror could have bits set; might
82 * have already done this as a result of hardware error handling
84 piobcnt = dd->ipath_piobcnt2k + dd->ipath_piobcnt4k;
85 /* read these before writing errorclear */
86 sbuf[0] = ipath_read_kreg64(
87 dd, dd->ipath_kregs->kr_sendbuffererror);
88 sbuf[1] = ipath_read_kreg64(
89 dd, dd->ipath_kregs->kr_sendbuffererror + 1);
91 sbuf[2] = ipath_read_kreg64(
92 dd, dd->ipath_kregs->kr_sendbuffererror + 2);
94 sbuf[3] = ipath_read_kreg64(
95 dd, dd->ipath_kregs->kr_sendbuffererror + 3);
99 if (sbuf[0] || sbuf[1] || (piobcnt > 128 && (sbuf[2] || sbuf[3]))) {
101 if (ipath_debug & (__IPATH_PKTDBG|__IPATH_DBG) &&
102 dd->ipath_lastcancel > jiffies) {
103 __IPATH_DBG_WHICH(__IPATH_PKTDBG|__IPATH_DBG,
104 "SendbufErrs %lx %lx", sbuf[0],
106 if (ipath_debug & __IPATH_PKTDBG && piobcnt > 128)
107 printk(" %lx %lx ", sbuf[2], sbuf[3]);
111 for (i = 0; i < piobcnt; i++)
112 if (test_bit(i, sbuf)) {
114 ipath_clrpiobuf(dd, i);
115 ipath_disarm_piobufs(dd, i, 1);
117 /* ignore armlaunch errs for a bit */
118 dd->ipath_lastcancel = jiffies+3;
123 /* These are all rcv-related errors which we want to count for stats */
124 #define E_SUM_PKTERRS \
125 (INFINIPATH_E_RHDRLEN | INFINIPATH_E_RBADTID | \
126 INFINIPATH_E_RBADVERSION | INFINIPATH_E_RHDR | \
127 INFINIPATH_E_RLONGPKTLEN | INFINIPATH_E_RSHORTPKTLEN | \
128 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RMINPKTLEN | \
129 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RUNSUPVL | \
130 INFINIPATH_E_RUNEXPCHAR | INFINIPATH_E_REBP)
132 /* These are all send-related errors which we want to count for stats */
134 (INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM | \
135 INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
136 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SUNSUPVL | \
137 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
138 INFINIPATH_E_INVALIDADDR)
141 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
142 * errors not related to freeze and cancelling buffers. Can't ignore
143 * armlaunch because could get more while still cleaning up, and need
144 * to cancel those as they happen.
146 #define E_SPKT_ERRS_IGNORE \
147 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
148 INFINIPATH_E_SMAXPKTLEN | INFINIPATH_E_SMINPKTLEN | \
149 INFINIPATH_E_SPKTLEN)
152 * these are errors that can occur when the link changes state while
153 * a packet is being sent or received. This doesn't cover things
154 * like EBP or VCRC that can be the result of a sending having the
155 * link change state, so we receive a "known bad" packet.
157 #define E_SUM_LINK_PKTERRS \
158 (INFINIPATH_E_SDROPPEDDATAPKT | INFINIPATH_E_SDROPPEDSMPPKT | \
159 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SPKTLEN | \
160 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RMINPKTLEN | \
161 INFINIPATH_E_RUNEXPCHAR)
163 static u64 handle_e_sum_errs(struct ipath_devdata *dd, ipath_err_t errs)
165 u64 ignore_this_time = 0;
167 ipath_disarm_senderrbufs(dd, 0);
168 if ((errs & E_SUM_LINK_PKTERRS) &&
169 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
171 * This can happen when SMA is trying to bring the link
172 * up, but the IB link changes state at the "wrong" time.
173 * The IB logic then complains that the packet isn't
174 * valid. We don't want to confuse people, so we just
175 * don't print them, except at debug
177 ipath_dbg("Ignoring packet errors %llx, because link not "
178 "ACTIVE\n", (unsigned long long) errs);
179 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
182 return ignore_this_time;
185 /* generic hw error messages... */
186 #define INFINIPATH_HWE_TXEMEMPARITYERR_MSG(a) \
188 .mask = ( INFINIPATH_HWE_TXEMEMPARITYERR_##a << \
189 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT ), \
190 .msg = "TXE " #a " Memory Parity" \
192 #define INFINIPATH_HWE_RXEMEMPARITYERR_MSG(a) \
194 .mask = ( INFINIPATH_HWE_RXEMEMPARITYERR_##a << \
195 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT ), \
196 .msg = "RXE " #a " Memory Parity" \
199 static const struct ipath_hwerror_msgs ipath_generic_hwerror_msgs[] = {
200 INFINIPATH_HWE_MSG(IBCBUSFRSPCPARITYERR, "IPATH2IB Parity"),
201 INFINIPATH_HWE_MSG(IBCBUSTOSPCPARITYERR, "IB2IPATH Parity"),
203 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOBUF),
204 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOPBC),
205 INFINIPATH_HWE_TXEMEMPARITYERR_MSG(PIOLAUNCHFIFO),
207 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(RCVBUF),
208 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(LOOKUPQ),
209 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EAGERTID),
210 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(EXPTID),
211 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(FLAGBUF),
212 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(DATAINFO),
213 INFINIPATH_HWE_RXEMEMPARITYERR_MSG(HDRINFO),
217 * ipath_format_hwmsg - format a single hwerror message
218 * @msg message buffer
219 * @msgl length of message buffer
220 * @hwmsg message to add to message buffer
222 static void ipath_format_hwmsg(char *msg, size_t msgl, const char *hwmsg)
224 strlcat(msg, "[", msgl);
225 strlcat(msg, hwmsg, msgl);
226 strlcat(msg, "]", msgl);
230 * ipath_format_hwerrors - format hardware error messages for display
231 * @hwerrs hardware errors bit vector
232 * @hwerrmsgs hardware error descriptions
233 * @nhwerrmsgs number of hwerrmsgs
234 * @msg message buffer
235 * @msgl message buffer length
237 void ipath_format_hwerrors(u64 hwerrs,
238 const struct ipath_hwerror_msgs *hwerrmsgs,
240 char *msg, size_t msgl)
244 sizeof(ipath_generic_hwerror_msgs) /
245 sizeof(ipath_generic_hwerror_msgs[0]);
247 for (i=0; i<glen; i++) {
248 if (hwerrs & ipath_generic_hwerror_msgs[i].mask) {
249 ipath_format_hwmsg(msg, msgl,
250 ipath_generic_hwerror_msgs[i].msg);
254 for (i=0; i<nhwerrmsgs; i++) {
255 if (hwerrs & hwerrmsgs[i].mask) {
256 ipath_format_hwmsg(msg, msgl, hwerrmsgs[i].msg);
261 /* return the strings for the most common link states */
262 static char *ib_linkstate(struct ipath_devdata *dd, u64 ibcs)
267 state = ipath_ib_state(dd, ibcs);
268 if (state == dd->ib_init)
270 else if (state == dd->ib_arm)
272 else if (state == dd->ib_active)
279 void signal_ib_event(struct ipath_devdata *dd, enum ib_event_type ev)
281 struct ib_event event;
283 event.device = &dd->verbs_dev->ibdev;
284 event.element.port_num = 1;
286 ib_dispatch_event(&event);
289 static void handle_e_ibstatuschanged(struct ipath_devdata *dd,
292 u32 ltstate, lstate, ibstate, lastlstate;
293 u32 init = dd->ib_init;
294 u32 arm = dd->ib_arm;
295 u32 active = dd->ib_active;
296 const u64 ibcs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_ibcstatus);
298 lstate = ipath_ib_linkstate(dd, ibcs); /* linkstate */
299 ibstate = ipath_ib_state(dd, ibcs);
300 /* linkstate at last interrupt */
301 lastlstate = ipath_ib_linkstate(dd, dd->ipath_lastibcstat);
302 ltstate = ipath_ib_linktrstate(dd, ibcs); /* linktrainingtate */
305 * Since going into a recovery state causes the link state to go
306 * down and since recovery is transitory, it is better if we "miss"
307 * ever seeing the link training state go into recovery (i.e.,
308 * ignore this transition for link state special handling purposes)
309 * without even updating ipath_lastibcstat.
311 if ((ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN) ||
312 (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT) ||
313 (ltstate == INFINIPATH_IBCS_LT_STATE_RECOVERIDLE))
317 * if linkstate transitions into INIT from any of the various down
318 * states, or if it transitions from any of the up (INIT or better)
319 * states into any of the down states (except link recovery), then
320 * call the chip-specific code to take appropriate actions.
322 if (lstate >= INFINIPATH_IBCS_L_STATE_INIT &&
323 lastlstate == INFINIPATH_IBCS_L_STATE_DOWN) {
324 /* transitioned to UP */
325 if (dd->ipath_f_ib_updown(dd, 1, ibcs)) {
326 /* link came up, so we must no longer be disabled */
327 dd->ipath_flags &= ~IPATH_IB_LINK_DISABLED;
328 ipath_cdbg(LINKVERB, "LinkUp handled, skipped\n");
329 goto skip_ibchange; /* chip-code handled */
331 } else if ((lastlstate >= INFINIPATH_IBCS_L_STATE_INIT ||
332 (dd->ipath_flags & IPATH_IB_FORCE_NOTIFY)) &&
333 ltstate <= INFINIPATH_IBCS_LT_STATE_CFGWAITRMT &&
334 ltstate != INFINIPATH_IBCS_LT_STATE_LINKUP) {
336 handled = dd->ipath_f_ib_updown(dd, 0, ibcs);
337 dd->ipath_flags &= ~IPATH_IB_FORCE_NOTIFY;
339 ipath_cdbg(LINKVERB, "LinkDown handled, skipped\n");
340 goto skip_ibchange; /* chip-code handled */
345 * Significant enough to always print and get into logs, if it was
346 * unexpected. If it was a requested state change, we'll have
347 * already cleared the flags, so we won't print this warning
349 if ((ibstate != arm && ibstate != active) &&
350 (dd->ipath_flags & (IPATH_LINKARMED | IPATH_LINKACTIVE))) {
351 dev_info(&dd->pcidev->dev, "Link state changed from %s "
352 "to %s\n", (dd->ipath_flags & IPATH_LINKARMED) ?
353 "ARM" : "ACTIVE", ib_linkstate(dd, ibcs));
356 if (ltstate == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
357 ltstate == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
359 lastlts = ipath_ib_linktrstate(dd, dd->ipath_lastibcstat);
361 * Ignore cycling back and forth from Polling.Active to
362 * Polling.Quiet while waiting for the other end of the link
363 * to come up, except to try and decide if we are connected
364 * to a live IB device or not. We will cycle back and
365 * forth between them if no cable is plugged in, the other
366 * device is powered off or disabled, etc.
368 if (lastlts == INFINIPATH_IBCS_LT_STATE_POLLACTIVE ||
369 lastlts == INFINIPATH_IBCS_LT_STATE_POLLQUIET) {
370 if (!(dd->ipath_flags & IPATH_IB_AUTONEG_INPROG) &&
371 (++dd->ipath_ibpollcnt == 40)) {
372 dd->ipath_flags |= IPATH_NOCABLE;
373 *dd->ipath_statusp |=
374 IPATH_STATUS_IB_NOCABLE;
375 ipath_cdbg(LINKVERB, "Set NOCABLE\n");
377 ipath_cdbg(LINKVERB, "POLL change to %s (%x)\n",
378 ipath_ibcstatus_str[ltstate], ibstate);
383 dd->ipath_ibpollcnt = 0; /* not poll*, now */
384 ipath_stats.sps_iblink++;
386 if (ibstate != init && dd->ipath_lastlinkrecov && ipath_linkrecovery) {
388 linkrecov = ipath_snap_cntr(dd,
389 dd->ipath_cregs->cr_iblinkerrrecovcnt);
390 if (linkrecov != dd->ipath_lastlinkrecov) {
391 ipath_dbg("IB linkrecov up %Lx (%s %s) recov %Lu\n",
392 ibcs, ib_linkstate(dd, ibcs),
393 ipath_ibcstatus_str[ltstate],
395 /* and no more until active again */
396 dd->ipath_lastlinkrecov = 0;
397 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
402 if (ibstate == init || ibstate == arm || ibstate == active) {
403 *dd->ipath_statusp &= ~IPATH_STATUS_IB_NOCABLE;
404 if (ibstate == init || ibstate == arm) {
405 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
406 if (dd->ipath_flags & IPATH_LINKACTIVE)
407 signal_ib_event(dd, IB_EVENT_PORT_ERR);
409 if (ibstate == arm) {
410 dd->ipath_flags |= IPATH_LINKARMED;
411 dd->ipath_flags &= ~(IPATH_LINKUNK |
412 IPATH_LINKINIT | IPATH_LINKDOWN |
413 IPATH_LINKACTIVE | IPATH_NOCABLE);
415 } else if (ibstate == init) {
417 * set INIT and DOWN. Down is checked by
418 * most of the other code, but INIT is
419 * useful to know in a few places.
421 dd->ipath_flags |= IPATH_LINKINIT |
423 dd->ipath_flags &= ~(IPATH_LINKUNK |
424 IPATH_LINKARMED | IPATH_LINKACTIVE |
427 } else { /* active */
428 dd->ipath_lastlinkrecov = ipath_snap_cntr(dd,
429 dd->ipath_cregs->cr_iblinkerrrecovcnt);
430 *dd->ipath_statusp |=
431 IPATH_STATUS_IB_READY | IPATH_STATUS_IB_CONF;
432 dd->ipath_flags |= IPATH_LINKACTIVE;
433 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
434 | IPATH_LINKDOWN | IPATH_LINKARMED |
436 signal_ib_event(dd, IB_EVENT_PORT_ACTIVE);
437 /* LED active not handled in chip _f_updown */
438 dd->ipath_f_setextled(dd, lstate, ltstate);
443 * print after we've already done the work, so as not to
444 * delay the state changes and notifications, for debugging
446 if (lstate == lastlstate)
447 ipath_cdbg(LINKVERB, "Unchanged from last: %s "
448 "(%x)\n", ib_linkstate(dd, ibcs), ibstate);
450 ipath_cdbg(VERBOSE, "Unit %u: link up to %s %s (%x)\n",
451 dd->ipath_unit, ib_linkstate(dd, ibcs),
452 ipath_ibcstatus_str[ltstate], ibstate);
454 if (dd->ipath_flags & IPATH_LINKACTIVE)
455 signal_ib_event(dd, IB_EVENT_PORT_ERR);
456 dd->ipath_flags |= IPATH_LINKDOWN;
457 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
460 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
461 dd->ipath_lli_counter = 0;
463 if (lastlstate != INFINIPATH_IBCS_L_STATE_DOWN)
464 ipath_cdbg(VERBOSE, "Unit %u link state down "
465 "(state 0x%x), from %s\n",
466 dd->ipath_unit, lstate,
467 ib_linkstate(dd, dd->ipath_lastibcstat));
469 ipath_cdbg(LINKVERB, "Unit %u link state changed "
470 "to %s (0x%x) from down (%x)\n",
472 ipath_ibcstatus_str[ltstate],
473 ibstate, lastlstate);
477 dd->ipath_lastibcstat = ibcs;
482 static void handle_supp_msgs(struct ipath_devdata *dd,
483 unsigned supp_msgs, char *msg, int msgsz)
486 * Print the message unless it's ibc status change only, which
487 * happens so often we never want to count it.
489 if (dd->ipath_lasterror & ~INFINIPATH_E_IBSTATUSCHANGED) {
491 iserr = ipath_decode_err(msg, msgsz,
492 dd->ipath_lasterror &
493 ~INFINIPATH_E_IBSTATUSCHANGED);
494 if (dd->ipath_lasterror &
495 ~(INFINIPATH_E_RRCVEGRFULL |
496 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
497 ipath_dev_err(dd, "Suppressed %u messages for "
498 "fast-repeating errors (%s) (%llx)\n",
501 dd->ipath_lasterror);
504 * rcvegrfull and rcvhdrqfull are "normal", for some
505 * types of processes (mostly benchmarks) that send
506 * huge numbers of messages, while not processing
507 * them. So only complain about these at debug
511 ipath_dbg("Suppressed %u messages for %s\n",
515 "Suppressed %u messages for %s\n",
521 static unsigned handle_frequent_errors(struct ipath_devdata *dd,
522 ipath_err_t errs, char *msg,
523 int msgsz, int *noprint)
526 static unsigned long nextmsg_time;
527 static unsigned nmsgs, supp_msgs;
530 * Throttle back "fast" messages to no more than 10 per 5 seconds.
531 * This isn't perfect, but it's a reasonable heuristic. If we get
532 * more than 10, give a 6x longer delay.
536 if (time_before(nc, nextmsg_time)) {
539 nextmsg_time = nc + HZ * 3;
541 else if (supp_msgs) {
542 handle_supp_msgs(dd, supp_msgs, msg, msgsz);
547 else if (!nmsgs++ || time_after(nc, nextmsg_time))
548 nextmsg_time = nc + HZ / 2;
553 static int handle_errors(struct ipath_devdata *dd, ipath_err_t errs)
556 u64 ignore_this_time = 0;
558 int chkerrpkts = 0, noprint = 0;
562 supp_msgs = handle_frequent_errors(dd, errs, msg, sizeof msg, &noprint);
564 /* don't report errors that are masked */
565 errs &= ~dd->ipath_maskederrs;
567 /* do these first, they are most important */
568 if (errs & INFINIPATH_E_HARDWARE) {
569 /* reuse same msg buf */
570 dd->ipath_f_handle_hwerrors(dd, msg, sizeof msg);
573 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx) {
574 mask = dd->ipath_eep_st_masks[log_idx].errs_to_log;
576 ipath_inc_eeprom_err(dd, log_idx, 1);
580 if (!noprint && (errs & ~dd->ipath_e_bitsextant))
581 ipath_dev_err(dd, "error interrupt with unknown errors "
582 "%llx set\n", (unsigned long long)
583 (errs & ~dd->ipath_e_bitsextant));
585 if (errs & E_SUM_ERRS)
586 ignore_this_time = handle_e_sum_errs(dd, errs);
587 else if ((errs & E_SUM_LINK_PKTERRS) &&
588 !(dd->ipath_flags & IPATH_LINKACTIVE)) {
590 * This can happen when SMA is trying to bring the link
591 * up, but the IB link changes state at the "wrong" time.
592 * The IB logic then complains that the packet isn't
593 * valid. We don't want to confuse people, so we just
594 * don't print them, except at debug
596 ipath_dbg("Ignoring packet errors %llx, because link not "
597 "ACTIVE\n", (unsigned long long) errs);
598 ignore_this_time = errs & E_SUM_LINK_PKTERRS;
601 if (supp_msgs == 250000) {
604 * It's not entirely reasonable assuming that the errors set
605 * in the last clear period are all responsible for the
606 * problem, but the alternative is to assume it's the only
607 * ones on this particular interrupt, which also isn't great
609 dd->ipath_maskederrs |= dd->ipath_lasterror | errs;
611 dd->ipath_errormask &= ~dd->ipath_maskederrs;
612 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
613 dd->ipath_errormask);
614 s_iserr = ipath_decode_err(msg, sizeof msg,
615 dd->ipath_maskederrs);
617 if (dd->ipath_maskederrs &
618 ~(INFINIPATH_E_RRCVEGRFULL |
619 INFINIPATH_E_RRCVHDRFULL | INFINIPATH_E_PKTERRS))
620 ipath_dev_err(dd, "Temporarily disabling "
621 "error(s) %llx reporting; too frequent (%s)\n",
622 (unsigned long long) dd->ipath_maskederrs,
626 * rcvegrfull and rcvhdrqfull are "normal",
627 * for some types of processes (mostly benchmarks)
628 * that send huge numbers of messages, while not
629 * processing them. So only complain about
630 * these at debug level.
633 ipath_dbg("Temporarily disabling reporting "
634 "too frequent queue full errors (%s)\n",
638 "Temporarily disabling reporting too"
639 " frequent packet errors (%s)\n",
644 * Re-enable the masked errors after around 3 minutes. in
645 * ipath_get_faststats(). If we have a series of fast
646 * repeating but different errors, the interval will keep
647 * stretching out, but that's OK, as that's pretty
650 dd->ipath_unmasktime = jiffies + HZ * 180;
653 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear, errs);
654 if (ignore_this_time)
655 errs &= ~ignore_this_time;
656 if (errs & ~dd->ipath_lasterror) {
657 errs &= ~dd->ipath_lasterror;
658 /* never suppress duplicate hwerrors or ibstatuschange */
659 dd->ipath_lasterror |= errs &
660 ~(INFINIPATH_E_HARDWARE |
661 INFINIPATH_E_IBSTATUSCHANGED);
664 /* likely due to cancel, so suppress */
665 if ((errs & (INFINIPATH_E_SPKTLEN | INFINIPATH_E_SPIOARMLAUNCH)) &&
666 dd->ipath_lastcancel > jiffies) {
667 ipath_dbg("Suppressed armlaunch/spktlen after error send cancel\n");
668 errs &= ~(INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SPKTLEN);
676 * the ones we mask off are handled specially below or above
678 ipath_decode_err(msg, sizeof msg,
679 errs & ~(INFINIPATH_E_IBSTATUSCHANGED |
680 INFINIPATH_E_RRCVEGRFULL |
681 INFINIPATH_E_RRCVHDRFULL |
682 INFINIPATH_E_HARDWARE));
684 /* so we don't need if (!noprint) at strlcat's below */
687 if (errs & E_SUM_PKTERRS) {
688 ipath_stats.sps_pkterrs++;
691 if (errs & E_SUM_ERRS)
692 ipath_stats.sps_errs++;
694 if (errs & (INFINIPATH_E_RICRC | INFINIPATH_E_RVCRC)) {
695 ipath_stats.sps_crcerrs++;
698 iserr = errs & ~(E_SUM_PKTERRS | INFINIPATH_E_PKTERRS);
702 * We don't want to print these two as they happen, or we can make
703 * the situation even worse, because it takes so long to print
704 * messages to serial consoles. Kernel ports get printed from
705 * fast_stats, no more than every 5 seconds, user ports get printed
708 if (errs & INFINIPATH_E_RRCVHDRFULL) {
710 ipath_stats.sps_hdrqfull++;
711 for (i = 0; i < dd->ipath_cfgports; i++) {
712 struct ipath_portdata *pd = dd->ipath_pd[i];
715 tl = ipath_get_hdrqtail(pd);
716 } else if (pd && pd->port_cnt &&
717 pd->port_rcvhdrtail_kvaddr) {
719 * don't report same point multiple times,
722 tl = *(u64 *) pd->port_rcvhdrtail_kvaddr;
723 if (tl == pd->port_lastrcvhdrqtail)
725 hd = ipath_read_ureg32(dd, ur_rcvhdrhead,
729 if (hd == (tl + 1) ||
730 (!hd && tl == dd->ipath_hdrqlast)) {
733 pd->port_lastrcvhdrqtail = tl;
735 /* flush hdrqfull so that poll() sees it */
737 wake_up_interruptible(&pd->port_wait);
741 if (errs & INFINIPATH_E_RRCVEGRFULL) {
742 struct ipath_portdata *pd = dd->ipath_pd[0];
745 * since this is of less importance and not likely to
746 * happen without also getting hdrfull, only count
747 * occurrences; don't check each port (or even the kernel
750 ipath_stats.sps_etidfull++;
751 if (pd->port_head != ipath_get_hdrqtail(pd))
756 * do this before IBSTATUSCHANGED, in case both bits set in a single
757 * interrupt; we want the STATUSCHANGE to "win", so we do our
758 * internal copy of state machine correctly
760 if (errs & INFINIPATH_E_RIBLOSTLINK) {
762 * force through block below
764 errs |= INFINIPATH_E_IBSTATUSCHANGED;
765 ipath_stats.sps_iblink++;
766 dd->ipath_flags |= IPATH_LINKDOWN;
767 dd->ipath_flags &= ~(IPATH_LINKUNK | IPATH_LINKINIT
768 | IPATH_LINKARMED | IPATH_LINKACTIVE);
769 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
771 ipath_dbg("Lost link, link now down (%s)\n",
772 ipath_ibcstatus_str[ipath_read_kreg64(dd,
773 dd->ipath_kregs->kr_ibcstatus) & 0xf]);
775 if (errs & INFINIPATH_E_IBSTATUSCHANGED)
776 handle_e_ibstatuschanged(dd, errs);
778 if (errs & INFINIPATH_E_RESET) {
780 ipath_dev_err(dd, "Got reset, requires re-init "
781 "(unload and reload driver)\n");
782 dd->ipath_flags &= ~IPATH_INITTED; /* needs re-init */
783 /* mark as having had error */
784 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
785 *dd->ipath_statusp &= ~IPATH_STATUS_IB_CONF;
788 if (!noprint && *msg) {
790 ipath_dev_err(dd, "%s error\n", msg);
792 dev_info(&dd->pcidev->dev, "%s packet problems\n",
795 if (dd->ipath_state_wanted & dd->ipath_flags) {
796 ipath_cdbg(VERBOSE, "driver wanted state %x, iflags now %x, "
797 "waking\n", dd->ipath_state_wanted,
799 wake_up_interruptible(&ipath_state_wait);
806 * try to cleanup as much as possible for anything that might have gone
807 * wrong while in freeze mode, such as pio buffers being written by user
808 * processes (causing armlaunch), send errors due to going into freeze mode,
809 * etc., and try to avoid causing extra interrupts while doing so.
810 * Forcibly update the in-memory pioavail register copies after cleanup
811 * because the chip won't do it for anything changing while in freeze mode
812 * (we don't want to wait for the next pio buffer state change).
813 * Make sure that we don't lose any important interrupts by using the chip
814 * feature that says that writing 0 to a bit in *clear that is set in
815 * *status will cause an interrupt to be generated again (if allowed by
818 void ipath_clear_freeze(struct ipath_devdata *dd)
823 /* disable error interrupts, to avoid confusion */
824 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask, 0ULL);
826 /* also disable interrupts; errormask is sometimes overwriten */
827 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
830 * clear all sends, because they have may been
831 * completed by usercode while in freeze mode, and
832 * therefore would not be sent, and eventually
833 * might cause the process to run out of bufs
835 ipath_cancel_sends(dd, 0);
836 ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
839 /* ensure pio avail updates continue */
840 ipath_force_pio_avail_update(dd);
843 * We just enabled pioavailupdate, so dma copy is almost certainly
844 * not yet right, so read the registers directly. Similar to init
846 for (i = 0; i < dd->ipath_pioavregs; i++) {
847 /* deal with 6110 chip bug */
848 im = (i > 3 && (dd->ipath_flags & IPATH_SWAP_PIOBUFS)) ?
850 val = ipath_read_kreg64(dd, (0x1000 / sizeof(u64)) + im);
851 dd->ipath_pioavailregs_dma[i] = cpu_to_le64(val);
852 dd->ipath_pioavailshadow[i] = val |
853 (~dd->ipath_pioavailkernel[i] <<
854 INFINIPATH_SENDPIOAVAIL_BUSY_SHIFT);
858 * force new interrupt if any hwerr, error or interrupt bits are
859 * still set, and clear "safe" send packet errors related to freeze
860 * and cancelling sends. Re-enable error interrupts before possible
861 * force of re-interrupt on pending interrupts.
863 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear, 0ULL);
864 ipath_write_kreg(dd, dd->ipath_kregs->kr_errorclear,
866 ipath_write_kreg(dd, dd->ipath_kregs->kr_errormask,
867 dd->ipath_errormask);
868 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, -1LL);
869 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, 0ULL);
873 /* this is separate to allow for better optimization of ipath_intr() */
875 static noinline void ipath_bad_intr(struct ipath_devdata *dd, u32 *unexpectp)
878 * sometimes happen during driver init and unload, don't want
879 * to process any interrupts at that point
882 /* this is just a bandaid, not a fix, if something goes badly
884 if (++*unexpectp > 100) {
885 if (++*unexpectp > 105) {
887 * ok, we must be taking somebody else's interrupts,
888 * due to a messed up mptable and/or PIRQ table, so
889 * unregister the interrupt. We've seen this during
890 * linuxbios development work, and it may happen in
893 if (dd->pcidev && dd->ipath_irq) {
894 ipath_dev_err(dd, "Now %u unexpected "
895 "interrupts, unregistering "
896 "interrupt handler\n",
898 ipath_dbg("free_irq of irq %d\n",
900 dd->ipath_f_free_irq(dd);
903 if (ipath_read_ireg(dd, dd->ipath_kregs->kr_intmask)) {
904 ipath_dev_err(dd, "%u unexpected interrupts, "
905 "disabling interrupts completely\n",
908 * disable all interrupts, something is very wrong
910 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask,
913 } else if (*unexpectp > 1)
914 ipath_dbg("Interrupt when not ready, should not happen, "
918 static noinline void ipath_bad_regread(struct ipath_devdata *dd)
922 /* separate routine, for better optimization of ipath_intr() */
925 * We print the message and disable interrupts, in hope of
926 * having a better chance of debugging the problem.
929 "Read of interrupt status failed (all bits set)\n");
931 /* disable all interrupts, something is very wrong */
932 ipath_write_kreg(dd, dd->ipath_kregs->kr_intmask, 0ULL);
934 ipath_dev_err(dd, "Still bad interrupt status, "
935 "unregistering interrupt\n");
936 dd->ipath_f_free_irq(dd);
937 } else if (allbits > 2) {
938 if ((allbits % 10000) == 0)
941 ipath_dev_err(dd, "Disabling interrupts, "
942 "multiple errors\n");
946 static void handle_layer_pioavail(struct ipath_devdata *dd)
951 ret = ipath_ib_piobufavail(dd->verbs_dev);
957 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
958 dd->ipath_sendctrl |= INFINIPATH_S_PIOINTBUFAVAIL;
959 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
961 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
962 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
966 * Handle receive interrupts for user ports; this means a user
967 * process was waiting for a packet to arrive, and didn't want
970 static void handle_urcv(struct ipath_devdata *dd, u64 istat)
977 * test_and_clear_bit(IPATH_PORT_WAITING_RCV) and
978 * test_and_clear_bit(IPATH_PORT_WAITING_URG) below
979 * would both like timely updates of the bits so that
980 * we don't pass them by unnecessarily. the rmb()
981 * here ensures that we see them promptly -- the
982 * corresponding wmb()'s are in ipath_poll_urgent()
983 * and ipath_poll_next()...
986 portr = ((istat >> dd->ipath_i_rcvavail_shift) &
987 dd->ipath_i_rcvavail_mask) |
988 ((istat >> dd->ipath_i_rcvurg_shift) &
989 dd->ipath_i_rcvurg_mask);
990 for (i = 1; i < dd->ipath_cfgports; i++) {
991 struct ipath_portdata *pd = dd->ipath_pd[i];
993 if (portr & (1 << i) && pd && pd->port_cnt) {
994 if (test_and_clear_bit(IPATH_PORT_WAITING_RCV,
996 clear_bit(i + dd->ipath_r_intravail_shift,
998 wake_up_interruptible(&pd->port_wait);
1000 } else if (test_and_clear_bit(IPATH_PORT_WAITING_URG,
1003 wake_up_interruptible(&pd->port_wait);
1008 /* only want to take one interrupt, so turn off the rcv
1009 * interrupt for all the ports that we set the rcv_waiting
1010 * (but never for kernel port)
1012 ipath_write_kreg(dd, dd->ipath_kregs->kr_rcvctrl,
1017 irqreturn_t ipath_intr(int irq, void *data)
1019 struct ipath_devdata *dd = data;
1020 u32 istat, chk0rcv = 0;
1021 ipath_err_t estat = 0;
1023 static unsigned unexpected = 0;
1026 ipath_stats.sps_ints++;
1028 if (dd->ipath_int_counter != (u32) -1)
1029 dd->ipath_int_counter++;
1031 if (!(dd->ipath_flags & IPATH_PRESENT)) {
1033 * This return value is not great, but we do not want the
1034 * interrupt core code to remove our interrupt handler
1035 * because we don't appear to be handling an interrupt
1036 * during a chip reset.
1042 * this needs to be flags&initted, not statusp, so we keep
1043 * taking interrupts even after link goes down, etc.
1044 * Also, we *must* clear the interrupt at some point, or we won't
1045 * take it again, which can be real bad for errors, etc...
1048 if (!(dd->ipath_flags & IPATH_INITTED)) {
1049 ipath_bad_intr(dd, &unexpected);
1054 istat = ipath_read_ireg(dd, dd->ipath_kregs->kr_intstatus);
1056 if (unlikely(!istat)) {
1057 ipath_stats.sps_nullintr++;
1058 ret = IRQ_NONE; /* not our interrupt, or already handled */
1061 if (unlikely(istat == -1)) {
1062 ipath_bad_regread(dd);
1063 /* don't know if it was our interrupt or not */
1071 if (unlikely(istat & ~dd->ipath_i_bitsextant))
1073 "interrupt with unknown interrupts %x set\n",
1074 istat & (u32) ~ dd->ipath_i_bitsextant);
1076 ipath_cdbg(VERBOSE, "intr stat=0x%x\n", istat);
1078 if (unlikely(istat & INFINIPATH_I_ERROR)) {
1079 ipath_stats.sps_errints++;
1080 estat = ipath_read_kreg64(dd,
1081 dd->ipath_kregs->kr_errorstatus);
1083 dev_info(&dd->pcidev->dev, "error interrupt (%x), "
1084 "but no error bits set!\n", istat);
1085 else if (estat == -1LL)
1087 * should we try clearing all, or hope next read
1090 ipath_dev_err(dd, "Read of error status failed "
1091 "(all bits set); ignoring\n");
1093 chk0rcv |= handle_errors(dd, estat);
1096 if (istat & INFINIPATH_I_GPIO) {
1098 * GPIO interrupts fall in two broad classes:
1099 * GPIO_2 indicates (on some HT4xx boards) that a packet
1100 * has arrived for Port 0. Checking for this
1101 * is controlled by flag IPATH_GPIO_INTR.
1102 * GPIO_3..5 on IBA6120 Rev2 and IBA6110 Rev4 chips indicate
1103 * errors that we need to count. Checking for this
1104 * is controlled by flag IPATH_GPIO_ERRINTRS.
1109 gpiostatus = ipath_read_kreg32(
1110 dd, dd->ipath_kregs->kr_gpio_status);
1111 /* First the error-counter case. */
1112 if ((gpiostatus & IPATH_GPIO_ERRINTR_MASK) &&
1113 (dd->ipath_flags & IPATH_GPIO_ERRINTRS)) {
1114 /* want to clear the bits we see asserted. */
1115 to_clear |= (gpiostatus & IPATH_GPIO_ERRINTR_MASK);
1118 * Count appropriately, clear bits out of our copy,
1119 * as they have been "handled".
1121 if (gpiostatus & (1 << IPATH_GPIO_RXUVL_BIT)) {
1122 ipath_dbg("FlowCtl on UnsupVL\n");
1123 dd->ipath_rxfc_unsupvl_errs++;
1125 if (gpiostatus & (1 << IPATH_GPIO_OVRUN_BIT)) {
1126 ipath_dbg("Overrun Threshold exceeded\n");
1127 dd->ipath_overrun_thresh_errs++;
1129 if (gpiostatus & (1 << IPATH_GPIO_LLI_BIT)) {
1130 ipath_dbg("Local Link Integrity error\n");
1131 dd->ipath_lli_errs++;
1133 gpiostatus &= ~IPATH_GPIO_ERRINTR_MASK;
1135 /* Now the Port0 Receive case */
1136 if ((gpiostatus & (1 << IPATH_GPIO_PORT0_BIT)) &&
1137 (dd->ipath_flags & IPATH_GPIO_INTR)) {
1139 * GPIO status bit 2 is set, and we expected it.
1140 * clear it and indicate in p0bits.
1141 * This probably only happens if a Port0 pkt
1142 * arrives at _just_ the wrong time, and we
1143 * handle that by seting chk0rcv;
1145 to_clear |= (1 << IPATH_GPIO_PORT0_BIT);
1146 gpiostatus &= ~(1 << IPATH_GPIO_PORT0_BIT);
1151 * Some unexpected bits remain. If they could have
1152 * caused the interrupt, complain and clear.
1153 * To avoid repetition of this condition, also clear
1154 * the mask. It is almost certainly due to error.
1156 const u32 mask = (u32) dd->ipath_gpio_mask;
1158 if (mask & gpiostatus) {
1159 ipath_dbg("Unexpected GPIO IRQ bits %x\n",
1161 to_clear |= (gpiostatus & mask);
1162 dd->ipath_gpio_mask &= ~(gpiostatus & mask);
1163 ipath_write_kreg(dd,
1164 dd->ipath_kregs->kr_gpio_mask,
1165 dd->ipath_gpio_mask);
1169 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_clear,
1175 * Clear the interrupt bits we found set, unless they are receive
1176 * related, in which case we already cleared them above, and don't
1177 * want to clear them again, because we might lose an interrupt.
1178 * Clear it early, so we "know" know the chip will have seen this by
1179 * the time we process the queue, and will re-interrupt if necessary.
1180 * The processor itself won't take the interrupt again until we return.
1182 ipath_write_kreg(dd, dd->ipath_kregs->kr_intclear, istat);
1185 * Handle kernel receive queues before checking for pio buffers
1186 * available since receives can overflow; piobuf waiters can afford
1187 * a few extra cycles, since they were waiting anyway, and user's
1188 * waiting for receive are at the bottom.
1190 kportrbits = (1ULL << dd->ipath_i_rcvavail_shift) |
1191 (1ULL << dd->ipath_i_rcvurg_shift);
1192 if (chk0rcv || (istat & kportrbits)) {
1193 istat &= ~kportrbits;
1194 ipath_kreceive(dd->ipath_pd[0]);
1197 if (istat & ((dd->ipath_i_rcvavail_mask << dd->ipath_i_rcvavail_shift) |
1198 (dd->ipath_i_rcvurg_mask << dd->ipath_i_rcvurg_shift)))
1199 handle_urcv(dd, istat);
1201 if (istat & INFINIPATH_I_SPIOBUFAVAIL) {
1202 unsigned long flags;
1204 spin_lock_irqsave(&dd->ipath_sendctrl_lock, flags);
1205 dd->ipath_sendctrl &= ~INFINIPATH_S_PIOINTBUFAVAIL;
1206 ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1207 dd->ipath_sendctrl);
1208 ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1209 spin_unlock_irqrestore(&dd->ipath_sendctrl_lock, flags);
1211 handle_layer_pioavail(dd);