drivers/infiniband/hw/ipath/ipath_iba6120.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 /*
  34  * This file contains all of the code that is specific to the
  35  * InfiniPath PCIe chip.
  36  */
  37
  38 #include <linux/interrupt.h>
  39 #include <linux/pci.h>
  40 #include <linux/delay.h>
  41
  42
  43 #include "ipath_kernel.h"
  44 #include "ipath_registers.h"
  45
  46 /*
  47  * This file contains all the chip-specific register information and
  48  * access functions for the QLogic InfiniPath PCI-Express chip.
  49  *
  50  * This lists the InfiniPath registers, in the actual chip layout.
  51  * This structure should never be directly accessed.
  52  */
  53 struct _infinipath_do_not_use_kernel_regs {
  54         unsigned long long Revision;
  55         unsigned long long Control;
  56         unsigned long long PageAlign;
  57         unsigned long long PortCnt;
  58         unsigned long long DebugPortSelect;
  59         unsigned long long Reserved0;
  60         unsigned long long SendRegBase;
  61         unsigned long long UserRegBase;
  62         unsigned long long CounterRegBase;
  63         unsigned long long Scratch;
  64         unsigned long long Reserved1;
  65         unsigned long long Reserved2;
  66         unsigned long long IntBlocked;
  67         unsigned long long IntMask;
  68         unsigned long long IntStatus;
  69         unsigned long long IntClear;
  70         unsigned long long ErrorMask;
  71         unsigned long long ErrorStatus;
  72         unsigned long long ErrorClear;
  73         unsigned long long HwErrMask;
  74         unsigned long long HwErrStatus;
  75         unsigned long long HwErrClear;
  76         unsigned long long HwDiagCtrl;
  77         unsigned long long MDIO;
  78         unsigned long long IBCStatus;
  79         unsigned long long IBCCtrl;
  80         unsigned long long ExtStatus;
  81         unsigned long long ExtCtrl;
  82         unsigned long long GPIOOut;
  83         unsigned long long GPIOMask;
  84         unsigned long long GPIOStatus;
  85         unsigned long long GPIOClear;
  86         unsigned long long RcvCtrl;
  87         unsigned long long RcvBTHQP;
  88         unsigned long long RcvHdrSize;
  89         unsigned long long RcvHdrCnt;
  90         unsigned long long RcvHdrEntSize;
  91         unsigned long long RcvTIDBase;
  92         unsigned long long RcvTIDCnt;
  93         unsigned long long RcvEgrBase;
  94         unsigned long long RcvEgrCnt;
  95         unsigned long long RcvBufBase;
  96         unsigned long long RcvBufSize;
  97         unsigned long long RxIntMemBase;
  98         unsigned long long RxIntMemSize;
  99         unsigned long long RcvPartitionKey;
 100         unsigned long long Reserved3;
 101         unsigned long long RcvPktLEDCnt;
 102         unsigned long long Reserved4[8];
 103         unsigned long long SendCtrl;
 104         unsigned long long SendPIOBufBase;
 105         unsigned long long SendPIOSize;
 106         unsigned long long SendPIOBufCnt;
 107         unsigned long long SendPIOAvailAddr;
 108         unsigned long long TxIntMemBase;
 109         unsigned long long TxIntMemSize;
 110         unsigned long long Reserved5;
 111         unsigned long long PCIeRBufTestReg0;
 112         unsigned long long PCIeRBufTestReg1;
 113         unsigned long long Reserved51[6];
 114         unsigned long long SendBufferError;
 115         unsigned long long SendBufferErrorCONT1;
 116         unsigned long long Reserved6SBE[6];
 117         unsigned long long RcvHdrAddr0;
 118         unsigned long long RcvHdrAddr1;
 119         unsigned long long RcvHdrAddr2;
 120         unsigned long long RcvHdrAddr3;
 121         unsigned long long RcvHdrAddr4;
 122         unsigned long long Reserved7RHA[11];
 123         unsigned long long RcvHdrTailAddr0;
 124         unsigned long long RcvHdrTailAddr1;
 125         unsigned long long RcvHdrTailAddr2;
 126         unsigned long long RcvHdrTailAddr3;
 127         unsigned long long RcvHdrTailAddr4;
 128         unsigned long long Reserved8RHTA[11];
 129         unsigned long long Reserved9SW[8];
 130         unsigned long long SerdesConfig0;
 131         unsigned long long SerdesConfig1;
 132         unsigned long long SerdesStatus;
 133         unsigned long long XGXSConfig;
 134         unsigned long long IBPLLCfg;
 135         unsigned long long Reserved10SW2[3];
 136         unsigned long long PCIEQ0SerdesConfig0;
 137         unsigned long long PCIEQ0SerdesConfig1;
 138         unsigned long long PCIEQ0SerdesStatus;
 139         unsigned long long Reserved11;
 140         unsigned long long PCIEQ1SerdesConfig0;
 141         unsigned long long PCIEQ1SerdesConfig1;
 142         unsigned long long PCIEQ1SerdesStatus;
 143         unsigned long long Reserved12;
 144 };
 145
 146 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 147     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 148 #define IPATH_CREG_OFFSET(field) (offsetof( \
 149     struct infinipath_counters, field) / sizeof(u64))
 150
 151 static const struct ipath_kregs ipath_pe_kregs = {
 152         .kr_control = IPATH_KREG_OFFSET(Control),
 153         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 154         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 155         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 156         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 157         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 158         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 159         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 160         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 161         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 162         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 163         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 164         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 165         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 166         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 167         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 168         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 169         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 170         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 171         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 172         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 173         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 174         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 175         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 176         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 177         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 178         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 179         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 180         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 181         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 182         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 183         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 184         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 185         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 186         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 187         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 188         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 189         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 190         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 191         .kr_revision = IPATH_KREG_OFFSET(Revision),
 192         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 193         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 194         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 195         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 196         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 197         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 198         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 199         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 200         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 201         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 202         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 203         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 204         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 205         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 206         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 207         .kr_ibpllcfg = IPATH_KREG_OFFSET(IBPLLCfg),
 208
 209         /*
 210          * These should not be used directly via ipath_write_kreg64(),
 211          * use them with ipath_write_kreg64_port(),
 212          */
 213         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 214         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0),
 215
 216         /* The rcvpktled register controls one of the debug port signals, so
 217          * a packet activity LED can be connected to it. */
 218         .kr_rcvpktledcnt = IPATH_KREG_OFFSET(RcvPktLEDCnt),
 219         .kr_pcierbuftestreg0 = IPATH_KREG_OFFSET(PCIeRBufTestReg0),
 220         .kr_pcierbuftestreg1 = IPATH_KREG_OFFSET(PCIeRBufTestReg1),
 221         .kr_pcieq0serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig0),
 222         .kr_pcieq0serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ0SerdesConfig1),
 223         .kr_pcieq0serdesstatus = IPATH_KREG_OFFSET(PCIEQ0SerdesStatus),
 224         .kr_pcieq1serdesconfig0 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig0),
 225         .kr_pcieq1serdesconfig1 = IPATH_KREG_OFFSET(PCIEQ1SerdesConfig1),
 226         .kr_pcieq1serdesstatus = IPATH_KREG_OFFSET(PCIEQ1SerdesStatus)
 227 };
 228
 229 static const struct ipath_cregs ipath_pe_cregs = {
 230         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 231         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 232         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 233         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 234         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 235         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 236         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 237         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 238         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 239         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 240         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 241         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 242         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 243         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 244         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 245         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 246         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 247         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 248         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 249         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 250         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 251         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 252         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 253         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 254         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 255         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 256         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 257         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 258         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 259         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 260         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 261         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 262         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 263 };
 264
 265 /* kr_intstatus, kr_intclear, kr_intmask bits */
 266 #define INFINIPATH_I_RCVURG_MASK ((1U<<5)-1)
 267 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<5)-1)
 268
 269 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 270 #define INFINIPATH_HWE_PCIEMEMPARITYERR_MASK  0x000000000000003fULL
 271 #define INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT 0
 272 #define INFINIPATH_HWE_PCIEPOISONEDTLP      0x0000000010000000ULL
 273 #define INFINIPATH_HWE_PCIECPLTIMEOUT       0x0000000020000000ULL
 274 #define INFINIPATH_HWE_PCIEBUSPARITYXTLH    0x0000000040000000ULL
 275 #define INFINIPATH_HWE_PCIEBUSPARITYXADM    0x0000000080000000ULL
 276 #define INFINIPATH_HWE_PCIEBUSPARITYRADM    0x0000000100000000ULL
 277 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 278 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 279 #define INFINIPATH_HWE_PCIE1PLLFAILED       0x0400000000000000ULL
 280 #define INFINIPATH_HWE_PCIE0PLLFAILED       0x0800000000000000ULL
 281 #define INFINIPATH_HWE_SERDESPLLFAILED      0x1000000000000000ULL
 282
 283 /* kr_extstatus bits */
 284 #define INFINIPATH_EXTS_FREQSEL 0x2
 285 #define INFINIPATH_EXTS_SERDESSEL 0x4
 286 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 287 #define INFINIPATH_EXTS_MEMBIST_FOUND       0x0000000000008000
 288
 289 #define _IPATH_GPIO_SDA_NUM 1
 290 #define _IPATH_GPIO_SCL_NUM 0
 291
 292 #define IPATH_GPIO_SDA (1ULL << \
 293         (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 294 #define IPATH_GPIO_SCL (1ULL << \
 295         (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 296
 297 /*
 298  * Rev2 silicon allows suppressing check for ArmLaunch errors.
 299  * this can speed up short packet sends on systems that do
 300  * not guaranteee write-order.
 301  */
 302 #define INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR (1ULL<<63)
 303
 304 /* 6120 specific hardware errors... */
 305 static const struct ipath_hwerror_msgs ipath_6120_hwerror_msgs[] = {
 306         INFINIPATH_HWE_MSG(PCIEPOISONEDTLP, "PCIe Poisoned TLP"),
 307         INFINIPATH_HWE_MSG(PCIECPLTIMEOUT, "PCIe completion timeout"),
 308         /*
 309          * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
 310          * parity or memory parity error failures, because most likely we
 311          * won't be able to talk to the core of the chip.  Nonetheless, we
 312          * might see them, if they are in parts of the PCIe core that aren't
 313          * essential.
 314          */
 315         INFINIPATH_HWE_MSG(PCIE1PLLFAILED, "PCIePLL1"),
 316         INFINIPATH_HWE_MSG(PCIE0PLLFAILED, "PCIePLL0"),
 317         INFINIPATH_HWE_MSG(PCIEBUSPARITYXTLH, "PCIe XTLH core parity"),
 318         INFINIPATH_HWE_MSG(PCIEBUSPARITYXADM, "PCIe ADM TX core parity"),
 319         INFINIPATH_HWE_MSG(PCIEBUSPARITYRADM, "PCIe ADM RX core parity"),
 320         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 321         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 322 };
 323
 324 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 325                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 326                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 327
 328 static int ipath_pe_txe_recover(struct ipath_devdata *);
 329
 330 /**
 331  * ipath_pe_handle_hwerrors - display hardware errors.
 332  * @dd: the infinipath device
 333  * @msg: the output buffer
 334  * @msgl: the size of the output buffer
 335  *
 336  * Use same msg buffer as regular errors to avoid excessive stack
 337  * use.  Most hardware errors are catastrophic, but for right now,
 338  * we'll print them and continue.  We reuse the same message buffer as
 339  * ipath_handle_errors() to avoid excessive stack usage.
 340  */
 341 static void ipath_pe_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 342                                      size_t msgl)
 343 {
 344         ipath_err_t hwerrs;
 345         u32 bits, ctrl;
 346         int isfatal = 0;
 347         char bitsmsg[64];
 348
 349         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 350         if (!hwerrs) {
 351                 /*
 352                  * better than printing cofusing messages
 353                  * This seems to be related to clearing the crc error, or
 354                  * the pll error during init.
 355                  */
 356                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 357                 return;
 358         } else if (hwerrs == ~0ULL) {
 359                 ipath_dev_err(dd, "Read of hardware error status failed "
 360                               "(all bits set); ignoring\n");
 361                 return;
 362         }
 363         ipath_stats.sps_hwerrs++;
 364
 365         /* Always clear the error status register, except MEMBISTFAIL,
 366          * regardless of whether we continue or stop using the chip.
 367          * We want that set so we know it failed, even across driver reload.
 368          * We'll still ignore it in the hwerrmask.  We do this partly for
 369          * diagnostics, but also for support */
 370         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 371                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 372
 373         hwerrs &= dd->ipath_hwerrmask;
 374
 375         /*
 376          * make sure we get this much out, unless told to be quiet,
 377          * or it's occurred within the last 5 seconds
 378          */
 379         if ((hwerrs & ~(dd->ipath_lasthwerror |
 380                         ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF |
 381                           INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC)
 382                          << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT))) ||
 383             (ipath_debug & __IPATH_VERBDBG))
 384                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 385                          "(cleared)\n", (unsigned long long) hwerrs);
 386         dd->ipath_lasthwerror |= hwerrs;
 387
 388         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 389                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 390                               "%llx set\n", (unsigned long long)
 391                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 392
 393         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 394         if (ctrl & INFINIPATH_C_FREEZEMODE) {
 395                 /*
 396                  * parity errors in send memory are recoverable,
 397                  * just cancel the send (if indicated in * sendbuffererror),
 398                  * count the occurrence, unfreeze (if no other handled
 399                  * hardware error bits are set), and continue. They can
 400                  * occur if a processor speculative read is done to the PIO
 401                  * buffer while we are sending a packet, for example.
 402                  */
 403                 if ((hwerrs & TXE_PIO_PARITY) && ipath_pe_txe_recover(dd))
 404                         hwerrs &= ~TXE_PIO_PARITY;
 405                 if (hwerrs) {
 406                         /*
 407                          * if any set that we aren't ignoring only make the
 408                          * complaint once, in case it's stuck or recurring,
 409                          * and we get here multiple times
 410                          */
 411                         if (dd->ipath_flags & IPATH_INITTED) {
 412                                 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 413                                               "mode), no longer usable, SN %.16s\n",
 414                                                   dd->ipath_serial);
 415                                 isfatal = 1;
 416                         }
 417                         /*
 418                          * Mark as having had an error for driver, and also
 419                          * for /sys and status word mapped to user programs.
 420                          * This marks unit as not usable, until reset
 421                          */
 422                         *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 423                         *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 424                         dd->ipath_flags &= ~IPATH_INITTED;
 425                 } else {
 426                         ipath_dbg("Clearing freezemode on ignored hardware "
 427                                   "error\n");
 428                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 429                                          dd->ipath_control);
 430                 }
 431         }
 432
 433         *msg = '\0';
 434
 435         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 436                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 437                         msgl);
 438                 /* ignore from now on, so disable until driver reloaded */
 439                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 440                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 441                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 442                                  dd->ipath_hwerrmask);
 443         }
 444
 445         ipath_format_hwerrors(hwerrs,
 446                               ipath_6120_hwerror_msgs,
 447                               sizeof(ipath_6120_hwerror_msgs)/
 448                               sizeof(ipath_6120_hwerror_msgs[0]),
 449                               msg, msgl);
 450
 451         if (hwerrs & (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK
 452                       << INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT)) {
 453                 bits = (u32) ((hwerrs >>
 454                                INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) &
 455                               INFINIPATH_HWE_PCIEMEMPARITYERR_MASK);
 456                 snprintf(bitsmsg, sizeof bitsmsg,
 457                          "[PCIe Mem Parity Errs %x] ", bits);
 458                 strlcat(msg, bitsmsg, msgl);
 459         }
 460
 461 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 462                          INFINIPATH_HWE_COREPLL_RFSLIP )
 463
 464         if (hwerrs & _IPATH_PLL_FAIL) {
 465                 snprintf(bitsmsg, sizeof bitsmsg,
 466                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 467                          (unsigned long long) hwerrs & _IPATH_PLL_FAIL);
 468                 strlcat(msg, bitsmsg, msgl);
 469                 /* ignore from now on, so disable until driver reloaded */
 470                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 471                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 472                                  dd->ipath_hwerrmask);
 473         }
 474
 475         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 476                 /*
 477                  * If it occurs, it is left masked since the eternal
 478                  * interface is unused
 479                  */
 480                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 481                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 482                                  dd->ipath_hwerrmask);
 483         }
 484
 485         ipath_dev_err(dd, "%s hardware error\n", msg);
 486         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg) {
 487                 /*
 488                  * for /sys status file ; if no trailing } is copied, we'll
 489                  * know it was truncated.
 490                  */
 491                 snprintf(dd->ipath_freezemsg, dd->ipath_freezelen,
 492                          "{%s}", msg);
 493         }
 494 }
 495
 496 /**
 497  * ipath_pe_boardname - fill in the board name
 498  * @dd: the infinipath device
 499  * @name: the output buffer
 500  * @namelen: the size of the output buffer
 501  *
 502  * info is based on the board revision register
 503  */
 504 static int ipath_pe_boardname(struct ipath_devdata *dd, char *name,
 505                               size_t namelen)
 506 {
 507         char *n = NULL;
 508         u8 boardrev = dd->ipath_boardrev;
 509         int ret;
 510
 511         switch (boardrev) {
 512         case 0:
 513                 n = "InfiniPath_Emulation";
 514                 break;
 515         case 1:
 516                 n = "InfiniPath_QLE7140-Bringup";
 517                 break;
 518         case 2:
 519                 n = "InfiniPath_QLE7140";
 520                 break;
 521         case 3:
 522                 n = "InfiniPath_QMI7140";
 523                 break;
 524         case 4:
 525                 n = "InfiniPath_QEM7140";
 526                 break;
 527         case 5:
 528                 n = "InfiniPath_QMH7140";
 529                 break;
 530         case 6:
 531                 n = "InfiniPath_QLE7142";
 532                 break;
 533         default:
 534                 ipath_dev_err(dd,
 535                               "Don't yet know about board with ID %u\n",
 536                               boardrev);
 537                 snprintf(name, namelen, "Unknown_InfiniPath_PCIe_%u",
 538                          boardrev);
 539                 break;
 540         }
 541         if (n)
 542                 snprintf(name, namelen, "%s", n);
 543
 544         if (dd->ipath_majrev != 4 || !dd->ipath_minrev || dd->ipath_minrev>2) {
 545                 ipath_dev_err(dd, "Unsupported InfiniPath hardware revision %u.%u!\n",
 546                               dd->ipath_majrev, dd->ipath_minrev);
 547                 ret = 1;
 548         } else
 549                 ret = 0;
 550
 551         return ret;
 552 }
 553
 554 /**
 555  * ipath_pe_init_hwerrors - enable hardware errors
 556  * @dd: the infinipath device
 557  *
 558  * now that we have finished initializing everything that might reasonably
 559  * cause a hardware error, and cleared those errors bits as they occur,
 560  * we can enable hardware errors in the mask (potentially enabling
 561  * freeze mode), and enable hardware errors as errors (along with
 562  * everything else) in errormask
 563  */
 564 static void ipath_pe_init_hwerrors(struct ipath_devdata *dd)
 565 {
 566         ipath_err_t val;
 567         u64 extsval;
 568
 569         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 570
 571         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
 572                 ipath_dev_err(dd, "MemBIST did not complete!\n");
 573         if (extsval & INFINIPATH_EXTS_MEMBIST_FOUND)
 574                 ipath_dbg("MemBIST corrected\n");
 575
 576         val = ~0ULL;    /* barring bugs, all hwerrors become interrupts, */
 577
 578         if (!dd->ipath_boardrev)        // no PLL for Emulator
 579                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 580
 581         if (dd->ipath_minrev < 2) {
 582                 /* workaround bug 9460 in internal interface bus parity
 583                  * checking. Fixed (HW bug 9490) in Rev2.
 584                  */
 585                 val &= ~INFINIPATH_HWE_PCIEBUSPARITYRADM;
 586         }
 587         dd->ipath_hwerrmask = val;
 588 }
 589
 590 /**
 591  * ipath_pe_bringup_serdes - bring up the serdes
 592  * @dd: the infinipath device
 593  */
 594 static int ipath_pe_bringup_serdes(struct ipath_devdata *dd)
 595 {
 596         u64 val, config1, prev_val;
 597         int ret = 0;
 598
 599         ipath_dbg("Trying to bringup serdes\n");
 600
 601         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
 602             INFINIPATH_HWE_SERDESPLLFAILED) {
 603                 ipath_dbg("At start, serdes PLL failed bit set "
 604                           "in hwerrstatus, clearing and continuing\n");
 605                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 606                                  INFINIPATH_HWE_SERDESPLLFAILED);
 607         }
 608
 609         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 610         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
 611
 612         ipath_cdbg(VERBOSE, "SerDes status config0=%llx config1=%llx, "
 613                    "xgxsconfig %llx\n", (unsigned long long) val,
 614                    (unsigned long long) config1, (unsigned long long)
 615                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 616
 617         /*
 618          * Force reset on, also set rxdetect enable.  Must do before reading
 619          * serdesstatus at least for simulation, or some of the bits in
 620          * serdes status will come back as undefined and cause simulation
 621          * failures
 622          */
 623         val |= INFINIPATH_SERDC0_RESET_PLL | INFINIPATH_SERDC0_RXDETECT_EN
 624                 | INFINIPATH_SERDC0_L1PWR_DN;
 625         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 626         /* be sure chip saw it */
 627         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 628         udelay(5);              /* need pll reset set at least for a bit */
 629         /*
 630          * after PLL is reset, set the per-lane Resets and TxIdle and
 631          * clear the PLL reset and rxdetect (to get falling edge).
 632          * Leave L1PWR bits set (permanently)
 633          */
 634         val &= ~(INFINIPATH_SERDC0_RXDETECT_EN | INFINIPATH_SERDC0_RESET_PLL
 635                  | INFINIPATH_SERDC0_L1PWR_DN);
 636         val |= INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE;
 637         ipath_cdbg(VERBOSE, "Clearing pll reset and setting lane resets "
 638                    "and txidle (%llx)\n", (unsigned long long) val);
 639         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 640         /* be sure chip saw it */
 641         ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 642         /* need PLL reset clear for at least 11 usec before lane
 643          * resets cleared; give it a few more to be sure */
 644         udelay(15);
 645         val &= ~(INFINIPATH_SERDC0_RESET_MASK | INFINIPATH_SERDC0_TXIDLE);
 646
 647         ipath_cdbg(VERBOSE, "Clearing lane resets and txidle "
 648                    "(writing %llx)\n", (unsigned long long) val);
 649         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 650         /* be sure chip saw it */
 651         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
 652
 653         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
 654         prev_val = val;
 655         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
 656              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
 657                 val &=
 658                         ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
 659                           INFINIPATH_XGXS_MDIOADDR_SHIFT);
 660                 /* MDIO address 3 */
 661                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
 662         }
 663         if (val & INFINIPATH_XGXS_RESET) {
 664                 val &= ~INFINIPATH_XGXS_RESET;
 665         }
 666         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
 667              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
 668                 /* need to compensate for Tx inversion in partner */
 669                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
 670                          INFINIPATH_XGXS_RX_POL_SHIFT);
 671                 val |= dd->ipath_rx_pol_inv <<
 672                         INFINIPATH_XGXS_RX_POL_SHIFT;
 673         }
 674         if (dd->ipath_minrev >= 2) {
 675                 /* Rev 2. can tolerate multiple writes to PBC, and
 676                  * allowing them can provide lower latency on some
 677                  * CPUs, but this feature is off by default, only
 678                  * turned on by setting D63 of XGXSconfig reg.
 679                  * May want to make this conditional more
 680                  * fine-grained in future. This is not exactly
 681                  * related to XGXS, but where the bit ended up.
 682                  */
 683                 val |= INFINIPATH_XGXS_SUPPRESS_ARMLAUNCH_ERR;
 684         }
 685         if (val != prev_val)
 686                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
 687
 688         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 689
 690         /* clear current and de-emphasis bits */
 691         config1 &= ~0x0ffffffff00ULL;
 692         /* set current to 20ma */
 693         config1 |= 0x00000000000ULL;
 694         /* set de-emphasis to -5.68dB */
 695         config1 |= 0x0cccc000000ULL;
 696         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
 697
 698         ipath_cdbg(VERBOSE, "done: SerDes status config0=%llx "
 699                    "config1=%llx, sstatus=%llx xgxs=%llx\n",
 700                    (unsigned long long) val, (unsigned long long) config1,
 701                    (unsigned long long)
 702                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
 703                    (unsigned long long)
 704                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
 705
 706         if (!ipath_waitfor_mdio_cmdready(dd)) {
 707                 ipath_write_kreg(
 708                         dd, dd->ipath_kregs->kr_mdio,
 709                         ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
 710                                        IPATH_MDIO_CTRL_XGXS_REG_8, 0));
 711                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
 712                                            IPATH_MDIO_DATAVALID, &val))
 713                         ipath_dbg("Never got MDIO data for XGXS "
 714                                   "status read\n");
 715                 else
 716                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
 717                                    "'bank' 31 %x\n", (u32) val);
 718         } else
 719                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
 720
 721         return ret;
 722 }
 723
 724 /**
 725  * ipath_pe_quiet_serdes - set serdes to txidle
 726  * @dd: the infinipath device
 727  * Called when driver is being unloaded
 728  */
 729 static void ipath_pe_quiet_serdes(struct ipath_devdata *dd)
 730 {
 731         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
 732
 733         val |= INFINIPATH_SERDC0_TXIDLE;
 734         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
 735                   (unsigned long long) val);
 736         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
 737 }
 738
 739 static int ipath_pe_intconfig(struct ipath_devdata *dd)
 740 {
 741         u64 val;
 742         u32 chiprev;
 743
 744         /*
 745          * If the chip supports added error indication via GPIO pins,
 746          * enable interrupts on those bits so the interrupt routine
 747          * can count the events. Also set flag so interrupt routine
 748          * can know they are expected.
 749          */
 750         chiprev = dd->ipath_revision >> INFINIPATH_R_CHIPREVMINOR_SHIFT;
 751         if ((chiprev & INFINIPATH_R_CHIPREVMINOR_MASK) > 1) {
 752                 /* Rev2+ reports extra errors via internal GPIO pins */
 753                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
 754                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_mask);
 755                 val |= IPATH_GPIO_ERRINTR_MASK;
 756                 ipath_write_kreg( dd, dd->ipath_kregs->kr_gpio_mask, val);
 757         }
 758         return 0;
 759 }
 760
 761 /**
 762  * ipath_setup_pe_setextled - set the state of the two external LEDs
 763  * @dd: the infinipath device
 764  * @lst: the L state
 765  * @ltst: the LT state
 766
 767  * These LEDs indicate the physical and logical state of IB link.
 768  * For this chip (at least with recommended board pinouts), LED1
 769  * is Yellow (logical state) and LED2 is Green (physical state),
 770  *
 771  * Note:  We try to match the Mellanox HCA LED behavior as best
 772  * we can.  Green indicates physical link state is OK (something is
 773  * plugged in, and we can train).
 774  * Amber indicates the link is logically up (ACTIVE).
 775  * Mellanox further blinks the amber LED to indicate data packet
 776  * activity, but we have no hardware support for that, so it would
 777  * require waking up every 10-20 msecs and checking the counters
 778  * on the chip, and then turning the LED off if appropriate.  That's
 779  * visible overhead, so not something we will do.
 780  *
 781  */
 782 static void ipath_setup_pe_setextled(struct ipath_devdata *dd, u64 lst,
 783                                      u64 ltst)
 784 {
 785         u64 extctl;
 786
 787         /* the diags use the LED to indicate diag info, so we leave
 788          * the external LED alone when the diags are running */
 789         if (ipath_diag_inuse)
 790                 return;
 791
 792         extctl = dd->ipath_extctrl & ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
 793                                        INFINIPATH_EXTC_LED2PRIPORT_ON);
 794
 795         if (ltst & INFINIPATH_IBCS_LT_STATE_LINKUP)
 796                 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
 797         if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
 798                 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
 799         dd->ipath_extctrl = extctl;
 800         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
 801 }
 802
 803 /**
 804  * ipath_setup_pe_cleanup - clean up any per-chip chip-specific stuff
 805  * @dd: the infinipath device
 806  *
 807  * This is called during driver unload.
 808  * We do the pci_disable_msi here, not in generic code, because it
 809  * isn't used for the HT chips. If we do end up needing pci_enable_msi
 810  * at some point in the future for HT, we'll move the call back
 811  * into the main init_one code.
 812  */
 813 static void ipath_setup_pe_cleanup(struct ipath_devdata *dd)
 814 {
 815         dd->ipath_msi_lo = 0;   /* just in case unload fails */
 816         pci_disable_msi(dd->pcidev);
 817 }
 818
 819 /**
 820  * ipath_setup_pe_config - setup PCIe config related stuff
 821  * @dd: the infinipath device
 822  * @pdev: the PCI device
 823  *
 824  * The pci_enable_msi() call will fail on systems with MSI quirks
 825  * such as those with AMD8131, even if the device of interest is not
 826  * attached to that device, (in the 2.6.13 - 2.6.15 kernels, at least, fixed
 827  * late in 2.6.16).
 828  * All that can be done is to edit the kernel source to remove the quirk
 829  * check until that is fixed.
 830  * We do not need to call enable_msi() for our HyperTransport chip,
 831  * even though it uses MSI, and we want to avoid the quirk warning, so
 832  * So we call enable_msi only for PCIe.  If we do end up needing
 833  * pci_enable_msi at some point in the future for HT, we'll move the
 834  * call back into the main init_one code.
 835  * We save the msi lo and hi values, so we can restore them after
 836  * chip reset (the kernel PCI infrastructure doesn't yet handle that
 837  * correctly).
 838  */
 839 static int ipath_setup_pe_config(struct ipath_devdata *dd,
 840                                  struct pci_dev *pdev)
 841 {
 842         int pos, ret;
 843
 844         dd->ipath_msi_lo = 0;   /* used as a flag during reset processing */
 845         ret = pci_enable_msi(dd->pcidev);
 846         if (ret)
 847                 ipath_dev_err(dd, "pci_enable_msi failed: %d, "
 848                               "interrupts may not work\n", ret);
 849         /* continue even if it fails, we may still be OK... */
 850         dd->ipath_irq = pdev->irq;
 851
 852         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 853                 u16 control;
 854                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 855                                       &dd->ipath_msi_lo);
 856                 pci_read_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 857                                       &dd->ipath_msi_hi);
 858                 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 859                                      &control);
 860                 /* now save the data (vector) info */
 861                 pci_read_config_word(dd->pcidev,
 862                                      pos + ((control & PCI_MSI_FLAGS_64BIT)
 863                                             ? 12 : 8),
 864                                      &dd->ipath_msi_data);
 865                 ipath_cdbg(VERBOSE, "Read msi data 0x%x from config offset "
 866                            "0x%x, control=0x%x\n", dd->ipath_msi_data,
 867                            pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
 868                            control);
 869                 /* we save the cachelinesize also, although it doesn't
 870                  * really matter */
 871                 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
 872                                      &dd->ipath_pci_cacheline);
 873         } else
 874                 ipath_dev_err(dd, "Can't find MSI capability, "
 875                               "can't save MSI settings for reset\n");
 876         if ((pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_EXP))) {
 877                 u16 linkstat;
 878                 pci_read_config_word(dd->pcidev, pos + PCI_EXP_LNKSTA,
 879                                      &linkstat);
 880                 linkstat >>= 4;
 881                 linkstat &= 0x1f;
 882                 if (linkstat != 8)
 883                         ipath_dev_err(dd, "PCIe width %u, "
 884                                       "performance reduced\n", linkstat);
 885         }
 886         else
 887                 ipath_dev_err(dd, "Can't find PCI Express "
 888                               "capability!\n");
 889         return 0;
 890 }
 891
 892 static void ipath_init_pe_variables(struct ipath_devdata *dd)
 893 {
 894         /*
 895          * bits for selecting i2c direction and values,
 896          * used for I2C serial flash
 897          */
 898         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
 899         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
 900         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
 901         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
 902
 903         /* variables for sanity checking interrupt and errors */
 904         dd->ipath_hwe_bitsextant =
 905                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
 906                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
 907                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
 908                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
 909                 (INFINIPATH_HWE_PCIEMEMPARITYERR_MASK <<
 910                  INFINIPATH_HWE_PCIEMEMPARITYERR_SHIFT) |
 911                 INFINIPATH_HWE_PCIE1PLLFAILED |
 912                 INFINIPATH_HWE_PCIE0PLLFAILED |
 913                 INFINIPATH_HWE_PCIEPOISONEDTLP |
 914                 INFINIPATH_HWE_PCIECPLTIMEOUT |
 915                 INFINIPATH_HWE_PCIEBUSPARITYXTLH |
 916                 INFINIPATH_HWE_PCIEBUSPARITYXADM |
 917                 INFINIPATH_HWE_PCIEBUSPARITYRADM |
 918                 INFINIPATH_HWE_MEMBISTFAILED |
 919                 INFINIPATH_HWE_COREPLL_FBSLIP |
 920                 INFINIPATH_HWE_COREPLL_RFSLIP |
 921                 INFINIPATH_HWE_SERDESPLLFAILED |
 922                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
 923                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
 924         dd->ipath_i_bitsextant =
 925                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
 926                 (INFINIPATH_I_RCVAVAIL_MASK <<
 927                  INFINIPATH_I_RCVAVAIL_SHIFT) |
 928                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
 929                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
 930         dd->ipath_e_bitsextant =
 931                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
 932                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
 933                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
 934                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
 935                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
 936                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
 937                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
 938                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
 939                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
 940                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
 941                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
 942                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
 943                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
 944                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
 945                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
 946                 INFINIPATH_E_HARDWARE;
 947
 948         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
 949         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
 950 }
 951
 952 /* setup the MSI stuff again after a reset.  I'd like to just call
 953  * pci_enable_msi() and request_irq() again, but when I do that,
 954  * the MSI enable bit doesn't get set in the command word, and
 955  * we switch to to a different interrupt vector, which is confusing,
 956  * so I instead just do it all inline.  Perhaps somehow can tie this
 957  * into the PCIe hotplug support at some point
 958  * Note, because I'm doing it all here, I don't call pci_disable_msi()
 959  * or free_irq() at the start of ipath_setup_pe_reset().
 960  */
 961 static int ipath_reinit_msi(struct ipath_devdata *dd)
 962 {
 963         int pos;
 964         u16 control;
 965         int ret;
 966
 967         if (!dd->ipath_msi_lo) {
 968                 dev_info(&dd->pcidev->dev, "Can't restore MSI config, "
 969                          "initial setup failed?\n");
 970                 ret = 0;
 971                 goto bail;
 972         }
 973
 974         if (!(pos = pci_find_capability(dd->pcidev, PCI_CAP_ID_MSI))) {
 975                 ipath_dev_err(dd, "Can't find MSI capability, "
 976                               "can't restore MSI settings\n");
 977                 ret = 0;
 978                 goto bail;
 979         }
 980         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
 981                    dd->ipath_msi_lo, pos + PCI_MSI_ADDRESS_LO);
 982         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO,
 983                                dd->ipath_msi_lo);
 984         ipath_cdbg(VERBOSE, "Writing msi_lo 0x%x to config offset 0x%x\n",
 985                    dd->ipath_msi_hi, pos + PCI_MSI_ADDRESS_HI);
 986         pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI,
 987                                dd->ipath_msi_hi);
 988         pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control);
 989         if (!(control & PCI_MSI_FLAGS_ENABLE)) {
 990                 ipath_cdbg(VERBOSE, "MSI control at off %x was %x, "
 991                            "setting MSI enable (%x)\n", pos + PCI_MSI_FLAGS,
 992                            control, control | PCI_MSI_FLAGS_ENABLE);
 993                 control |= PCI_MSI_FLAGS_ENABLE;
 994                 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS,
 995                                       control);
 996         }
 997         /* now rewrite the data (vector) info */
 998         pci_write_config_word(dd->pcidev, pos +
 999                               ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8),
1000                               dd->ipath_msi_data);
1001         /* we restore the cachelinesize also, although it doesn't really
1002          * matter */
1003         pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE,
1004                               dd->ipath_pci_cacheline);
1005         /* and now set the pci master bit again */
1006         pci_set_master(dd->pcidev);
1007         ret = 1;
1008
1009 bail:
1010         return ret;
1011 }
1012
1013 /* This routine sleeps, so it can only be called from user context, not
1014  * from interrupt context.  If we need interrupt context, we can split
1015  * it into two routines.
1016 */
1017 static int ipath_setup_pe_reset(struct ipath_devdata *dd)
1018 {
1019         u64 val;
1020         int i;
1021         int ret;
1022
1023         /* Use ERROR so it shows up in logs, etc. */
1024         ipath_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->ipath_unit);
1025         /* keep chip from being accessed in a few places */
1026         dd->ipath_flags &= ~(IPATH_INITTED|IPATH_PRESENT);
1027         val = dd->ipath_control | INFINIPATH_C_RESET;
1028         ipath_write_kreg(dd, dd->ipath_kregs->kr_control, val);
1029         mb();
1030
1031         for (i = 1; i <= 5; i++) {
1032                 int r;
1033                 /* allow MBIST, etc. to complete; longer on each retry.
1034                  * We sometimes get machine checks from bus timeout if no
1035                  * response, so for now, make it *really* long.
1036                  */
1037                 msleep(1000 + (1 + i) * 2000);
1038                 if ((r =
1039                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0,
1040                                             dd->ipath_pcibar0)))
1041                         ipath_dev_err(dd, "rewrite of BAR0 failed: %d\n",
1042                                       r);
1043                 if ((r =
1044                      pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1,
1045                                             dd->ipath_pcibar1)))
1046                         ipath_dev_err(dd, "rewrite of BAR1 failed: %d\n",
1047                                       r);
1048                 /* now re-enable memory access */
1049                 if ((r = pci_enable_device(dd->pcidev)))
1050                         ipath_dev_err(dd, "pci_enable_device failed after "
1051                                       "reset: %d\n", r);
1052                 /* whether it worked or not, mark as present, again */
1053                 dd->ipath_flags |= IPATH_PRESENT;
1054                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_revision);
1055                 if (val == dd->ipath_revision) {
1056                         ipath_cdbg(VERBOSE, "Got matching revision "
1057                                    "register %llx on try %d\n",
1058                                    (unsigned long long) val, i);
1059                         ret = ipath_reinit_msi(dd);
1060                         goto bail;
1061                 }
1062                 /* Probably getting -1 back */
1063                 ipath_dbg("Didn't get expected revision register, "
1064                           "got %llx, try %d\n", (unsigned long long) val,
1065                           i + 1);
1066         }
1067         ret = 0; /* failed */
1068
1069 bail:
1070         return ret;
1071 }
1072
1073 /**
1074  * ipath_pe_put_tid - write a TID in chip
1075  * @dd: the infinipath device
1076  * @tidptr: pointer to the expected TID (in chip) to udpate
1077  * @tidtype: 0 for eager, 1 for expected
1078  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1079  *
1080  * This exists as a separate routine to allow for special locking etc.
1081  * It's used for both the full cleanup on exit, as well as the normal
1082  * setup and teardown.
1083  */
1084 static void ipath_pe_put_tid(struct ipath_devdata *dd, u64 __iomem *tidptr,
1085                              u32 type, unsigned long pa)
1086 {
1087         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1088         unsigned long flags = 0; /* keep gcc quiet */
1089
1090         if (pa != dd->ipath_tidinvalid) {
1091                 if (pa & ((1U << 11) - 1)) {
1092                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1093                                  "not 4KB aligned!\n", pa);
1094                         return;
1095                 }
1096                 pa >>= 11;
1097                 /* paranoia check */
1098                 if (pa & (7<<29))
1099                         ipath_dev_err(dd,
1100                                       "BUG: Physical page address 0x%lx "
1101                                       "has bits set in 31-29\n", pa);
1102
1103                 if (type == 0)
1104                         pa |= dd->ipath_tidtemplate;
1105                 else /* for now, always full 4KB page */
1106                         pa |= 2 << 29;
1107         }
1108
1109         /* workaround chip bug 9437 by writing each TID twice
1110          * and holding a spinlock around the writes, so they don't
1111          * intermix with other TID (eager or expected) writes
1112          * Unfortunately, this call can be done from interrupt level
1113          * for the port 0 eager TIDs, so we have to use irqsave
1114          */
1115         spin_lock_irqsave(&dd->ipath_tid_lock, flags);
1116         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xfeeddeaf);
1117         if (dd->ipath_kregbase)
1118                 writel(pa, tidp32);
1119         ipath_write_kreg(dd, dd->ipath_kregs->kr_scratch, 0xdeadbeef);
1120         mmiowb();
1121         spin_unlock_irqrestore(&dd->ipath_tid_lock, flags);
1122 }
1123 /**
1124  * ipath_pe_put_tid_2 - write a TID in chip, Revision 2 or higher
1125  * @dd: the infinipath device
1126  * @tidptr: pointer to the expected TID (in chip) to udpate
1127  * @tidtype: 0 for eager, 1 for expected
1128  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1129  *
1130  * This exists as a separate routine to allow for selection of the
1131  * appropriate "flavor". The static calls in cleanup just use the
1132  * revision-agnostic form, as they are not performance critical.
1133  */
1134 static void ipath_pe_put_tid_2(struct ipath_devdata *dd, u64 __iomem *tidptr,
1135                              u32 type, unsigned long pa)
1136 {
1137         u32 __iomem *tidp32 = (u32 __iomem *)tidptr;
1138
1139         if (pa != dd->ipath_tidinvalid) {
1140                 if (pa & ((1U << 11) - 1)) {
1141                         dev_info(&dd->pcidev->dev, "BUG: physaddr %lx "
1142                                  "not 2KB aligned!\n", pa);
1143                         return;
1144                 }
1145                 pa >>= 11;
1146                 /* paranoia check */
1147                 if (pa & (7<<29))
1148                         ipath_dev_err(dd,
1149                                       "BUG: Physical page address 0x%lx "
1150                                       "has bits set in 31-29\n", pa);
1151
1152                 if (type == 0)
1153                         pa |= dd->ipath_tidtemplate;
1154                 else /* for now, always full 4KB page */
1155                         pa |= 2 << 29;
1156         }
1157         if (dd->ipath_kregbase)
1158                 writel(pa, tidp32);
1159         mmiowb();
1160 }
1161
1162
1163 /**
1164  * ipath_pe_clear_tid - clear all TID entries for a port, expected and eager
1165  * @dd: the infinipath device
1166  * @port: the port
1167  *
1168  * clear all TID entries for a port, expected and eager.
1169  * Used from ipath_close().  On this chip, TIDs are only 32 bits,
1170  * not 64, but they are still on 64 bit boundaries, so tidbase
1171  * is declared as u64 * for the pointer math, even though we write 32 bits
1172  */
1173 static void ipath_pe_clear_tids(struct ipath_devdata *dd, unsigned port)
1174 {
1175         u64 __iomem *tidbase;
1176         unsigned long tidinv;
1177         int i;
1178
1179         if (!dd->ipath_kregbase)
1180                 return;
1181
1182         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1183
1184         tidinv = dd->ipath_tidinvalid;
1185         tidbase = (u64 __iomem *)
1186                 ((char __iomem *)(dd->ipath_kregbase) +
1187                  dd->ipath_rcvtidbase +
1188                  port * dd->ipath_rcvtidcnt * sizeof(*tidbase));
1189
1190         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1191                 ipath_pe_put_tid(dd, &tidbase[i], 0, tidinv);
1192
1193         tidbase = (u64 __iomem *)
1194                 ((char __iomem *)(dd->ipath_kregbase) +
1195                  dd->ipath_rcvegrbase +
1196                  port * dd->ipath_rcvegrcnt * sizeof(*tidbase));
1197
1198         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1199                 ipath_pe_put_tid(dd, &tidbase[i], 1, tidinv);
1200 }
1201
1202 /**
1203  * ipath_pe_tidtemplate - setup constants for TID updates
1204  * @dd: the infinipath device
1205  *
1206  * We setup stuff that we use a lot, to avoid calculating each time
1207  */
1208 static void ipath_pe_tidtemplate(struct ipath_devdata *dd)
1209 {
1210         u32 egrsize = dd->ipath_rcvegrbufsize;
1211
1212         /* For now, we always allocate 4KB buffers (at init) so we can
1213          * receive max size packets.  We may want a module parameter to
1214          * specify 2KB or 4KB and/or make be per port instead of per device
1215          * for those who want to reduce memory footprint.  Note that the
1216          * ipath_rcvhdrentsize size must be large enough to hold the largest
1217          * IB header (currently 96 bytes) that we expect to handle (plus of
1218          * course the 2 dwords of RHF).
1219          */
1220         if (egrsize == 2048)
1221                 dd->ipath_tidtemplate = 1U << 29;
1222         else if (egrsize == 4096)
1223                 dd->ipath_tidtemplate = 2U << 29;
1224         else {
1225                 egrsize = 4096;
1226                 dev_info(&dd->pcidev->dev, "BUG: unsupported egrbufsize "
1227                          "%u, using %u\n", dd->ipath_rcvegrbufsize,
1228                          egrsize);
1229                 dd->ipath_tidtemplate = 2U << 29;
1230         }
1231         dd->ipath_tidinvalid = 0;
1232 }
1233
1234 static int ipath_pe_early_init(struct ipath_devdata *dd)
1235 {
1236         dd->ipath_flags |= IPATH_4BYTE_TID;
1237
1238         /*
1239          * For openfabrics, we need to be able to handle an IB header of
1240          * 24 dwords.  HT chip has arbitrary sized receive buffers, so we
1241          * made them the same size as the PIO buffers.  This chip does not
1242          * handle arbitrary size buffers, so we need the header large enough
1243          * to handle largest IB header, but still have room for a 2KB MTU
1244          * standard IB packet.
1245          */
1246         dd->ipath_rcvhdrentsize = 24;
1247         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1248
1249         /*
1250          * To truly support a 4KB MTU (for usermode), we need to
1251          * bump this to a larger value.  For now, we use them for
1252          * the kernel only.
1253          */
1254         dd->ipath_rcvegrbufsize = 2048;
1255         /*
1256          * the min() check here is currently a nop, but it may not always
1257          * be, depending on just how we do ipath_rcvegrbufsize
1258          */
1259         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1260                                  dd->ipath_rcvegrbufsize +
1261                                  (dd->ipath_rcvhdrentsize << 2));
1262         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1263
1264         /*
1265          * We can request a receive interrupt for 1 or
1266          * more packets from current offset.  For now, we set this
1267          * up for a single packet.
1268          */
1269         dd->ipath_rhdrhead_intr_off = 1ULL<<32;
1270
1271         ipath_get_eeprom_info(dd);
1272
1273         return 0;
1274 }
1275
1276 int __attribute__((weak)) ipath_unordered_wc(void)
1277 {
1278         return 0;
1279 }
1280
1281 /**
1282  * ipath_init_pe_get_base_info - set chip-specific flags for user code
1283  * @pd: the infinipath port
1284  * @kbase: ipath_base_info pointer
1285  *
1286  * We set the PCIE flag because the lower bandwidth on PCIe vs
1287  * HyperTransport can affect some user packet algorithms.
1288  */
1289 static int ipath_pe_get_base_info(struct ipath_portdata *pd, void *kbase)
1290 {
1291         struct ipath_base_info *kinfo = kbase;
1292         struct ipath_devdata *dd;
1293
1294         if (ipath_unordered_wc()) {
1295                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_FORCE_WC_ORDER;
1296                 ipath_cdbg(PROC, "Intel processor, forcing WC order\n");
1297         }
1298         else
1299                 ipath_cdbg(PROC, "Not Intel processor, WC ordered\n");
1300
1301         if (pd == NULL)
1302                 goto done;
1303
1304         dd = pd->port_dd;
1305
1306         if (dd != NULL && dd->ipath_minrev >= 2) {
1307                 ipath_cdbg(PROC, "IBA6120 Rev2, allow multiple PBC write\n");
1308                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_PBC_REWRITE;
1309                 ipath_cdbg(PROC, "IBA6120 Rev2, allow loose DMA alignment\n");
1310                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_LOOSE_DMA_ALIGN;
1311         }
1312
1313 done:
1314         kinfo->spi_runtime_flags |= IPATH_RUNTIME_PCIE;
1315         return 0;
1316 }
1317
1318 static void ipath_pe_free_irq(struct ipath_devdata *dd)
1319 {
1320         free_irq(dd->ipath_irq, dd);
1321         dd->ipath_irq = 0;
1322 }
1323
1324 /*
1325  * On platforms using this chip, and not having ordered WC stores, we
1326  * can get TXE parity errors due to speculative reads to the PIO buffers,
1327  * and this, due to a chip bug can result in (many) false parity error
1328  * reports.  So it's a debug print on those, and an info print on systems
1329  * where the speculative reads don't occur.
1330  * Because we can get lots of false errors, we have no upper limit
1331  * on recovery attempts on those platforms.
1332  */
1333 static int ipath_pe_txe_recover(struct ipath_devdata *dd)
1334 {
1335         if (ipath_unordered_wc())
1336                 ipath_dbg("Recovering from TXE PIO parity error\n");
1337         else {
1338                 int cnt = ++ipath_stats.sps_txeparity;
1339                 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1340                         if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1341                                 ipath_dev_err(dd,
1342                                         "Too many attempts to recover from "
1343                                         "TXE parity, giving up\n");
1344                         return 0;
1345                 }
1346                 dev_info(&dd->pcidev->dev,
1347                         "Recovering from TXE PIO parity error\n");
1348         }
1349         ipath_disarm_senderrbufs(dd, 1);
1350         return 1;
1351 }
1352
1353 /**
1354  * ipath_init_iba6120_funcs - set up the chip-specific function pointers
1355  * @dd: the infinipath device
1356  *
1357  * This is global, and is called directly at init to set up the
1358  * chip-specific function pointers for later use.
1359  */
1360 void ipath_init_iba6120_funcs(struct ipath_devdata *dd)
1361 {
1362         dd->ipath_f_intrsetup = ipath_pe_intconfig;
1363         dd->ipath_f_bus = ipath_setup_pe_config;
1364         dd->ipath_f_reset = ipath_setup_pe_reset;
1365         dd->ipath_f_get_boardname = ipath_pe_boardname;
1366         dd->ipath_f_init_hwerrors = ipath_pe_init_hwerrors;
1367         dd->ipath_f_early_init = ipath_pe_early_init;
1368         dd->ipath_f_handle_hwerrors = ipath_pe_handle_hwerrors;
1369         dd->ipath_f_quiet_serdes = ipath_pe_quiet_serdes;
1370         dd->ipath_f_bringup_serdes = ipath_pe_bringup_serdes;
1371         dd->ipath_f_clear_tids = ipath_pe_clear_tids;
1372         if (dd->ipath_minrev >= 2)
1373                 dd->ipath_f_put_tid = ipath_pe_put_tid_2;
1374         else
1375                 dd->ipath_f_put_tid = ipath_pe_put_tid;
1376         dd->ipath_f_cleanup = ipath_setup_pe_cleanup;
1377         dd->ipath_f_setextled = ipath_setup_pe_setextled;
1378         dd->ipath_f_get_base_info = ipath_pe_get_base_info;
1379         dd->ipath_f_free_irq = ipath_pe_free_irq;
1380
1381         /* initialize chip-specific variables */
1382         dd->ipath_f_tidtemplate = ipath_pe_tidtemplate;
1383
1384         /*
1385          * setup the register offsets, since they are different for each
1386          * chip
1387          */
1388         dd->ipath_kregs = &ipath_pe_kregs;
1389         dd->ipath_cregs = &ipath_pe_cregs;
1390
1391         ipath_init_pe_variables(dd);
1392 }
1393