2 * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
3 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the InfiniPath
39 #include <linux/vmalloc.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/htirq.h>
44 #include "ipath_kernel.h"
45 #include "ipath_registers.h"
47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
51 * This lists the InfiniPath registers, in the actual chip layout.
52 * This structure should never be directly accessed.
54 * The names are in InterCap form because they're taken straight from
55 * the chip specification. Since they're only used in this file, they
56 * don't pollute the rest of the source.
59 struct _infinipath_do_not_use_kernel_regs {
60 unsigned long long Revision;
61 unsigned long long Control;
62 unsigned long long PageAlign;
63 unsigned long long PortCnt;
64 unsigned long long DebugPortSelect;
65 unsigned long long DebugPort;
66 unsigned long long SendRegBase;
67 unsigned long long UserRegBase;
68 unsigned long long CounterRegBase;
69 unsigned long long Scratch;
70 unsigned long long ReservedMisc1;
71 unsigned long long InterruptConfig;
72 unsigned long long IntBlocked;
73 unsigned long long IntMask;
74 unsigned long long IntStatus;
75 unsigned long long IntClear;
76 unsigned long long ErrorMask;
77 unsigned long long ErrorStatus;
78 unsigned long long ErrorClear;
79 unsigned long long HwErrMask;
80 unsigned long long HwErrStatus;
81 unsigned long long HwErrClear;
82 unsigned long long HwDiagCtrl;
83 unsigned long long MDIO;
84 unsigned long long IBCStatus;
85 unsigned long long IBCCtrl;
86 unsigned long long ExtStatus;
87 unsigned long long ExtCtrl;
88 unsigned long long GPIOOut;
89 unsigned long long GPIOMask;
90 unsigned long long GPIOStatus;
91 unsigned long long GPIOClear;
92 unsigned long long RcvCtrl;
93 unsigned long long RcvBTHQP;
94 unsigned long long RcvHdrSize;
95 unsigned long long RcvHdrCnt;
96 unsigned long long RcvHdrEntSize;
97 unsigned long long RcvTIDBase;
98 unsigned long long RcvTIDCnt;
99 unsigned long long RcvEgrBase;
100 unsigned long long RcvEgrCnt;
101 unsigned long long RcvBufBase;
102 unsigned long long RcvBufSize;
103 unsigned long long RxIntMemBase;
104 unsigned long long RxIntMemSize;
105 unsigned long long RcvPartitionKey;
106 unsigned long long ReservedRcv[10];
107 unsigned long long SendCtrl;
108 unsigned long long SendPIOBufBase;
109 unsigned long long SendPIOSize;
110 unsigned long long SendPIOBufCnt;
111 unsigned long long SendPIOAvailAddr;
112 unsigned long long TxIntMemBase;
113 unsigned long long TxIntMemSize;
114 unsigned long long ReservedSend[9];
115 unsigned long long SendBufferError;
116 unsigned long long SendBufferErrorCONT1;
117 unsigned long long SendBufferErrorCONT2;
118 unsigned long long SendBufferErrorCONT3;
119 unsigned long long ReservedSBE[4];
120 unsigned long long RcvHdrAddr0;
121 unsigned long long RcvHdrAddr1;
122 unsigned long long RcvHdrAddr2;
123 unsigned long long RcvHdrAddr3;
124 unsigned long long RcvHdrAddr4;
125 unsigned long long RcvHdrAddr5;
126 unsigned long long RcvHdrAddr6;
127 unsigned long long RcvHdrAddr7;
128 unsigned long long RcvHdrAddr8;
129 unsigned long long ReservedRHA[7];
130 unsigned long long RcvHdrTailAddr0;
131 unsigned long long RcvHdrTailAddr1;
132 unsigned long long RcvHdrTailAddr2;
133 unsigned long long RcvHdrTailAddr3;
134 unsigned long long RcvHdrTailAddr4;
135 unsigned long long RcvHdrTailAddr5;
136 unsigned long long RcvHdrTailAddr6;
137 unsigned long long RcvHdrTailAddr7;
138 unsigned long long RcvHdrTailAddr8;
139 unsigned long long ReservedRHTA[7];
140 unsigned long long Sync; /* Software only */
141 unsigned long long Dump; /* Software only */
142 unsigned long long SimVer; /* Software only */
143 unsigned long long ReservedSW[5];
144 unsigned long long SerdesConfig0;
145 unsigned long long SerdesConfig1;
146 unsigned long long SerdesStatus;
147 unsigned long long XGXSConfig;
148 unsigned long long ReservedSW2[4];
151 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
152 _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
153 #define IPATH_CREG_OFFSET(field) (offsetof( \
154 struct infinipath_counters, field) / sizeof(u64))
156 static const struct ipath_kregs ipath_ht_kregs = {
157 .kr_control = IPATH_KREG_OFFSET(Control),
158 .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
159 .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
160 .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
161 .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
162 .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
163 .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
164 .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
165 .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
166 .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
167 .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
168 .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
169 .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
170 .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
171 .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
172 .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
173 .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
174 .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
175 .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
176 .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
177 .kr_intclear = IPATH_KREG_OFFSET(IntClear),
178 .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
179 .kr_intmask = IPATH_KREG_OFFSET(IntMask),
180 .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
181 .kr_mdio = IPATH_KREG_OFFSET(MDIO),
182 .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
183 .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
184 .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
185 .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
186 .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
187 .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
188 .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
189 .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
190 .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
191 .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
192 .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
193 .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
194 .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
195 .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
196 .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
197 .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
198 .kr_revision = IPATH_KREG_OFFSET(Revision),
199 .kr_scratch = IPATH_KREG_OFFSET(Scratch),
200 .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
201 .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
202 .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
203 .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
204 .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
205 .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
206 .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
207 .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
208 .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
209 .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
210 .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
211 .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
212 .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
213 .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
215 * These should not be used directly via ipath_write_kreg64(),
216 * use them with ipath_write_kreg64_port(),
218 .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
219 .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
222 static const struct ipath_cregs ipath_ht_cregs = {
223 .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
224 .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
225 .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
226 .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
227 .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
228 .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
229 .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
230 .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
231 .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
232 .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
233 .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
234 .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
235 /* calc from Reg_CounterRegBase + offset */
236 .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
237 .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
238 .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
239 .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
240 .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
241 .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
242 .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
243 .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
244 .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
245 .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
246 .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
247 .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
248 .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
249 .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
250 .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
251 .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
252 .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
253 .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
254 .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
255 .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
256 .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
259 /* kr_intstatus, kr_intclear, kr_intmask bits */
260 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
261 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
263 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
264 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
265 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
266 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR 0x0000000000800000ULL
267 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR 0x0000000001000000ULL
268 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR 0x0000000002000000ULL
269 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR 0x0000000004000000ULL
270 #define INFINIPATH_HWE_HTCMISCERR4 0x0000000008000000ULL
271 #define INFINIPATH_HWE_HTCMISCERR5 0x0000000010000000ULL
272 #define INFINIPATH_HWE_HTCMISCERR6 0x0000000020000000ULL
273 #define INFINIPATH_HWE_HTCMISCERR7 0x0000000040000000ULL
274 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR 0x0000000080000000ULL
275 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
276 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR 0x0000000200000000ULL
277 #define INFINIPATH_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
278 #define INFINIPATH_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
279 #define INFINIPATH_HWE_HTBPLL_FBSLIP 0x0200000000000000ULL
280 #define INFINIPATH_HWE_HTBPLL_RFSLIP 0x0400000000000000ULL
281 #define INFINIPATH_HWE_HTAPLL_FBSLIP 0x0800000000000000ULL
282 #define INFINIPATH_HWE_HTAPLL_RFSLIP 0x1000000000000000ULL
283 #define INFINIPATH_HWE_SERDESPLLFAILED 0x2000000000000000ULL
285 /* kr_extstatus bits */
286 #define INFINIPATH_EXTS_FREQSEL 0x2
287 #define INFINIPATH_EXTS_SERDESSEL 0x4
288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST 0x0000000000004000
289 #define INFINIPATH_EXTS_MEMBIST_CORRECT 0x0000000000008000
292 /* TID entries (memory), HT-only */
293 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
294 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
295 #define INFINIPATH_RT_ADDR_SHIFT 0
296 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
297 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
299 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
300 #define INFINIPATH_R_TAILUPD_SHIFT 31
302 /* kr_xgxsconfig bits */
303 #define INFINIPATH_XGXS_RESET 0x7ULL
306 * masks and bits that are different in different chips, or present only
309 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
310 INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
311 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
312 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
314 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
315 INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
316 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
317 INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
318 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
319 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
320 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
321 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
323 #define _IPATH_GPIO_SDA_NUM 1
324 #define _IPATH_GPIO_SCL_NUM 0
326 #define IPATH_GPIO_SDA \
327 (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
328 #define IPATH_GPIO_SCL \
329 (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
331 /* keep the code below somewhat more readonable; not used elsewhere */
332 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
333 infinipath_hwe_htclnkabyte1crcerr)
334 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr | \
335 infinipath_hwe_htclnkbbyte1crcerr)
336 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr | \
337 infinipath_hwe_htclnkbbyte0crcerr)
338 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr | \
339 infinipath_hwe_htclnkbbyte1crcerr)
341 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
342 char *msg, size_t msgl)
345 ipath_err_t crcbits = hwerrs &
346 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
347 /* don't check if 8bit HT */
348 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
349 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
350 /* don't check if 8bit HT */
351 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
352 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
354 * we'll want to ignore link errors on link that is
355 * not in use, if any. For now, complain about both
359 snprintf(bitsmsg, sizeof bitsmsg,
360 "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
361 !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
362 "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
363 ? "1 (B)" : "0+1 (A+B)"),
364 !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
365 : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
366 "0+1"), (unsigned long long) crcbits);
367 strlcat(msg, bitsmsg, msgl);
370 * print extra info for debugging. slave/primary
371 * config word 4, 8 (link control 0, 1)
374 if (pci_read_config_word(dd->pcidev,
375 dd->ipath_ht_slave_off + 0x4,
377 dev_info(&dd->pcidev->dev, "Couldn't read "
378 "linkctrl0 of slave/primary "
380 else if (!(ctrl0 & 1 << 6))
381 /* not if EOC bit set */
382 ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
383 ((ctrl0 >> 8) & 7) ? " CRC" : "",
384 ((ctrl0 >> 4) & 1) ? "linkfail" :
386 if (pci_read_config_word(dd->pcidev,
387 dd->ipath_ht_slave_off + 0x8,
389 dev_info(&dd->pcidev->dev, "Couldn't read "
390 "linkctrl1 of slave/primary "
392 else if (!(ctrl1 & 1 << 6))
393 /* not if EOC bit set */
394 ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
395 ((ctrl1 >> 8) & 7) ? " CRC" : "",
396 ((ctrl1 >> 4) & 1) ? "linkfail" :
399 /* disable until driver reloaded */
400 dd->ipath_hwerrmask &= ~crcbits;
401 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
402 dd->ipath_hwerrmask);
403 ipath_dbg("HT crc errs: %s\n", msg);
405 ipath_dbg("ignoring HT crc errors 0x%llx, "
406 "not in use\n", (unsigned long long)
407 (hwerrs & (_IPATH_HTLINK0_CRCBITS |
408 _IPATH_HTLINK1_CRCBITS)));
411 /* 6110 specific hardware errors... */
412 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
413 INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
414 INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
415 INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
416 INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
417 INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
418 INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
419 INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
420 INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
423 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
424 INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
425 << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
426 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
427 << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
429 static int ipath_ht_txe_recover(struct ipath_devdata *);
432 * ipath_ht_handle_hwerrors - display hardware errors.
433 * @dd: the infinipath device
434 * @msg: the output buffer
435 * @msgl: the size of the output buffer
437 * Use same msg buffer as regular errors to avoid excessive stack
438 * use. Most hardware errors are catastrophic, but for right now,
439 * we'll print them and continue. We reuse the same message buffer as
440 * ipath_handle_errors() to avoid excessive stack usage.
442 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
451 hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
454 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
456 * better than printing cofusing messages
457 * This seems to be related to clearing the crc error, or
458 * the pll error during init.
461 } else if (hwerrs == -1LL) {
462 ipath_dev_err(dd, "Read of hardware error status failed "
463 "(all bits set); ignoring\n");
466 ipath_stats.sps_hwerrs++;
468 /* Always clear the error status register, except MEMBISTFAIL,
469 * regardless of whether we continue or stop using the chip.
470 * We want that set so we know it failed, even across driver reload.
471 * We'll still ignore it in the hwerrmask. We do this partly for
472 * diagnostics, but also for support */
473 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
474 hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
476 hwerrs &= dd->ipath_hwerrmask;
478 /* We log some errors to EEPROM, check if we have any of those. */
479 for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
480 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
481 ipath_inc_eeprom_err(dd, log_idx, 1);
484 * make sure we get this much out, unless told to be quiet,
485 * it's a parity error we may recover from,
486 * or it's occurred within the last 5 seconds
488 if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
489 RXE_EAGER_PARITY)) ||
490 (ipath_debug & __IPATH_VERBDBG))
491 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
492 "(cleared)\n", (unsigned long long) hwerrs);
493 dd->ipath_lasthwerror |= hwerrs;
495 if (hwerrs & ~dd->ipath_hwe_bitsextant)
496 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
497 "%llx set\n", (unsigned long long)
498 (hwerrs & ~dd->ipath_hwe_bitsextant));
500 ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
501 if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
503 * parity errors in send memory are recoverable,
504 * just cancel the send (if indicated in * sendbuffererror),
505 * count the occurrence, unfreeze (if no other handled
506 * hardware error bits are set), and continue. They can
507 * occur if a processor speculative read is done to the PIO
508 * buffer while we are sending a packet, for example.
510 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
511 hwerrs &= ~TXE_PIO_PARITY;
512 if (hwerrs & RXE_EAGER_PARITY)
513 ipath_dev_err(dd, "RXE parity, Eager TID error is not "
516 ipath_dbg("Clearing freezemode on ignored or "
517 "recovered hardware error\n");
518 ipath_clear_freeze(dd);
525 * may someday want to decode into which bits are which
526 * functional area for parity errors, etc.
528 if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
529 << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
530 bits = (u32) ((hwerrs >>
531 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
532 INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
533 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
535 strlcat(msg, bitsmsg, msgl);
538 ipath_format_hwerrors(hwerrs,
539 ipath_6110_hwerror_msgs,
540 sizeof(ipath_6110_hwerror_msgs) /
541 sizeof(ipath_6110_hwerror_msgs[0]),
544 if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
545 hwerr_crcbits(dd, hwerrs, msg, msgl);
547 if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
548 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
550 /* ignore from now on, so disable until driver reloaded */
551 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
552 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
553 dd->ipath_hwerrmask);
555 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP | \
556 INFINIPATH_HWE_COREPLL_RFSLIP | \
557 INFINIPATH_HWE_HTBPLL_FBSLIP | \
558 INFINIPATH_HWE_HTBPLL_RFSLIP | \
559 INFINIPATH_HWE_HTAPLL_FBSLIP | \
560 INFINIPATH_HWE_HTAPLL_RFSLIP)
562 if (hwerrs & _IPATH_PLL_FAIL) {
563 snprintf(bitsmsg, sizeof bitsmsg,
564 "[PLL failed (%llx), InfiniPath hardware unusable]",
565 (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
566 strlcat(msg, bitsmsg, msgl);
567 /* ignore from now on, so disable until driver reloaded */
568 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
569 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
570 dd->ipath_hwerrmask);
573 if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
575 * If it occurs, it is left masked since the eternal
576 * interface is unused
578 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
579 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
580 dd->ipath_hwerrmask);
585 * if any set that we aren't ignoring; only
586 * make the complaint once, in case it's stuck
587 * or recurring, and we get here multiple
589 * force link down, so switch knows, and
590 * LEDs are turned off
592 if (dd->ipath_flags & IPATH_INITTED) {
593 ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
594 ipath_setup_ht_setextled(dd,
595 INFINIPATH_IBCS_L_STATE_DOWN,
596 INFINIPATH_IBCS_LT_STATE_DISABLED);
597 ipath_dev_err(dd, "Fatal Hardware Error (freeze "
598 "mode), no longer usable, SN %.16s\n",
602 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
603 /* mark as having had error */
604 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
606 * mark as not usable, at a minimum until driver
607 * is reloaded, probably until reboot, since no
608 * other reset is possible.
610 dd->ipath_flags &= ~IPATH_INITTED;
613 *msg = 0; /* recovered from all of them */
615 ipath_dev_err(dd, "%s hardware error\n", msg);
616 if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
618 * for status file; if no trailing brace is copied,
619 * we'll know it was truncated.
621 snprintf(dd->ipath_freezemsg,
622 dd->ipath_freezelen, "{%s}", msg);
628 * ipath_ht_boardname - fill in the board name
629 * @dd: the infinipath device
630 * @name: the output buffer
631 * @namelen: the size of the output buffer
633 * fill in the board name, based on the board revision register
635 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
639 u8 boardrev = dd->ipath_boardrev;
645 * original production board; two production levels, with
646 * different serial number ranges. See ipath_ht_early_init() for
647 * case where we enable IPATH_GPIO_INTR for later serial # range.
648 * Original 112* serial number is no longer supported.
650 n = "InfiniPath_QHT7040";
653 /* small form factor production board */
654 n = "InfiniPath_QHT7140";
656 default: /* don't know, just print the number */
657 ipath_dev_err(dd, "Don't yet know about board "
658 "with ID %u\n", boardrev);
659 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
665 snprintf(name, namelen, "%s", n);
668 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
671 if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
672 dd->ipath_minrev > 4)) {
674 * This version of the driver only supports Rev 3.2 - 3.4
677 "Unsupported InfiniPath hardware revision %u.%u!\n",
678 dd->ipath_majrev, dd->ipath_minrev);
683 * pkt/word counters are 32 bit, and therefore wrap fast enough
684 * that we snapshot them from a timer, and maintain 64 bit shadow
687 dd->ipath_flags |= IPATH_32BITCOUNTERS;
688 dd->ipath_flags |= IPATH_GPIO_INTR;
689 if (dd->ipath_htspeed != 800)
691 "Incorrectly configured for HT @ %uMHz\n",
699 static void ipath_check_htlink(struct ipath_devdata *dd)
701 u8 linkerr, link_off, i;
703 for (i = 0; i < 2; i++) {
704 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
705 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
706 dev_info(&dd->pcidev->dev, "Couldn't read "
707 "linkerror%d of HT slave/primary block\n",
709 else if (linkerr & 0xf0) {
710 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
711 "clearing\n", linkerr >> 4, i);
713 * writing the linkerr bits that are set should
716 if (pci_write_config_byte(dd->pcidev, link_off,
718 ipath_dbg("Failed write to clear HT "
720 if (pci_read_config_byte(dd->pcidev, link_off,
722 dev_info(&dd->pcidev->dev,
723 "Couldn't reread linkerror%d of "
724 "HT slave/primary block\n", i);
725 else if (linkerr & 0xf0)
726 dev_info(&dd->pcidev->dev,
727 "HT linkerror%d bits 0x%x "
728 "couldn't be cleared\n",
734 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
736 ipath_dbg("No reset possible for this InfiniPath hardware\n");
740 #define HT_INTR_DISC_CONFIG 0x80 /* HT interrupt and discovery cap */
741 #define HT_INTR_REG_INDEX 2 /* intconfig requires indirect accesses */
744 * Bits 13-15 of command==0 is slave/primary block. Clear any HT CRC
745 * errors. We only bother to do this at load time, because it's OK if
746 * it happened before we were loaded (first time after boot/reset),
747 * but any time after that, it's fatal anyway. Also need to not check
748 * for for upper byte errors if we are in 8 bit mode, so figure out
749 * our width. For now, at least, also complain if it's 8 bit.
751 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
752 int pos, u8 cap_type)
754 u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
758 dd->ipath_ht_slave_off = pos;
759 /* command word, master_host bit */
760 /* master host || slave */
761 if ((cap_type >> 2) & 1)
765 ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
766 link_a_b_off ? 1 : 0,
767 link_a_b_off ? 'B' : 'A');
772 * check both link control registers; clear both HT CRC sets if
775 for (i = 0; i < 2; i++) {
776 link_off = pos + i * 4 + 0x4;
777 if (pci_read_config_word(pdev, link_off, &linkctrl))
778 ipath_dev_err(dd, "Couldn't read HT link control%d "
780 else if (linkctrl & (0xf << 8)) {
781 ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
782 "bits %x\n", i, linkctrl & (0xf << 8));
784 * now write them back to clear the error.
786 pci_write_config_byte(pdev, link_off,
787 linkctrl & (0xf << 8));
792 * As with HT CRC bits, same for protocol errors that might occur
795 for (i = 0; i < 2; i++) {
796 link_off = pos + i * 4 + 0xd;
797 if (pci_read_config_byte(pdev, link_off, &linkerr))
798 dev_info(&pdev->dev, "Couldn't read linkerror%d "
799 "of HT slave/primary block\n", i);
800 else if (linkerr & 0xf0) {
801 ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
802 "clearing\n", linkerr >> 4, i);
804 * writing the linkerr bits that are set will clear
807 if (pci_write_config_byte
808 (pdev, link_off, linkerr))
809 ipath_dbg("Failed write to clear HT "
811 if (pci_read_config_byte(pdev, link_off, &linkerr))
812 dev_info(&pdev->dev, "Couldn't reread "
813 "linkerror%d of HT slave/primary "
815 else if (linkerr & 0xf0)
816 dev_info(&pdev->dev, "HT linkerror%d bits "
817 "0x%x couldn't be cleared\n",
823 * this is just for our link to the host, not devices connected
827 if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
828 ipath_dev_err(dd, "Couldn't read HT link width "
829 "config register\n");
832 switch (linkwidth & 7) {
846 default: /* if wrong, assume 8 bit */
851 dd->ipath_htwidth = width;
853 if (linkwidth != 0x11) {
854 ipath_dev_err(dd, "Not configured for 16 bit HT "
855 "(%x)\n", linkwidth);
856 if (!(linkwidth & 0xf)) {
857 ipath_dbg("Will ignore HT lane1 errors\n");
858 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
864 * this is just for our link to the host, not devices connected
867 if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
868 ipath_dev_err(dd, "Couldn't read HT link frequency "
869 "config register\n");
872 switch (linkwidth & 0xf) {
893 * assume reserved and vendor-specific are 200...
899 dd->ipath_htspeed = speed;
903 static int ipath_ht_intconfig(struct ipath_devdata *dd)
907 if (dd->ipath_intconfig) {
908 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
909 dd->ipath_intconfig); /* interrupt address */
912 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
913 "interrupt address\n");
920 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
921 struct ht_irq_msg *msg)
923 struct ipath_devdata *dd = pci_get_drvdata(dev);
924 u64 prev_intconfig = dd->ipath_intconfig;
926 dd->ipath_intconfig = msg->address_lo;
927 dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
930 * If the previous value of dd->ipath_intconfig is zero, we're
931 * getting configured for the first time, and must not program the
932 * intconfig register here (it will be programmed later, when the
933 * hardware is ready). Otherwise, we should.
936 ipath_ht_intconfig(dd);
940 * ipath_setup_ht_config - setup the interruptconfig register
941 * @dd: the infinipath device
942 * @pdev: the PCI device
944 * setup the interruptconfig register from the HT config info.
945 * Also clear CRC errors in HT linkcontrol, if necessary.
946 * This is done only for the real hardware. It is done before
947 * chip address space is initted, so can't touch infinipath registers
949 static int ipath_setup_ht_config(struct ipath_devdata *dd,
950 struct pci_dev *pdev)
954 ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
956 ipath_dev_err(dd, "Couldn't create interrupt handler: "
964 * Handle clearing CRC errors in linkctrl register if necessary. We
965 * do this early, before we ever enable errors or hardware errors,
966 * mostly to avoid causing the chip to enter freeze mode.
968 pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
970 ipath_dev_err(dd, "Couldn't find HyperTransport "
971 "capability; no interrupts\n");
978 /* the HT capability type byte is 3 bytes after the
981 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
982 dev_info(&pdev->dev, "Couldn't read config "
983 "command @ %d\n", pos);
986 if (!(cap_type & 0xE0))
987 slave_or_pri_blk(dd, pdev, pos, cap_type);
988 } while ((pos = pci_find_next_capability(pdev, pos,
996 * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
997 * @dd: the infinipath device
999 * Called during driver unload.
1000 * This is currently a nop for the HT chip, not for all chips
1002 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1007 * ipath_setup_ht_setextled - set the state of the two external LEDs
1008 * @dd: the infinipath device
1010 * @ltst: the LT state
1012 * Set the state of the two external LEDs, to indicate physical and
1013 * logical state of IB link. For this chip (at least with recommended
1014 * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1017 * Note: We try to match the Mellanox HCA LED behavior as best
1018 * we can. Green indicates physical link state is OK (something is
1019 * plugged in, and we can train).
1020 * Amber indicates the link is logically up (ACTIVE).
1021 * Mellanox further blinks the amber LED to indicate data packet
1022 * activity, but we have no hardware support for that, so it would
1023 * require waking up every 10-20 msecs and checking the counters
1024 * on the chip, and then turning the LED off if appropriate. That's
1025 * visible overhead, so not something we will do.
1028 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1032 unsigned long flags = 0;
1034 /* the diags use the LED to indicate diag info, so we leave
1035 * the external LED alone when the diags are running */
1036 if (ipath_diag_inuse)
1039 /* Allow override of LED display for, e.g. Locating system in rack */
1040 if (dd->ipath_led_override) {
1041 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1042 ? INFINIPATH_IBCS_LT_STATE_LINKUP
1043 : INFINIPATH_IBCS_LT_STATE_DISABLED;
1044 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1045 ? INFINIPATH_IBCS_L_STATE_ACTIVE
1046 : INFINIPATH_IBCS_L_STATE_DOWN;
1049 spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1051 * start by setting both LED control bits to off, then turn
1052 * on the appropriate bit(s).
1054 if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1056 * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1057 * is inverted, because it is normally used to indicate
1058 * a hardware fault at reset, if there were errors
1060 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1061 | INFINIPATH_EXTC_LEDGBLERR_OFF;
1062 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1063 extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1064 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1065 extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1068 extctl = dd->ipath_extctrl &
1069 ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1070 INFINIPATH_EXTC_LED2PRIPORT_ON);
1071 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1072 extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1073 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1074 extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1076 dd->ipath_extctrl = extctl;
1077 ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1078 spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1081 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1083 dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1084 dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1085 dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1086 dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1088 /* Fill in shifts for RcvCtrl. */
1089 dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1090 dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1091 dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1092 dd->ipath_r_portcfg_shift = 0; /* Not on IBA6110 */
1094 dd->ipath_i_bitsextant =
1095 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1096 (INFINIPATH_I_RCVAVAIL_MASK <<
1097 INFINIPATH_I_RCVAVAIL_SHIFT) |
1098 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1099 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1101 dd->ipath_e_bitsextant =
1102 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1103 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1104 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1105 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1106 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1107 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1108 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1109 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1110 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1111 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1112 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1113 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1114 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1115 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1116 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1117 INFINIPATH_E_HARDWARE;
1119 dd->ipath_hwe_bitsextant =
1120 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1121 INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1122 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1123 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1124 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1125 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1126 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1127 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1128 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1129 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1130 INFINIPATH_HWE_HTCMISCERR4 |
1131 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1132 INFINIPATH_HWE_HTCMISCERR7 |
1133 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1134 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1135 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1136 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1137 INFINIPATH_HWE_MEMBISTFAILED |
1138 INFINIPATH_HWE_COREPLL_FBSLIP |
1139 INFINIPATH_HWE_COREPLL_RFSLIP |
1140 INFINIPATH_HWE_HTBPLL_FBSLIP |
1141 INFINIPATH_HWE_HTBPLL_RFSLIP |
1142 INFINIPATH_HWE_HTAPLL_FBSLIP |
1143 INFINIPATH_HWE_HTAPLL_RFSLIP |
1144 INFINIPATH_HWE_SERDESPLLFAILED |
1145 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1146 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1148 dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1149 dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1152 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1153 * 2 is Some Misc, 3 is reserved for future.
1155 dd->ipath_eep_st_masks[0].hwerrs_to_log =
1156 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1157 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1159 dd->ipath_eep_st_masks[1].hwerrs_to_log =
1160 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1161 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1163 dd->ipath_eep_st_masks[2].errs_to_log =
1164 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1169 * ipath_ht_init_hwerrors - enable hardware errors
1170 * @dd: the infinipath device
1172 * now that we have finished initializing everything that might reasonably
1173 * cause a hardware error, and cleared those errors bits as they occur,
1174 * we can enable hardware errors in the mask (potentially enabling
1175 * freeze mode), and enable hardware errors as errors (along with
1176 * everything else) in errormask
1178 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1183 extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1185 if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1186 ipath_dev_err(dd, "MemBIST did not complete!\n");
1187 if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1188 ipath_dbg("MemBIST corrected\n");
1190 ipath_check_htlink(dd);
1192 /* barring bugs, all hwerrors become interrupts, which can */
1194 /* don't look at crc lane1 if 8 bit */
1195 if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1196 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1197 /* don't look at crc lane1 if 8 bit */
1198 if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1199 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1202 * disable RXDSYNCMEMPARITY because external serdes is unused,
1203 * and therefore the logic will never be used or initialized,
1204 * and uninitialized state will normally result in this error
1205 * being asserted. Similarly for the external serdess pll
1208 val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1209 INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1212 * Disable MISCERR4 because of an inversion in the HT core
1213 * logic checking for errors that cause this bit to be set.
1214 * The errata can also cause the protocol error bit to be set
1215 * in the HT config space linkerror register(s).
1217 val &= ~INFINIPATH_HWE_HTCMISCERR4;
1220 * PLL ignored because MDIO interface has a logic problem
1221 * for reads, on Comstock and Ponderosa. BRINGUP
1223 if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1224 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1225 dd->ipath_hwerrmask = val;
1229 * ipath_ht_bringup_serdes - bring up the serdes
1230 * @dd: the infinipath device
1232 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1235 int ret = 0, change = 0;
1237 ipath_dbg("Trying to bringup serdes\n");
1239 if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1240 INFINIPATH_HWE_SERDESPLLFAILED)
1242 ipath_dbg("At start, serdes PLL failed bit set in "
1243 "hwerrstatus, clearing and continuing\n");
1244 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1245 INFINIPATH_HWE_SERDESPLLFAILED);
1248 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1249 config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1251 ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1252 "config1=%llx, sstatus=%llx xgxs %llx\n",
1253 (unsigned long long) val, (unsigned long long) config1,
1254 (unsigned long long)
1255 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1256 (unsigned long long)
1257 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1259 /* force reset on */
1260 val |= INFINIPATH_SERDC0_RESET_PLL
1261 /* | INFINIPATH_SERDC0_RESET_MASK */
1263 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1264 udelay(15); /* need pll reset set at least for a bit */
1266 if (val & INFINIPATH_SERDC0_RESET_PLL) {
1267 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1268 /* set lane resets, and tx idle, during pll reset */
1269 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1270 INFINIPATH_SERDC0_TXIDLE;
1271 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1272 "%llx)\n", (unsigned long long) val2);
1273 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1276 * be sure chip saw it
1278 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1280 * need pll reset clear at least 11 usec before lane
1281 * resets cleared; give it a few more
1284 val = val2; /* for check below */
1287 if (val & (INFINIPATH_SERDC0_RESET_PLL |
1288 INFINIPATH_SERDC0_RESET_MASK |
1289 INFINIPATH_SERDC0_TXIDLE)) {
1290 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1291 INFINIPATH_SERDC0_RESET_MASK |
1292 INFINIPATH_SERDC0_TXIDLE);
1294 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1298 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1299 if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1300 INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1301 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1302 INFINIPATH_XGXS_MDIOADDR_SHIFT);
1306 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1309 if (val & INFINIPATH_XGXS_RESET) {
1310 /* normally true after boot */
1311 val &= ~INFINIPATH_XGXS_RESET;
1314 if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1315 INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1316 /* need to compensate for Tx inversion in partner */
1317 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1318 INFINIPATH_XGXS_RX_POL_SHIFT);
1319 val |= dd->ipath_rx_pol_inv <<
1320 INFINIPATH_XGXS_RX_POL_SHIFT;
1324 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1326 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1328 /* clear current and de-emphasis bits */
1329 config1 &= ~0x0ffffffff00ULL;
1330 /* set current to 20ma */
1331 config1 |= 0x00000000000ULL;
1332 /* set de-emphasis to -5.68dB */
1333 config1 |= 0x0cccc000000ULL;
1334 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1336 ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1337 "config1=%llx, sstatus=%llx xgxs %llx\n",
1338 (unsigned long long) val, (unsigned long long) config1,
1339 (unsigned long long)
1340 ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1341 (unsigned long long)
1342 ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1344 if (!ipath_waitfor_mdio_cmdready(dd)) {
1345 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1346 ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1347 IPATH_MDIO_CTRL_XGXS_REG_8,
1349 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1350 IPATH_MDIO_DATAVALID, &val))
1351 ipath_dbg("Never got MDIO data for XGXS status "
1354 ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1355 "'bank' 31 %x\n", (u32) val);
1357 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1359 return ret; /* for now, say we always succeeded */
1363 * ipath_ht_quiet_serdes - set serdes to txidle
1364 * @dd: the infinipath device
1365 * driver is being unloaded
1367 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1369 u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1371 val |= INFINIPATH_SERDC0_TXIDLE;
1372 ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1373 (unsigned long long) val);
1374 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1378 * ipath_pe_put_tid - write a TID in chip
1379 * @dd: the infinipath device
1380 * @tidptr: pointer to the expected TID (in chip) to udpate
1381 * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1382 * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1384 * This exists as a separate routine to allow for special locking etc.
1385 * It's used for both the full cleanup on exit, as well as the normal
1386 * setup and teardown.
1388 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1389 u64 __iomem *tidptr, u32 type,
1392 if (!dd->ipath_kregbase)
1395 if (pa != dd->ipath_tidinvalid) {
1396 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1397 dev_info(&dd->pcidev->dev,
1398 "physaddr %lx has more than "
1399 "40 bits, using only 40!!!\n", pa);
1400 pa &= INFINIPATH_RT_ADDR_MASK;
1402 if (type == RCVHQ_RCV_TYPE_EAGER)
1403 pa |= dd->ipath_tidtemplate;
1405 /* in words (fixed, full page). */
1406 u64 lenvalid = PAGE_SIZE >> 2;
1407 lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1408 pa |= lenvalid | INFINIPATH_RT_VALID;
1416 * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1417 * @dd: the infinipath device
1420 * Used from ipath_close(), and at chip initialization.
1422 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1424 u64 __iomem *tidbase;
1427 if (!dd->ipath_kregbase)
1430 ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1433 * need to invalidate all of the expected TID entries for this
1434 * port, so we don't have valid entries that might somehow get
1435 * used (early in next use of this port, or through some bug)
1437 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1438 dd->ipath_rcvtidbase +
1439 port * dd->ipath_rcvtidcnt *
1441 for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1442 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1443 dd->ipath_tidinvalid);
1445 tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1446 dd->ipath_rcvegrbase +
1447 port * dd->ipath_rcvegrcnt *
1450 for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1451 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1452 dd->ipath_tidinvalid);
1456 * ipath_ht_tidtemplate - setup constants for TID updates
1457 * @dd: the infinipath device
1459 * We setup stuff that we use a lot, to avoid calculating each time
1461 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1463 dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1464 dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1465 dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1468 * work around chip errata bug 7358, by marking invalid tids
1469 * as having max length
1471 dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1472 INFINIPATH_RT_BUFSIZE_SHIFT;
1475 static int ipath_ht_early_init(struct ipath_devdata *dd)
1477 u32 __iomem *piobuf;
1482 * one cache line; long IB headers will spill over into received
1485 dd->ipath_rcvhdrentsize = 16;
1486 dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1489 * For HT, we allocate a somewhat overly large eager buffer,
1490 * such that we can guarantee that we can receive the largest
1491 * packet that we can send out. To truly support a 4KB MTU,
1492 * we need to bump this to a large value. To date, other than
1493 * testing, we have never encountered an HCA that can really
1494 * send 4KB MTU packets, so we do not handle that (we'll get
1495 * errors interrupts if we ever see one).
1497 dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1500 * the min() check here is currently a nop, but it may not
1501 * always be, depending on just how we do ipath_rcvegrbufsize
1503 dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1504 dd->ipath_rcvegrbufsize);
1505 dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1506 ipath_ht_tidtemplate(dd);
1509 * zero all the TID entries at startup. We do this for sanity,
1510 * in case of a previous driver crash of some kind, and also
1511 * because the chip powers up with these memories in an unknown
1512 * state. Use portcnt, not cfgports, since this is for the
1513 * full chip, not for current (possibly different) configuration
1515 * Chip Errata bug 6447
1517 for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1518 ipath_ht_clear_tids(dd, val32);
1521 * write the pbc of each buffer, to be sure it's initialized, then
1522 * cancel all the buffers, and also abort any packets that might
1523 * have been in flight for some reason (the latter is for driver
1524 * unload/reload, but isn't a bad idea at first init). PIO send
1525 * isn't enabled at this point, so there is no danger of sending
1526 * these out on the wire.
1527 * Chip Errata bug 6610
1529 piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1530 dd->ipath_piobufbase);
1531 pioincr = dd->ipath_palign / sizeof(*piobuf);
1532 for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1534 * reasonable word count, just to init pbc
1540 ipath_get_eeprom_info(dd);
1541 if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1542 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1544 * Later production QHT7040 has same changes as QHT7140, so
1545 * can use GPIO interrupts. They have serial #'s starting
1546 * with 128, rather than 112.
1548 if (dd->ipath_serial[0] == '1' &&
1549 dd->ipath_serial[1] == '2' &&
1550 dd->ipath_serial[2] == '8')
1551 dd->ipath_flags |= IPATH_GPIO_INTR;
1553 ipath_dev_err(dd, "Unsupported InfiniPath board "
1554 "(serial number %.16s)!\n",
1560 if (dd->ipath_minrev >= 4) {
1561 /* Rev4+ reports extra errors via internal GPIO pins */
1562 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1563 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1564 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1565 dd->ipath_gpio_mask);
1572 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1574 int cnt = ++ipath_stats.sps_txeparity;
1575 if (cnt >= IPATH_MAX_PARITY_ATTEMPTS) {
1576 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1578 "Too many attempts to recover from "
1579 "TXE parity, giving up\n");
1582 dev_info(&dd->pcidev->dev,
1583 "Recovering from TXE PIO parity error\n");
1589 * ipath_init_ht_get_base_info - set chip-specific flags for user code
1590 * @dd: the infinipath device
1591 * @kbase: ipath_base_info pointer
1593 * We set the PCIE flag because the lower bandwidth on PCIe vs
1594 * HyperTransport can affect some user packet algorithms.
1596 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1598 struct ipath_base_info *kinfo = kbase;
1600 kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1601 IPATH_RUNTIME_PIO_REGSWAPPED;
1603 if (pd->port_dd->ipath_minrev < 4)
1604 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
1609 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1611 free_irq(dd->ipath_irq, dd);
1612 ht_destroy_irq(dd->ipath_irq);
1614 dd->ipath_intconfig = 0;
1618 * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1619 * @dd: the infinipath device
1621 * This is global, and is called directly at init to set up the
1622 * chip-specific function pointers for later use.
1624 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1626 dd->ipath_f_intrsetup = ipath_ht_intconfig;
1627 dd->ipath_f_bus = ipath_setup_ht_config;
1628 dd->ipath_f_reset = ipath_setup_ht_reset;
1629 dd->ipath_f_get_boardname = ipath_ht_boardname;
1630 dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1631 dd->ipath_f_early_init = ipath_ht_early_init;
1632 dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1633 dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1634 dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1635 dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1636 dd->ipath_f_put_tid = ipath_ht_put_tid;
1637 dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1638 dd->ipath_f_setextled = ipath_setup_ht_setextled;
1639 dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1640 dd->ipath_f_free_irq = ipath_ht_free_irq;
1643 * initialize chip-specific variables
1645 dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1648 * setup the register offsets, since they are different for each
1651 dd->ipath_kregs = &ipath_ht_kregs;
1652 dd->ipath_cregs = &ipath_ht_cregs;
1655 * do very early init that is needed before ipath_f_bus is
1658 ipath_init_ht_variables(dd);