drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006 QLogic, Inc. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/vmalloc.h>
  40 #include <linux/pci.h>
  41 #include <linux/delay.h>
  42 #include <linux/htirq.h>
  43
  44 #include "ipath_kernel.h"
  45 #include "ipath_registers.h"
  46
  47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
  48
  49
  50 /*
  51  * This lists the InfiniPath registers, in the actual chip layout.
  52  * This structure should never be directly accessed.
  53  *
  54  * The names are in InterCap form because they're taken straight from
  55  * the chip specification.  Since they're only used in this file, they
  56  * don't pollute the rest of the source.
  57 */
  58
  59 struct _infinipath_do_not_use_kernel_regs {
  60         unsigned long long Revision;
  61         unsigned long long Control;
  62         unsigned long long PageAlign;
  63         unsigned long long PortCnt;
  64         unsigned long long DebugPortSelect;
  65         unsigned long long DebugPort;
  66         unsigned long long SendRegBase;
  67         unsigned long long UserRegBase;
  68         unsigned long long CounterRegBase;
  69         unsigned long long Scratch;
  70         unsigned long long ReservedMisc1;
  71         unsigned long long InterruptConfig;
  72         unsigned long long IntBlocked;
  73         unsigned long long IntMask;
  74         unsigned long long IntStatus;
  75         unsigned long long IntClear;
  76         unsigned long long ErrorMask;
  77         unsigned long long ErrorStatus;
  78         unsigned long long ErrorClear;
  79         unsigned long long HwErrMask;
  80         unsigned long long HwErrStatus;
  81         unsigned long long HwErrClear;
  82         unsigned long long HwDiagCtrl;
  83         unsigned long long MDIO;
  84         unsigned long long IBCStatus;
  85         unsigned long long IBCCtrl;
  86         unsigned long long ExtStatus;
  87         unsigned long long ExtCtrl;
  88         unsigned long long GPIOOut;
  89         unsigned long long GPIOMask;
  90         unsigned long long GPIOStatus;
  91         unsigned long long GPIOClear;
  92         unsigned long long RcvCtrl;
  93         unsigned long long RcvBTHQP;
  94         unsigned long long RcvHdrSize;
  95         unsigned long long RcvHdrCnt;
  96         unsigned long long RcvHdrEntSize;
  97         unsigned long long RcvTIDBase;
  98         unsigned long long RcvTIDCnt;
  99         unsigned long long RcvEgrBase;
 100         unsigned long long RcvEgrCnt;
 101         unsigned long long RcvBufBase;
 102         unsigned long long RcvBufSize;
 103         unsigned long long RxIntMemBase;
 104         unsigned long long RxIntMemSize;
 105         unsigned long long RcvPartitionKey;
 106         unsigned long long ReservedRcv[10];
 107         unsigned long long SendCtrl;
 108         unsigned long long SendPIOBufBase;
 109         unsigned long long SendPIOSize;
 110         unsigned long long SendPIOBufCnt;
 111         unsigned long long SendPIOAvailAddr;
 112         unsigned long long TxIntMemBase;
 113         unsigned long long TxIntMemSize;
 114         unsigned long long ReservedSend[9];
 115         unsigned long long SendBufferError;
 116         unsigned long long SendBufferErrorCONT1;
 117         unsigned long long SendBufferErrorCONT2;
 118         unsigned long long SendBufferErrorCONT3;
 119         unsigned long long ReservedSBE[4];
 120         unsigned long long RcvHdrAddr0;
 121         unsigned long long RcvHdrAddr1;
 122         unsigned long long RcvHdrAddr2;
 123         unsigned long long RcvHdrAddr3;
 124         unsigned long long RcvHdrAddr4;
 125         unsigned long long RcvHdrAddr5;
 126         unsigned long long RcvHdrAddr6;
 127         unsigned long long RcvHdrAddr7;
 128         unsigned long long RcvHdrAddr8;
 129         unsigned long long ReservedRHA[7];
 130         unsigned long long RcvHdrTailAddr0;
 131         unsigned long long RcvHdrTailAddr1;
 132         unsigned long long RcvHdrTailAddr2;
 133         unsigned long long RcvHdrTailAddr3;
 134         unsigned long long RcvHdrTailAddr4;
 135         unsigned long long RcvHdrTailAddr5;
 136         unsigned long long RcvHdrTailAddr6;
 137         unsigned long long RcvHdrTailAddr7;
 138         unsigned long long RcvHdrTailAddr8;
 139         unsigned long long ReservedRHTA[7];
 140         unsigned long long Sync;        /* Software only */
 141         unsigned long long Dump;        /* Software only */
 142         unsigned long long SimVer;      /* Software only */
 143         unsigned long long ReservedSW[5];
 144         unsigned long long SerdesConfig0;
 145         unsigned long long SerdesConfig1;
 146         unsigned long long SerdesStatus;
 147         unsigned long long XGXSConfig;
 148         unsigned long long ReservedSW2[4];
 149 };
 150
 151 #define IPATH_KREG_OFFSET(field) (offsetof(struct \
 152     _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 153 #define IPATH_CREG_OFFSET(field) (offsetof( \
 154     struct infinipath_counters, field) / sizeof(u64))
 155
 156 static const struct ipath_kregs ipath_ht_kregs = {
 157         .kr_control = IPATH_KREG_OFFSET(Control),
 158         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 159         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 160         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 161         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 162         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 163         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 164         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 165         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 166         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 167         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 168         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 169         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 170         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 171         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 172         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 173         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 174         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 175         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 176         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 177         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 178         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 179         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 180         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 181         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 182         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 183         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 184         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 185         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 186         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 187         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 188         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 189         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 190         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 191         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 192         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 193         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 194         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 195         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 196         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 197         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 198         .kr_revision = IPATH_KREG_OFFSET(Revision),
 199         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 200         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 201         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 202         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 203         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 204         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 205         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 206         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 207         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 208         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 209         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 210         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 211         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 212         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 213         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 214         /*
 215          * These should not be used directly via ipath_write_kreg64(),
 216          * use them with ipath_write_kreg64_port(),
 217          */
 218         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 219         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 220 };
 221
 222 static const struct ipath_cregs ipath_ht_cregs = {
 223         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 224         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 225         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 226         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 227         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 228         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 229         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 230         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 231         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 232         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 233         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 234         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 235         /* calc from Reg_CounterRegBase + offset */
 236         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 237         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 238         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 239         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 240         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 241         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 242         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 243         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 244         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 245         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 246         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 247         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 248         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 249         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 250         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 251         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 252         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 253         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 254         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 255         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 256         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 257 };
 258
 259 /* kr_intstatus, kr_intclear, kr_intmask bits */
 260 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 261 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 262
 263 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 264 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 265 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 266 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 267 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 268 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 269 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 270 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 271 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 272 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 273 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 274 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 275 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 276 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 277 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 278 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 279 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 280 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 281 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 282 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 283 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 284
 285 /* kr_extstatus bits */
 286 #define INFINIPATH_EXTS_FREQSEL 0x2
 287 #define INFINIPATH_EXTS_SERDESSEL 0x4
 288 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 289 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 290
 291
 292 /* TID entries (memory), HT-only */
 293 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
 294 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 295 #define INFINIPATH_RT_ADDR_SHIFT 0
 296 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
 297 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
 298
 299 /*
 300  * masks and bits that are different in different chips, or present only
 301  * in one
 302  */
 303 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 304     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 305 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 306     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 307
 308 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 309     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 310 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 311     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 312 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 313     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 314 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 315     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 316
 317 #define _IPATH_GPIO_SDA_NUM 1
 318 #define _IPATH_GPIO_SCL_NUM 0
 319
 320 #define IPATH_GPIO_SDA \
 321         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 322 #define IPATH_GPIO_SCL \
 323         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 324
 325 /* keep the code below somewhat more readonable; not used elsewhere */
 326 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 327                                 infinipath_hwe_htclnkabyte1crcerr)
 328 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 329                                 infinipath_hwe_htclnkbbyte1crcerr)
 330 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 331                                 infinipath_hwe_htclnkbbyte0crcerr)
 332 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 333                                 infinipath_hwe_htclnkbbyte1crcerr)
 334
 335 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 336                           char *msg, size_t msgl)
 337 {
 338         char bitsmsg[64];
 339         ipath_err_t crcbits = hwerrs &
 340                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 341         /* don't check if 8bit HT */
 342         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 343                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 344         /* don't check if 8bit HT */
 345         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 346                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 347         /*
 348          * we'll want to ignore link errors on link that is
 349          * not in use, if any.  For now, complain about both
 350          */
 351         if (crcbits) {
 352                 u16 ctrl0, ctrl1;
 353                 snprintf(bitsmsg, sizeof bitsmsg,
 354                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 355                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 356                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 357                                     ? "1 (B)" : "0+1 (A+B)"),
 358                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 359                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 360                             "0+1"), (unsigned long long) crcbits);
 361                 strlcat(msg, bitsmsg, msgl);
 362
 363                 /*
 364                  * print extra info for debugging.  slave/primary
 365                  * config word 4, 8 (link control 0, 1)
 366                  */
 367
 368                 if (pci_read_config_word(dd->pcidev,
 369                                          dd->ipath_ht_slave_off + 0x4,
 370                                          &ctrl0))
 371                         dev_info(&dd->pcidev->dev, "Couldn't read "
 372                                  "linkctrl0 of slave/primary "
 373                                  "config block\n");
 374                 else if (!(ctrl0 & 1 << 6))
 375                         /* not if EOC bit set */
 376                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 377                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 378                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 379                                   "");
 380                 if (pci_read_config_word(dd->pcidev,
 381                                          dd->ipath_ht_slave_off + 0x8,
 382                                          &ctrl1))
 383                         dev_info(&dd->pcidev->dev, "Couldn't read "
 384                                  "linkctrl1 of slave/primary "
 385                                  "config block\n");
 386                 else if (!(ctrl1 & 1 << 6))
 387                         /* not if EOC bit set */
 388                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 389                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 390                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 391                                   "");
 392
 393                 /* disable until driver reloaded */
 394                 dd->ipath_hwerrmask &= ~crcbits;
 395                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 396                                  dd->ipath_hwerrmask);
 397                 ipath_dbg("HT crc errs: %s\n", msg);
 398         } else
 399                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 400                           "not in use\n", (unsigned long long)
 401                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 402                                      _IPATH_HTLINK1_CRCBITS)));
 403 }
 404
 405 /* 6110 specific hardware errors... */
 406 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 407         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 408         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 409         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 410         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 411         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 412         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 413         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 414         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 415 };
 416
 417 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 418                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 419                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 420 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
 421                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
 422
 423 static int ipath_ht_txe_recover(struct ipath_devdata *);
 424
 425 /**
 426  * ipath_ht_handle_hwerrors - display hardware errors.
 427  * @dd: the infinipath device
 428  * @msg: the output buffer
 429  * @msgl: the size of the output buffer
 430  *
 431  * Use same msg buffer as regular errors to avoid excessive stack
 432  * use.  Most hardware errors are catastrophic, but for right now,
 433  * we'll print them and continue.  We reuse the same message buffer as
 434  * ipath_handle_errors() to avoid excessive stack usage.
 435  */
 436 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 437                                      size_t msgl)
 438 {
 439         ipath_err_t hwerrs;
 440         u32 bits, ctrl;
 441         int isfatal = 0;
 442         char bitsmsg[64];
 443         int log_idx;
 444
 445         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 446
 447         if (!hwerrs) {
 448                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 449                 /*
 450                  * better than printing cofusing messages
 451                  * This seems to be related to clearing the crc error, or
 452                  * the pll error during init.
 453                  */
 454                 goto bail;
 455         } else if (hwerrs == -1LL) {
 456                 ipath_dev_err(dd, "Read of hardware error status failed "
 457                               "(all bits set); ignoring\n");
 458                 goto bail;
 459         }
 460         ipath_stats.sps_hwerrs++;
 461
 462         /* Always clear the error status register, except MEMBISTFAIL,
 463          * regardless of whether we continue or stop using the chip.
 464          * We want that set so we know it failed, even across driver reload.
 465          * We'll still ignore it in the hwerrmask.  We do this partly for
 466          * diagnostics, but also for support */
 467         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 468                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 469
 470         hwerrs &= dd->ipath_hwerrmask;
 471
 472         /* We log some errors to EEPROM, check if we have any of those. */
 473         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 474                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 475                         ipath_inc_eeprom_err(dd, log_idx, 1);
 476
 477         /*
 478          * make sure we get this much out, unless told to be quiet,
 479          * it's a parity error we may recover from,
 480          * or it's occurred within the last 5 seconds
 481          */
 482         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
 483                 RXE_EAGER_PARITY)) ||
 484                 (ipath_debug & __IPATH_VERBDBG))
 485                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 486                          "(cleared)\n", (unsigned long long) hwerrs);
 487         dd->ipath_lasthwerror |= hwerrs;
 488
 489         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 490                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 491                               "%llx set\n", (unsigned long long)
 492                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 493
 494         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 495         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
 496                 /*
 497                  * parity errors in send memory are recoverable,
 498                  * just cancel the send (if indicated in * sendbuffererror),
 499                  * count the occurrence, unfreeze (if no other handled
 500                  * hardware error bits are set), and continue. They can
 501                  * occur if a processor speculative read is done to the PIO
 502                  * buffer while we are sending a packet, for example.
 503                  */
 504                 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
 505                         hwerrs &= ~TXE_PIO_PARITY;
 506                 if (hwerrs & RXE_EAGER_PARITY)
 507                         ipath_dev_err(dd, "RXE parity, Eager TID error is not "
 508                                 "recoverable\n");
 509                 if (!hwerrs) {
 510                         ipath_dbg("Clearing freezemode on ignored or "
 511                                   "recovered hardware error\n");
 512                         ctrl &= ~INFINIPATH_C_FREEZEMODE;
 513                         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
 514                                          ctrl);
 515                 }
 516         }
 517
 518         *msg = '\0';
 519
 520         /*
 521          * may someday want to decode into which bits are which
 522          * functional area for parity errors, etc.
 523          */
 524         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 525                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 526                 bits = (u32) ((hwerrs >>
 527                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 528                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 529                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 530                          bits);
 531                 strlcat(msg, bitsmsg, msgl);
 532         }
 533
 534         ipath_format_hwerrors(hwerrs,
 535                               ipath_6110_hwerror_msgs,
 536                               sizeof(ipath_6110_hwerror_msgs) /
 537                               sizeof(ipath_6110_hwerror_msgs[0]),
 538                               msg, msgl);
 539
 540         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 541                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 542
 543         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 544                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 545                         msgl);
 546                 /* ignore from now on, so disable until driver reloaded */
 547                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 548                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 549                                  dd->ipath_hwerrmask);
 550         }
 551 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 552                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 553                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 554                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 555                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 556                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 557
 558         if (hwerrs & _IPATH_PLL_FAIL) {
 559                 snprintf(bitsmsg, sizeof bitsmsg,
 560                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 561                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 562                 strlcat(msg, bitsmsg, msgl);
 563                 /* ignore from now on, so disable until driver reloaded */
 564                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 565                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 566                                  dd->ipath_hwerrmask);
 567         }
 568
 569         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 570                 /*
 571                  * If it occurs, it is left masked since the eternal
 572                  * interface is unused
 573                  */
 574                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 575                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 576                                  dd->ipath_hwerrmask);
 577         }
 578
 579         if (hwerrs) {
 580                 /*
 581                  * if any set that we aren't ignoring; only
 582                  * make the complaint once, in case it's stuck
 583                  * or recurring, and we get here multiple
 584                  * times.
 585                  * force link down, so switch knows, and
 586                  * LEDs are turned off
 587                  */
 588                 if (dd->ipath_flags & IPATH_INITTED) {
 589                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 590                         ipath_setup_ht_setextled(dd,
 591                                 INFINIPATH_IBCS_L_STATE_DOWN,
 592                                 INFINIPATH_IBCS_LT_STATE_DISABLED);
 593                         ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 594                                           "mode), no longer usable, SN %.16s\n",
 595                                           dd->ipath_serial);
 596                         isfatal = 1;
 597                 }
 598                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 599                 /* mark as having had error */
 600                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 601                 /*
 602                  * mark as not usable, at a minimum until driver
 603                  * is reloaded, probably until reboot, since no
 604                  * other reset is possible.
 605                  */
 606                 dd->ipath_flags &= ~IPATH_INITTED;
 607         }
 608         else
 609                 *msg = 0; /* recovered from all of them */
 610         if (*msg)
 611                 ipath_dev_err(dd, "%s hardware error\n", msg);
 612         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 613                 /*
 614                  * for status file; if no trailing brace is copied,
 615                  * we'll know it was truncated.
 616                  */
 617                 snprintf(dd->ipath_freezemsg,
 618                          dd->ipath_freezelen, "{%s}", msg);
 619
 620 bail:;
 621 }
 622
 623 /**
 624  * ipath_ht_boardname - fill in the board name
 625  * @dd: the infinipath device
 626  * @name: the output buffer
 627  * @namelen: the size of the output buffer
 628  *
 629  * fill in the board name, based on the board revision register
 630  */
 631 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 632                               size_t namelen)
 633 {
 634         char *n = NULL;
 635         u8 boardrev = dd->ipath_boardrev;
 636         int ret;
 637
 638         switch (boardrev) {
 639         case 4:         /* Ponderosa is one of the bringup boards */
 640                 n = "Ponderosa";
 641                 break;
 642         case 5:
 643                 /*
 644                  * original production board; two production levels, with
 645                  * different serial number ranges.   See ipath_ht_early_init() for
 646                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 647                  */
 648                 n = "InfiniPath_QHT7040";
 649                 break;
 650         case 6:
 651                 n = "OEM_Board_3";
 652                 break;
 653         case 7:
 654                 /* small form factor production board */
 655                 n = "InfiniPath_QHT7140";
 656                 break;
 657         case 8:
 658                 n = "LS/X-1";
 659                 break;
 660         case 9:         /* Comstock bringup test board */
 661                 n = "Comstock";
 662                 break;
 663         case 10:
 664                 n = "OEM_Board_2";
 665                 break;
 666         case 11:
 667                 n = "InfiniPath_HT-470"; /* obsoleted */
 668                 break;
 669         case 12:
 670                 n = "OEM_Board_4";
 671                 break;
 672         default:                /* don't know, just print the number */
 673                 ipath_dev_err(dd, "Don't yet know about board "
 674                               "with ID %u\n", boardrev);
 675                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 676                          boardrev);
 677                 break;
 678         }
 679         if (n)
 680                 snprintf(name, namelen, "%s", n);
 681
 682         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
 683                 dd->ipath_minrev > 3)) {
 684                 /*
 685                  * This version of the driver only supports Rev 3.2 and 3.3
 686                  */
 687                 ipath_dev_err(dd,
 688                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 689                               dd->ipath_majrev, dd->ipath_minrev);
 690                 ret = 1;
 691                 goto bail;
 692         }
 693         /*
 694          * pkt/word counters are 32 bit, and therefore wrap fast enough
 695          * that we snapshot them from a timer, and maintain 64 bit shadow
 696          * copies
 697          */
 698         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 699         if (dd->ipath_htspeed != 800)
 700                 ipath_dev_err(dd,
 701                               "Incorrectly configured for HT @ %uMHz\n",
 702                               dd->ipath_htspeed);
 703         if (dd->ipath_boardrev == 7 || dd->ipath_boardrev == 11 ||
 704             dd->ipath_boardrev == 6)
 705                 dd->ipath_flags |= IPATH_GPIO_INTR;
 706         else
 707                 dd->ipath_flags |= IPATH_POLL_RX_INTR;
 708         if (dd->ipath_boardrev == 8) {  /* LS/X-1 */
 709                 u64 val;
 710                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
 711                 if (val & INFINIPATH_EXTS_SERDESSEL) {
 712                         /*
 713                          * hardware disabled
 714                          *
 715                          * This means that the chip is hardware disabled,
 716                          * and will not be able to bring up the link,
 717                          * in any case.  We special case this and abort
 718                          * early, to avoid later messages.  We also set
 719                          * the DISABLED status bit
 720                          */
 721                         ipath_dbg("Unit %u is hardware-disabled\n",
 722                                   dd->ipath_unit);
 723                         *dd->ipath_statusp |= IPATH_STATUS_DISABLED;
 724                         /* this value is handled differently */
 725                         ret = 2;
 726                         goto bail;
 727                 }
 728         }
 729         ret = 0;
 730
 731 bail:
 732         return ret;
 733 }
 734
 735 static void ipath_check_htlink(struct ipath_devdata *dd)
 736 {
 737         u8 linkerr, link_off, i;
 738
 739         for (i = 0; i < 2; i++) {
 740                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 741                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 742                         dev_info(&dd->pcidev->dev, "Couldn't read "
 743                                  "linkerror%d of HT slave/primary block\n",
 744                                  i);
 745                 else if (linkerr & 0xf0) {
 746                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 747                                    "clearing\n", linkerr >> 4, i);
 748                         /*
 749                          * writing the linkerr bits that are set should
 750                          * clear them
 751                          */
 752                         if (pci_write_config_byte(dd->pcidev, link_off,
 753                                                   linkerr))
 754                                 ipath_dbg("Failed write to clear HT "
 755                                           "linkerror%d\n", i);
 756                         if (pci_read_config_byte(dd->pcidev, link_off,
 757                                                  &linkerr))
 758                                 dev_info(&dd->pcidev->dev,
 759                                          "Couldn't reread linkerror%d of "
 760                                          "HT slave/primary block\n", i);
 761                         else if (linkerr & 0xf0)
 762                                 dev_info(&dd->pcidev->dev,
 763                                          "HT linkerror%d bits 0x%x "
 764                                          "couldn't be cleared\n",
 765                                          i, linkerr >> 4);
 766                 }
 767         }
 768 }
 769
 770 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 771 {
 772         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 773         return 0;
 774 }
 775
 776 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 777 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 778
 779 /*
 780  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 781  * errors.  We only bother to do this at load time, because it's OK if
 782  * it happened before we were loaded (first time after boot/reset),
 783  * but any time after that, it's fatal anyway.  Also need to not check
 784  * for for upper byte errors if we are in 8 bit mode, so figure out
 785  * our width.  For now, at least, also complain if it's 8 bit.
 786  */
 787 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 788                              int pos, u8 cap_type)
 789 {
 790         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 791         u16 linkctrl = 0;
 792         int i;
 793
 794         dd->ipath_ht_slave_off = pos;
 795         /* command word, master_host bit */
 796         /* master host || slave */
 797         if ((cap_type >> 2) & 1)
 798                 link_a_b_off = 4;
 799         else
 800                 link_a_b_off = 0;
 801         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 802                    link_a_b_off ? 1 : 0,
 803                    link_a_b_off ? 'B' : 'A');
 804
 805         link_a_b_off += pos;
 806
 807         /*
 808          * check both link control registers; clear both HT CRC sets if
 809          * necessary.
 810          */
 811         for (i = 0; i < 2; i++) {
 812                 link_off = pos + i * 4 + 0x4;
 813                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 814                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 815                                       "register\n", i);
 816                 else if (linkctrl & (0xf << 8)) {
 817                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 818                                    "bits %x\n", i, linkctrl & (0xf << 8));
 819                         /*
 820                          * now write them back to clear the error.
 821                          */
 822                         pci_write_config_byte(pdev, link_off,
 823                                               linkctrl & (0xf << 8));
 824                 }
 825         }
 826
 827         /*
 828          * As with HT CRC bits, same for protocol errors that might occur
 829          * during boot.
 830          */
 831         for (i = 0; i < 2; i++) {
 832                 link_off = pos + i * 4 + 0xd;
 833                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 834                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 835                                  "of HT slave/primary block\n", i);
 836                 else if (linkerr & 0xf0) {
 837                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 838                                    "clearing\n", linkerr >> 4, i);
 839                         /*
 840                          * writing the linkerr bits that are set will clear
 841                          * them
 842                          */
 843                         if (pci_write_config_byte
 844                             (pdev, link_off, linkerr))
 845                                 ipath_dbg("Failed write to clear HT "
 846                                           "linkerror%d\n", i);
 847                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 848                                 dev_info(&pdev->dev, "Couldn't reread "
 849                                          "linkerror%d of HT slave/primary "
 850                                          "block\n", i);
 851                         else if (linkerr & 0xf0)
 852                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 853                                          "0x%x couldn't be cleared\n",
 854                                          i, linkerr >> 4);
 855                 }
 856         }
 857
 858         /*
 859          * this is just for our link to the host, not devices connected
 860          * through tunnel.
 861          */
 862
 863         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 864                 ipath_dev_err(dd, "Couldn't read HT link width "
 865                               "config register\n");
 866         else {
 867                 u32 width;
 868                 switch (linkwidth & 7) {
 869                 case 5:
 870                         width = 4;
 871                         break;
 872                 case 4:
 873                         width = 2;
 874                         break;
 875                 case 3:
 876                         width = 32;
 877                         break;
 878                 case 1:
 879                         width = 16;
 880                         break;
 881                 case 0:
 882                 default:        /* if wrong, assume 8 bit */
 883                         width = 8;
 884                         break;
 885                 }
 886
 887                 dd->ipath_htwidth = width;
 888
 889                 if (linkwidth != 0x11) {
 890                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 891                                       "(%x)\n", linkwidth);
 892                         if (!(linkwidth & 0xf)) {
 893                                 ipath_dbg("Will ignore HT lane1 errors\n");
 894                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 895                         }
 896                 }
 897         }
 898
 899         /*
 900          * this is just for our link to the host, not devices connected
 901          * through tunnel.
 902          */
 903         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 904                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 905                               "config register\n");
 906         else {
 907                 u32 speed;
 908                 switch (linkwidth & 0xf) {
 909                 case 6:
 910                         speed = 1000;
 911                         break;
 912                 case 5:
 913                         speed = 800;
 914                         break;
 915                 case 4:
 916                         speed = 600;
 917                         break;
 918                 case 3:
 919                         speed = 500;
 920                         break;
 921                 case 2:
 922                         speed = 400;
 923                         break;
 924                 case 1:
 925                         speed = 300;
 926                         break;
 927                 default:
 928                         /*
 929                          * assume reserved and vendor-specific are 200...
 930                          */
 931                 case 0:
 932                         speed = 200;
 933                         break;
 934                 }
 935                 dd->ipath_htspeed = speed;
 936         }
 937 }
 938
 939 static int ipath_ht_intconfig(struct ipath_devdata *dd)
 940 {
 941         int ret;
 942
 943         if (dd->ipath_intconfig) {
 944                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
 945                                  dd->ipath_intconfig);  /* interrupt address */
 946                 ret = 0;
 947         } else {
 948                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
 949                               "interrupt address\n");
 950                 ret = -EINVAL;
 951         }
 952
 953         return ret;
 954 }
 955
 956 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
 957                                 struct ht_irq_msg *msg)
 958 {
 959         struct ipath_devdata *dd = pci_get_drvdata(dev);
 960         u64 prev_intconfig = dd->ipath_intconfig;
 961
 962         dd->ipath_intconfig = msg->address_lo;
 963         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
 964
 965         /*
 966          * If the previous value of dd->ipath_intconfig is zero, we're
 967          * getting configured for the first time, and must not program the
 968          * intconfig register here (it will be programmed later, when the
 969          * hardware is ready).  Otherwise, we should.
 970          */
 971         if (prev_intconfig)
 972                 ipath_ht_intconfig(dd);
 973 }
 974
 975 /**
 976  * ipath_setup_ht_config - setup the interruptconfig register
 977  * @dd: the infinipath device
 978  * @pdev: the PCI device
 979  *
 980  * setup the interruptconfig register from the HT config info.
 981  * Also clear CRC errors in HT linkcontrol, if necessary.
 982  * This is done only for the real hardware.  It is done before
 983  * chip address space is initted, so can't touch infinipath registers
 984  */
 985 static int ipath_setup_ht_config(struct ipath_devdata *dd,
 986                                  struct pci_dev *pdev)
 987 {
 988         int pos, ret;
 989
 990         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
 991         if (ret < 0) {
 992                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
 993                               "err %d\n", ret);
 994                 goto bail;
 995         }
 996         dd->ipath_irq = ret;
 997         ret = 0;
 998
 999         /*
1000          * Handle clearing CRC errors in linkctrl register if necessary.  We
1001          * do this early, before we ever enable errors or hardware errors,
1002          * mostly to avoid causing the chip to enter freeze mode.
1003          */
1004         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
1005         if (!pos) {
1006                 ipath_dev_err(dd, "Couldn't find HyperTransport "
1007                               "capability; no interrupts\n");
1008                 ret = -ENODEV;
1009                 goto bail;
1010         }
1011         do {
1012                 u8 cap_type;
1013
1014                 /* the HT capability type byte is 3 bytes after the
1015                  * capability byte.
1016                  */
1017                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1018                         dev_info(&pdev->dev, "Couldn't read config "
1019                                  "command @ %d\n", pos);
1020                         continue;
1021                 }
1022                 if (!(cap_type & 0xE0))
1023                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1024         } while ((pos = pci_find_next_capability(pdev, pos,
1025                                                  PCI_CAP_ID_HT)));
1026
1027 bail:
1028         return ret;
1029 }
1030
1031 /**
1032  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1033  * @dd: the infinipath device
1034  *
1035  * Called during driver unload.
1036  * This is currently a nop for the HT chip, not for all chips
1037  */
1038 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1039 {
1040 }
1041
1042 /**
1043  * ipath_setup_ht_setextled - set the state of the two external LEDs
1044  * @dd: the infinipath device
1045  * @lst: the L state
1046  * @ltst: the LT state
1047  *
1048  * Set the state of the two external LEDs, to indicate physical and
1049  * logical state of IB link.   For this chip (at least with recommended
1050  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1051  * (logical state)
1052  *
1053  * Note:  We try to match the Mellanox HCA LED behavior as best
1054  * we can.  Green indicates physical link state is OK (something is
1055  * plugged in, and we can train).
1056  * Amber indicates the link is logically up (ACTIVE).
1057  * Mellanox further blinks the amber LED to indicate data packet
1058  * activity, but we have no hardware support for that, so it would
1059  * require waking up every 10-20 msecs and checking the counters
1060  * on the chip, and then turning the LED off if appropriate.  That's
1061  * visible overhead, so not something we will do.
1062  *
1063  */
1064 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1065                                      u64 lst, u64 ltst)
1066 {
1067         u64 extctl;
1068         unsigned long flags = 0;
1069
1070         /* the diags use the LED to indicate diag info, so we leave
1071          * the external LED alone when the diags are running */
1072         if (ipath_diag_inuse)
1073                 return;
1074
1075         /* Allow override of LED display for, e.g. Locating system in rack */
1076         if (dd->ipath_led_override) {
1077                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1078                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
1079                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
1080                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1081                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
1082                         : INFINIPATH_IBCS_L_STATE_DOWN;
1083         }
1084
1085         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1086         /*
1087          * start by setting both LED control bits to off, then turn
1088          * on the appropriate bit(s).
1089          */
1090         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1091                 /*
1092                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1093                  * is inverted,  because it is normally used to indicate
1094                  * a hardware fault at reset, if there were errors
1095                  */
1096                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1097                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1098                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1099                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1100                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1101                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1102         }
1103         else {
1104                 extctl = dd->ipath_extctrl &
1105                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1106                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1107                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1108                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1109                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1110                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1111         }
1112         dd->ipath_extctrl = extctl;
1113         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1114         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1115 }
1116
1117 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1118 {
1119         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1120         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1121         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1122         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1123
1124         dd->ipath_i_bitsextant =
1125                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1126                 (INFINIPATH_I_RCVAVAIL_MASK <<
1127                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1128                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1129                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1130
1131         dd->ipath_e_bitsextant =
1132                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1133                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1134                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1135                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1136                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1137                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1138                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1139                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1140                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1141                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1142                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1143                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1144                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1145                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1146                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1147                 INFINIPATH_E_HARDWARE;
1148
1149         dd->ipath_hwe_bitsextant =
1150                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1151                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1152                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1153                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1154                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1155                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1156                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1157                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1158                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1159                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1160                 INFINIPATH_HWE_HTCMISCERR4 |
1161                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1162                 INFINIPATH_HWE_HTCMISCERR7 |
1163                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1164                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1165                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1166                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1167                 INFINIPATH_HWE_MEMBISTFAILED |
1168                 INFINIPATH_HWE_COREPLL_FBSLIP |
1169                 INFINIPATH_HWE_COREPLL_RFSLIP |
1170                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1171                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1172                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1173                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1174                 INFINIPATH_HWE_SERDESPLLFAILED |
1175                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1176                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1177
1178         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1179         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1180
1181         /*
1182          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1183          * 2 is Some Misc, 3 is reserved for future.
1184          */
1185         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1186                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1187                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1188
1189         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1190                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1191                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1192
1193         dd->ipath_eep_st_masks[2].errs_to_log =
1194                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET;
1195
1196 }
1197
1198 /**
1199  * ipath_ht_init_hwerrors - enable hardware errors
1200  * @dd: the infinipath device
1201  *
1202  * now that we have finished initializing everything that might reasonably
1203  * cause a hardware error, and cleared those errors bits as they occur,
1204  * we can enable hardware errors in the mask (potentially enabling
1205  * freeze mode), and enable hardware errors as errors (along with
1206  * everything else) in errormask
1207  */
1208 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1209 {
1210         ipath_err_t val;
1211         u64 extsval;
1212
1213         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1214
1215         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1216                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1217         if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1218                 ipath_dbg("MemBIST corrected\n");
1219
1220         ipath_check_htlink(dd);
1221
1222         /* barring bugs, all hwerrors become interrupts, which can */
1223         val = -1LL;
1224         /* don't look at crc lane1 if 8 bit */
1225         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1226                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1227         /* don't look at crc lane1 if 8 bit */
1228         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1229                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1230
1231         /*
1232          * disable RXDSYNCMEMPARITY because external serdes is unused,
1233          * and therefore the logic will never be used or initialized,
1234          * and uninitialized state will normally result in this error
1235          * being asserted.  Similarly for the external serdess pll
1236          * lock signal.
1237          */
1238         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1239                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1240
1241         /*
1242          * Disable MISCERR4 because of an inversion in the HT core
1243          * logic checking for errors that cause this bit to be set.
1244          * The errata can also cause the protocol error bit to be set
1245          * in the HT config space linkerror register(s).
1246          */
1247         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1248
1249         /*
1250          * PLL ignored because MDIO interface has a logic problem
1251          * for reads, on Comstock and Ponderosa.  BRINGUP
1252          */
1253         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1254                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1255         dd->ipath_hwerrmask = val;
1256 }
1257
1258 /**
1259  * ipath_ht_bringup_serdes - bring up the serdes
1260  * @dd: the infinipath device
1261  */
1262 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1263 {
1264         u64 val, config1;
1265         int ret = 0, change = 0;
1266
1267         ipath_dbg("Trying to bringup serdes\n");
1268
1269         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1270             INFINIPATH_HWE_SERDESPLLFAILED)
1271         {
1272                 ipath_dbg("At start, serdes PLL failed bit set in "
1273                           "hwerrstatus, clearing and continuing\n");
1274                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1275                                  INFINIPATH_HWE_SERDESPLLFAILED);
1276         }
1277
1278         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1279         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1280
1281         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1282                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1283                    (unsigned long long) val, (unsigned long long) config1,
1284                    (unsigned long long)
1285                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1286                    (unsigned long long)
1287                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1288
1289         /* force reset on */
1290         val |= INFINIPATH_SERDC0_RESET_PLL
1291                 /* | INFINIPATH_SERDC0_RESET_MASK */
1292                 ;
1293         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1294         udelay(15);             /* need pll reset set at least for a bit */
1295
1296         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1297                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1298                 /* set lane resets, and tx idle, during pll reset */
1299                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1300                         INFINIPATH_SERDC0_TXIDLE;
1301                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1302                            "%llx)\n", (unsigned long long) val2);
1303                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1304                                  val2);
1305                 /*
1306                  * be sure chip saw it
1307                  */
1308                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1309                 /*
1310                  * need pll reset clear at least 11 usec before lane
1311                  * resets cleared; give it a few more
1312                  */
1313                 udelay(15);
1314                 val = val2;     /* for check below */
1315         }
1316
1317         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1318                    INFINIPATH_SERDC0_RESET_MASK |
1319                    INFINIPATH_SERDC0_TXIDLE)) {
1320                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1321                          INFINIPATH_SERDC0_RESET_MASK |
1322                          INFINIPATH_SERDC0_TXIDLE);
1323                 /* clear them */
1324                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1325                                  val);
1326         }
1327
1328         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1329         if (((val >> INFINIPATH_XGXS_MDIOADDR_SHIFT) &
1330              INFINIPATH_XGXS_MDIOADDR_MASK) != 3) {
1331                 val &= ~(INFINIPATH_XGXS_MDIOADDR_MASK <<
1332                          INFINIPATH_XGXS_MDIOADDR_SHIFT);
1333                 /*
1334                  * we use address 3
1335                  */
1336                 val |= 3ULL << INFINIPATH_XGXS_MDIOADDR_SHIFT;
1337                 change = 1;
1338         }
1339         if (val & INFINIPATH_XGXS_RESET) {
1340                 /* normally true after boot */
1341                 val &= ~INFINIPATH_XGXS_RESET;
1342                 change = 1;
1343         }
1344         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1345              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1346                 /* need to compensate for Tx inversion in partner */
1347                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1348                          INFINIPATH_XGXS_RX_POL_SHIFT);
1349                 val |= dd->ipath_rx_pol_inv <<
1350                         INFINIPATH_XGXS_RX_POL_SHIFT;
1351                 change = 1;
1352         }
1353         if (change)
1354                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1355
1356         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1357
1358         /* clear current and de-emphasis bits */
1359         config1 &= ~0x0ffffffff00ULL;
1360         /* set current to 20ma */
1361         config1 |= 0x00000000000ULL;
1362         /* set de-emphasis to -5.68dB */
1363         config1 |= 0x0cccc000000ULL;
1364         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1365
1366         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1367                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1368                    (unsigned long long) val, (unsigned long long) config1,
1369                    (unsigned long long)
1370                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1371                    (unsigned long long)
1372                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1373
1374         if (!ipath_waitfor_mdio_cmdready(dd)) {
1375                 ipath_write_kreg(dd, dd->ipath_kregs->kr_mdio,
1376                                  ipath_mdio_req(IPATH_MDIO_CMD_READ, 31,
1377                                                 IPATH_MDIO_CTRL_XGXS_REG_8,
1378                                                 0));
1379                 if (ipath_waitfor_complete(dd, dd->ipath_kregs->kr_mdio,
1380                                            IPATH_MDIO_DATAVALID, &val))
1381                         ipath_dbg("Never got MDIO data for XGXS status "
1382                                   "read\n");
1383                 else
1384                         ipath_cdbg(VERBOSE, "MDIO Read reg8, "
1385                                    "'bank' 31 %x\n", (u32) val);
1386         } else
1387                 ipath_dbg("Never got MDIO cmdready for XGXS status read\n");
1388
1389         return ret;             /* for now, say we always succeeded */
1390 }
1391
1392 /**
1393  * ipath_ht_quiet_serdes - set serdes to txidle
1394  * @dd: the infinipath device
1395  * driver is being unloaded
1396  */
1397 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1398 {
1399         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1400
1401         val |= INFINIPATH_SERDC0_TXIDLE;
1402         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1403                   (unsigned long long) val);
1404         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1405 }
1406
1407 /**
1408  * ipath_pe_put_tid - write a TID in chip
1409  * @dd: the infinipath device
1410  * @tidptr: pointer to the expected TID (in chip) to udpate
1411  * @tidtype: 0 for eager, 1 for expected
1412  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1413  *
1414  * This exists as a separate routine to allow for special locking etc.
1415  * It's used for both the full cleanup on exit, as well as the normal
1416  * setup and teardown.
1417  */
1418 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1419                              u64 __iomem *tidptr, u32 type,
1420                              unsigned long pa)
1421 {
1422         if (!dd->ipath_kregbase)
1423                 return;
1424
1425         if (pa != dd->ipath_tidinvalid) {
1426                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1427                         dev_info(&dd->pcidev->dev,
1428                                  "physaddr %lx has more than "
1429                                  "40 bits, using only 40!!!\n", pa);
1430                         pa &= INFINIPATH_RT_ADDR_MASK;
1431                 }
1432                 if (type == 0)
1433                         pa |= dd->ipath_tidtemplate;
1434                 else {
1435                         /* in words (fixed, full page).  */
1436                         u64 lenvalid = PAGE_SIZE >> 2;
1437                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1438                         pa |= lenvalid | INFINIPATH_RT_VALID;
1439                 }
1440         }
1441         writeq(pa, tidptr);
1442 }
1443
1444
1445 /**
1446  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1447  * @dd: the infinipath device
1448  * @port: the port
1449  *
1450  * Used from ipath_close(), and at chip initialization.
1451  */
1452 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1453 {
1454         u64 __iomem *tidbase;
1455         int i;
1456
1457         if (!dd->ipath_kregbase)
1458                 return;
1459
1460         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1461
1462         /*
1463          * need to invalidate all of the expected TID entries for this
1464          * port, so we don't have valid entries that might somehow get
1465          * used (early in next use of this port, or through some bug)
1466          */
1467         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1468                                    dd->ipath_rcvtidbase +
1469                                    port * dd->ipath_rcvtidcnt *
1470                                    sizeof(*tidbase));
1471         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1472                 ipath_ht_put_tid(dd, &tidbase[i], 1, dd->ipath_tidinvalid);
1473
1474         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1475                                    dd->ipath_rcvegrbase +
1476                                    port * dd->ipath_rcvegrcnt *
1477                                    sizeof(*tidbase));
1478
1479         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1480                 ipath_ht_put_tid(dd, &tidbase[i], 0, dd->ipath_tidinvalid);
1481 }
1482
1483 /**
1484  * ipath_ht_tidtemplate - setup constants for TID updates
1485  * @dd: the infinipath device
1486  *
1487  * We setup stuff that we use a lot, to avoid calculating each time
1488  */
1489 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1490 {
1491         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1492         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1493         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1494
1495         /*
1496          * work around chip errata bug 7358, by marking invalid tids
1497          * as having max length
1498          */
1499         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1500                 INFINIPATH_RT_BUFSIZE_SHIFT;
1501 }
1502
1503 static int ipath_ht_early_init(struct ipath_devdata *dd)
1504 {
1505         u32 __iomem *piobuf;
1506         u32 pioincr, val32;
1507         int i;
1508
1509         /*
1510          * one cache line; long IB headers will spill over into received
1511          * buffer
1512          */
1513         dd->ipath_rcvhdrentsize = 16;
1514         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1515
1516         /*
1517          * For HT, we allocate a somewhat overly large eager buffer,
1518          * such that we can guarantee that we can receive the largest
1519          * packet that we can send out.  To truly support a 4KB MTU,
1520          * we need to bump this to a large value.  To date, other than
1521          * testing, we have never encountered an HCA that can really
1522          * send 4KB MTU packets, so we do not handle that (we'll get
1523          * errors interrupts if we ever see one).
1524          */
1525         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1526
1527         /*
1528          * the min() check here is currently a nop, but it may not
1529          * always be, depending on just how we do ipath_rcvegrbufsize
1530          */
1531         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1532                                  dd->ipath_rcvegrbufsize);
1533         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1534         ipath_ht_tidtemplate(dd);
1535
1536         /*
1537          * zero all the TID entries at startup.  We do this for sanity,
1538          * in case of a previous driver crash of some kind, and also
1539          * because the chip powers up with these memories in an unknown
1540          * state.  Use portcnt, not cfgports, since this is for the
1541          * full chip, not for current (possibly different) configuration
1542          * value.
1543          * Chip Errata bug 6447
1544          */
1545         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1546                 ipath_ht_clear_tids(dd, val32);
1547
1548         /*
1549          * write the pbc of each buffer, to be sure it's initialized, then
1550          * cancel all the buffers, and also abort any packets that might
1551          * have been in flight for some reason (the latter is for driver
1552          * unload/reload, but isn't a bad idea at first init).  PIO send
1553          * isn't enabled at this point, so there is no danger of sending
1554          * these out on the wire.
1555          * Chip Errata bug 6610
1556          */
1557         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1558                                   dd->ipath_piobufbase);
1559         pioincr = dd->ipath_palign / sizeof(*piobuf);
1560         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1561                 /*
1562                  * reasonable word count, just to init pbc
1563                  */
1564                 writel(16, piobuf);
1565                 piobuf += pioincr;
1566         }
1567         /*
1568          * self-clearing
1569          */
1570         ipath_write_kreg(dd, dd->ipath_kregs->kr_sendctrl,
1571                          INFINIPATH_S_ABORT);
1572
1573         ipath_get_eeprom_info(dd);
1574         if (dd->ipath_boardrev == 5 && dd->ipath_serial[0] == '1' &&
1575                 dd->ipath_serial[1] == '2' && dd->ipath_serial[2] == '8') {
1576                 /*
1577                  * Later production QHT7040 has same changes as QHT7140, so
1578                  * can use GPIO interrupts.  They have serial #'s starting
1579                  * with 128, rather than 112.
1580                  */
1581                 dd->ipath_flags |= IPATH_GPIO_INTR;
1582                 dd->ipath_flags &= ~IPATH_POLL_RX_INTR;
1583         }
1584         return 0;
1585 }
1586
1587
1588 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1589 {
1590         int cnt = ++ipath_stats.sps_txeparity;
1591         if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1592                 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1593                         ipath_dev_err(dd,
1594                                 "Too many attempts to recover from "
1595                                 "TXE parity, giving up\n");
1596                 return 0;
1597         }
1598         dev_info(&dd->pcidev->dev,
1599                 "Recovering from TXE PIO parity error\n");
1600         ipath_disarm_senderrbufs(dd, 1);
1601         return 1;
1602 }
1603
1604
1605 /**
1606  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1607  * @dd: the infinipath device
1608  * @kbase: ipath_base_info pointer
1609  *
1610  * We set the PCIE flag because the lower bandwidth on PCIe vs
1611  * HyperTransport can affect some user packet algorithms.
1612  */
1613 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1614 {
1615         struct ipath_base_info *kinfo = kbase;
1616
1617         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1618                 IPATH_RUNTIME_RCVHDR_COPY;
1619
1620         return 0;
1621 }
1622
1623 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1624 {
1625         free_irq(dd->ipath_irq, dd);
1626         ht_destroy_irq(dd->ipath_irq);
1627         dd->ipath_irq = 0;
1628         dd->ipath_intconfig = 0;
1629 }
1630
1631 /**
1632  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1633  * @dd: the infinipath device
1634  *
1635  * This is global, and is called directly at init to set up the
1636  * chip-specific function pointers for later use.
1637  */
1638 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1639 {
1640         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1641         dd->ipath_f_bus = ipath_setup_ht_config;
1642         dd->ipath_f_reset = ipath_setup_ht_reset;
1643         dd->ipath_f_get_boardname = ipath_ht_boardname;
1644         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1645         dd->ipath_f_early_init = ipath_ht_early_init;
1646         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1647         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1648         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1649         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1650         dd->ipath_f_put_tid = ipath_ht_put_tid;
1651         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1652         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1653         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1654         dd->ipath_f_free_irq = ipath_ht_free_irq;
1655
1656         /*
1657          * initialize chip-specific variables
1658          */
1659         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1660
1661         /*
1662          * setup the register offsets, since they are different for each
1663          * chip
1664          */
1665         dd->ipath_kregs = &ipath_ht_kregs;
1666         dd->ipath_cregs = &ipath_ht_cregs;
1667
1668         /*
1669          * do very early init that is needed before ipath_f_bus is
1670          * called
1671          */
1672         ipath_init_ht_variables(dd);
1673 }