drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/vmalloc.h>
  40 #include <linux/pci.h>
  41 #include <linux/delay.h>
  42 #include <linux/htirq.h>
  43
  44 #include "ipath_kernel.h"
  45 #include "ipath_registers.h"
  46
  47 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
  48
  49
  50 /*
  51  * This lists the InfiniPath registers, in the actual chip layout.
  52  * This structure should never be directly accessed.
  53  *
  54  * The names are in InterCap form because they're taken straight from
  55  * the chip specification.  Since they're only used in this file, they
  56  * don't pollute the rest of the source.
  57 */
  58
  59 struct _infinipath_do_not_use_kernel_regs {
  60         unsigned long long Revision;
  61         unsigned long long Control;
  62         unsigned long long PageAlign;
  63         unsigned long long PortCnt;
  64         unsigned long long DebugPortSelect;
  65         unsigned long long DebugPort;
  66         unsigned long long SendRegBase;
  67         unsigned long long UserRegBase;
  68         unsigned long long CounterRegBase;
  69         unsigned long long Scratch;
  70         unsigned long long ReservedMisc1;
  71         unsigned long long InterruptConfig;
  72         unsigned long long IntBlocked;
  73         unsigned long long IntMask;
  74         unsigned long long IntStatus;
  75         unsigned long long IntClear;
  76         unsigned long long ErrorMask;
  77         unsigned long long ErrorStatus;
  78         unsigned long long ErrorClear;
  79         unsigned long long HwErrMask;
  80         unsigned long long HwErrStatus;
  81         unsigned long long HwErrClear;
  82         unsigned long long HwDiagCtrl;
  83         unsigned long long MDIO;
  84         unsigned long long IBCStatus;
  85         unsigned long long IBCCtrl;
  86         unsigned long long ExtStatus;
  87         unsigned long long ExtCtrl;
  88         unsigned long long GPIOOut;
  89         unsigned long long GPIOMask;
  90         unsigned long long GPIOStatus;
  91         unsigned long long GPIOClear;
  92         unsigned long long RcvCtrl;
  93         unsigned long long RcvBTHQP;
  94         unsigned long long RcvHdrSize;
  95         unsigned long long RcvHdrCnt;
  96         unsigned long long RcvHdrEntSize;
  97         unsigned long long RcvTIDBase;
  98         unsigned long long RcvTIDCnt;
  99         unsigned long long RcvEgrBase;
 100         unsigned long long RcvEgrCnt;
 101         unsigned long long RcvBufBase;
 102         unsigned long long RcvBufSize;
 103         unsigned long long RxIntMemBase;
 104         unsigned long long RxIntMemSize;
 105         unsigned long long RcvPartitionKey;
 106         unsigned long long ReservedRcv[10];
 107         unsigned long long SendCtrl;
 108         unsigned long long SendPIOBufBase;
 109         unsigned long long SendPIOSize;
 110         unsigned long long SendPIOBufCnt;
 111         unsigned long long SendPIOAvailAddr;
 112         unsigned long long TxIntMemBase;
 113         unsigned long long TxIntMemSize;
 114         unsigned long long ReservedSend[9];
 115         unsigned long long SendBufferError;
 116         unsigned long long SendBufferErrorCONT1;
 117         unsigned long long SendBufferErrorCONT2;
 118         unsigned long long SendBufferErrorCONT3;
 119         unsigned long long ReservedSBE[4];
 120         unsigned long long RcvHdrAddr0;
 121         unsigned long long RcvHdrAddr1;
 122         unsigned long long RcvHdrAddr2;
 123         unsigned long long RcvHdrAddr3;
 124         unsigned long long RcvHdrAddr4;
 125         unsigned long long RcvHdrAddr5;
 126         unsigned long long RcvHdrAddr6;
 127         unsigned long long RcvHdrAddr7;
 128         unsigned long long RcvHdrAddr8;
 129         unsigned long long ReservedRHA[7];
 130         unsigned long long RcvHdrTailAddr0;
 131         unsigned long long RcvHdrTailAddr1;
 132         unsigned long long RcvHdrTailAddr2;
 133         unsigned long long RcvHdrTailAddr3;
 134         unsigned long long RcvHdrTailAddr4;
 135         unsigned long long RcvHdrTailAddr5;
 136         unsigned long long RcvHdrTailAddr6;
 137         unsigned long long RcvHdrTailAddr7;
 138         unsigned long long RcvHdrTailAddr8;
 139         unsigned long long ReservedRHTA[7];
 140         unsigned long long Sync;        /* Software only */
 141         unsigned long long Dump;        /* Software only */
 142         unsigned long long SimVer;      /* Software only */
 143         unsigned long long ReservedSW[5];
 144         unsigned long long SerdesConfig0;
 145         unsigned long long SerdesConfig1;
 146         unsigned long long SerdesStatus;
 147         unsigned long long XGXSConfig;
 148         unsigned long long ReservedSW2[4];
 149 };
 150
 151 struct _infinipath_do_not_use_counters {
 152         __u64 LBIntCnt;
 153         __u64 LBFlowStallCnt;
 154         __u64 Reserved1;
 155         __u64 TxUnsupVLErrCnt;
 156         __u64 TxDataPktCnt;
 157         __u64 TxFlowPktCnt;
 158         __u64 TxDwordCnt;
 159         __u64 TxLenErrCnt;
 160         __u64 TxMaxMinLenErrCnt;
 161         __u64 TxUnderrunCnt;
 162         __u64 TxFlowStallCnt;
 163         __u64 TxDroppedPktCnt;
 164         __u64 RxDroppedPktCnt;
 165         __u64 RxDataPktCnt;
 166         __u64 RxFlowPktCnt;
 167         __u64 RxDwordCnt;
 168         __u64 RxLenErrCnt;
 169         __u64 RxMaxMinLenErrCnt;
 170         __u64 RxICRCErrCnt;
 171         __u64 RxVCRCErrCnt;
 172         __u64 RxFlowCtrlErrCnt;
 173         __u64 RxBadFormatCnt;
 174         __u64 RxLinkProblemCnt;
 175         __u64 RxEBPCnt;
 176         __u64 RxLPCRCErrCnt;
 177         __u64 RxBufOvflCnt;
 178         __u64 RxTIDFullErrCnt;
 179         __u64 RxTIDValidErrCnt;
 180         __u64 RxPKeyMismatchCnt;
 181         __u64 RxP0HdrEgrOvflCnt;
 182         __u64 RxP1HdrEgrOvflCnt;
 183         __u64 RxP2HdrEgrOvflCnt;
 184         __u64 RxP3HdrEgrOvflCnt;
 185         __u64 RxP4HdrEgrOvflCnt;
 186         __u64 RxP5HdrEgrOvflCnt;
 187         __u64 RxP6HdrEgrOvflCnt;
 188         __u64 RxP7HdrEgrOvflCnt;
 189         __u64 RxP8HdrEgrOvflCnt;
 190         __u64 Reserved6;
 191         __u64 Reserved7;
 192         __u64 IBStatusChangeCnt;
 193         __u64 IBLinkErrRecoveryCnt;
 194         __u64 IBLinkDownedCnt;
 195         __u64 IBSymbolErrCnt;
 196 };
 197
 198 #define IPATH_KREG_OFFSET(field) (offsetof( \
 199         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 200 #define IPATH_CREG_OFFSET(field) (offsetof( \
 201         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
 202
 203 static const struct ipath_kregs ipath_ht_kregs = {
 204         .kr_control = IPATH_KREG_OFFSET(Control),
 205         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 206         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 207         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 208         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 209         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 210         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 211         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 212         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 213         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 214         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 215         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 216         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 217         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 218         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 219         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 220         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 221         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 222         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 223         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 224         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 225         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 226         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 227         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 228         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 229         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 230         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 231         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 232         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 233         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 234         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 235         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 236         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 237         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 238         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 239         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 240         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 241         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 242         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 243         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 244         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 245         .kr_revision = IPATH_KREG_OFFSET(Revision),
 246         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 247         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 248         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 249         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 250         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 251         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 252         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 253         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 254         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 255         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 256         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 257         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 258         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 259         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 260         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 261         /*
 262          * These should not be used directly via ipath_write_kreg64(),
 263          * use them with ipath_write_kreg64_port(),
 264          */
 265         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 266         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 267 };
 268
 269 static const struct ipath_cregs ipath_ht_cregs = {
 270         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 271         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 272         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 273         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 274         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 275         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 276         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 277         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 278         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 279         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 280         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 281         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 282         /* calc from Reg_CounterRegBase + offset */
 283         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 284         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 285         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 286         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 287         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 288         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 289         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 290         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 291         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 292         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 293         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 294         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 295         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 296         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 297         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 298         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 299         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 300         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 301         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 302         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 303         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 304 };
 305
 306 /* kr_intstatus, kr_intclear, kr_intmask bits */
 307 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 308 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 309
 310 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 311 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 312 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 313 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 314 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 315 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 316 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 317 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 318 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 319 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 320 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 321 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 322 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 323 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 324 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 325 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 326 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 327 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 328 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 329 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 330 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 331
 332 #define IBA6110_IBCS_LINKTRAININGSTATE_MASK 0xf
 333 #define IBA6110_IBCS_LINKSTATE_SHIFT 4
 334
 335 /* kr_extstatus bits */
 336 #define INFINIPATH_EXTS_FREQSEL 0x2
 337 #define INFINIPATH_EXTS_SERDESSEL 0x4
 338 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 339 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 340
 341
 342 /* TID entries (memory), HT-only */
 343 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
 344 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 345 #define INFINIPATH_RT_ADDR_SHIFT 0
 346 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
 347 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
 348
 349 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
 350 #define INFINIPATH_R_TAILUPD_SHIFT 31
 351
 352 /* kr_xgxsconfig bits */
 353 #define INFINIPATH_XGXS_RESET          0x7ULL
 354
 355 /*
 356  * masks and bits that are different in different chips, or present only
 357  * in one
 358  */
 359 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 360     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 361 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 362     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 363
 364 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 365     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 366 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 367     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 368 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 369     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 370 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 371     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 372
 373 #define _IPATH_GPIO_SDA_NUM 1
 374 #define _IPATH_GPIO_SCL_NUM 0
 375
 376 #define IPATH_GPIO_SDA \
 377         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 378 #define IPATH_GPIO_SCL \
 379         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 380
 381 /* keep the code below somewhat more readonable; not used elsewhere */
 382 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 383                                 infinipath_hwe_htclnkabyte1crcerr)
 384 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 385                                 infinipath_hwe_htclnkbbyte1crcerr)
 386 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 387                                 infinipath_hwe_htclnkbbyte0crcerr)
 388 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 389                                 infinipath_hwe_htclnkbbyte1crcerr)
 390
 391 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 392                           char *msg, size_t msgl)
 393 {
 394         char bitsmsg[64];
 395         ipath_err_t crcbits = hwerrs &
 396                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 397         /* don't check if 8bit HT */
 398         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 399                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 400         /* don't check if 8bit HT */
 401         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 402                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 403         /*
 404          * we'll want to ignore link errors on link that is
 405          * not in use, if any.  For now, complain about both
 406          */
 407         if (crcbits) {
 408                 u16 ctrl0, ctrl1;
 409                 snprintf(bitsmsg, sizeof bitsmsg,
 410                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 411                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 412                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 413                                     ? "1 (B)" : "0+1 (A+B)"),
 414                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 415                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 416                             "0+1"), (unsigned long long) crcbits);
 417                 strlcat(msg, bitsmsg, msgl);
 418
 419                 /*
 420                  * print extra info for debugging.  slave/primary
 421                  * config word 4, 8 (link control 0, 1)
 422                  */
 423
 424                 if (pci_read_config_word(dd->pcidev,
 425                                          dd->ipath_ht_slave_off + 0x4,
 426                                          &ctrl0))
 427                         dev_info(&dd->pcidev->dev, "Couldn't read "
 428                                  "linkctrl0 of slave/primary "
 429                                  "config block\n");
 430                 else if (!(ctrl0 & 1 << 6))
 431                         /* not if EOC bit set */
 432                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 433                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 434                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 435                                   "");
 436                 if (pci_read_config_word(dd->pcidev,
 437                                          dd->ipath_ht_slave_off + 0x8,
 438                                          &ctrl1))
 439                         dev_info(&dd->pcidev->dev, "Couldn't read "
 440                                  "linkctrl1 of slave/primary "
 441                                  "config block\n");
 442                 else if (!(ctrl1 & 1 << 6))
 443                         /* not if EOC bit set */
 444                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 445                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 446                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 447                                   "");
 448
 449                 /* disable until driver reloaded */
 450                 dd->ipath_hwerrmask &= ~crcbits;
 451                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 452                                  dd->ipath_hwerrmask);
 453                 ipath_dbg("HT crc errs: %s\n", msg);
 454         } else
 455                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 456                           "not in use\n", (unsigned long long)
 457                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 458                                      _IPATH_HTLINK1_CRCBITS)));
 459 }
 460
 461 /* 6110 specific hardware errors... */
 462 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 463         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 464         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 465         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 466         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 467         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 468         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 469         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 470         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 471 };
 472
 473 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 474                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 475                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 476 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
 477                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
 478
 479 static int ipath_ht_txe_recover(struct ipath_devdata *);
 480
 481 /**
 482  * ipath_ht_handle_hwerrors - display hardware errors.
 483  * @dd: the infinipath device
 484  * @msg: the output buffer
 485  * @msgl: the size of the output buffer
 486  *
 487  * Use same msg buffer as regular errors to avoid excessive stack
 488  * use.  Most hardware errors are catastrophic, but for right now,
 489  * we'll print them and continue.  We reuse the same message buffer as
 490  * ipath_handle_errors() to avoid excessive stack usage.
 491  */
 492 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 493                                      size_t msgl)
 494 {
 495         ipath_err_t hwerrs;
 496         u32 bits, ctrl;
 497         int isfatal = 0;
 498         char bitsmsg[64];
 499         int log_idx;
 500
 501         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 502
 503         if (!hwerrs) {
 504                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 505                 /*
 506                  * better than printing cofusing messages
 507                  * This seems to be related to clearing the crc error, or
 508                  * the pll error during init.
 509                  */
 510                 goto bail;
 511         } else if (hwerrs == -1LL) {
 512                 ipath_dev_err(dd, "Read of hardware error status failed "
 513                               "(all bits set); ignoring\n");
 514                 goto bail;
 515         }
 516         ipath_stats.sps_hwerrs++;
 517
 518         /* Always clear the error status register, except MEMBISTFAIL,
 519          * regardless of whether we continue or stop using the chip.
 520          * We want that set so we know it failed, even across driver reload.
 521          * We'll still ignore it in the hwerrmask.  We do this partly for
 522          * diagnostics, but also for support */
 523         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 524                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 525
 526         hwerrs &= dd->ipath_hwerrmask;
 527
 528         /* We log some errors to EEPROM, check if we have any of those. */
 529         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 530                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 531                         ipath_inc_eeprom_err(dd, log_idx, 1);
 532
 533         /*
 534          * make sure we get this much out, unless told to be quiet,
 535          * it's a parity error we may recover from,
 536          * or it's occurred within the last 5 seconds
 537          */
 538         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
 539                 RXE_EAGER_PARITY)) ||
 540                 (ipath_debug & __IPATH_VERBDBG))
 541                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 542                          "(cleared)\n", (unsigned long long) hwerrs);
 543         dd->ipath_lasthwerror |= hwerrs;
 544
 545         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 546                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 547                               "%llx set\n", (unsigned long long)
 548                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 549
 550         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 551         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
 552                 /*
 553                  * parity errors in send memory are recoverable,
 554                  * just cancel the send (if indicated in * sendbuffererror),
 555                  * count the occurrence, unfreeze (if no other handled
 556                  * hardware error bits are set), and continue. They can
 557                  * occur if a processor speculative read is done to the PIO
 558                  * buffer while we are sending a packet, for example.
 559                  */
 560                 if ((hwerrs & TXE_PIO_PARITY) && ipath_ht_txe_recover(dd))
 561                         hwerrs &= ~TXE_PIO_PARITY;
 562                 if (hwerrs & RXE_EAGER_PARITY)
 563                         ipath_dev_err(dd, "RXE parity, Eager TID error is not "
 564                                 "recoverable\n");
 565                 if (!hwerrs) {
 566                         ipath_dbg("Clearing freezemode on ignored or "
 567                                   "recovered hardware error\n");
 568                         ipath_clear_freeze(dd);
 569                 }
 570         }
 571
 572         *msg = '\0';
 573
 574         /*
 575          * may someday want to decode into which bits are which
 576          * functional area for parity errors, etc.
 577          */
 578         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 579                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 580                 bits = (u32) ((hwerrs >>
 581                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 582                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 583                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 584                          bits);
 585                 strlcat(msg, bitsmsg, msgl);
 586         }
 587
 588         ipath_format_hwerrors(hwerrs,
 589                               ipath_6110_hwerror_msgs,
 590                               sizeof(ipath_6110_hwerror_msgs) /
 591                               sizeof(ipath_6110_hwerror_msgs[0]),
 592                               msg, msgl);
 593
 594         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 595                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 596
 597         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 598                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 599                         msgl);
 600                 /* ignore from now on, so disable until driver reloaded */
 601                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 602                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 603                                  dd->ipath_hwerrmask);
 604         }
 605 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 606                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 607                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 608                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 609                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 610                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 611
 612         if (hwerrs & _IPATH_PLL_FAIL) {
 613                 snprintf(bitsmsg, sizeof bitsmsg,
 614                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 615                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 616                 strlcat(msg, bitsmsg, msgl);
 617                 /* ignore from now on, so disable until driver reloaded */
 618                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 619                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 620                                  dd->ipath_hwerrmask);
 621         }
 622
 623         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 624                 /*
 625                  * If it occurs, it is left masked since the eternal
 626                  * interface is unused
 627                  */
 628                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 629                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 630                                  dd->ipath_hwerrmask);
 631         }
 632
 633         if (hwerrs) {
 634                 /*
 635                  * if any set that we aren't ignoring; only
 636                  * make the complaint once, in case it's stuck
 637                  * or recurring, and we get here multiple
 638                  * times.
 639                  * force link down, so switch knows, and
 640                  * LEDs are turned off
 641                  */
 642                 if (dd->ipath_flags & IPATH_INITTED) {
 643                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 644                         ipath_setup_ht_setextled(dd,
 645                                 INFINIPATH_IBCS_L_STATE_DOWN,
 646                                 INFINIPATH_IBCS_LT_STATE_DISABLED);
 647                         ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 648                                           "mode), no longer usable, SN %.16s\n",
 649                                           dd->ipath_serial);
 650                         isfatal = 1;
 651                 }
 652                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 653                 /* mark as having had error */
 654                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 655                 /*
 656                  * mark as not usable, at a minimum until driver
 657                  * is reloaded, probably until reboot, since no
 658                  * other reset is possible.
 659                  */
 660                 dd->ipath_flags &= ~IPATH_INITTED;
 661         }
 662         else
 663                 *msg = 0; /* recovered from all of them */
 664         if (*msg)
 665                 ipath_dev_err(dd, "%s hardware error\n", msg);
 666         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 667                 /*
 668                  * for status file; if no trailing brace is copied,
 669                  * we'll know it was truncated.
 670                  */
 671                 snprintf(dd->ipath_freezemsg,
 672                          dd->ipath_freezelen, "{%s}", msg);
 673
 674 bail:;
 675 }
 676
 677 /**
 678  * ipath_ht_boardname - fill in the board name
 679  * @dd: the infinipath device
 680  * @name: the output buffer
 681  * @namelen: the size of the output buffer
 682  *
 683  * fill in the board name, based on the board revision register
 684  */
 685 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 686                               size_t namelen)
 687 {
 688         char *n = NULL;
 689         u8 boardrev = dd->ipath_boardrev;
 690         int ret = 0;
 691
 692         switch (boardrev) {
 693         case 5:
 694                 /*
 695                  * original production board; two production levels, with
 696                  * different serial number ranges.   See ipath_ht_early_init() for
 697                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 698                  * Original 112* serial number is no longer supported.
 699                  */
 700                 n = "InfiniPath_QHT7040";
 701                 break;
 702         case 7:
 703                 /* small form factor production board */
 704                 n = "InfiniPath_QHT7140";
 705                 break;
 706         default:                /* don't know, just print the number */
 707                 ipath_dev_err(dd, "Don't yet know about board "
 708                               "with ID %u\n", boardrev);
 709                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 710                          boardrev);
 711                 break;
 712         }
 713         if (n)
 714                 snprintf(name, namelen, "%s", n);
 715
 716         if (ret) {
 717                 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
 718                 goto bail;
 719         }
 720         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
 721                 dd->ipath_minrev > 4)) {
 722                 /*
 723                  * This version of the driver only supports Rev 3.2 - 3.4
 724                  */
 725                 ipath_dev_err(dd,
 726                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 727                               dd->ipath_majrev, dd->ipath_minrev);
 728                 ret = 1;
 729                 goto bail;
 730         }
 731         /*
 732          * pkt/word counters are 32 bit, and therefore wrap fast enough
 733          * that we snapshot them from a timer, and maintain 64 bit shadow
 734          * copies
 735          */
 736         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 737         dd->ipath_flags |= IPATH_GPIO_INTR;
 738         if (dd->ipath_htspeed != 800)
 739                 ipath_dev_err(dd,
 740                               "Incorrectly configured for HT @ %uMHz\n",
 741                               dd->ipath_htspeed);
 742         ret = 0;
 743
 744         /*
 745          * set here, not in ipath_init_*_funcs because we have to do
 746          * it after we can read chip registers.
 747          */
 748         dd->ipath_ureg_align =
 749                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 750
 751 bail:
 752         return ret;
 753 }
 754
 755 static void ipath_check_htlink(struct ipath_devdata *dd)
 756 {
 757         u8 linkerr, link_off, i;
 758
 759         for (i = 0; i < 2; i++) {
 760                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 761                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 762                         dev_info(&dd->pcidev->dev, "Couldn't read "
 763                                  "linkerror%d of HT slave/primary block\n",
 764                                  i);
 765                 else if (linkerr & 0xf0) {
 766                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 767                                    "clearing\n", linkerr >> 4, i);
 768                         /*
 769                          * writing the linkerr bits that are set should
 770                          * clear them
 771                          */
 772                         if (pci_write_config_byte(dd->pcidev, link_off,
 773                                                   linkerr))
 774                                 ipath_dbg("Failed write to clear HT "
 775                                           "linkerror%d\n", i);
 776                         if (pci_read_config_byte(dd->pcidev, link_off,
 777                                                  &linkerr))
 778                                 dev_info(&dd->pcidev->dev,
 779                                          "Couldn't reread linkerror%d of "
 780                                          "HT slave/primary block\n", i);
 781                         else if (linkerr & 0xf0)
 782                                 dev_info(&dd->pcidev->dev,
 783                                          "HT linkerror%d bits 0x%x "
 784                                          "couldn't be cleared\n",
 785                                          i, linkerr >> 4);
 786                 }
 787         }
 788 }
 789
 790 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 791 {
 792         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 793         return 0;
 794 }
 795
 796 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 797 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 798
 799 /*
 800  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 801  * errors.  We only bother to do this at load time, because it's OK if
 802  * it happened before we were loaded (first time after boot/reset),
 803  * but any time after that, it's fatal anyway.  Also need to not check
 804  * for for upper byte errors if we are in 8 bit mode, so figure out
 805  * our width.  For now, at least, also complain if it's 8 bit.
 806  */
 807 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 808                              int pos, u8 cap_type)
 809 {
 810         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 811         u16 linkctrl = 0;
 812         int i;
 813
 814         dd->ipath_ht_slave_off = pos;
 815         /* command word, master_host bit */
 816         /* master host || slave */
 817         if ((cap_type >> 2) & 1)
 818                 link_a_b_off = 4;
 819         else
 820                 link_a_b_off = 0;
 821         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 822                    link_a_b_off ? 1 : 0,
 823                    link_a_b_off ? 'B' : 'A');
 824
 825         link_a_b_off += pos;
 826
 827         /*
 828          * check both link control registers; clear both HT CRC sets if
 829          * necessary.
 830          */
 831         for (i = 0; i < 2; i++) {
 832                 link_off = pos + i * 4 + 0x4;
 833                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 834                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 835                                       "register\n", i);
 836                 else if (linkctrl & (0xf << 8)) {
 837                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 838                                    "bits %x\n", i, linkctrl & (0xf << 8));
 839                         /*
 840                          * now write them back to clear the error.
 841                          */
 842                         pci_write_config_byte(pdev, link_off,
 843                                               linkctrl & (0xf << 8));
 844                 }
 845         }
 846
 847         /*
 848          * As with HT CRC bits, same for protocol errors that might occur
 849          * during boot.
 850          */
 851         for (i = 0; i < 2; i++) {
 852                 link_off = pos + i * 4 + 0xd;
 853                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 854                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 855                                  "of HT slave/primary block\n", i);
 856                 else if (linkerr & 0xf0) {
 857                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 858                                    "clearing\n", linkerr >> 4, i);
 859                         /*
 860                          * writing the linkerr bits that are set will clear
 861                          * them
 862                          */
 863                         if (pci_write_config_byte
 864                             (pdev, link_off, linkerr))
 865                                 ipath_dbg("Failed write to clear HT "
 866                                           "linkerror%d\n", i);
 867                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 868                                 dev_info(&pdev->dev, "Couldn't reread "
 869                                          "linkerror%d of HT slave/primary "
 870                                          "block\n", i);
 871                         else if (linkerr & 0xf0)
 872                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 873                                          "0x%x couldn't be cleared\n",
 874                                          i, linkerr >> 4);
 875                 }
 876         }
 877
 878         /*
 879          * this is just for our link to the host, not devices connected
 880          * through tunnel.
 881          */
 882
 883         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 884                 ipath_dev_err(dd, "Couldn't read HT link width "
 885                               "config register\n");
 886         else {
 887                 u32 width;
 888                 switch (linkwidth & 7) {
 889                 case 5:
 890                         width = 4;
 891                         break;
 892                 case 4:
 893                         width = 2;
 894                         break;
 895                 case 3:
 896                         width = 32;
 897                         break;
 898                 case 1:
 899                         width = 16;
 900                         break;
 901                 case 0:
 902                 default:        /* if wrong, assume 8 bit */
 903                         width = 8;
 904                         break;
 905                 }
 906
 907                 dd->ipath_htwidth = width;
 908
 909                 if (linkwidth != 0x11) {
 910                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 911                                       "(%x)\n", linkwidth);
 912                         if (!(linkwidth & 0xf)) {
 913                                 ipath_dbg("Will ignore HT lane1 errors\n");
 914                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 915                         }
 916                 }
 917         }
 918
 919         /*
 920          * this is just for our link to the host, not devices connected
 921          * through tunnel.
 922          */
 923         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 924                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 925                               "config register\n");
 926         else {
 927                 u32 speed;
 928                 switch (linkwidth & 0xf) {
 929                 case 6:
 930                         speed = 1000;
 931                         break;
 932                 case 5:
 933                         speed = 800;
 934                         break;
 935                 case 4:
 936                         speed = 600;
 937                         break;
 938                 case 3:
 939                         speed = 500;
 940                         break;
 941                 case 2:
 942                         speed = 400;
 943                         break;
 944                 case 1:
 945                         speed = 300;
 946                         break;
 947                 default:
 948                         /*
 949                          * assume reserved and vendor-specific are 200...
 950                          */
 951                 case 0:
 952                         speed = 200;
 953                         break;
 954                 }
 955                 dd->ipath_htspeed = speed;
 956         }
 957 }
 958
 959 static int ipath_ht_intconfig(struct ipath_devdata *dd)
 960 {
 961         int ret;
 962
 963         if (dd->ipath_intconfig) {
 964                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
 965                                  dd->ipath_intconfig);  /* interrupt address */
 966                 ret = 0;
 967         } else {
 968                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
 969                               "interrupt address\n");
 970                 ret = -EINVAL;
 971         }
 972
 973         return ret;
 974 }
 975
 976 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
 977                                 struct ht_irq_msg *msg)
 978 {
 979         struct ipath_devdata *dd = pci_get_drvdata(dev);
 980         u64 prev_intconfig = dd->ipath_intconfig;
 981
 982         dd->ipath_intconfig = msg->address_lo;
 983         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
 984
 985         /*
 986          * If the previous value of dd->ipath_intconfig is zero, we're
 987          * getting configured for the first time, and must not program the
 988          * intconfig register here (it will be programmed later, when the
 989          * hardware is ready).  Otherwise, we should.
 990          */
 991         if (prev_intconfig)
 992                 ipath_ht_intconfig(dd);
 993 }
 994
 995 /**
 996  * ipath_setup_ht_config - setup the interruptconfig register
 997  * @dd: the infinipath device
 998  * @pdev: the PCI device
 999  *
1000  * setup the interruptconfig register from the HT config info.
1001  * Also clear CRC errors in HT linkcontrol, if necessary.
1002  * This is done only for the real hardware.  It is done before
1003  * chip address space is initted, so can't touch infinipath registers
1004  */
1005 static int ipath_setup_ht_config(struct ipath_devdata *dd,
1006                                  struct pci_dev *pdev)
1007 {
1008         int pos, ret;
1009
1010         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
1011         if (ret < 0) {
1012                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
1013                               "err %d\n", ret);
1014                 goto bail;
1015         }
1016         dd->ipath_irq = ret;
1017         ret = 0;
1018
1019         /*
1020          * Handle clearing CRC errors in linkctrl register if necessary.  We
1021          * do this early, before we ever enable errors or hardware errors,
1022          * mostly to avoid causing the chip to enter freeze mode.
1023          */
1024         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
1025         if (!pos) {
1026                 ipath_dev_err(dd, "Couldn't find HyperTransport "
1027                               "capability; no interrupts\n");
1028                 ret = -ENODEV;
1029                 goto bail;
1030         }
1031         do {
1032                 u8 cap_type;
1033
1034                 /*
1035                  * The HT capability type byte is 3 bytes after the
1036                  * capability byte.
1037                  */
1038                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1039                         dev_info(&pdev->dev, "Couldn't read config "
1040                                  "command @ %d\n", pos);
1041                         continue;
1042                 }
1043                 if (!(cap_type & 0xE0))
1044                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1045         } while ((pos = pci_find_next_capability(pdev, pos,
1046                                                  PCI_CAP_ID_HT)));
1047
1048         dd->ipath_flags |= IPATH_SWAP_PIOBUFS;
1049
1050 bail:
1051         return ret;
1052 }
1053
1054 /**
1055  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1056  * @dd: the infinipath device
1057  *
1058  * Called during driver unload.
1059  * This is currently a nop for the HT chip, not for all chips
1060  */
1061 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1062 {
1063 }
1064
1065 /**
1066  * ipath_setup_ht_setextled - set the state of the two external LEDs
1067  * @dd: the infinipath device
1068  * @lst: the L state
1069  * @ltst: the LT state
1070  *
1071  * Set the state of the two external LEDs, to indicate physical and
1072  * logical state of IB link.   For this chip (at least with recommended
1073  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1074  * (logical state)
1075  *
1076  * Note:  We try to match the Mellanox HCA LED behavior as best
1077  * we can.  Green indicates physical link state is OK (something is
1078  * plugged in, and we can train).
1079  * Amber indicates the link is logically up (ACTIVE).
1080  * Mellanox further blinks the amber LED to indicate data packet
1081  * activity, but we have no hardware support for that, so it would
1082  * require waking up every 10-20 msecs and checking the counters
1083  * on the chip, and then turning the LED off if appropriate.  That's
1084  * visible overhead, so not something we will do.
1085  *
1086  */
1087 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1088                                      u64 lst, u64 ltst)
1089 {
1090         u64 extctl;
1091         unsigned long flags = 0;
1092
1093         /* the diags use the LED to indicate diag info, so we leave
1094          * the external LED alone when the diags are running */
1095         if (ipath_diag_inuse)
1096                 return;
1097
1098         /* Allow override of LED display for, e.g. Locating system in rack */
1099         if (dd->ipath_led_override) {
1100                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1101                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
1102                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
1103                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1104                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
1105                         : INFINIPATH_IBCS_L_STATE_DOWN;
1106         }
1107
1108         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1109         /*
1110          * start by setting both LED control bits to off, then turn
1111          * on the appropriate bit(s).
1112          */
1113         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1114                 /*
1115                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1116                  * is inverted,  because it is normally used to indicate
1117                  * a hardware fault at reset, if there were errors
1118                  */
1119                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1120                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1121                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1122                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1123                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1124                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1125         }
1126         else {
1127                 extctl = dd->ipath_extctrl &
1128                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1129                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1130                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1131                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1132                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1133                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1134         }
1135         dd->ipath_extctrl = extctl;
1136         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1137         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1138 }
1139
1140 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1141 {
1142         /*
1143          * setup the register offsets, since they are different for each
1144          * chip
1145          */
1146         dd->ipath_kregs = &ipath_ht_kregs;
1147         dd->ipath_cregs = &ipath_ht_cregs;
1148
1149         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1150         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1151         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1152         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1153
1154         /*
1155          * Fill in data for field-values that change in newer chips.
1156          * We dynamically specify only the mask for LINKTRAININGSTATE
1157          * and only the shift for LINKSTATE, as they are the only ones
1158          * that change.  Also precalculate the 3 link states of interest
1159          * and the combined mask.
1160          */
1161         dd->ibcs_ls_shift = IBA6110_IBCS_LINKSTATE_SHIFT;
1162         dd->ibcs_lts_mask = IBA6110_IBCS_LINKTRAININGSTATE_MASK;
1163         dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1164                 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1165         dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1166                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1167                 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1168         dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1169                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1170                 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1171         dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1172                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1173                 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1174
1175         /*
1176          * Fill in data for ibcc field-values that change in newer chips.
1177          * We dynamically specify only the mask for LINKINITCMD
1178          * and only the shift for LINKCMD and MAXPKTLEN, as they are
1179          * the only ones that change.
1180          */
1181         dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1182         dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1183         dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1184
1185         /* Fill in shifts for RcvCtrl. */
1186         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1187         dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1188         dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1189         dd->ipath_r_portcfg_shift = 0; /* Not on IBA6110 */
1190
1191         dd->ipath_i_bitsextant =
1192                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1193                 (INFINIPATH_I_RCVAVAIL_MASK <<
1194                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1195                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1196                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1197
1198         dd->ipath_e_bitsextant =
1199                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1200                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1201                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1202                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1203                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1204                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1205                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1206                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1207                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1208                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1209                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1210                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1211                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1212                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1213                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1214                 INFINIPATH_E_HARDWARE;
1215
1216         dd->ipath_hwe_bitsextant =
1217                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1218                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1219                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1220                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1221                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1222                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1223                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1224                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1225                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1226                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1227                 INFINIPATH_HWE_HTCMISCERR4 |
1228                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1229                 INFINIPATH_HWE_HTCMISCERR7 |
1230                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1231                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1232                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1233                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1234                 INFINIPATH_HWE_MEMBISTFAILED |
1235                 INFINIPATH_HWE_COREPLL_FBSLIP |
1236                 INFINIPATH_HWE_COREPLL_RFSLIP |
1237                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1238                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1239                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1240                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1241                 INFINIPATH_HWE_SERDESPLLFAILED |
1242                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1243                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1244
1245         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1246         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1247         dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1248         dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1249
1250         /*
1251          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1252          * 2 is Some Misc, 3 is reserved for future.
1253          */
1254         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1255                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1256                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1257
1258         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1259                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1260                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1261
1262         dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1263
1264         dd->delay_mult = 2; /* SDR, 4X, can't change */
1265
1266         dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1267         dd->ipath_link_speed_supported = IPATH_IB_SDR;
1268         dd->ipath_link_width_enabled = IB_WIDTH_4X;
1269         dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1270         /* these can't change for this chip, so set once */
1271         dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1272         dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1273 }
1274
1275 /**
1276  * ipath_ht_init_hwerrors - enable hardware errors
1277  * @dd: the infinipath device
1278  *
1279  * now that we have finished initializing everything that might reasonably
1280  * cause a hardware error, and cleared those errors bits as they occur,
1281  * we can enable hardware errors in the mask (potentially enabling
1282  * freeze mode), and enable hardware errors as errors (along with
1283  * everything else) in errormask
1284  */
1285 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1286 {
1287         ipath_err_t val;
1288         u64 extsval;
1289
1290         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1291
1292         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1293                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1294         if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1295                 ipath_dbg("MemBIST corrected\n");
1296
1297         ipath_check_htlink(dd);
1298
1299         /* barring bugs, all hwerrors become interrupts, which can */
1300         val = -1LL;
1301         /* don't look at crc lane1 if 8 bit */
1302         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1303                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1304         /* don't look at crc lane1 if 8 bit */
1305         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1306                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1307
1308         /*
1309          * disable RXDSYNCMEMPARITY because external serdes is unused,
1310          * and therefore the logic will never be used or initialized,
1311          * and uninitialized state will normally result in this error
1312          * being asserted.  Similarly for the external serdess pll
1313          * lock signal.
1314          */
1315         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1316                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1317
1318         /*
1319          * Disable MISCERR4 because of an inversion in the HT core
1320          * logic checking for errors that cause this bit to be set.
1321          * The errata can also cause the protocol error bit to be set
1322          * in the HT config space linkerror register(s).
1323          */
1324         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1325
1326         /*
1327          * PLL ignored because unused MDIO interface has a logic problem
1328          */
1329         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1330                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1331         dd->ipath_hwerrmask = val;
1332 }
1333
1334
1335
1336
1337 /**
1338  * ipath_ht_bringup_serdes - bring up the serdes
1339  * @dd: the infinipath device
1340  */
1341 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1342 {
1343         u64 val, config1;
1344         int ret = 0, change = 0;
1345
1346         ipath_dbg("Trying to bringup serdes\n");
1347
1348         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1349             INFINIPATH_HWE_SERDESPLLFAILED)
1350         {
1351                 ipath_dbg("At start, serdes PLL failed bit set in "
1352                           "hwerrstatus, clearing and continuing\n");
1353                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1354                                  INFINIPATH_HWE_SERDESPLLFAILED);
1355         }
1356
1357         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1358         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1359
1360         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1361                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1362                    (unsigned long long) val, (unsigned long long) config1,
1363                    (unsigned long long)
1364                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1365                    (unsigned long long)
1366                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1367
1368         /* force reset on */
1369         val |= INFINIPATH_SERDC0_RESET_PLL
1370                 /* | INFINIPATH_SERDC0_RESET_MASK */
1371                 ;
1372         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1373         udelay(15);             /* need pll reset set at least for a bit */
1374
1375         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1376                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1377                 /* set lane resets, and tx idle, during pll reset */
1378                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1379                         INFINIPATH_SERDC0_TXIDLE;
1380                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1381                            "%llx)\n", (unsigned long long) val2);
1382                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1383                                  val2);
1384                 /*
1385                  * be sure chip saw it
1386                  */
1387                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1388                 /*
1389                  * need pll reset clear at least 11 usec before lane
1390                  * resets cleared; give it a few more
1391                  */
1392                 udelay(15);
1393                 val = val2;     /* for check below */
1394         }
1395
1396         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1397                    INFINIPATH_SERDC0_RESET_MASK |
1398                    INFINIPATH_SERDC0_TXIDLE)) {
1399                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1400                          INFINIPATH_SERDC0_RESET_MASK |
1401                          INFINIPATH_SERDC0_TXIDLE);
1402                 /* clear them */
1403                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1404                                  val);
1405         }
1406
1407         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1408         if (val & INFINIPATH_XGXS_RESET) {
1409                 /* normally true after boot */
1410                 val &= ~INFINIPATH_XGXS_RESET;
1411                 change = 1;
1412         }
1413         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1414              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1415                 /* need to compensate for Tx inversion in partner */
1416                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1417                          INFINIPATH_XGXS_RX_POL_SHIFT);
1418                 val |= dd->ipath_rx_pol_inv <<
1419                         INFINIPATH_XGXS_RX_POL_SHIFT;
1420                 change = 1;
1421         }
1422         if (change)
1423                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1424
1425         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1426
1427         /* clear current and de-emphasis bits */
1428         config1 &= ~0x0ffffffff00ULL;
1429         /* set current to 20ma */
1430         config1 |= 0x00000000000ULL;
1431         /* set de-emphasis to -5.68dB */
1432         config1 |= 0x0cccc000000ULL;
1433         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1434
1435         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1436                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1437                    (unsigned long long) val, (unsigned long long) config1,
1438                    (unsigned long long)
1439                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1440                    (unsigned long long)
1441                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1442
1443         return ret;             /* for now, say we always succeeded */
1444 }
1445
1446 /**
1447  * ipath_ht_quiet_serdes - set serdes to txidle
1448  * @dd: the infinipath device
1449  * driver is being unloaded
1450  */
1451 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1452 {
1453         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1454
1455         val |= INFINIPATH_SERDC0_TXIDLE;
1456         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1457                   (unsigned long long) val);
1458         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1459 }
1460
1461 /**
1462  * ipath_pe_put_tid - write a TID in chip
1463  * @dd: the infinipath device
1464  * @tidptr: pointer to the expected TID (in chip) to udpate
1465  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1466  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1467  *
1468  * This exists as a separate routine to allow for special locking etc.
1469  * It's used for both the full cleanup on exit, as well as the normal
1470  * setup and teardown.
1471  */
1472 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1473                              u64 __iomem *tidptr, u32 type,
1474                              unsigned long pa)
1475 {
1476         if (!dd->ipath_kregbase)
1477                 return;
1478
1479         if (pa != dd->ipath_tidinvalid) {
1480                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1481                         dev_info(&dd->pcidev->dev,
1482                                  "physaddr %lx has more than "
1483                                  "40 bits, using only 40!!!\n", pa);
1484                         pa &= INFINIPATH_RT_ADDR_MASK;
1485                 }
1486                 if (type == RCVHQ_RCV_TYPE_EAGER)
1487                         pa |= dd->ipath_tidtemplate;
1488                 else {
1489                         /* in words (fixed, full page).  */
1490                         u64 lenvalid = PAGE_SIZE >> 2;
1491                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1492                         pa |= lenvalid | INFINIPATH_RT_VALID;
1493                 }
1494         }
1495
1496         writeq(pa, tidptr);
1497 }
1498
1499
1500 /**
1501  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1502  * @dd: the infinipath device
1503  * @port: the port
1504  *
1505  * Used from ipath_close(), and at chip initialization.
1506  */
1507 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1508 {
1509         u64 __iomem *tidbase;
1510         int i;
1511
1512         if (!dd->ipath_kregbase)
1513                 return;
1514
1515         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1516
1517         /*
1518          * need to invalidate all of the expected TID entries for this
1519          * port, so we don't have valid entries that might somehow get
1520          * used (early in next use of this port, or through some bug)
1521          */
1522         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1523                                    dd->ipath_rcvtidbase +
1524                                    port * dd->ipath_rcvtidcnt *
1525                                    sizeof(*tidbase));
1526         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1527                 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1528                                  dd->ipath_tidinvalid);
1529
1530         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1531                                    dd->ipath_rcvegrbase +
1532                                    port * dd->ipath_rcvegrcnt *
1533                                    sizeof(*tidbase));
1534
1535         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1536                 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1537                                  dd->ipath_tidinvalid);
1538 }
1539
1540 /**
1541  * ipath_ht_tidtemplate - setup constants for TID updates
1542  * @dd: the infinipath device
1543  *
1544  * We setup stuff that we use a lot, to avoid calculating each time
1545  */
1546 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1547 {
1548         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1549         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1550         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1551
1552         /*
1553          * work around chip errata bug 7358, by marking invalid tids
1554          * as having max length
1555          */
1556         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1557                 INFINIPATH_RT_BUFSIZE_SHIFT;
1558 }
1559
1560 static int ipath_ht_early_init(struct ipath_devdata *dd)
1561 {
1562         u32 __iomem *piobuf;
1563         u32 pioincr, val32;
1564         int i;
1565
1566         /*
1567          * one cache line; long IB headers will spill over into received
1568          * buffer
1569          */
1570         dd->ipath_rcvhdrentsize = 16;
1571         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1572
1573         /*
1574          * For HT, we allocate a somewhat overly large eager buffer,
1575          * such that we can guarantee that we can receive the largest
1576          * packet that we can send out.  To truly support a 4KB MTU,
1577          * we need to bump this to a large value.  To date, other than
1578          * testing, we have never encountered an HCA that can really
1579          * send 4KB MTU packets, so we do not handle that (we'll get
1580          * errors interrupts if we ever see one).
1581          */
1582         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1583
1584         /*
1585          * the min() check here is currently a nop, but it may not
1586          * always be, depending on just how we do ipath_rcvegrbufsize
1587          */
1588         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1589                                  dd->ipath_rcvegrbufsize);
1590         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1591         ipath_ht_tidtemplate(dd);
1592
1593         /*
1594          * zero all the TID entries at startup.  We do this for sanity,
1595          * in case of a previous driver crash of some kind, and also
1596          * because the chip powers up with these memories in an unknown
1597          * state.  Use portcnt, not cfgports, since this is for the
1598          * full chip, not for current (possibly different) configuration
1599          * value.
1600          * Chip Errata bug 6447
1601          */
1602         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1603                 ipath_ht_clear_tids(dd, val32);
1604
1605         /*
1606          * write the pbc of each buffer, to be sure it's initialized, then
1607          * cancel all the buffers, and also abort any packets that might
1608          * have been in flight for some reason (the latter is for driver
1609          * unload/reload, but isn't a bad idea at first init).  PIO send
1610          * isn't enabled at this point, so there is no danger of sending
1611          * these out on the wire.
1612          * Chip Errata bug 6610
1613          */
1614         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1615                                   dd->ipath_piobufbase);
1616         pioincr = dd->ipath_palign / sizeof(*piobuf);
1617         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1618                 /*
1619                  * reasonable word count, just to init pbc
1620                  */
1621                 writel(16, piobuf);
1622                 piobuf += pioincr;
1623         }
1624
1625         ipath_get_eeprom_info(dd);
1626         if (dd->ipath_boardrev == 5) {
1627                 /*
1628                  * Later production QHT7040 has same changes as QHT7140, so
1629                  * can use GPIO interrupts.  They have serial #'s starting
1630                  * with 128, rather than 112.
1631                  */
1632                 if (dd->ipath_serial[0] == '1' &&
1633                     dd->ipath_serial[1] == '2' &&
1634                     dd->ipath_serial[2] == '8')
1635                         dd->ipath_flags |= IPATH_GPIO_INTR;
1636                 else {
1637                         ipath_dev_err(dd, "Unsupported InfiniPath board "
1638                                 "(serial number %.16s)!\n",
1639                                 dd->ipath_serial);
1640                         return 1;
1641                 }
1642         }
1643
1644         if (dd->ipath_minrev >= 4) {
1645                 /* Rev4+ reports extra errors via internal GPIO pins */
1646                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1647                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1648                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1649                                  dd->ipath_gpio_mask);
1650         }
1651
1652         return 0;
1653 }
1654
1655
1656 static int ipath_ht_txe_recover(struct ipath_devdata *dd)
1657 {
1658         int cnt = ++ipath_stats.sps_txeparity;
1659         if (cnt >= IPATH_MAX_PARITY_ATTEMPTS)  {
1660                 if (cnt == IPATH_MAX_PARITY_ATTEMPTS)
1661                         ipath_dev_err(dd,
1662                                 "Too many attempts to recover from "
1663                                 "TXE parity, giving up\n");
1664                 return 0;
1665         }
1666         dev_info(&dd->pcidev->dev,
1667                 "Recovering from TXE PIO parity error\n");
1668         return 1;
1669 }
1670
1671
1672 /**
1673  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1674  * @dd: the infinipath device
1675  * @kbase: ipath_base_info pointer
1676  *
1677  * We set the PCIE flag because the lower bandwidth on PCIe vs
1678  * HyperTransport can affect some user packet algorithms.
1679  */
1680 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1681 {
1682         struct ipath_base_info *kinfo = kbase;
1683
1684         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1685                 IPATH_RUNTIME_PIO_REGSWAPPED;
1686
1687         if (pd->port_dd->ipath_minrev < 4)
1688                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
1689
1690         return 0;
1691 }
1692
1693 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1694 {
1695         free_irq(dd->ipath_irq, dd);
1696         ht_destroy_irq(dd->ipath_irq);
1697         dd->ipath_irq = 0;
1698         dd->ipath_intconfig = 0;
1699 }
1700
1701 static struct ipath_message_header *
1702 ipath_ht_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1703 {
1704         return (struct ipath_message_header *)
1705                 &rhf_addr[sizeof(u64) / sizeof(u32)];
1706 }
1707
1708 static void ipath_ht_config_ports(struct ipath_devdata *dd, ushort cfgports)
1709 {
1710         dd->ipath_portcnt =
1711                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1712         dd->ipath_p0_rcvegrcnt =
1713                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1714 }
1715
1716 static void ipath_ht_read_counters(struct ipath_devdata *dd,
1717                                    struct infinipath_counters *cntrs)
1718 {
1719         cntrs->LBIntCnt =
1720                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1721         cntrs->LBFlowStallCnt =
1722                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1723         cntrs->TxSDmaDescCnt = 0;
1724         cntrs->TxUnsupVLErrCnt =
1725                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1726         cntrs->TxDataPktCnt =
1727                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1728         cntrs->TxFlowPktCnt =
1729                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1730         cntrs->TxDwordCnt =
1731                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1732         cntrs->TxLenErrCnt =
1733                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1734         cntrs->TxMaxMinLenErrCnt =
1735                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1736         cntrs->TxUnderrunCnt =
1737                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1738         cntrs->TxFlowStallCnt =
1739                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1740         cntrs->TxDroppedPktCnt =
1741                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1742         cntrs->RxDroppedPktCnt =
1743                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1744         cntrs->RxDataPktCnt =
1745                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1746         cntrs->RxFlowPktCnt =
1747                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1748         cntrs->RxDwordCnt =
1749                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1750         cntrs->RxLenErrCnt =
1751                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1752         cntrs->RxMaxMinLenErrCnt =
1753                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1754         cntrs->RxICRCErrCnt =
1755                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1756         cntrs->RxVCRCErrCnt =
1757                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1758         cntrs->RxFlowCtrlErrCnt =
1759                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1760         cntrs->RxBadFormatCnt =
1761                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1762         cntrs->RxLinkProblemCnt =
1763                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1764         cntrs->RxEBPCnt =
1765                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1766         cntrs->RxLPCRCErrCnt =
1767                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1768         cntrs->RxBufOvflCnt =
1769                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1770         cntrs->RxTIDFullErrCnt =
1771                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1772         cntrs->RxTIDValidErrCnt =
1773                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1774         cntrs->RxPKeyMismatchCnt =
1775                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1776         cntrs->RxP0HdrEgrOvflCnt =
1777                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1778         cntrs->RxP1HdrEgrOvflCnt =
1779                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1780         cntrs->RxP2HdrEgrOvflCnt =
1781                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1782         cntrs->RxP3HdrEgrOvflCnt =
1783                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1784         cntrs->RxP4HdrEgrOvflCnt =
1785                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1786         cntrs->RxP5HdrEgrOvflCnt =
1787                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP5HdrEgrOvflCnt));
1788         cntrs->RxP6HdrEgrOvflCnt =
1789                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP6HdrEgrOvflCnt));
1790         cntrs->RxP7HdrEgrOvflCnt =
1791                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP7HdrEgrOvflCnt));
1792         cntrs->RxP8HdrEgrOvflCnt =
1793                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP8HdrEgrOvflCnt));
1794         cntrs->RxP9HdrEgrOvflCnt = 0;
1795         cntrs->RxP10HdrEgrOvflCnt = 0;
1796         cntrs->RxP11HdrEgrOvflCnt = 0;
1797         cntrs->RxP12HdrEgrOvflCnt = 0;
1798         cntrs->RxP13HdrEgrOvflCnt = 0;
1799         cntrs->RxP14HdrEgrOvflCnt = 0;
1800         cntrs->RxP15HdrEgrOvflCnt = 0;
1801         cntrs->RxP16HdrEgrOvflCnt = 0;
1802         cntrs->IBStatusChangeCnt =
1803                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1804         cntrs->IBLinkErrRecoveryCnt =
1805                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1806         cntrs->IBLinkDownedCnt =
1807                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1808         cntrs->IBSymbolErrCnt =
1809                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1810         cntrs->RxVL15DroppedPktCnt = 0;
1811         cntrs->RxOtherLocalPhyErrCnt = 0;
1812         cntrs->PcieRetryBufDiagQwordCnt = 0;
1813         cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1814         cntrs->LocalLinkIntegrityErrCnt =
1815                 (dd->ipath_flags & IPATH_GPIO_ERRINTRS) ?
1816                 dd->ipath_lli_errs : dd->ipath_lli_errors;
1817         cntrs->RxVlErrCnt = 0;
1818         cntrs->RxDlidFltrCnt = 0;
1819 }
1820
1821
1822 /* no interrupt fallback for these chips */
1823 static int ipath_ht_nointr_fallback(struct ipath_devdata *dd)
1824 {
1825         return 0;
1826 }
1827
1828
1829 /*
1830  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
1831  * than resetting the IBC or external link state, and useful in some
1832  * cases to cause some retraining.  To do this right, we reset IBC
1833  * as well.
1834  */
1835 static void ipath_ht_xgxs_reset(struct ipath_devdata *dd)
1836 {
1837         u64 val, prev_val;
1838
1839         prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1840         val = prev_val | INFINIPATH_XGXS_RESET;
1841         prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1842         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1843                          dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1844         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1845         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1846         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1847         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1848                          dd->ipath_control);
1849 }
1850
1851
1852 static int ipath_ht_get_ib_cfg(struct ipath_devdata *dd, int which)
1853 {
1854         int ret;
1855
1856         switch (which) {
1857         case IPATH_IB_CFG_LWID:
1858                 ret = dd->ipath_link_width_active;
1859                 break;
1860         case IPATH_IB_CFG_SPD:
1861                 ret = dd->ipath_link_speed_active;
1862                 break;
1863         case IPATH_IB_CFG_LWID_ENB:
1864                 ret = dd->ipath_link_width_enabled;
1865                 break;
1866         case IPATH_IB_CFG_SPD_ENB:
1867                 ret = dd->ipath_link_speed_enabled;
1868                 break;
1869         default:
1870                 ret =  -ENOTSUPP;
1871                 break;
1872         }
1873         return ret;
1874 }
1875
1876
1877 /* we assume range checking is already done, if needed */
1878 static int ipath_ht_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1879 {
1880         int ret = 0;
1881
1882         if (which == IPATH_IB_CFG_LWID_ENB)
1883                 dd->ipath_link_width_enabled = val;
1884         else if (which == IPATH_IB_CFG_SPD_ENB)
1885                 dd->ipath_link_speed_enabled = val;
1886         else
1887                 ret = -ENOTSUPP;
1888         return ret;
1889 }
1890
1891
1892 static void ipath_ht_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1893 {
1894 }
1895
1896
1897 static int ipath_ht_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1898 {
1899         ipath_setup_ht_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1900                 ipath_ib_linktrstate(dd, ibcs));
1901         return 0;
1902 }
1903
1904
1905 /**
1906  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1907  * @dd: the infinipath device
1908  *
1909  * This is global, and is called directly at init to set up the
1910  * chip-specific function pointers for later use.
1911  */
1912 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1913 {
1914         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1915         dd->ipath_f_bus = ipath_setup_ht_config;
1916         dd->ipath_f_reset = ipath_setup_ht_reset;
1917         dd->ipath_f_get_boardname = ipath_ht_boardname;
1918         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1919         dd->ipath_f_early_init = ipath_ht_early_init;
1920         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1921         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1922         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1923         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1924         dd->ipath_f_put_tid = ipath_ht_put_tid;
1925         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1926         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1927         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1928         dd->ipath_f_free_irq = ipath_ht_free_irq;
1929         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1930         dd->ipath_f_intr_fallback = ipath_ht_nointr_fallback;
1931         dd->ipath_f_get_msgheader = ipath_ht_get_msgheader;
1932         dd->ipath_f_config_ports = ipath_ht_config_ports;
1933         dd->ipath_f_read_counters = ipath_ht_read_counters;
1934         dd->ipath_f_xgxs_reset = ipath_ht_xgxs_reset;
1935         dd->ipath_f_get_ib_cfg = ipath_ht_get_ib_cfg;
1936         dd->ipath_f_set_ib_cfg = ipath_ht_set_ib_cfg;
1937         dd->ipath_f_config_jint = ipath_ht_config_jint;
1938         dd->ipath_f_ib_updown = ipath_ht_ib_updown;
1939
1940         /*
1941          * initialize chip-specific variables
1942          */
1943         ipath_init_ht_variables(dd);
1944 }