drivers/infiniband/hw/ipath/ipath_iba6110.c

   1 /*
   2  * Copyright (c) 2006, 2007 QLogic Corporation. All rights reserved.
   3  * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33
  34 /*
  35  * This file contains all of the code that is specific to the InfiniPath
  36  * HT chip.
  37  */
  38
  39 #include <linux/vmalloc.h>
  40 #include <linux/pci.h>
  41 #include <linux/delay.h>
  42 #include <linux/htirq.h>
  43 #include <rdma/ib_verbs.h>
  44
  45 #include "ipath_kernel.h"
  46 #include "ipath_registers.h"
  47
  48 static void ipath_setup_ht_setextled(struct ipath_devdata *, u64, u64);
  49
  50
  51 /*
  52  * This lists the InfiniPath registers, in the actual chip layout.
  53  * This structure should never be directly accessed.
  54  *
  55  * The names are in InterCap form because they're taken straight from
  56  * the chip specification.  Since they're only used in this file, they
  57  * don't pollute the rest of the source.
  58 */
  59
  60 struct _infinipath_do_not_use_kernel_regs {
  61         unsigned long long Revision;
  62         unsigned long long Control;
  63         unsigned long long PageAlign;
  64         unsigned long long PortCnt;
  65         unsigned long long DebugPortSelect;
  66         unsigned long long DebugPort;
  67         unsigned long long SendRegBase;
  68         unsigned long long UserRegBase;
  69         unsigned long long CounterRegBase;
  70         unsigned long long Scratch;
  71         unsigned long long ReservedMisc1;
  72         unsigned long long InterruptConfig;
  73         unsigned long long IntBlocked;
  74         unsigned long long IntMask;
  75         unsigned long long IntStatus;
  76         unsigned long long IntClear;
  77         unsigned long long ErrorMask;
  78         unsigned long long ErrorStatus;
  79         unsigned long long ErrorClear;
  80         unsigned long long HwErrMask;
  81         unsigned long long HwErrStatus;
  82         unsigned long long HwErrClear;
  83         unsigned long long HwDiagCtrl;
  84         unsigned long long MDIO;
  85         unsigned long long IBCStatus;
  86         unsigned long long IBCCtrl;
  87         unsigned long long ExtStatus;
  88         unsigned long long ExtCtrl;
  89         unsigned long long GPIOOut;
  90         unsigned long long GPIOMask;
  91         unsigned long long GPIOStatus;
  92         unsigned long long GPIOClear;
  93         unsigned long long RcvCtrl;
  94         unsigned long long RcvBTHQP;
  95         unsigned long long RcvHdrSize;
  96         unsigned long long RcvHdrCnt;
  97         unsigned long long RcvHdrEntSize;
  98         unsigned long long RcvTIDBase;
  99         unsigned long long RcvTIDCnt;
 100         unsigned long long RcvEgrBase;
 101         unsigned long long RcvEgrCnt;
 102         unsigned long long RcvBufBase;
 103         unsigned long long RcvBufSize;
 104         unsigned long long RxIntMemBase;
 105         unsigned long long RxIntMemSize;
 106         unsigned long long RcvPartitionKey;
 107         unsigned long long ReservedRcv[10];
 108         unsigned long long SendCtrl;
 109         unsigned long long SendPIOBufBase;
 110         unsigned long long SendPIOSize;
 111         unsigned long long SendPIOBufCnt;
 112         unsigned long long SendPIOAvailAddr;
 113         unsigned long long TxIntMemBase;
 114         unsigned long long TxIntMemSize;
 115         unsigned long long ReservedSend[9];
 116         unsigned long long SendBufferError;
 117         unsigned long long SendBufferErrorCONT1;
 118         unsigned long long SendBufferErrorCONT2;
 119         unsigned long long SendBufferErrorCONT3;
 120         unsigned long long ReservedSBE[4];
 121         unsigned long long RcvHdrAddr0;
 122         unsigned long long RcvHdrAddr1;
 123         unsigned long long RcvHdrAddr2;
 124         unsigned long long RcvHdrAddr3;
 125         unsigned long long RcvHdrAddr4;
 126         unsigned long long RcvHdrAddr5;
 127         unsigned long long RcvHdrAddr6;
 128         unsigned long long RcvHdrAddr7;
 129         unsigned long long RcvHdrAddr8;
 130         unsigned long long ReservedRHA[7];
 131         unsigned long long RcvHdrTailAddr0;
 132         unsigned long long RcvHdrTailAddr1;
 133         unsigned long long RcvHdrTailAddr2;
 134         unsigned long long RcvHdrTailAddr3;
 135         unsigned long long RcvHdrTailAddr4;
 136         unsigned long long RcvHdrTailAddr5;
 137         unsigned long long RcvHdrTailAddr6;
 138         unsigned long long RcvHdrTailAddr7;
 139         unsigned long long RcvHdrTailAddr8;
 140         unsigned long long ReservedRHTA[7];
 141         unsigned long long Sync;        /* Software only */
 142         unsigned long long Dump;        /* Software only */
 143         unsigned long long SimVer;      /* Software only */
 144         unsigned long long ReservedSW[5];
 145         unsigned long long SerdesConfig0;
 146         unsigned long long SerdesConfig1;
 147         unsigned long long SerdesStatus;
 148         unsigned long long XGXSConfig;
 149         unsigned long long ReservedSW2[4];
 150 };
 151
 152 struct _infinipath_do_not_use_counters {
 153         __u64 LBIntCnt;
 154         __u64 LBFlowStallCnt;
 155         __u64 Reserved1;
 156         __u64 TxUnsupVLErrCnt;
 157         __u64 TxDataPktCnt;
 158         __u64 TxFlowPktCnt;
 159         __u64 TxDwordCnt;
 160         __u64 TxLenErrCnt;
 161         __u64 TxMaxMinLenErrCnt;
 162         __u64 TxUnderrunCnt;
 163         __u64 TxFlowStallCnt;
 164         __u64 TxDroppedPktCnt;
 165         __u64 RxDroppedPktCnt;
 166         __u64 RxDataPktCnt;
 167         __u64 RxFlowPktCnt;
 168         __u64 RxDwordCnt;
 169         __u64 RxLenErrCnt;
 170         __u64 RxMaxMinLenErrCnt;
 171         __u64 RxICRCErrCnt;
 172         __u64 RxVCRCErrCnt;
 173         __u64 RxFlowCtrlErrCnt;
 174         __u64 RxBadFormatCnt;
 175         __u64 RxLinkProblemCnt;
 176         __u64 RxEBPCnt;
 177         __u64 RxLPCRCErrCnt;
 178         __u64 RxBufOvflCnt;
 179         __u64 RxTIDFullErrCnt;
 180         __u64 RxTIDValidErrCnt;
 181         __u64 RxPKeyMismatchCnt;
 182         __u64 RxP0HdrEgrOvflCnt;
 183         __u64 RxP1HdrEgrOvflCnt;
 184         __u64 RxP2HdrEgrOvflCnt;
 185         __u64 RxP3HdrEgrOvflCnt;
 186         __u64 RxP4HdrEgrOvflCnt;
 187         __u64 RxP5HdrEgrOvflCnt;
 188         __u64 RxP6HdrEgrOvflCnt;
 189         __u64 RxP7HdrEgrOvflCnt;
 190         __u64 RxP8HdrEgrOvflCnt;
 191         __u64 Reserved6;
 192         __u64 Reserved7;
 193         __u64 IBStatusChangeCnt;
 194         __u64 IBLinkErrRecoveryCnt;
 195         __u64 IBLinkDownedCnt;
 196         __u64 IBSymbolErrCnt;
 197 };
 198
 199 #define IPATH_KREG_OFFSET(field) (offsetof( \
 200         struct _infinipath_do_not_use_kernel_regs, field) / sizeof(u64))
 201 #define IPATH_CREG_OFFSET(field) (offsetof( \
 202         struct _infinipath_do_not_use_counters, field) / sizeof(u64))
 203
 204 static const struct ipath_kregs ipath_ht_kregs = {
 205         .kr_control = IPATH_KREG_OFFSET(Control),
 206         .kr_counterregbase = IPATH_KREG_OFFSET(CounterRegBase),
 207         .kr_debugport = IPATH_KREG_OFFSET(DebugPort),
 208         .kr_debugportselect = IPATH_KREG_OFFSET(DebugPortSelect),
 209         .kr_errorclear = IPATH_KREG_OFFSET(ErrorClear),
 210         .kr_errormask = IPATH_KREG_OFFSET(ErrorMask),
 211         .kr_errorstatus = IPATH_KREG_OFFSET(ErrorStatus),
 212         .kr_extctrl = IPATH_KREG_OFFSET(ExtCtrl),
 213         .kr_extstatus = IPATH_KREG_OFFSET(ExtStatus),
 214         .kr_gpio_clear = IPATH_KREG_OFFSET(GPIOClear),
 215         .kr_gpio_mask = IPATH_KREG_OFFSET(GPIOMask),
 216         .kr_gpio_out = IPATH_KREG_OFFSET(GPIOOut),
 217         .kr_gpio_status = IPATH_KREG_OFFSET(GPIOStatus),
 218         .kr_hwdiagctrl = IPATH_KREG_OFFSET(HwDiagCtrl),
 219         .kr_hwerrclear = IPATH_KREG_OFFSET(HwErrClear),
 220         .kr_hwerrmask = IPATH_KREG_OFFSET(HwErrMask),
 221         .kr_hwerrstatus = IPATH_KREG_OFFSET(HwErrStatus),
 222         .kr_ibcctrl = IPATH_KREG_OFFSET(IBCCtrl),
 223         .kr_ibcstatus = IPATH_KREG_OFFSET(IBCStatus),
 224         .kr_intblocked = IPATH_KREG_OFFSET(IntBlocked),
 225         .kr_intclear = IPATH_KREG_OFFSET(IntClear),
 226         .kr_interruptconfig = IPATH_KREG_OFFSET(InterruptConfig),
 227         .kr_intmask = IPATH_KREG_OFFSET(IntMask),
 228         .kr_intstatus = IPATH_KREG_OFFSET(IntStatus),
 229         .kr_mdio = IPATH_KREG_OFFSET(MDIO),
 230         .kr_pagealign = IPATH_KREG_OFFSET(PageAlign),
 231         .kr_partitionkey = IPATH_KREG_OFFSET(RcvPartitionKey),
 232         .kr_portcnt = IPATH_KREG_OFFSET(PortCnt),
 233         .kr_rcvbthqp = IPATH_KREG_OFFSET(RcvBTHQP),
 234         .kr_rcvbufbase = IPATH_KREG_OFFSET(RcvBufBase),
 235         .kr_rcvbufsize = IPATH_KREG_OFFSET(RcvBufSize),
 236         .kr_rcvctrl = IPATH_KREG_OFFSET(RcvCtrl),
 237         .kr_rcvegrbase = IPATH_KREG_OFFSET(RcvEgrBase),
 238         .kr_rcvegrcnt = IPATH_KREG_OFFSET(RcvEgrCnt),
 239         .kr_rcvhdrcnt = IPATH_KREG_OFFSET(RcvHdrCnt),
 240         .kr_rcvhdrentsize = IPATH_KREG_OFFSET(RcvHdrEntSize),
 241         .kr_rcvhdrsize = IPATH_KREG_OFFSET(RcvHdrSize),
 242         .kr_rcvintmembase = IPATH_KREG_OFFSET(RxIntMemBase),
 243         .kr_rcvintmemsize = IPATH_KREG_OFFSET(RxIntMemSize),
 244         .kr_rcvtidbase = IPATH_KREG_OFFSET(RcvTIDBase),
 245         .kr_rcvtidcnt = IPATH_KREG_OFFSET(RcvTIDCnt),
 246         .kr_revision = IPATH_KREG_OFFSET(Revision),
 247         .kr_scratch = IPATH_KREG_OFFSET(Scratch),
 248         .kr_sendbuffererror = IPATH_KREG_OFFSET(SendBufferError),
 249         .kr_sendctrl = IPATH_KREG_OFFSET(SendCtrl),
 250         .kr_sendpioavailaddr = IPATH_KREG_OFFSET(SendPIOAvailAddr),
 251         .kr_sendpiobufbase = IPATH_KREG_OFFSET(SendPIOBufBase),
 252         .kr_sendpiobufcnt = IPATH_KREG_OFFSET(SendPIOBufCnt),
 253         .kr_sendpiosize = IPATH_KREG_OFFSET(SendPIOSize),
 254         .kr_sendregbase = IPATH_KREG_OFFSET(SendRegBase),
 255         .kr_txintmembase = IPATH_KREG_OFFSET(TxIntMemBase),
 256         .kr_txintmemsize = IPATH_KREG_OFFSET(TxIntMemSize),
 257         .kr_userregbase = IPATH_KREG_OFFSET(UserRegBase),
 258         .kr_serdesconfig0 = IPATH_KREG_OFFSET(SerdesConfig0),
 259         .kr_serdesconfig1 = IPATH_KREG_OFFSET(SerdesConfig1),
 260         .kr_serdesstatus = IPATH_KREG_OFFSET(SerdesStatus),
 261         .kr_xgxsconfig = IPATH_KREG_OFFSET(XGXSConfig),
 262         /*
 263          * These should not be used directly via ipath_write_kreg64(),
 264          * use them with ipath_write_kreg64_port(),
 265          */
 266         .kr_rcvhdraddr = IPATH_KREG_OFFSET(RcvHdrAddr0),
 267         .kr_rcvhdrtailaddr = IPATH_KREG_OFFSET(RcvHdrTailAddr0)
 268 };
 269
 270 static const struct ipath_cregs ipath_ht_cregs = {
 271         .cr_badformatcnt = IPATH_CREG_OFFSET(RxBadFormatCnt),
 272         .cr_erricrccnt = IPATH_CREG_OFFSET(RxICRCErrCnt),
 273         .cr_errlinkcnt = IPATH_CREG_OFFSET(RxLinkProblemCnt),
 274         .cr_errlpcrccnt = IPATH_CREG_OFFSET(RxLPCRCErrCnt),
 275         .cr_errpkey = IPATH_CREG_OFFSET(RxPKeyMismatchCnt),
 276         .cr_errrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowCtrlErrCnt),
 277         .cr_err_rlencnt = IPATH_CREG_OFFSET(RxLenErrCnt),
 278         .cr_errslencnt = IPATH_CREG_OFFSET(TxLenErrCnt),
 279         .cr_errtidfull = IPATH_CREG_OFFSET(RxTIDFullErrCnt),
 280         .cr_errtidvalid = IPATH_CREG_OFFSET(RxTIDValidErrCnt),
 281         .cr_errvcrccnt = IPATH_CREG_OFFSET(RxVCRCErrCnt),
 282         .cr_ibstatuschange = IPATH_CREG_OFFSET(IBStatusChangeCnt),
 283         /* calc from Reg_CounterRegBase + offset */
 284         .cr_intcnt = IPATH_CREG_OFFSET(LBIntCnt),
 285         .cr_invalidrlencnt = IPATH_CREG_OFFSET(RxMaxMinLenErrCnt),
 286         .cr_invalidslencnt = IPATH_CREG_OFFSET(TxMaxMinLenErrCnt),
 287         .cr_lbflowstallcnt = IPATH_CREG_OFFSET(LBFlowStallCnt),
 288         .cr_pktrcvcnt = IPATH_CREG_OFFSET(RxDataPktCnt),
 289         .cr_pktrcvflowctrlcnt = IPATH_CREG_OFFSET(RxFlowPktCnt),
 290         .cr_pktsendcnt = IPATH_CREG_OFFSET(TxDataPktCnt),
 291         .cr_pktsendflowcnt = IPATH_CREG_OFFSET(TxFlowPktCnt),
 292         .cr_portovflcnt = IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt),
 293         .cr_rcvebpcnt = IPATH_CREG_OFFSET(RxEBPCnt),
 294         .cr_rcvovflcnt = IPATH_CREG_OFFSET(RxBufOvflCnt),
 295         .cr_senddropped = IPATH_CREG_OFFSET(TxDroppedPktCnt),
 296         .cr_sendstallcnt = IPATH_CREG_OFFSET(TxFlowStallCnt),
 297         .cr_sendunderruncnt = IPATH_CREG_OFFSET(TxUnderrunCnt),
 298         .cr_wordrcvcnt = IPATH_CREG_OFFSET(RxDwordCnt),
 299         .cr_wordsendcnt = IPATH_CREG_OFFSET(TxDwordCnt),
 300         .cr_unsupvlcnt = IPATH_CREG_OFFSET(TxUnsupVLErrCnt),
 301         .cr_rxdroppktcnt = IPATH_CREG_OFFSET(RxDroppedPktCnt),
 302         .cr_iblinkerrrecovcnt = IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt),
 303         .cr_iblinkdowncnt = IPATH_CREG_OFFSET(IBLinkDownedCnt),
 304         .cr_ibsymbolerrcnt = IPATH_CREG_OFFSET(IBSymbolErrCnt)
 305 };
 306
 307 /* kr_intstatus, kr_intclear, kr_intmask bits */
 308 #define INFINIPATH_I_RCVURG_MASK ((1U<<9)-1)
 309 #define INFINIPATH_I_RCVAVAIL_MASK ((1U<<9)-1)
 310
 311 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
 312 #define INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT 0
 313 #define INFINIPATH_HWE_HTCMEMPARITYERR_MASK 0x3FFFFFULL
 314 #define INFINIPATH_HWE_HTCLNKABYTE0CRCERR   0x0000000000800000ULL
 315 #define INFINIPATH_HWE_HTCLNKABYTE1CRCERR   0x0000000001000000ULL
 316 #define INFINIPATH_HWE_HTCLNKBBYTE0CRCERR   0x0000000002000000ULL
 317 #define INFINIPATH_HWE_HTCLNKBBYTE1CRCERR   0x0000000004000000ULL
 318 #define INFINIPATH_HWE_HTCMISCERR4          0x0000000008000000ULL
 319 #define INFINIPATH_HWE_HTCMISCERR5          0x0000000010000000ULL
 320 #define INFINIPATH_HWE_HTCMISCERR6          0x0000000020000000ULL
 321 #define INFINIPATH_HWE_HTCMISCERR7          0x0000000040000000ULL
 322 #define INFINIPATH_HWE_HTCBUSTREQPARITYERR  0x0000000080000000ULL
 323 #define INFINIPATH_HWE_HTCBUSTRESPPARITYERR 0x0000000100000000ULL
 324 #define INFINIPATH_HWE_HTCBUSIREQPARITYERR  0x0000000200000000ULL
 325 #define INFINIPATH_HWE_COREPLL_FBSLIP       0x0080000000000000ULL
 326 #define INFINIPATH_HWE_COREPLL_RFSLIP       0x0100000000000000ULL
 327 #define INFINIPATH_HWE_HTBPLL_FBSLIP        0x0200000000000000ULL
 328 #define INFINIPATH_HWE_HTBPLL_RFSLIP        0x0400000000000000ULL
 329 #define INFINIPATH_HWE_HTAPLL_FBSLIP        0x0800000000000000ULL
 330 #define INFINIPATH_HWE_HTAPLL_RFSLIP        0x1000000000000000ULL
 331 #define INFINIPATH_HWE_SERDESPLLFAILED      0x2000000000000000ULL
 332
 333 #define IBA6110_IBCS_LINKTRAININGSTATE_MASK 0xf
 334 #define IBA6110_IBCS_LINKSTATE_SHIFT 4
 335
 336 /* kr_extstatus bits */
 337 #define INFINIPATH_EXTS_FREQSEL 0x2
 338 #define INFINIPATH_EXTS_SERDESSEL 0x4
 339 #define INFINIPATH_EXTS_MEMBIST_ENDTEST     0x0000000000004000
 340 #define INFINIPATH_EXTS_MEMBIST_CORRECT     0x0000000000008000
 341
 342
 343 /* TID entries (memory), HT-only */
 344 #define INFINIPATH_RT_ADDR_MASK 0xFFFFFFFFFFULL /* 40 bits valid */
 345 #define INFINIPATH_RT_VALID 0x8000000000000000ULL
 346 #define INFINIPATH_RT_ADDR_SHIFT 0
 347 #define INFINIPATH_RT_BUFSIZE_MASK 0x3FFFULL
 348 #define INFINIPATH_RT_BUFSIZE_SHIFT 48
 349
 350 #define INFINIPATH_R_INTRAVAIL_SHIFT 16
 351 #define INFINIPATH_R_TAILUPD_SHIFT 31
 352
 353 /* kr_xgxsconfig bits */
 354 #define INFINIPATH_XGXS_RESET          0x7ULL
 355
 356 /*
 357  * masks and bits that are different in different chips, or present only
 358  * in one
 359  */
 360 static const ipath_err_t infinipath_hwe_htcmemparityerr_mask =
 361     INFINIPATH_HWE_HTCMEMPARITYERR_MASK;
 362 static const ipath_err_t infinipath_hwe_htcmemparityerr_shift =
 363     INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT;
 364
 365 static const ipath_err_t infinipath_hwe_htclnkabyte0crcerr =
 366     INFINIPATH_HWE_HTCLNKABYTE0CRCERR;
 367 static const ipath_err_t infinipath_hwe_htclnkabyte1crcerr =
 368     INFINIPATH_HWE_HTCLNKABYTE1CRCERR;
 369 static const ipath_err_t infinipath_hwe_htclnkbbyte0crcerr =
 370     INFINIPATH_HWE_HTCLNKBBYTE0CRCERR;
 371 static const ipath_err_t infinipath_hwe_htclnkbbyte1crcerr =
 372     INFINIPATH_HWE_HTCLNKBBYTE1CRCERR;
 373
 374 #define _IPATH_GPIO_SDA_NUM 1
 375 #define _IPATH_GPIO_SCL_NUM 0
 376
 377 #define IPATH_GPIO_SDA \
 378         (1ULL << (_IPATH_GPIO_SDA_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 379 #define IPATH_GPIO_SCL \
 380         (1ULL << (_IPATH_GPIO_SCL_NUM+INFINIPATH_EXTC_GPIOOE_SHIFT))
 381
 382 /* keep the code below somewhat more readonable; not used elsewhere */
 383 #define _IPATH_HTLINK0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 384                                 infinipath_hwe_htclnkabyte1crcerr)
 385 #define _IPATH_HTLINK1_CRCBITS (infinipath_hwe_htclnkbbyte0crcerr |     \
 386                                 infinipath_hwe_htclnkbbyte1crcerr)
 387 #define _IPATH_HTLANE0_CRCBITS (infinipath_hwe_htclnkabyte0crcerr |     \
 388                                 infinipath_hwe_htclnkbbyte0crcerr)
 389 #define _IPATH_HTLANE1_CRCBITS (infinipath_hwe_htclnkabyte1crcerr |     \
 390                                 infinipath_hwe_htclnkbbyte1crcerr)
 391
 392 static void hwerr_crcbits(struct ipath_devdata *dd, ipath_err_t hwerrs,
 393                           char *msg, size_t msgl)
 394 {
 395         char bitsmsg[64];
 396         ipath_err_t crcbits = hwerrs &
 397                 (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS);
 398         /* don't check if 8bit HT */
 399         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
 400                 crcbits &= ~infinipath_hwe_htclnkabyte1crcerr;
 401         /* don't check if 8bit HT */
 402         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
 403                 crcbits &= ~infinipath_hwe_htclnkbbyte1crcerr;
 404         /*
 405          * we'll want to ignore link errors on link that is
 406          * not in use, if any.  For now, complain about both
 407          */
 408         if (crcbits) {
 409                 u16 ctrl0, ctrl1;
 410                 snprintf(bitsmsg, sizeof bitsmsg,
 411                          "[HT%s lane %s CRC (%llx); powercycle to completely clear]",
 412                          !(crcbits & _IPATH_HTLINK1_CRCBITS) ?
 413                          "0 (A)" : (!(crcbits & _IPATH_HTLINK0_CRCBITS)
 414                                     ? "1 (B)" : "0+1 (A+B)"),
 415                          !(crcbits & _IPATH_HTLANE1_CRCBITS) ? "0"
 416                          : (!(crcbits & _IPATH_HTLANE0_CRCBITS) ? "1" :
 417                             "0+1"), (unsigned long long) crcbits);
 418                 strlcat(msg, bitsmsg, msgl);
 419
 420                 /*
 421                  * print extra info for debugging.  slave/primary
 422                  * config word 4, 8 (link control 0, 1)
 423                  */
 424
 425                 if (pci_read_config_word(dd->pcidev,
 426                                          dd->ipath_ht_slave_off + 0x4,
 427                                          &ctrl0))
 428                         dev_info(&dd->pcidev->dev, "Couldn't read "
 429                                  "linkctrl0 of slave/primary "
 430                                  "config block\n");
 431                 else if (!(ctrl0 & 1 << 6))
 432                         /* not if EOC bit set */
 433                         ipath_dbg("HT linkctrl0 0x%x%s%s\n", ctrl0,
 434                                   ((ctrl0 >> 8) & 7) ? " CRC" : "",
 435                                   ((ctrl0 >> 4) & 1) ? "linkfail" :
 436                                   "");
 437                 if (pci_read_config_word(dd->pcidev,
 438                                          dd->ipath_ht_slave_off + 0x8,
 439                                          &ctrl1))
 440                         dev_info(&dd->pcidev->dev, "Couldn't read "
 441                                  "linkctrl1 of slave/primary "
 442                                  "config block\n");
 443                 else if (!(ctrl1 & 1 << 6))
 444                         /* not if EOC bit set */
 445                         ipath_dbg("HT linkctrl1 0x%x%s%s\n", ctrl1,
 446                                   ((ctrl1 >> 8) & 7) ? " CRC" : "",
 447                                   ((ctrl1 >> 4) & 1) ? "linkfail" :
 448                                   "");
 449
 450                 /* disable until driver reloaded */
 451                 dd->ipath_hwerrmask &= ~crcbits;
 452                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 453                                  dd->ipath_hwerrmask);
 454                 ipath_dbg("HT crc errs: %s\n", msg);
 455         } else
 456                 ipath_dbg("ignoring HT crc errors 0x%llx, "
 457                           "not in use\n", (unsigned long long)
 458                           (hwerrs & (_IPATH_HTLINK0_CRCBITS |
 459                                      _IPATH_HTLINK1_CRCBITS)));
 460 }
 461
 462 /* 6110 specific hardware errors... */
 463 static const struct ipath_hwerror_msgs ipath_6110_hwerror_msgs[] = {
 464         INFINIPATH_HWE_MSG(HTCBUSIREQPARITYERR, "HTC Ireq Parity"),
 465         INFINIPATH_HWE_MSG(HTCBUSTREQPARITYERR, "HTC Treq Parity"),
 466         INFINIPATH_HWE_MSG(HTCBUSTRESPPARITYERR, "HTC Tresp Parity"),
 467         INFINIPATH_HWE_MSG(HTCMISCERR5, "HT core Misc5"),
 468         INFINIPATH_HWE_MSG(HTCMISCERR6, "HT core Misc6"),
 469         INFINIPATH_HWE_MSG(HTCMISCERR7, "HT core Misc7"),
 470         INFINIPATH_HWE_MSG(RXDSYNCMEMPARITYERR, "Rx Dsync"),
 471         INFINIPATH_HWE_MSG(SERDESPLLFAILED, "SerDes PLL"),
 472 };
 473
 474 #define TXE_PIO_PARITY ((INFINIPATH_HWE_TXEMEMPARITYERR_PIOBUF | \
 475                         INFINIPATH_HWE_TXEMEMPARITYERR_PIOPBC) \
 476                         << INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT)
 477 #define RXE_EAGER_PARITY (INFINIPATH_HWE_RXEMEMPARITYERR_EAGERTID \
 478                           << INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT)
 479
 480 static void ipath_ht_txe_recover(struct ipath_devdata *dd)
 481 {
 482         ++ipath_stats.sps_txeparity;
 483         dev_info(&dd->pcidev->dev,
 484                 "Recovering from TXE PIO parity error\n");
 485 }
 486
 487
 488 /**
 489  * ipath_ht_handle_hwerrors - display hardware errors.
 490  * @dd: the infinipath device
 491  * @msg: the output buffer
 492  * @msgl: the size of the output buffer
 493  *
 494  * Use same msg buffer as regular errors to avoid excessive stack
 495  * use.  Most hardware errors are catastrophic, but for right now,
 496  * we'll print them and continue.  We reuse the same message buffer as
 497  * ipath_handle_errors() to avoid excessive stack usage.
 498  */
 499 static void ipath_ht_handle_hwerrors(struct ipath_devdata *dd, char *msg,
 500                                      size_t msgl)
 501 {
 502         ipath_err_t hwerrs;
 503         u32 bits, ctrl;
 504         int isfatal = 0;
 505         char bitsmsg[64];
 506         int log_idx;
 507
 508         hwerrs = ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus);
 509
 510         if (!hwerrs) {
 511                 ipath_cdbg(VERBOSE, "Called but no hardware errors set\n");
 512                 /*
 513                  * better than printing cofusing messages
 514                  * This seems to be related to clearing the crc error, or
 515                  * the pll error during init.
 516                  */
 517                 goto bail;
 518         } else if (hwerrs == -1LL) {
 519                 ipath_dev_err(dd, "Read of hardware error status failed "
 520                               "(all bits set); ignoring\n");
 521                 goto bail;
 522         }
 523         ipath_stats.sps_hwerrs++;
 524
 525         /* Always clear the error status register, except MEMBISTFAIL,
 526          * regardless of whether we continue or stop using the chip.
 527          * We want that set so we know it failed, even across driver reload.
 528          * We'll still ignore it in the hwerrmask.  We do this partly for
 529          * diagnostics, but also for support */
 530         ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
 531                          hwerrs&~INFINIPATH_HWE_MEMBISTFAILED);
 532
 533         hwerrs &= dd->ipath_hwerrmask;
 534
 535         /* We log some errors to EEPROM, check if we have any of those. */
 536         for (log_idx = 0; log_idx < IPATH_EEP_LOG_CNT; ++log_idx)
 537                 if (hwerrs & dd->ipath_eep_st_masks[log_idx].hwerrs_to_log)
 538                         ipath_inc_eeprom_err(dd, log_idx, 1);
 539
 540         /*
 541          * make sure we get this much out, unless told to be quiet,
 542          * it's a parity error we may recover from,
 543          * or it's occurred within the last 5 seconds
 544          */
 545         if ((hwerrs & ~(dd->ipath_lasthwerror | TXE_PIO_PARITY |
 546                 RXE_EAGER_PARITY)) ||
 547                 (ipath_debug & __IPATH_VERBDBG))
 548                 dev_info(&dd->pcidev->dev, "Hardware error: hwerr=0x%llx "
 549                          "(cleared)\n", (unsigned long long) hwerrs);
 550         dd->ipath_lasthwerror |= hwerrs;
 551
 552         if (hwerrs & ~dd->ipath_hwe_bitsextant)
 553                 ipath_dev_err(dd, "hwerror interrupt with unknown errors "
 554                               "%llx set\n", (unsigned long long)
 555                               (hwerrs & ~dd->ipath_hwe_bitsextant));
 556
 557         ctrl = ipath_read_kreg32(dd, dd->ipath_kregs->kr_control);
 558         if ((ctrl & INFINIPATH_C_FREEZEMODE) && !ipath_diag_inuse) {
 559                 /*
 560                  * parity errors in send memory are recoverable,
 561                  * just cancel the send (if indicated in * sendbuffererror),
 562                  * count the occurrence, unfreeze (if no other handled
 563                  * hardware error bits are set), and continue. They can
 564                  * occur if a processor speculative read is done to the PIO
 565                  * buffer while we are sending a packet, for example.
 566                  */
 567                 if (hwerrs & TXE_PIO_PARITY) {
 568                         ipath_ht_txe_recover(dd);
 569                         hwerrs &= ~TXE_PIO_PARITY;
 570                 }
 571
 572                 if (!hwerrs) {
 573                         ipath_dbg("Clearing freezemode on ignored or "
 574                                   "recovered hardware error\n");
 575                         ipath_clear_freeze(dd);
 576                 }
 577         }
 578
 579         *msg = '\0';
 580
 581         /*
 582          * may someday want to decode into which bits are which
 583          * functional area for parity errors, etc.
 584          */
 585         if (hwerrs & (infinipath_hwe_htcmemparityerr_mask
 586                       << INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT)) {
 587                 bits = (u32) ((hwerrs >>
 588                                INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) &
 589                               INFINIPATH_HWE_HTCMEMPARITYERR_MASK);
 590                 snprintf(bitsmsg, sizeof bitsmsg, "[HTC Parity Errs %x] ",
 591                          bits);
 592                 strlcat(msg, bitsmsg, msgl);
 593         }
 594
 595         ipath_format_hwerrors(hwerrs,
 596                               ipath_6110_hwerror_msgs,
 597                               sizeof(ipath_6110_hwerror_msgs) /
 598                               sizeof(ipath_6110_hwerror_msgs[0]),
 599                               msg, msgl);
 600
 601         if (hwerrs & (_IPATH_HTLINK0_CRCBITS | _IPATH_HTLINK1_CRCBITS))
 602                 hwerr_crcbits(dd, hwerrs, msg, msgl);
 603
 604         if (hwerrs & INFINIPATH_HWE_MEMBISTFAILED) {
 605                 strlcat(msg, "[Memory BIST test failed, InfiniPath hardware unusable]",
 606                         msgl);
 607                 /* ignore from now on, so disable until driver reloaded */
 608                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_MEMBISTFAILED;
 609                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 610                                  dd->ipath_hwerrmask);
 611         }
 612 #define _IPATH_PLL_FAIL (INFINIPATH_HWE_COREPLL_FBSLIP |        \
 613                          INFINIPATH_HWE_COREPLL_RFSLIP |        \
 614                          INFINIPATH_HWE_HTBPLL_FBSLIP |         \
 615                          INFINIPATH_HWE_HTBPLL_RFSLIP |         \
 616                          INFINIPATH_HWE_HTAPLL_FBSLIP |         \
 617                          INFINIPATH_HWE_HTAPLL_RFSLIP)
 618
 619         if (hwerrs & _IPATH_PLL_FAIL) {
 620                 snprintf(bitsmsg, sizeof bitsmsg,
 621                          "[PLL failed (%llx), InfiniPath hardware unusable]",
 622                          (unsigned long long) (hwerrs & _IPATH_PLL_FAIL));
 623                 strlcat(msg, bitsmsg, msgl);
 624                 /* ignore from now on, so disable until driver reloaded */
 625                 dd->ipath_hwerrmask &= ~(hwerrs & _IPATH_PLL_FAIL);
 626                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 627                                  dd->ipath_hwerrmask);
 628         }
 629
 630         if (hwerrs & INFINIPATH_HWE_SERDESPLLFAILED) {
 631                 /*
 632                  * If it occurs, it is left masked since the eternal
 633                  * interface is unused
 634                  */
 635                 dd->ipath_hwerrmask &= ~INFINIPATH_HWE_SERDESPLLFAILED;
 636                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrmask,
 637                                  dd->ipath_hwerrmask);
 638         }
 639
 640         if (hwerrs) {
 641                 /*
 642                  * if any set that we aren't ignoring; only
 643                  * make the complaint once, in case it's stuck
 644                  * or recurring, and we get here multiple
 645                  * times.
 646                  * force link down, so switch knows, and
 647                  * LEDs are turned off
 648                  */
 649                 if (dd->ipath_flags & IPATH_INITTED) {
 650                         ipath_set_linkstate(dd, IPATH_IB_LINKDOWN);
 651                         ipath_setup_ht_setextled(dd,
 652                                 INFINIPATH_IBCS_L_STATE_DOWN,
 653                                 INFINIPATH_IBCS_LT_STATE_DISABLED);
 654                         ipath_dev_err(dd, "Fatal Hardware Error (freeze "
 655                                           "mode), no longer usable, SN %.16s\n",
 656                                           dd->ipath_serial);
 657                         isfatal = 1;
 658                 }
 659                 *dd->ipath_statusp &= ~IPATH_STATUS_IB_READY;
 660                 /* mark as having had error */
 661                 *dd->ipath_statusp |= IPATH_STATUS_HWERROR;
 662                 /*
 663                  * mark as not usable, at a minimum until driver
 664                  * is reloaded, probably until reboot, since no
 665                  * other reset is possible.
 666                  */
 667                 dd->ipath_flags &= ~IPATH_INITTED;
 668         }
 669         else
 670                 *msg = 0; /* recovered from all of them */
 671         if (*msg)
 672                 ipath_dev_err(dd, "%s hardware error\n", msg);
 673         if (isfatal && !ipath_diag_inuse && dd->ipath_freezemsg)
 674                 /*
 675                  * for status file; if no trailing brace is copied,
 676                  * we'll know it was truncated.
 677                  */
 678                 snprintf(dd->ipath_freezemsg,
 679                          dd->ipath_freezelen, "{%s}", msg);
 680
 681 bail:;
 682 }
 683
 684 /**
 685  * ipath_ht_boardname - fill in the board name
 686  * @dd: the infinipath device
 687  * @name: the output buffer
 688  * @namelen: the size of the output buffer
 689  *
 690  * fill in the board name, based on the board revision register
 691  */
 692 static int ipath_ht_boardname(struct ipath_devdata *dd, char *name,
 693                               size_t namelen)
 694 {
 695         char *n = NULL;
 696         u8 boardrev = dd->ipath_boardrev;
 697         int ret = 0;
 698
 699         switch (boardrev) {
 700         case 5:
 701                 /*
 702                  * original production board; two production levels, with
 703                  * different serial number ranges.   See ipath_ht_early_init() for
 704                  * case where we enable IPATH_GPIO_INTR for later serial # range.
 705                  * Original 112* serial number is no longer supported.
 706                  */
 707                 n = "InfiniPath_QHT7040";
 708                 break;
 709         case 7:
 710                 /* small form factor production board */
 711                 n = "InfiniPath_QHT7140";
 712                 break;
 713         default:                /* don't know, just print the number */
 714                 ipath_dev_err(dd, "Don't yet know about board "
 715                               "with ID %u\n", boardrev);
 716                 snprintf(name, namelen, "Unknown_InfiniPath_QHT7xxx_%u",
 717                          boardrev);
 718                 break;
 719         }
 720         if (n)
 721                 snprintf(name, namelen, "%s", n);
 722
 723         if (ret) {
 724                 ipath_dev_err(dd, "Unsupported InfiniPath board %s!\n", name);
 725                 goto bail;
 726         }
 727         if (dd->ipath_majrev != 3 || (dd->ipath_minrev < 2 ||
 728                 dd->ipath_minrev > 4)) {
 729                 /*
 730                  * This version of the driver only supports Rev 3.2 - 3.4
 731                  */
 732                 ipath_dev_err(dd,
 733                               "Unsupported InfiniPath hardware revision %u.%u!\n",
 734                               dd->ipath_majrev, dd->ipath_minrev);
 735                 ret = 1;
 736                 goto bail;
 737         }
 738         /*
 739          * pkt/word counters are 32 bit, and therefore wrap fast enough
 740          * that we snapshot them from a timer, and maintain 64 bit shadow
 741          * copies
 742          */
 743         dd->ipath_flags |= IPATH_32BITCOUNTERS;
 744         dd->ipath_flags |= IPATH_GPIO_INTR;
 745         if (dd->ipath_lbus_speed != 800)
 746                 ipath_dev_err(dd,
 747                               "Incorrectly configured for HT @ %uMHz\n",
 748                               dd->ipath_lbus_speed);
 749
 750         /*
 751          * set here, not in ipath_init_*_funcs because we have to do
 752          * it after we can read chip registers.
 753          */
 754         dd->ipath_ureg_align =
 755                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_pagealign);
 756
 757 bail:
 758         return ret;
 759 }
 760
 761 static void ipath_check_htlink(struct ipath_devdata *dd)
 762 {
 763         u8 linkerr, link_off, i;
 764
 765         for (i = 0; i < 2; i++) {
 766                 link_off = dd->ipath_ht_slave_off + i * 4 + 0xd;
 767                 if (pci_read_config_byte(dd->pcidev, link_off, &linkerr))
 768                         dev_info(&dd->pcidev->dev, "Couldn't read "
 769                                  "linkerror%d of HT slave/primary block\n",
 770                                  i);
 771                 else if (linkerr & 0xf0) {
 772                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 773                                    "clearing\n", linkerr >> 4, i);
 774                         /*
 775                          * writing the linkerr bits that are set should
 776                          * clear them
 777                          */
 778                         if (pci_write_config_byte(dd->pcidev, link_off,
 779                                                   linkerr))
 780                                 ipath_dbg("Failed write to clear HT "
 781                                           "linkerror%d\n", i);
 782                         if (pci_read_config_byte(dd->pcidev, link_off,
 783                                                  &linkerr))
 784                                 dev_info(&dd->pcidev->dev,
 785                                          "Couldn't reread linkerror%d of "
 786                                          "HT slave/primary block\n", i);
 787                         else if (linkerr & 0xf0)
 788                                 dev_info(&dd->pcidev->dev,
 789                                          "HT linkerror%d bits 0x%x "
 790                                          "couldn't be cleared\n",
 791                                          i, linkerr >> 4);
 792                 }
 793         }
 794 }
 795
 796 static int ipath_setup_ht_reset(struct ipath_devdata *dd)
 797 {
 798         ipath_dbg("No reset possible for this InfiniPath hardware\n");
 799         return 0;
 800 }
 801
 802 #define HT_INTR_DISC_CONFIG  0x80       /* HT interrupt and discovery cap */
 803 #define HT_INTR_REG_INDEX    2  /* intconfig requires indirect accesses */
 804
 805 /*
 806  * Bits 13-15 of command==0 is slave/primary block.  Clear any HT CRC
 807  * errors.  We only bother to do this at load time, because it's OK if
 808  * it happened before we were loaded (first time after boot/reset),
 809  * but any time after that, it's fatal anyway.  Also need to not check
 810  * for for upper byte errors if we are in 8 bit mode, so figure out
 811  * our width.  For now, at least, also complain if it's 8 bit.
 812  */
 813 static void slave_or_pri_blk(struct ipath_devdata *dd, struct pci_dev *pdev,
 814                              int pos, u8 cap_type)
 815 {
 816         u8 linkwidth = 0, linkerr, link_a_b_off, link_off;
 817         u16 linkctrl = 0;
 818         int i;
 819
 820         dd->ipath_ht_slave_off = pos;
 821         /* command word, master_host bit */
 822         /* master host || slave */
 823         if ((cap_type >> 2) & 1)
 824                 link_a_b_off = 4;
 825         else
 826                 link_a_b_off = 0;
 827         ipath_cdbg(VERBOSE, "HT%u (Link %c) connected to processor\n",
 828                    link_a_b_off ? 1 : 0,
 829                    link_a_b_off ? 'B' : 'A');
 830
 831         link_a_b_off += pos;
 832
 833         /*
 834          * check both link control registers; clear both HT CRC sets if
 835          * necessary.
 836          */
 837         for (i = 0; i < 2; i++) {
 838                 link_off = pos + i * 4 + 0x4;
 839                 if (pci_read_config_word(pdev, link_off, &linkctrl))
 840                         ipath_dev_err(dd, "Couldn't read HT link control%d "
 841                                       "register\n", i);
 842                 else if (linkctrl & (0xf << 8)) {
 843                         ipath_cdbg(VERBOSE, "Clear linkctrl%d CRC Error "
 844                                    "bits %x\n", i, linkctrl & (0xf << 8));
 845                         /*
 846                          * now write them back to clear the error.
 847                          */
 848                         pci_write_config_byte(pdev, link_off,
 849                                               linkctrl & (0xf << 8));
 850                 }
 851         }
 852
 853         /*
 854          * As with HT CRC bits, same for protocol errors that might occur
 855          * during boot.
 856          */
 857         for (i = 0; i < 2; i++) {
 858                 link_off = pos + i * 4 + 0xd;
 859                 if (pci_read_config_byte(pdev, link_off, &linkerr))
 860                         dev_info(&pdev->dev, "Couldn't read linkerror%d "
 861                                  "of HT slave/primary block\n", i);
 862                 else if (linkerr & 0xf0) {
 863                         ipath_cdbg(VERBOSE, "HT linkerr%d bits 0x%x set, "
 864                                    "clearing\n", linkerr >> 4, i);
 865                         /*
 866                          * writing the linkerr bits that are set will clear
 867                          * them
 868                          */
 869                         if (pci_write_config_byte
 870                             (pdev, link_off, linkerr))
 871                                 ipath_dbg("Failed write to clear HT "
 872                                           "linkerror%d\n", i);
 873                         if (pci_read_config_byte(pdev, link_off, &linkerr))
 874                                 dev_info(&pdev->dev, "Couldn't reread "
 875                                          "linkerror%d of HT slave/primary "
 876                                          "block\n", i);
 877                         else if (linkerr & 0xf0)
 878                                 dev_info(&pdev->dev, "HT linkerror%d bits "
 879                                          "0x%x couldn't be cleared\n",
 880                                          i, linkerr >> 4);
 881                 }
 882         }
 883
 884         /*
 885          * this is just for our link to the host, not devices connected
 886          * through tunnel.
 887          */
 888
 889         if (pci_read_config_byte(pdev, link_a_b_off + 7, &linkwidth))
 890                 ipath_dev_err(dd, "Couldn't read HT link width "
 891                               "config register\n");
 892         else {
 893                 u32 width;
 894                 switch (linkwidth & 7) {
 895                 case 5:
 896                         width = 4;
 897                         break;
 898                 case 4:
 899                         width = 2;
 900                         break;
 901                 case 3:
 902                         width = 32;
 903                         break;
 904                 case 1:
 905                         width = 16;
 906                         break;
 907                 case 0:
 908                 default:        /* if wrong, assume 8 bit */
 909                         width = 8;
 910                         break;
 911                 }
 912
 913                 dd->ipath_lbus_width = width;
 914
 915                 if (linkwidth != 0x11) {
 916                         ipath_dev_err(dd, "Not configured for 16 bit HT "
 917                                       "(%x)\n", linkwidth);
 918                         if (!(linkwidth & 0xf)) {
 919                                 ipath_dbg("Will ignore HT lane1 errors\n");
 920                                 dd->ipath_flags |= IPATH_8BIT_IN_HT0;
 921                         }
 922                 }
 923         }
 924
 925         /*
 926          * this is just for our link to the host, not devices connected
 927          * through tunnel.
 928          */
 929         if (pci_read_config_byte(pdev, link_a_b_off + 0xd, &linkwidth))
 930                 ipath_dev_err(dd, "Couldn't read HT link frequency "
 931                               "config register\n");
 932         else {
 933                 u32 speed;
 934                 switch (linkwidth & 0xf) {
 935                 case 6:
 936                         speed = 1000;
 937                         break;
 938                 case 5:
 939                         speed = 800;
 940                         break;
 941                 case 4:
 942                         speed = 600;
 943                         break;
 944                 case 3:
 945                         speed = 500;
 946                         break;
 947                 case 2:
 948                         speed = 400;
 949                         break;
 950                 case 1:
 951                         speed = 300;
 952                         break;
 953                 default:
 954                         /*
 955                          * assume reserved and vendor-specific are 200...
 956                          */
 957                 case 0:
 958                         speed = 200;
 959                         break;
 960                 }
 961                 dd->ipath_lbus_speed = speed;
 962         }
 963
 964         snprintf(dd->ipath_lbus_info, sizeof(dd->ipath_lbus_info),
 965                 "HyperTransport,%uMHz,x%u\n",
 966                 dd->ipath_lbus_speed,
 967                 dd->ipath_lbus_width);
 968 }
 969
 970 static int ipath_ht_intconfig(struct ipath_devdata *dd)
 971 {
 972         int ret;
 973
 974         if (dd->ipath_intconfig) {
 975                 ipath_write_kreg(dd, dd->ipath_kregs->kr_interruptconfig,
 976                                  dd->ipath_intconfig);  /* interrupt address */
 977                 ret = 0;
 978         } else {
 979                 ipath_dev_err(dd, "No interrupts enabled, couldn't setup "
 980                               "interrupt address\n");
 981                 ret = -EINVAL;
 982         }
 983
 984         return ret;
 985 }
 986
 987 static void ipath_ht_irq_update(struct pci_dev *dev, int irq,
 988                                 struct ht_irq_msg *msg)
 989 {
 990         struct ipath_devdata *dd = pci_get_drvdata(dev);
 991         u64 prev_intconfig = dd->ipath_intconfig;
 992
 993         dd->ipath_intconfig = msg->address_lo;
 994         dd->ipath_intconfig |= ((u64) msg->address_hi) << 32;
 995
 996         /*
 997          * If the previous value of dd->ipath_intconfig is zero, we're
 998          * getting configured for the first time, and must not program the
 999          * intconfig register here (it will be programmed later, when the
1000          * hardware is ready).  Otherwise, we should.
1001          */
1002         if (prev_intconfig)
1003                 ipath_ht_intconfig(dd);
1004 }
1005
1006 /**
1007  * ipath_setup_ht_config - setup the interruptconfig register
1008  * @dd: the infinipath device
1009  * @pdev: the PCI device
1010  *
1011  * setup the interruptconfig register from the HT config info.
1012  * Also clear CRC errors in HT linkcontrol, if necessary.
1013  * This is done only for the real hardware.  It is done before
1014  * chip address space is initted, so can't touch infinipath registers
1015  */
1016 static int ipath_setup_ht_config(struct ipath_devdata *dd,
1017                                  struct pci_dev *pdev)
1018 {
1019         int pos, ret;
1020
1021         ret = __ht_create_irq(pdev, 0, ipath_ht_irq_update);
1022         if (ret < 0) {
1023                 ipath_dev_err(dd, "Couldn't create interrupt handler: "
1024                               "err %d\n", ret);
1025                 goto bail;
1026         }
1027         dd->ipath_irq = ret;
1028         ret = 0;
1029
1030         /*
1031          * Handle clearing CRC errors in linkctrl register if necessary.  We
1032          * do this early, before we ever enable errors or hardware errors,
1033          * mostly to avoid causing the chip to enter freeze mode.
1034          */
1035         pos = pci_find_capability(pdev, PCI_CAP_ID_HT);
1036         if (!pos) {
1037                 ipath_dev_err(dd, "Couldn't find HyperTransport "
1038                               "capability; no interrupts\n");
1039                 ret = -ENODEV;
1040                 goto bail;
1041         }
1042         do {
1043                 u8 cap_type;
1044
1045                 /*
1046                  * The HT capability type byte is 3 bytes after the
1047                  * capability byte.
1048                  */
1049                 if (pci_read_config_byte(pdev, pos + 3, &cap_type)) {
1050                         dev_info(&pdev->dev, "Couldn't read config "
1051                                  "command @ %d\n", pos);
1052                         continue;
1053                 }
1054                 if (!(cap_type & 0xE0))
1055                         slave_or_pri_blk(dd, pdev, pos, cap_type);
1056         } while ((pos = pci_find_next_capability(pdev, pos,
1057                                                  PCI_CAP_ID_HT)));
1058
1059         dd->ipath_flags |= IPATH_SWAP_PIOBUFS;
1060
1061 bail:
1062         return ret;
1063 }
1064
1065 /**
1066  * ipath_setup_ht_cleanup - clean up any per-chip chip-specific stuff
1067  * @dd: the infinipath device
1068  *
1069  * Called during driver unload.
1070  * This is currently a nop for the HT chip, not for all chips
1071  */
1072 static void ipath_setup_ht_cleanup(struct ipath_devdata *dd)
1073 {
1074 }
1075
1076 /**
1077  * ipath_setup_ht_setextled - set the state of the two external LEDs
1078  * @dd: the infinipath device
1079  * @lst: the L state
1080  * @ltst: the LT state
1081  *
1082  * Set the state of the two external LEDs, to indicate physical and
1083  * logical state of IB link.   For this chip (at least with recommended
1084  * board pinouts), LED1 is Green (physical state), and LED2 is Yellow
1085  * (logical state)
1086  *
1087  * Note:  We try to match the Mellanox HCA LED behavior as best
1088  * we can.  Green indicates physical link state is OK (something is
1089  * plugged in, and we can train).
1090  * Amber indicates the link is logically up (ACTIVE).
1091  * Mellanox further blinks the amber LED to indicate data packet
1092  * activity, but we have no hardware support for that, so it would
1093  * require waking up every 10-20 msecs and checking the counters
1094  * on the chip, and then turning the LED off if appropriate.  That's
1095  * visible overhead, so not something we will do.
1096  *
1097  */
1098 static void ipath_setup_ht_setextled(struct ipath_devdata *dd,
1099                                      u64 lst, u64 ltst)
1100 {
1101         u64 extctl;
1102         unsigned long flags = 0;
1103
1104         /* the diags use the LED to indicate diag info, so we leave
1105          * the external LED alone when the diags are running */
1106         if (ipath_diag_inuse)
1107                 return;
1108
1109         /* Allow override of LED display for, e.g. Locating system in rack */
1110         if (dd->ipath_led_override) {
1111                 ltst = (dd->ipath_led_override & IPATH_LED_PHYS)
1112                         ? INFINIPATH_IBCS_LT_STATE_LINKUP
1113                         : INFINIPATH_IBCS_LT_STATE_DISABLED;
1114                 lst = (dd->ipath_led_override & IPATH_LED_LOG)
1115                         ? INFINIPATH_IBCS_L_STATE_ACTIVE
1116                         : INFINIPATH_IBCS_L_STATE_DOWN;
1117         }
1118
1119         spin_lock_irqsave(&dd->ipath_gpio_lock, flags);
1120         /*
1121          * start by setting both LED control bits to off, then turn
1122          * on the appropriate bit(s).
1123          */
1124         if (dd->ipath_boardrev == 8) { /* LS/X-1 uses different pins */
1125                 /*
1126                  * major difference is that INFINIPATH_EXTC_LEDGBLERR_OFF
1127                  * is inverted,  because it is normally used to indicate
1128                  * a hardware fault at reset, if there were errors
1129                  */
1130                 extctl = (dd->ipath_extctrl & ~INFINIPATH_EXTC_LEDGBLOK_ON)
1131                         | INFINIPATH_EXTC_LEDGBLERR_OFF;
1132                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1133                         extctl &= ~INFINIPATH_EXTC_LEDGBLERR_OFF;
1134                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1135                         extctl |= INFINIPATH_EXTC_LEDGBLOK_ON;
1136         }
1137         else {
1138                 extctl = dd->ipath_extctrl &
1139                         ~(INFINIPATH_EXTC_LED1PRIPORT_ON |
1140                           INFINIPATH_EXTC_LED2PRIPORT_ON);
1141                 if (ltst == INFINIPATH_IBCS_LT_STATE_LINKUP)
1142                         extctl |= INFINIPATH_EXTC_LED1PRIPORT_ON;
1143                 if (lst == INFINIPATH_IBCS_L_STATE_ACTIVE)
1144                         extctl |= INFINIPATH_EXTC_LED2PRIPORT_ON;
1145         }
1146         dd->ipath_extctrl = extctl;
1147         ipath_write_kreg(dd, dd->ipath_kregs->kr_extctrl, extctl);
1148         spin_unlock_irqrestore(&dd->ipath_gpio_lock, flags);
1149 }
1150
1151 static void ipath_init_ht_variables(struct ipath_devdata *dd)
1152 {
1153         /*
1154          * setup the register offsets, since they are different for each
1155          * chip
1156          */
1157         dd->ipath_kregs = &ipath_ht_kregs;
1158         dd->ipath_cregs = &ipath_ht_cregs;
1159
1160         dd->ipath_gpio_sda_num = _IPATH_GPIO_SDA_NUM;
1161         dd->ipath_gpio_scl_num = _IPATH_GPIO_SCL_NUM;
1162         dd->ipath_gpio_sda = IPATH_GPIO_SDA;
1163         dd->ipath_gpio_scl = IPATH_GPIO_SCL;
1164
1165         /*
1166          * Fill in data for field-values that change in newer chips.
1167          * We dynamically specify only the mask for LINKTRAININGSTATE
1168          * and only the shift for LINKSTATE, as they are the only ones
1169          * that change.  Also precalculate the 3 link states of interest
1170          * and the combined mask.
1171          */
1172         dd->ibcs_ls_shift = IBA6110_IBCS_LINKSTATE_SHIFT;
1173         dd->ibcs_lts_mask = IBA6110_IBCS_LINKTRAININGSTATE_MASK;
1174         dd->ibcs_mask = (INFINIPATH_IBCS_LINKSTATE_MASK <<
1175                 dd->ibcs_ls_shift) | dd->ibcs_lts_mask;
1176         dd->ib_init = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1177                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1178                 (INFINIPATH_IBCS_L_STATE_INIT << dd->ibcs_ls_shift);
1179         dd->ib_arm = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1180                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1181                 (INFINIPATH_IBCS_L_STATE_ARM << dd->ibcs_ls_shift);
1182         dd->ib_active = (INFINIPATH_IBCS_LT_STATE_LINKUP <<
1183                 INFINIPATH_IBCS_LINKTRAININGSTATE_SHIFT) |
1184                 (INFINIPATH_IBCS_L_STATE_ACTIVE << dd->ibcs_ls_shift);
1185
1186         /*
1187          * Fill in data for ibcc field-values that change in newer chips.
1188          * We dynamically specify only the mask for LINKINITCMD
1189          * and only the shift for LINKCMD and MAXPKTLEN, as they are
1190          * the only ones that change.
1191          */
1192         dd->ibcc_lic_mask = INFINIPATH_IBCC_LINKINITCMD_MASK;
1193         dd->ibcc_lc_shift = INFINIPATH_IBCC_LINKCMD_SHIFT;
1194         dd->ibcc_mpl_shift = INFINIPATH_IBCC_MAXPKTLEN_SHIFT;
1195
1196         /* Fill in shifts for RcvCtrl. */
1197         dd->ipath_r_portenable_shift = INFINIPATH_R_PORTENABLE_SHIFT;
1198         dd->ipath_r_intravail_shift = INFINIPATH_R_INTRAVAIL_SHIFT;
1199         dd->ipath_r_tailupd_shift = INFINIPATH_R_TAILUPD_SHIFT;
1200         dd->ipath_r_portcfg_shift = 0; /* Not on IBA6110 */
1201
1202         dd->ipath_i_bitsextant =
1203                 (INFINIPATH_I_RCVURG_MASK << INFINIPATH_I_RCVURG_SHIFT) |
1204                 (INFINIPATH_I_RCVAVAIL_MASK <<
1205                  INFINIPATH_I_RCVAVAIL_SHIFT) |
1206                 INFINIPATH_I_ERROR | INFINIPATH_I_SPIOSENT |
1207                 INFINIPATH_I_SPIOBUFAVAIL | INFINIPATH_I_GPIO;
1208
1209         dd->ipath_e_bitsextant =
1210                 INFINIPATH_E_RFORMATERR | INFINIPATH_E_RVCRC |
1211                 INFINIPATH_E_RICRC | INFINIPATH_E_RMINPKTLEN |
1212                 INFINIPATH_E_RMAXPKTLEN | INFINIPATH_E_RLONGPKTLEN |
1213                 INFINIPATH_E_RSHORTPKTLEN | INFINIPATH_E_RUNEXPCHAR |
1214                 INFINIPATH_E_RUNSUPVL | INFINIPATH_E_REBP |
1215                 INFINIPATH_E_RIBFLOW | INFINIPATH_E_RBADVERSION |
1216                 INFINIPATH_E_RRCVEGRFULL | INFINIPATH_E_RRCVHDRFULL |
1217                 INFINIPATH_E_RBADTID | INFINIPATH_E_RHDRLEN |
1218                 INFINIPATH_E_RHDR | INFINIPATH_E_RIBLOSTLINK |
1219                 INFINIPATH_E_SMINPKTLEN | INFINIPATH_E_SMAXPKTLEN |
1220                 INFINIPATH_E_SUNDERRUN | INFINIPATH_E_SPKTLEN |
1221                 INFINIPATH_E_SDROPPEDSMPPKT | INFINIPATH_E_SDROPPEDDATAPKT |
1222                 INFINIPATH_E_SPIOARMLAUNCH | INFINIPATH_E_SUNEXPERRPKTNUM |
1223                 INFINIPATH_E_SUNSUPVL | INFINIPATH_E_IBSTATUSCHANGED |
1224                 INFINIPATH_E_INVALIDADDR | INFINIPATH_E_RESET |
1225                 INFINIPATH_E_HARDWARE;
1226
1227         dd->ipath_hwe_bitsextant =
1228                 (INFINIPATH_HWE_HTCMEMPARITYERR_MASK <<
1229                  INFINIPATH_HWE_HTCMEMPARITYERR_SHIFT) |
1230                 (INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1231                  INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT) |
1232                 (INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1233                  INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT) |
1234                 INFINIPATH_HWE_HTCLNKABYTE0CRCERR |
1235                 INFINIPATH_HWE_HTCLNKABYTE1CRCERR |
1236                 INFINIPATH_HWE_HTCLNKBBYTE0CRCERR |
1237                 INFINIPATH_HWE_HTCLNKBBYTE1CRCERR |
1238                 INFINIPATH_HWE_HTCMISCERR4 |
1239                 INFINIPATH_HWE_HTCMISCERR5 | INFINIPATH_HWE_HTCMISCERR6 |
1240                 INFINIPATH_HWE_HTCMISCERR7 |
1241                 INFINIPATH_HWE_HTCBUSTREQPARITYERR |
1242                 INFINIPATH_HWE_HTCBUSTRESPPARITYERR |
1243                 INFINIPATH_HWE_HTCBUSIREQPARITYERR |
1244                 INFINIPATH_HWE_RXDSYNCMEMPARITYERR |
1245                 INFINIPATH_HWE_MEMBISTFAILED |
1246                 INFINIPATH_HWE_COREPLL_FBSLIP |
1247                 INFINIPATH_HWE_COREPLL_RFSLIP |
1248                 INFINIPATH_HWE_HTBPLL_FBSLIP |
1249                 INFINIPATH_HWE_HTBPLL_RFSLIP |
1250                 INFINIPATH_HWE_HTAPLL_FBSLIP |
1251                 INFINIPATH_HWE_HTAPLL_RFSLIP |
1252                 INFINIPATH_HWE_SERDESPLLFAILED |
1253                 INFINIPATH_HWE_IBCBUSTOSPCPARITYERR |
1254                 INFINIPATH_HWE_IBCBUSFRSPCPARITYERR;
1255
1256         dd->ipath_i_rcvavail_mask = INFINIPATH_I_RCVAVAIL_MASK;
1257         dd->ipath_i_rcvurg_mask = INFINIPATH_I_RCVURG_MASK;
1258         dd->ipath_i_rcvavail_shift = INFINIPATH_I_RCVAVAIL_SHIFT;
1259         dd->ipath_i_rcvurg_shift = INFINIPATH_I_RCVURG_SHIFT;
1260
1261         /*
1262          * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
1263          * 2 is Some Misc, 3 is reserved for future.
1264          */
1265         dd->ipath_eep_st_masks[0].hwerrs_to_log =
1266                 INFINIPATH_HWE_TXEMEMPARITYERR_MASK <<
1267                 INFINIPATH_HWE_TXEMEMPARITYERR_SHIFT;
1268
1269         dd->ipath_eep_st_masks[1].hwerrs_to_log =
1270                 INFINIPATH_HWE_RXEMEMPARITYERR_MASK <<
1271                 INFINIPATH_HWE_RXEMEMPARITYERR_SHIFT;
1272
1273         dd->ipath_eep_st_masks[2].errs_to_log = INFINIPATH_E_RESET;
1274
1275         dd->delay_mult = 2; /* SDR, 4X, can't change */
1276
1277         dd->ipath_link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
1278         dd->ipath_link_speed_supported = IPATH_IB_SDR;
1279         dd->ipath_link_width_enabled = IB_WIDTH_4X;
1280         dd->ipath_link_speed_enabled = dd->ipath_link_speed_supported;
1281         /* these can't change for this chip, so set once */
1282         dd->ipath_link_width_active = dd->ipath_link_width_enabled;
1283         dd->ipath_link_speed_active = dd->ipath_link_speed_enabled;
1284 }
1285
1286 /**
1287  * ipath_ht_init_hwerrors - enable hardware errors
1288  * @dd: the infinipath device
1289  *
1290  * now that we have finished initializing everything that might reasonably
1291  * cause a hardware error, and cleared those errors bits as they occur,
1292  * we can enable hardware errors in the mask (potentially enabling
1293  * freeze mode), and enable hardware errors as errors (along with
1294  * everything else) in errormask
1295  */
1296 static void ipath_ht_init_hwerrors(struct ipath_devdata *dd)
1297 {
1298         ipath_err_t val;
1299         u64 extsval;
1300
1301         extsval = ipath_read_kreg64(dd, dd->ipath_kregs->kr_extstatus);
1302
1303         if (!(extsval & INFINIPATH_EXTS_MEMBIST_ENDTEST))
1304                 ipath_dev_err(dd, "MemBIST did not complete!\n");
1305         if (extsval & INFINIPATH_EXTS_MEMBIST_CORRECT)
1306                 ipath_dbg("MemBIST corrected\n");
1307
1308         ipath_check_htlink(dd);
1309
1310         /* barring bugs, all hwerrors become interrupts, which can */
1311         val = -1LL;
1312         /* don't look at crc lane1 if 8 bit */
1313         if (dd->ipath_flags & IPATH_8BIT_IN_HT0)
1314                 val &= ~infinipath_hwe_htclnkabyte1crcerr;
1315         /* don't look at crc lane1 if 8 bit */
1316         if (dd->ipath_flags & IPATH_8BIT_IN_HT1)
1317                 val &= ~infinipath_hwe_htclnkbbyte1crcerr;
1318
1319         /*
1320          * disable RXDSYNCMEMPARITY because external serdes is unused,
1321          * and therefore the logic will never be used or initialized,
1322          * and uninitialized state will normally result in this error
1323          * being asserted.  Similarly for the external serdess pll
1324          * lock signal.
1325          */
1326         val &= ~(INFINIPATH_HWE_SERDESPLLFAILED |
1327                  INFINIPATH_HWE_RXDSYNCMEMPARITYERR);
1328
1329         /*
1330          * Disable MISCERR4 because of an inversion in the HT core
1331          * logic checking for errors that cause this bit to be set.
1332          * The errata can also cause the protocol error bit to be set
1333          * in the HT config space linkerror register(s).
1334          */
1335         val &= ~INFINIPATH_HWE_HTCMISCERR4;
1336
1337         /*
1338          * PLL ignored because unused MDIO interface has a logic problem
1339          */
1340         if (dd->ipath_boardrev == 4 || dd->ipath_boardrev == 9)
1341                 val &= ~INFINIPATH_HWE_SERDESPLLFAILED;
1342         dd->ipath_hwerrmask = val;
1343 }
1344
1345
1346
1347
1348 /**
1349  * ipath_ht_bringup_serdes - bring up the serdes
1350  * @dd: the infinipath device
1351  */
1352 static int ipath_ht_bringup_serdes(struct ipath_devdata *dd)
1353 {
1354         u64 val, config1;
1355         int ret = 0, change = 0;
1356
1357         ipath_dbg("Trying to bringup serdes\n");
1358
1359         if (ipath_read_kreg64(dd, dd->ipath_kregs->kr_hwerrstatus) &
1360             INFINIPATH_HWE_SERDESPLLFAILED)
1361         {
1362                 ipath_dbg("At start, serdes PLL failed bit set in "
1363                           "hwerrstatus, clearing and continuing\n");
1364                 ipath_write_kreg(dd, dd->ipath_kregs->kr_hwerrclear,
1365                                  INFINIPATH_HWE_SERDESPLLFAILED);
1366         }
1367
1368         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1369         config1 = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig1);
1370
1371         ipath_cdbg(VERBOSE, "Initial serdes status is config0=%llx "
1372                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1373                    (unsigned long long) val, (unsigned long long) config1,
1374                    (unsigned long long)
1375                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1376                    (unsigned long long)
1377                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1378
1379         /* force reset on */
1380         val |= INFINIPATH_SERDC0_RESET_PLL
1381                 /* | INFINIPATH_SERDC0_RESET_MASK */
1382                 ;
1383         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1384         udelay(15);             /* need pll reset set at least for a bit */
1385
1386         if (val & INFINIPATH_SERDC0_RESET_PLL) {
1387                 u64 val2 = val &= ~INFINIPATH_SERDC0_RESET_PLL;
1388                 /* set lane resets, and tx idle, during pll reset */
1389                 val2 |= INFINIPATH_SERDC0_RESET_MASK |
1390                         INFINIPATH_SERDC0_TXIDLE;
1391                 ipath_cdbg(VERBOSE, "Clearing serdes PLL reset (writing "
1392                            "%llx)\n", (unsigned long long) val2);
1393                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1394                                  val2);
1395                 /*
1396                  * be sure chip saw it
1397                  */
1398                 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_scratch);
1399                 /*
1400                  * need pll reset clear at least 11 usec before lane
1401                  * resets cleared; give it a few more
1402                  */
1403                 udelay(15);
1404                 val = val2;     /* for check below */
1405         }
1406
1407         if (val & (INFINIPATH_SERDC0_RESET_PLL |
1408                    INFINIPATH_SERDC0_RESET_MASK |
1409                    INFINIPATH_SERDC0_TXIDLE)) {
1410                 val &= ~(INFINIPATH_SERDC0_RESET_PLL |
1411                          INFINIPATH_SERDC0_RESET_MASK |
1412                          INFINIPATH_SERDC0_TXIDLE);
1413                 /* clear them */
1414                 ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0,
1415                                  val);
1416         }
1417
1418         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1419         if (val & INFINIPATH_XGXS_RESET) {
1420                 /* normally true after boot */
1421                 val &= ~INFINIPATH_XGXS_RESET;
1422                 change = 1;
1423         }
1424         if (((val >> INFINIPATH_XGXS_RX_POL_SHIFT) &
1425              INFINIPATH_XGXS_RX_POL_MASK) != dd->ipath_rx_pol_inv ) {
1426                 /* need to compensate for Tx inversion in partner */
1427                 val &= ~(INFINIPATH_XGXS_RX_POL_MASK <<
1428                          INFINIPATH_XGXS_RX_POL_SHIFT);
1429                 val |= dd->ipath_rx_pol_inv <<
1430                         INFINIPATH_XGXS_RX_POL_SHIFT;
1431                 change = 1;
1432         }
1433         if (change)
1434                 ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1435
1436         val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1437
1438         /* clear current and de-emphasis bits */
1439         config1 &= ~0x0ffffffff00ULL;
1440         /* set current to 20ma */
1441         config1 |= 0x00000000000ULL;
1442         /* set de-emphasis to -5.68dB */
1443         config1 |= 0x0cccc000000ULL;
1444         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig1, config1);
1445
1446         ipath_cdbg(VERBOSE, "After setup: serdes status is config0=%llx "
1447                    "config1=%llx, sstatus=%llx xgxs %llx\n",
1448                    (unsigned long long) val, (unsigned long long) config1,
1449                    (unsigned long long)
1450                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesstatus),
1451                    (unsigned long long)
1452                    ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig));
1453
1454         return ret;             /* for now, say we always succeeded */
1455 }
1456
1457 /**
1458  * ipath_ht_quiet_serdes - set serdes to txidle
1459  * @dd: the infinipath device
1460  * driver is being unloaded
1461  */
1462 static void ipath_ht_quiet_serdes(struct ipath_devdata *dd)
1463 {
1464         u64 val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_serdesconfig0);
1465
1466         val |= INFINIPATH_SERDC0_TXIDLE;
1467         ipath_dbg("Setting TxIdleEn on serdes (config0 = %llx)\n",
1468                   (unsigned long long) val);
1469         ipath_write_kreg(dd, dd->ipath_kregs->kr_serdesconfig0, val);
1470 }
1471
1472 /**
1473  * ipath_pe_put_tid - write a TID in chip
1474  * @dd: the infinipath device
1475  * @tidptr: pointer to the expected TID (in chip) to udpate
1476  * @tidtype: RCVHQ_RCV_TYPE_EAGER (1) for eager, RCVHQ_RCV_TYPE_EXPECTED (0) for expected
1477  * @pa: physical address of in memory buffer; ipath_tidinvalid if freeing
1478  *
1479  * This exists as a separate routine to allow for special locking etc.
1480  * It's used for both the full cleanup on exit, as well as the normal
1481  * setup and teardown.
1482  */
1483 static void ipath_ht_put_tid(struct ipath_devdata *dd,
1484                              u64 __iomem *tidptr, u32 type,
1485                              unsigned long pa)
1486 {
1487         if (!dd->ipath_kregbase)
1488                 return;
1489
1490         if (pa != dd->ipath_tidinvalid) {
1491                 if (unlikely((pa & ~INFINIPATH_RT_ADDR_MASK))) {
1492                         dev_info(&dd->pcidev->dev,
1493                                  "physaddr %lx has more than "
1494                                  "40 bits, using only 40!!!\n", pa);
1495                         pa &= INFINIPATH_RT_ADDR_MASK;
1496                 }
1497                 if (type == RCVHQ_RCV_TYPE_EAGER)
1498                         pa |= dd->ipath_tidtemplate;
1499                 else {
1500                         /* in words (fixed, full page).  */
1501                         u64 lenvalid = PAGE_SIZE >> 2;
1502                         lenvalid <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1503                         pa |= lenvalid | INFINIPATH_RT_VALID;
1504                 }
1505         }
1506
1507         writeq(pa, tidptr);
1508 }
1509
1510
1511 /**
1512  * ipath_ht_clear_tid - clear all TID entries for a port, expected and eager
1513  * @dd: the infinipath device
1514  * @port: the port
1515  *
1516  * Used from ipath_close(), and at chip initialization.
1517  */
1518 static void ipath_ht_clear_tids(struct ipath_devdata *dd, unsigned port)
1519 {
1520         u64 __iomem *tidbase;
1521         int i;
1522
1523         if (!dd->ipath_kregbase)
1524                 return;
1525
1526         ipath_cdbg(VERBOSE, "Invalidate TIDs for port %u\n", port);
1527
1528         /*
1529          * need to invalidate all of the expected TID entries for this
1530          * port, so we don't have valid entries that might somehow get
1531          * used (early in next use of this port, or through some bug)
1532          */
1533         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1534                                    dd->ipath_rcvtidbase +
1535                                    port * dd->ipath_rcvtidcnt *
1536                                    sizeof(*tidbase));
1537         for (i = 0; i < dd->ipath_rcvtidcnt; i++)
1538                 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
1539                                  dd->ipath_tidinvalid);
1540
1541         tidbase = (u64 __iomem *) ((char __iomem *)(dd->ipath_kregbase) +
1542                                    dd->ipath_rcvegrbase +
1543                                    port * dd->ipath_rcvegrcnt *
1544                                    sizeof(*tidbase));
1545
1546         for (i = 0; i < dd->ipath_rcvegrcnt; i++)
1547                 ipath_ht_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
1548                                  dd->ipath_tidinvalid);
1549 }
1550
1551 /**
1552  * ipath_ht_tidtemplate - setup constants for TID updates
1553  * @dd: the infinipath device
1554  *
1555  * We setup stuff that we use a lot, to avoid calculating each time
1556  */
1557 static void ipath_ht_tidtemplate(struct ipath_devdata *dd)
1558 {
1559         dd->ipath_tidtemplate = dd->ipath_ibmaxlen >> 2;
1560         dd->ipath_tidtemplate <<= INFINIPATH_RT_BUFSIZE_SHIFT;
1561         dd->ipath_tidtemplate |= INFINIPATH_RT_VALID;
1562
1563         /*
1564          * work around chip errata bug 7358, by marking invalid tids
1565          * as having max length
1566          */
1567         dd->ipath_tidinvalid = (-1LL & INFINIPATH_RT_BUFSIZE_MASK) <<
1568                 INFINIPATH_RT_BUFSIZE_SHIFT;
1569 }
1570
1571 static int ipath_ht_early_init(struct ipath_devdata *dd)
1572 {
1573         u32 __iomem *piobuf;
1574         u32 pioincr, val32;
1575         int i;
1576
1577         /*
1578          * one cache line; long IB headers will spill over into received
1579          * buffer
1580          */
1581         dd->ipath_rcvhdrentsize = 16;
1582         dd->ipath_rcvhdrsize = IPATH_DFLT_RCVHDRSIZE;
1583
1584         /*
1585          * For HT, we allocate a somewhat overly large eager buffer,
1586          * such that we can guarantee that we can receive the largest
1587          * packet that we can send out.  To truly support a 4KB MTU,
1588          * we need to bump this to a large value.  To date, other than
1589          * testing, we have never encountered an HCA that can really
1590          * send 4KB MTU packets, so we do not handle that (we'll get
1591          * errors interrupts if we ever see one).
1592          */
1593         dd->ipath_rcvegrbufsize = dd->ipath_piosize2k;
1594
1595         /*
1596          * the min() check here is currently a nop, but it may not
1597          * always be, depending on just how we do ipath_rcvegrbufsize
1598          */
1599         dd->ipath_ibmaxlen = min(dd->ipath_piosize2k,
1600                                  dd->ipath_rcvegrbufsize);
1601         dd->ipath_init_ibmaxlen = dd->ipath_ibmaxlen;
1602         ipath_ht_tidtemplate(dd);
1603
1604         /*
1605          * zero all the TID entries at startup.  We do this for sanity,
1606          * in case of a previous driver crash of some kind, and also
1607          * because the chip powers up with these memories in an unknown
1608          * state.  Use portcnt, not cfgports, since this is for the
1609          * full chip, not for current (possibly different) configuration
1610          * value.
1611          * Chip Errata bug 6447
1612          */
1613         for (val32 = 0; val32 < dd->ipath_portcnt; val32++)
1614                 ipath_ht_clear_tids(dd, val32);
1615
1616         /*
1617          * write the pbc of each buffer, to be sure it's initialized, then
1618          * cancel all the buffers, and also abort any packets that might
1619          * have been in flight for some reason (the latter is for driver
1620          * unload/reload, but isn't a bad idea at first init).  PIO send
1621          * isn't enabled at this point, so there is no danger of sending
1622          * these out on the wire.
1623          * Chip Errata bug 6610
1624          */
1625         piobuf = (u32 __iomem *) (((char __iomem *)(dd->ipath_kregbase)) +
1626                                   dd->ipath_piobufbase);
1627         pioincr = dd->ipath_palign / sizeof(*piobuf);
1628         for (i = 0; i < dd->ipath_piobcnt2k; i++) {
1629                 /*
1630                  * reasonable word count, just to init pbc
1631                  */
1632                 writel(16, piobuf);
1633                 piobuf += pioincr;
1634         }
1635
1636         ipath_get_eeprom_info(dd);
1637         if (dd->ipath_boardrev == 5) {
1638                 /*
1639                  * Later production QHT7040 has same changes as QHT7140, so
1640                  * can use GPIO interrupts.  They have serial #'s starting
1641                  * with 128, rather than 112.
1642                  */
1643                 if (dd->ipath_serial[0] == '1' &&
1644                     dd->ipath_serial[1] == '2' &&
1645                     dd->ipath_serial[2] == '8')
1646                         dd->ipath_flags |= IPATH_GPIO_INTR;
1647                 else {
1648                         ipath_dev_err(dd, "Unsupported InfiniPath board "
1649                                 "(serial number %.16s)!\n",
1650                                 dd->ipath_serial);
1651                         return 1;
1652                 }
1653         }
1654
1655         if (dd->ipath_minrev >= 4) {
1656                 /* Rev4+ reports extra errors via internal GPIO pins */
1657                 dd->ipath_flags |= IPATH_GPIO_ERRINTRS;
1658                 dd->ipath_gpio_mask |= IPATH_GPIO_ERRINTR_MASK;
1659                 ipath_write_kreg(dd, dd->ipath_kregs->kr_gpio_mask,
1660                                  dd->ipath_gpio_mask);
1661         }
1662
1663         return 0;
1664 }
1665
1666
1667 /**
1668  * ipath_init_ht_get_base_info - set chip-specific flags for user code
1669  * @dd: the infinipath device
1670  * @kbase: ipath_base_info pointer
1671  *
1672  * We set the PCIE flag because the lower bandwidth on PCIe vs
1673  * HyperTransport can affect some user packet algorithms.
1674  */
1675 static int ipath_ht_get_base_info(struct ipath_portdata *pd, void *kbase)
1676 {
1677         struct ipath_base_info *kinfo = kbase;
1678
1679         kinfo->spi_runtime_flags |= IPATH_RUNTIME_HT |
1680                 IPATH_RUNTIME_PIO_REGSWAPPED;
1681
1682         if (pd->port_dd->ipath_minrev < 4)
1683                 kinfo->spi_runtime_flags |= IPATH_RUNTIME_RCVHDR_COPY;
1684
1685         return 0;
1686 }
1687
1688 static void ipath_ht_free_irq(struct ipath_devdata *dd)
1689 {
1690         free_irq(dd->ipath_irq, dd);
1691         ht_destroy_irq(dd->ipath_irq);
1692         dd->ipath_irq = 0;
1693         dd->ipath_intconfig = 0;
1694 }
1695
1696 static struct ipath_message_header *
1697 ipath_ht_get_msgheader(struct ipath_devdata *dd, __le32 *rhf_addr)
1698 {
1699         return (struct ipath_message_header *)
1700                 &rhf_addr[sizeof(u64) / sizeof(u32)];
1701 }
1702
1703 static void ipath_ht_config_ports(struct ipath_devdata *dd, ushort cfgports)
1704 {
1705         dd->ipath_portcnt =
1706                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_portcnt);
1707         dd->ipath_p0_rcvegrcnt =
1708                 ipath_read_kreg32(dd, dd->ipath_kregs->kr_rcvegrcnt);
1709 }
1710
1711 static void ipath_ht_read_counters(struct ipath_devdata *dd,
1712                                    struct infinipath_counters *cntrs)
1713 {
1714         cntrs->LBIntCnt =
1715                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBIntCnt));
1716         cntrs->LBFlowStallCnt =
1717                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(LBFlowStallCnt));
1718         cntrs->TxSDmaDescCnt = 0;
1719         cntrs->TxUnsupVLErrCnt =
1720                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnsupVLErrCnt));
1721         cntrs->TxDataPktCnt =
1722                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDataPktCnt));
1723         cntrs->TxFlowPktCnt =
1724                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowPktCnt));
1725         cntrs->TxDwordCnt =
1726                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDwordCnt));
1727         cntrs->TxLenErrCnt =
1728                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxLenErrCnt));
1729         cntrs->TxMaxMinLenErrCnt =
1730                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxMaxMinLenErrCnt));
1731         cntrs->TxUnderrunCnt =
1732                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxUnderrunCnt));
1733         cntrs->TxFlowStallCnt =
1734                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxFlowStallCnt));
1735         cntrs->TxDroppedPktCnt =
1736                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(TxDroppedPktCnt));
1737         cntrs->RxDroppedPktCnt =
1738                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDroppedPktCnt));
1739         cntrs->RxDataPktCnt =
1740                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDataPktCnt));
1741         cntrs->RxFlowPktCnt =
1742                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowPktCnt));
1743         cntrs->RxDwordCnt =
1744                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxDwordCnt));
1745         cntrs->RxLenErrCnt =
1746                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLenErrCnt));
1747         cntrs->RxMaxMinLenErrCnt =
1748                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxMaxMinLenErrCnt));
1749         cntrs->RxICRCErrCnt =
1750                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxICRCErrCnt));
1751         cntrs->RxVCRCErrCnt =
1752                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxVCRCErrCnt));
1753         cntrs->RxFlowCtrlErrCnt =
1754                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxFlowCtrlErrCnt));
1755         cntrs->RxBadFormatCnt =
1756                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBadFormatCnt));
1757         cntrs->RxLinkProblemCnt =
1758                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLinkProblemCnt));
1759         cntrs->RxEBPCnt =
1760                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxEBPCnt));
1761         cntrs->RxLPCRCErrCnt =
1762                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxLPCRCErrCnt));
1763         cntrs->RxBufOvflCnt =
1764                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxBufOvflCnt));
1765         cntrs->RxTIDFullErrCnt =
1766                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDFullErrCnt));
1767         cntrs->RxTIDValidErrCnt =
1768                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxTIDValidErrCnt));
1769         cntrs->RxPKeyMismatchCnt =
1770                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxPKeyMismatchCnt));
1771         cntrs->RxP0HdrEgrOvflCnt =
1772                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP0HdrEgrOvflCnt));
1773         cntrs->RxP1HdrEgrOvflCnt =
1774                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP1HdrEgrOvflCnt));
1775         cntrs->RxP2HdrEgrOvflCnt =
1776                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP2HdrEgrOvflCnt));
1777         cntrs->RxP3HdrEgrOvflCnt =
1778                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP3HdrEgrOvflCnt));
1779         cntrs->RxP4HdrEgrOvflCnt =
1780                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP4HdrEgrOvflCnt));
1781         cntrs->RxP5HdrEgrOvflCnt =
1782                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP5HdrEgrOvflCnt));
1783         cntrs->RxP6HdrEgrOvflCnt =
1784                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP6HdrEgrOvflCnt));
1785         cntrs->RxP7HdrEgrOvflCnt =
1786                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP7HdrEgrOvflCnt));
1787         cntrs->RxP8HdrEgrOvflCnt =
1788                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(RxP8HdrEgrOvflCnt));
1789         cntrs->RxP9HdrEgrOvflCnt = 0;
1790         cntrs->RxP10HdrEgrOvflCnt = 0;
1791         cntrs->RxP11HdrEgrOvflCnt = 0;
1792         cntrs->RxP12HdrEgrOvflCnt = 0;
1793         cntrs->RxP13HdrEgrOvflCnt = 0;
1794         cntrs->RxP14HdrEgrOvflCnt = 0;
1795         cntrs->RxP15HdrEgrOvflCnt = 0;
1796         cntrs->RxP16HdrEgrOvflCnt = 0;
1797         cntrs->IBStatusChangeCnt =
1798                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBStatusChangeCnt));
1799         cntrs->IBLinkErrRecoveryCnt =
1800                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkErrRecoveryCnt));
1801         cntrs->IBLinkDownedCnt =
1802                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBLinkDownedCnt));
1803         cntrs->IBSymbolErrCnt =
1804                 ipath_snap_cntr(dd, IPATH_CREG_OFFSET(IBSymbolErrCnt));
1805         cntrs->RxVL15DroppedPktCnt = 0;
1806         cntrs->RxOtherLocalPhyErrCnt = 0;
1807         cntrs->PcieRetryBufDiagQwordCnt = 0;
1808         cntrs->ExcessBufferOvflCnt = dd->ipath_overrun_thresh_errs;
1809         cntrs->LocalLinkIntegrityErrCnt =
1810                 (dd->ipath_flags & IPATH_GPIO_ERRINTRS) ?
1811                 dd->ipath_lli_errs : dd->ipath_lli_errors;
1812         cntrs->RxVlErrCnt = 0;
1813         cntrs->RxDlidFltrCnt = 0;
1814 }
1815
1816
1817 /* no interrupt fallback for these chips */
1818 static int ipath_ht_nointr_fallback(struct ipath_devdata *dd)
1819 {
1820         return 0;
1821 }
1822
1823
1824 /*
1825  * reset the XGXS (between serdes and IBC).  Slightly less intrusive
1826  * than resetting the IBC or external link state, and useful in some
1827  * cases to cause some retraining.  To do this right, we reset IBC
1828  * as well.
1829  */
1830 static void ipath_ht_xgxs_reset(struct ipath_devdata *dd)
1831 {
1832         u64 val, prev_val;
1833
1834         prev_val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_xgxsconfig);
1835         val = prev_val | INFINIPATH_XGXS_RESET;
1836         prev_val &= ~INFINIPATH_XGXS_RESET; /* be sure */
1837         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1838                          dd->ipath_control & ~INFINIPATH_C_LINKENABLE);
1839         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, val);
1840         ipath_read_kreg32(dd, dd->ipath_kregs->kr_scratch);
1841         ipath_write_kreg(dd, dd->ipath_kregs->kr_xgxsconfig, prev_val);
1842         ipath_write_kreg(dd, dd->ipath_kregs->kr_control,
1843                          dd->ipath_control);
1844 }
1845
1846
1847 static int ipath_ht_get_ib_cfg(struct ipath_devdata *dd, int which)
1848 {
1849         int ret;
1850
1851         switch (which) {
1852         case IPATH_IB_CFG_LWID:
1853                 ret = dd->ipath_link_width_active;
1854                 break;
1855         case IPATH_IB_CFG_SPD:
1856                 ret = dd->ipath_link_speed_active;
1857                 break;
1858         case IPATH_IB_CFG_LWID_ENB:
1859                 ret = dd->ipath_link_width_enabled;
1860                 break;
1861         case IPATH_IB_CFG_SPD_ENB:
1862                 ret = dd->ipath_link_speed_enabled;
1863                 break;
1864         default:
1865                 ret =  -ENOTSUPP;
1866                 break;
1867         }
1868         return ret;
1869 }
1870
1871
1872 /* we assume range checking is already done, if needed */
1873 static int ipath_ht_set_ib_cfg(struct ipath_devdata *dd, int which, u32 val)
1874 {
1875         int ret = 0;
1876
1877         if (which == IPATH_IB_CFG_LWID_ENB)
1878                 dd->ipath_link_width_enabled = val;
1879         else if (which == IPATH_IB_CFG_SPD_ENB)
1880                 dd->ipath_link_speed_enabled = val;
1881         else
1882                 ret = -ENOTSUPP;
1883         return ret;
1884 }
1885
1886
1887 static void ipath_ht_config_jint(struct ipath_devdata *dd, u16 a, u16 b)
1888 {
1889 }
1890
1891
1892 static int ipath_ht_ib_updown(struct ipath_devdata *dd, int ibup, u64 ibcs)
1893 {
1894         ipath_setup_ht_setextled(dd, ipath_ib_linkstate(dd, ibcs),
1895                 ipath_ib_linktrstate(dd, ibcs));
1896         return 0;
1897 }
1898
1899
1900 /**
1901  * ipath_init_iba6110_funcs - set up the chip-specific function pointers
1902  * @dd: the infinipath device
1903  *
1904  * This is global, and is called directly at init to set up the
1905  * chip-specific function pointers for later use.
1906  */
1907 void ipath_init_iba6110_funcs(struct ipath_devdata *dd)
1908 {
1909         dd->ipath_f_intrsetup = ipath_ht_intconfig;
1910         dd->ipath_f_bus = ipath_setup_ht_config;
1911         dd->ipath_f_reset = ipath_setup_ht_reset;
1912         dd->ipath_f_get_boardname = ipath_ht_boardname;
1913         dd->ipath_f_init_hwerrors = ipath_ht_init_hwerrors;
1914         dd->ipath_f_early_init = ipath_ht_early_init;
1915         dd->ipath_f_handle_hwerrors = ipath_ht_handle_hwerrors;
1916         dd->ipath_f_quiet_serdes = ipath_ht_quiet_serdes;
1917         dd->ipath_f_bringup_serdes = ipath_ht_bringup_serdes;
1918         dd->ipath_f_clear_tids = ipath_ht_clear_tids;
1919         dd->ipath_f_put_tid = ipath_ht_put_tid;
1920         dd->ipath_f_cleanup = ipath_setup_ht_cleanup;
1921         dd->ipath_f_setextled = ipath_setup_ht_setextled;
1922         dd->ipath_f_get_base_info = ipath_ht_get_base_info;
1923         dd->ipath_f_free_irq = ipath_ht_free_irq;
1924         dd->ipath_f_tidtemplate = ipath_ht_tidtemplate;
1925         dd->ipath_f_intr_fallback = ipath_ht_nointr_fallback;
1926         dd->ipath_f_get_msgheader = ipath_ht_get_msgheader;
1927         dd->ipath_f_config_ports = ipath_ht_config_ports;
1928         dd->ipath_f_read_counters = ipath_ht_read_counters;
1929         dd->ipath_f_xgxs_reset = ipath_ht_xgxs_reset;
1930         dd->ipath_f_get_ib_cfg = ipath_ht_get_ib_cfg;
1931         dd->ipath_f_set_ib_cfg = ipath_ht_set_ib_cfg;
1932         dd->ipath_f_config_jint = ipath_ht_config_jint;
1933         dd->ipath_f_ib_updown = ipath_ht_ib_updown;
1934
1935         /*
1936          * initialize chip-specific variables
1937          */
1938         ipath_init_ht_variables(dd);
1939 }