2 * IBM eServer eHCA Infiniband device driver for Linux on POWER
6 * Authors: Joachim Fenkes <fenkes@de.ibm.com>
7 * Stefan Roscher <stefan.roscher@de.ibm.com>
8 * Waleri Fomin <fomin@de.ibm.com>
9 * Hoang-Nam Nguyen <hnguyen@de.ibm.com>
10 * Reinhard Ernst <rernst@de.ibm.com>
11 * Heiko J Schick <schickhj@de.ibm.com>
13 * Copyright (c) 2005 IBM Corporation
15 * All rights reserved.
17 * This source code is distributed under a dual license of GPL v2.0 and OpenIB
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions are met:
25 * Redistributions of source code must retain the above copyright notice, this
26 * list of conditions and the following disclaimer.
28 * Redistributions in binary form must reproduce the above copyright notice,
29 * this list of conditions and the following disclaimer in the documentation
30 * and/or other materials
31 * provided with the distribution.
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
34 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
36 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
37 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
38 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
39 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
41 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGE.
47 #include <asm/current.h>
49 #include "ehca_classes.h"
50 #include "ehca_tools.h"
52 #include "ehca_iverbs.h"
56 static struct kmem_cache *qp_cache;
59 * attributes not supported by query qp
61 #define QP_ATTR_QUERY_NOT_SUPPORTED (IB_QP_MAX_DEST_RD_ATOMIC | \
62 IB_QP_MAX_QP_RD_ATOMIC | \
63 IB_QP_ACCESS_FLAGS | \
64 IB_QP_EN_SQD_ASYNC_NOTIFY)
67 * ehca (internal) qp state values
80 * qp state transitions as defined by IB Arch Rel 1.1 page 431
82 enum ib_qp_statetrans {
94 IB_QPST_MAX /* nr of transitions, this must be last!!! */
98 * ib2ehca_qp_state maps IB to ehca qp_state
99 * returns ehca qp state corresponding to given ib qp state
101 static inline enum ehca_qp_state ib2ehca_qp_state(enum ib_qp_state ib_qp_state)
103 switch (ib_qp_state) {
105 return EHCA_QPS_RESET;
107 return EHCA_QPS_INIT;
119 ehca_gen_err("invalid ib_qp_state=%x", ib_qp_state);
125 * ehca2ib_qp_state maps ehca to IB qp_state
126 * returns ib qp state corresponding to given ehca qp state
128 static inline enum ib_qp_state ehca2ib_qp_state(enum ehca_qp_state
131 switch (ehca_qp_state) {
147 ehca_gen_err("invalid ehca_qp_state=%x", ehca_qp_state);
153 * ehca_qp_type used as index for req_attr and opt_attr of
154 * struct ehca_modqp_statetrans
165 * ib2ehcaqptype maps Ib to ehca qp_type
166 * returns ehca qp type corresponding to ib qp type
168 static inline enum ehca_qp_type ib2ehcaqptype(enum ib_qp_type ibqptype)
181 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
186 static inline enum ib_qp_statetrans get_modqp_statetrans(int ib_fromstate,
190 switch (ib_tostate) {
192 index = IB_QPST_ANY2RESET;
195 switch (ib_fromstate) {
197 index = IB_QPST_RESET2INIT;
200 index = IB_QPST_INIT2INIT;
205 if (ib_fromstate == IB_QPS_INIT)
206 index = IB_QPST_INIT2RTR;
209 switch (ib_fromstate) {
211 index = IB_QPST_RTR2RTS;
214 index = IB_QPST_RTS2RTS;
217 index = IB_QPST_SQD2RTS;
220 index = IB_QPST_SQE2RTS;
225 if (ib_fromstate == IB_QPS_RTS)
226 index = IB_QPST_RTS2SQD;
231 index = IB_QPST_ANY2ERR;
240 * ibqptype2servicetype returns hcp service type corresponding to given
241 * ib qp type used by create_qp()
243 static inline int ibqptype2servicetype(enum ib_qp_type ibqptype)
255 case IB_QPT_RAW_IPV6:
260 ehca_gen_err("Invalid ibqptype=%x", ibqptype);
266 * init userspace queue info from ipz_queue data
268 static inline void queue2resp(struct ipzu_queue_resp *resp,
269 struct ipz_queue *queue)
271 resp->qe_size = queue->qe_size;
272 resp->act_nr_of_sg = queue->act_nr_of_sg;
273 resp->queue_length = queue->queue_length;
274 resp->pagesize = queue->pagesize;
275 resp->toggle_state = queue->toggle_state;
276 resp->offset = queue->offset;
280 * init_qp_queue initializes/constructs r/squeue and registers queue pages.
282 static inline int init_qp_queue(struct ehca_shca *shca,
284 struct ehca_qp *my_qp,
285 struct ipz_queue *queue,
288 struct ehca_alloc_queue_parms *parms,
291 int ret, cnt, ipz_rc, nr_q_pages;
294 struct ib_device *ib_dev = &shca->ib_device;
295 struct ipz_adapter_handle ipz_hca_handle = shca->ipz_hca_handle;
297 if (!parms->queue_size)
300 if (parms->is_small) {
302 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
303 128 << parms->page_size,
304 wqe_size, parms->act_nr_sges, 1);
306 nr_q_pages = parms->queue_size;
307 ipz_rc = ipz_queue_ctor(pd, queue, nr_q_pages,
308 EHCA_PAGESIZE, wqe_size,
309 parms->act_nr_sges, 0);
313 ehca_err(ib_dev, "Cannot allocate page for queue. ipz_rc=%x",
318 /* register queue pages */
319 for (cnt = 0; cnt < nr_q_pages; cnt++) {
320 vpage = ipz_qpageit_get_inc(queue);
322 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
323 "failed p_vpage= %p", vpage);
327 rpage = virt_to_abs(vpage);
329 h_ret = hipz_h_register_rpage_qp(ipz_hca_handle,
330 my_qp->ipz_qp_handle,
332 rpage, parms->is_small ? 0 : 1,
333 my_qp->galpas.kernel);
334 if (cnt == (nr_q_pages - 1)) { /* last page! */
335 if (h_ret != expected_hret) {
336 ehca_err(ib_dev, "hipz_qp_register_rpage() "
337 "h_ret= %lx ", h_ret);
338 ret = ehca2ib_return_code(h_ret);
341 vpage = ipz_qpageit_get_inc(&my_qp->ipz_rqueue);
343 ehca_err(ib_dev, "ipz_qpageit_get_inc() "
344 "should not succeed vpage=%p", vpage);
349 if (h_ret != H_PAGE_REGISTERED) {
350 ehca_err(ib_dev, "hipz_qp_register_rpage() "
351 "h_ret= %lx ", h_ret);
352 ret = ehca2ib_return_code(h_ret);
358 ipz_qeit_reset(queue);
363 ipz_queue_dtor(pd, queue);
367 static inline int ehca_calc_wqe_size(int act_nr_sge, int is_llqp)
370 return 128 << act_nr_sge;
372 return offsetof(struct ehca_wqe,
373 u.nud.sg_list[act_nr_sge]);
376 static void ehca_determine_small_queue(struct ehca_alloc_queue_parms *queue,
377 int req_nr_sge, int is_llqp)
379 u32 wqe_size, q_size;
380 int act_nr_sge = req_nr_sge;
383 /* round up #SGEs so WQE size is a power of 2 */
384 for (act_nr_sge = 4; act_nr_sge <= 252;
385 act_nr_sge = 4 + 2 * act_nr_sge)
386 if (act_nr_sge >= req_nr_sge)
389 wqe_size = ehca_calc_wqe_size(act_nr_sge, is_llqp);
390 q_size = wqe_size * (queue->max_wr + 1);
393 queue->page_size = 2;
394 else if (q_size <= 1024)
395 queue->page_size = 3;
397 queue->page_size = 0;
399 queue->is_small = (queue->page_size != 0);
403 * Create an ib_qp struct that is either a QP or an SRQ, depending on
404 * the value of the is_srq parameter. If init_attr and srq_init_attr share
405 * fields, the field out of init_attr is used.
407 static struct ehca_qp *internal_create_qp(
409 struct ib_qp_init_attr *init_attr,
410 struct ib_srq_init_attr *srq_init_attr,
411 struct ib_udata *udata, int is_srq)
413 struct ehca_qp *my_qp;
414 struct ehca_pd *my_pd = container_of(pd, struct ehca_pd, ib_pd);
415 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
417 struct ib_ucontext *context = NULL;
419 int is_llqp = 0, has_srq = 0;
420 int qp_type, max_send_sge, max_recv_sge, ret;
422 /* h_call's out parameters */
423 struct ehca_alloc_qp_parms parms;
424 u32 swqe_size = 0, rwqe_size = 0, ib_qp_num;
427 memset(&parms, 0, sizeof(parms));
428 qp_type = init_attr->qp_type;
430 if (init_attr->sq_sig_type != IB_SIGNAL_REQ_WR &&
431 init_attr->sq_sig_type != IB_SIGNAL_ALL_WR) {
432 ehca_err(pd->device, "init_attr->sg_sig_type=%x not allowed",
433 init_attr->sq_sig_type);
434 return ERR_PTR(-EINVAL);
438 if (qp_type & 0x80) {
440 parms.ext_type = EQPT_LLQP;
441 parms.ll_comp_flags = qp_type & LLQP_COMP_MASK;
444 init_attr->qp_type &= 0x1F;
446 /* handle SRQ base QPs */
447 if (init_attr->srq) {
448 struct ehca_qp *my_srq =
449 container_of(init_attr->srq, struct ehca_qp, ib_srq);
452 parms.ext_type = EQPT_SRQBASE;
453 parms.srq_qpn = my_srq->real_qp_num;
454 parms.srq_token = my_srq->token;
457 if (is_llqp && has_srq) {
458 ehca_err(pd->device, "LLQPs can't have an SRQ");
459 return ERR_PTR(-EINVAL);
464 parms.ext_type = EQPT_SRQ;
465 parms.srq_limit = srq_init_attr->attr.srq_limit;
466 if (init_attr->cap.max_recv_sge > 3) {
467 ehca_err(pd->device, "no more than three SGEs "
468 "supported for SRQ pd=%p max_sge=%x",
469 pd, init_attr->cap.max_recv_sge);
470 return ERR_PTR(-EINVAL);
475 if (qp_type != IB_QPT_UD &&
476 qp_type != IB_QPT_UC &&
477 qp_type != IB_QPT_RC &&
478 qp_type != IB_QPT_SMI &&
479 qp_type != IB_QPT_GSI) {
480 ehca_err(pd->device, "wrong QP Type=%x", qp_type);
481 return ERR_PTR(-EINVAL);
487 if ((init_attr->cap.max_send_wr > 255) ||
488 (init_attr->cap.max_recv_wr > 255)) {
490 "Invalid Number of max_sq_wr=%x "
491 "or max_rq_wr=%x for RC LLQP",
492 init_attr->cap.max_send_wr,
493 init_attr->cap.max_recv_wr);
494 return ERR_PTR(-EINVAL);
498 if (!EHCA_BMASK_GET(HCA_CAP_UD_LL_QP, shca->hca_cap)) {
499 ehca_err(pd->device, "UD LLQP not supported "
501 return ERR_PTR(-ENOSYS);
503 if (!(init_attr->cap.max_send_sge <= 5
504 && init_attr->cap.max_send_sge >= 1
505 && init_attr->cap.max_recv_sge <= 5
506 && init_attr->cap.max_recv_sge >= 1)) {
508 "Invalid Number of max_send_sge=%x "
509 "or max_recv_sge=%x for UD LLQP",
510 init_attr->cap.max_send_sge,
511 init_attr->cap.max_recv_sge);
512 return ERR_PTR(-EINVAL);
513 } else if (init_attr->cap.max_send_wr > 255) {
516 "ax_send_wr=%x for UD QP_TYPE=%x",
517 init_attr->cap.max_send_wr, qp_type);
518 return ERR_PTR(-EINVAL);
522 ehca_err(pd->device, "unsupported LL QP Type=%x",
524 return ERR_PTR(-EINVAL);
529 if (pd->uobject && udata)
530 context = pd->uobject->context;
532 my_qp = kmem_cache_zalloc(qp_cache, GFP_KERNEL);
534 ehca_err(pd->device, "pd=%p not enough memory to alloc qp", pd);
535 return ERR_PTR(-ENOMEM);
538 spin_lock_init(&my_qp->spinlock_s);
539 spin_lock_init(&my_qp->spinlock_r);
540 my_qp->qp_type = qp_type;
541 my_qp->ext_type = parms.ext_type;
543 if (init_attr->recv_cq)
545 container_of(init_attr->recv_cq, struct ehca_cq, ib_cq);
546 if (init_attr->send_cq)
548 container_of(init_attr->send_cq, struct ehca_cq, ib_cq);
551 if (!idr_pre_get(&ehca_qp_idr, GFP_KERNEL)) {
553 ehca_err(pd->device, "Can't reserve idr resources.");
554 goto create_qp_exit0;
557 write_lock_irqsave(&ehca_qp_idr_lock, flags);
558 ret = idr_get_new(&ehca_qp_idr, my_qp, &my_qp->token);
559 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
560 } while (ret == -EAGAIN);
564 ehca_err(pd->device, "Can't allocate new idr entry.");
565 goto create_qp_exit0;
568 if (my_qp->token > 0x1FFFFFF) {
570 ehca_err(pd->device, "Invalid number of qp");
571 goto create_qp_exit1;
574 parms.servicetype = ibqptype2servicetype(qp_type);
575 if (parms.servicetype < 0) {
577 ehca_err(pd->device, "Invalid qp_type=%x", qp_type);
578 goto create_qp_exit1;
581 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
582 parms.sigtype = HCALL_SIGT_EVERY;
584 parms.sigtype = HCALL_SIGT_BY_WQE;
586 /* UD_AV CIRCUMVENTION */
587 max_send_sge = init_attr->cap.max_send_sge;
588 max_recv_sge = init_attr->cap.max_recv_sge;
589 if (parms.servicetype == ST_UD && !is_llqp) {
594 parms.token = my_qp->token;
595 parms.eq_handle = shca->eq.ipz_eq_handle;
596 parms.pd = my_pd->fw_pd;
598 parms.send_cq_handle = my_qp->send_cq->ipz_cq_handle;
600 parms.recv_cq_handle = my_qp->recv_cq->ipz_cq_handle;
602 parms.squeue.max_wr = init_attr->cap.max_send_wr;
603 parms.rqueue.max_wr = init_attr->cap.max_recv_wr;
604 parms.squeue.max_sge = max_send_sge;
605 parms.rqueue.max_sge = max_recv_sge;
607 if (EHCA_BMASK_GET(HCA_CAP_MINI_QP, shca->hca_cap)) {
609 ehca_determine_small_queue(
610 &parms.squeue, max_send_sge, is_llqp);
612 ehca_determine_small_queue(
613 &parms.rqueue, max_recv_sge, is_llqp);
615 (parms.squeue.is_small || parms.rqueue.is_small);
618 h_ret = hipz_h_alloc_resource_qp(shca->ipz_hca_handle, &parms);
619 if (h_ret != H_SUCCESS) {
620 ehca_err(pd->device, "h_alloc_resource_qp() failed h_ret=%lx",
622 ret = ehca2ib_return_code(h_ret);
623 goto create_qp_exit1;
626 ib_qp_num = my_qp->real_qp_num = parms.real_qp_num;
627 my_qp->ipz_qp_handle = parms.qp_handle;
628 my_qp->galpas = parms.galpas;
630 swqe_size = ehca_calc_wqe_size(parms.squeue.act_nr_sges, is_llqp);
631 rwqe_size = ehca_calc_wqe_size(parms.rqueue.act_nr_sges, is_llqp);
636 parms.squeue.act_nr_sges = 1;
637 parms.rqueue.act_nr_sges = 1;
643 /* UD circumvention */
645 parms.squeue.act_nr_sges = 1;
646 parms.rqueue.act_nr_sges = 1;
648 parms.squeue.act_nr_sges -= 2;
649 parms.rqueue.act_nr_sges -= 2;
652 if (IB_QPT_GSI == qp_type || IB_QPT_SMI == qp_type) {
653 parms.squeue.act_nr_wqes = init_attr->cap.max_send_wr;
654 parms.rqueue.act_nr_wqes = init_attr->cap.max_recv_wr;
655 parms.squeue.act_nr_sges = init_attr->cap.max_send_sge;
656 parms.rqueue.act_nr_sges = init_attr->cap.max_recv_sge;
657 ib_qp_num = (qp_type == IB_QPT_SMI) ? 0 : 1;
666 /* initialize r/squeue and register queue pages */
669 shca, my_pd, my_qp, &my_qp->ipz_squeue, 0,
670 HAS_RQ(my_qp) ? H_PAGE_REGISTERED : H_SUCCESS,
671 &parms.squeue, swqe_size);
673 ehca_err(pd->device, "Couldn't initialize squeue "
674 "and pages ret=%x", ret);
675 goto create_qp_exit2;
681 shca, my_pd, my_qp, &my_qp->ipz_rqueue, 1,
682 H_SUCCESS, &parms.rqueue, rwqe_size);
684 ehca_err(pd->device, "Couldn't initialize rqueue "
685 "and pages ret=%x", ret);
686 goto create_qp_exit3;
691 my_qp->ib_srq.pd = &my_pd->ib_pd;
692 my_qp->ib_srq.device = my_pd->ib_pd.device;
694 my_qp->ib_srq.srq_context = init_attr->qp_context;
695 my_qp->ib_srq.event_handler = init_attr->event_handler;
697 my_qp->ib_qp.qp_num = ib_qp_num;
698 my_qp->ib_qp.pd = &my_pd->ib_pd;
699 my_qp->ib_qp.device = my_pd->ib_pd.device;
701 my_qp->ib_qp.recv_cq = init_attr->recv_cq;
702 my_qp->ib_qp.send_cq = init_attr->send_cq;
704 my_qp->ib_qp.qp_type = qp_type;
705 my_qp->ib_qp.srq = init_attr->srq;
707 my_qp->ib_qp.qp_context = init_attr->qp_context;
708 my_qp->ib_qp.event_handler = init_attr->event_handler;
711 init_attr->cap.max_inline_data = 0; /* not supported yet */
712 init_attr->cap.max_recv_sge = parms.rqueue.act_nr_sges;
713 init_attr->cap.max_recv_wr = parms.rqueue.act_nr_wqes;
714 init_attr->cap.max_send_sge = parms.squeue.act_nr_sges;
715 init_attr->cap.max_send_wr = parms.squeue.act_nr_wqes;
716 my_qp->init_attr = *init_attr;
718 /* NOTE: define_apq0() not supported yet */
719 if (qp_type == IB_QPT_GSI) {
720 h_ret = ehca_define_sqp(shca, my_qp, init_attr);
721 if (h_ret != H_SUCCESS) {
722 ret = ehca2ib_return_code(h_ret);
723 goto create_qp_exit4;
727 if (my_qp->send_cq) {
728 ret = ehca_cq_assign_qp(my_qp->send_cq, my_qp);
731 "Couldn't assign qp to send_cq ret=%x", ret);
732 goto create_qp_exit4;
736 /* copy queues, galpa data to user space */
737 if (context && udata) {
738 struct ehca_create_qp_resp resp;
739 memset(&resp, 0, sizeof(resp));
741 resp.qp_num = my_qp->real_qp_num;
742 resp.token = my_qp->token;
743 resp.qp_type = my_qp->qp_type;
744 resp.ext_type = my_qp->ext_type;
745 resp.qkey = my_qp->qkey;
746 resp.real_qp_num = my_qp->real_qp_num;
749 queue2resp(&resp.ipz_squeue, &my_qp->ipz_squeue);
751 queue2resp(&resp.ipz_rqueue, &my_qp->ipz_rqueue);
752 resp.fw_handle_ofs = (u32)
753 (my_qp->galpas.user.fw_handle & (PAGE_SIZE - 1));
755 if (ib_copy_to_udata(udata, &resp, sizeof resp)) {
756 ehca_err(pd->device, "Copy to udata failed");
758 goto create_qp_exit4;
766 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
770 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
773 hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
776 write_lock_irqsave(&ehca_qp_idr_lock, flags);
777 idr_remove(&ehca_qp_idr, my_qp->token);
778 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
781 kmem_cache_free(qp_cache, my_qp);
785 struct ib_qp *ehca_create_qp(struct ib_pd *pd,
786 struct ib_qp_init_attr *qp_init_attr,
787 struct ib_udata *udata)
791 ret = internal_create_qp(pd, qp_init_attr, NULL, udata, 0);
792 return IS_ERR(ret) ? (struct ib_qp *)ret : &ret->ib_qp;
795 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
796 struct ib_uobject *uobject);
798 struct ib_srq *ehca_create_srq(struct ib_pd *pd,
799 struct ib_srq_init_attr *srq_init_attr,
800 struct ib_udata *udata)
802 struct ib_qp_init_attr qp_init_attr;
803 struct ehca_qp *my_qp;
805 struct ehca_shca *shca = container_of(pd->device, struct ehca_shca,
807 struct hcp_modify_qp_control_block *mqpcb;
808 u64 hret, update_mask;
810 /* For common attributes, internal_create_qp() takes its info
811 * out of qp_init_attr, so copy all common attrs there.
813 memset(&qp_init_attr, 0, sizeof(qp_init_attr));
814 qp_init_attr.event_handler = srq_init_attr->event_handler;
815 qp_init_attr.qp_context = srq_init_attr->srq_context;
816 qp_init_attr.sq_sig_type = IB_SIGNAL_ALL_WR;
817 qp_init_attr.qp_type = IB_QPT_RC;
818 qp_init_attr.cap.max_recv_wr = srq_init_attr->attr.max_wr;
819 qp_init_attr.cap.max_recv_sge = srq_init_attr->attr.max_sge;
821 my_qp = internal_create_qp(pd, &qp_init_attr, srq_init_attr, udata, 1);
823 return (struct ib_srq *)my_qp;
825 /* copy back return values */
826 srq_init_attr->attr.max_wr = qp_init_attr.cap.max_recv_wr;
827 srq_init_attr->attr.max_sge = qp_init_attr.cap.max_recv_sge;
829 /* drive SRQ into RTR state */
830 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
832 ehca_err(pd->device, "Could not get zeroed page for mqpcb "
833 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
834 ret = ERR_PTR(-ENOMEM);
838 mqpcb->qp_state = EHCA_QPS_INIT;
839 mqpcb->prim_phys_port = 1;
840 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
841 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
842 my_qp->ipz_qp_handle,
845 mqpcb, my_qp->galpas.kernel);
846 if (hret != H_SUCCESS) {
847 ehca_err(pd->device, "Could not modify SRQ to INIT"
848 "ehca_qp=%p qp_num=%x hret=%lx",
849 my_qp, my_qp->real_qp_num, hret);
853 mqpcb->qp_enable = 1;
854 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
855 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
856 my_qp->ipz_qp_handle,
859 mqpcb, my_qp->galpas.kernel);
860 if (hret != H_SUCCESS) {
861 ehca_err(pd->device, "Could not enable SRQ"
862 "ehca_qp=%p qp_num=%x hret=%lx",
863 my_qp, my_qp->real_qp_num, hret);
867 mqpcb->qp_state = EHCA_QPS_RTR;
868 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
869 hret = hipz_h_modify_qp(shca->ipz_hca_handle,
870 my_qp->ipz_qp_handle,
873 mqpcb, my_qp->galpas.kernel);
874 if (hret != H_SUCCESS) {
875 ehca_err(pd->device, "Could not modify SRQ to RTR"
876 "ehca_qp=%p qp_num=%x hret=%lx",
877 my_qp, my_qp->real_qp_num, hret);
881 return &my_qp->ib_srq;
884 ret = ERR_PTR(ehca2ib_return_code(hret));
885 ehca_free_fw_ctrlblock(mqpcb);
888 internal_destroy_qp(pd->device, my_qp, my_qp->ib_srq.uobject);
894 * prepare_sqe_rts called by internal_modify_qp() at trans sqe -> rts
895 * set purge bit of bad wqe and subsequent wqes to avoid reentering sqe
896 * returns total number of bad wqes in bad_wqe_cnt
898 static int prepare_sqe_rts(struct ehca_qp *my_qp, struct ehca_shca *shca,
902 struct ipz_queue *squeue;
903 void *bad_send_wqe_p, *bad_send_wqe_v;
905 struct ehca_wqe *wqe;
906 int qp_num = my_qp->ib_qp.qp_num;
908 /* get send wqe pointer */
909 h_ret = hipz_h_disable_and_get_wqe(shca->ipz_hca_handle,
910 my_qp->ipz_qp_handle, &my_qp->pf,
911 &bad_send_wqe_p, NULL, 2);
912 if (h_ret != H_SUCCESS) {
913 ehca_err(&shca->ib_device, "hipz_h_disable_and_get_wqe() failed"
914 " ehca_qp=%p qp_num=%x h_ret=%lx",
915 my_qp, qp_num, h_ret);
916 return ehca2ib_return_code(h_ret);
918 bad_send_wqe_p = (void *)((u64)bad_send_wqe_p & (~(1L << 63)));
919 ehca_dbg(&shca->ib_device, "qp_num=%x bad_send_wqe_p=%p",
920 qp_num, bad_send_wqe_p);
921 /* convert wqe pointer to vadr */
922 bad_send_wqe_v = abs_to_virt((u64)bad_send_wqe_p);
923 if (ehca_debug_level)
924 ehca_dmp(bad_send_wqe_v, 32, "qp_num=%x bad_wqe", qp_num);
925 squeue = &my_qp->ipz_squeue;
926 if (ipz_queue_abs_to_offset(squeue, (u64)bad_send_wqe_p, &q_ofs)) {
927 ehca_err(&shca->ib_device, "failed to get wqe offset qp_num=%x"
928 " bad_send_wqe_p=%p", qp_num, bad_send_wqe_p);
932 /* loop sets wqe's purge bit */
933 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
935 while (wqe->optype != 0xff && wqe->wqef != 0xff) {
936 if (ehca_debug_level)
937 ehca_dmp(wqe, 32, "qp_num=%x wqe", qp_num);
938 wqe->nr_of_data_seg = 0; /* suppress data access */
939 wqe->wqef = WQEF_PURGE; /* WQE to be purged */
940 q_ofs = ipz_queue_advance_offset(squeue, q_ofs);
941 wqe = (struct ehca_wqe *)ipz_qeit_calc(squeue, q_ofs);
942 *bad_wqe_cnt = (*bad_wqe_cnt)+1;
945 * bad wqe will be reprocessed and ignored when pol_cq() is called,
946 * i.e. nr of wqes with flush error status is one less
948 ehca_dbg(&shca->ib_device, "qp_num=%x flusherr_wqe_cnt=%x",
949 qp_num, (*bad_wqe_cnt)-1);
956 * internal_modify_qp with circumvention to handle aqp0 properly
957 * smi_reset2init indicates if this is an internal reset-to-init-call for
958 * smi. This flag must always be zero if called from ehca_modify_qp()!
959 * This internal func was intorduced to avoid recursion of ehca_modify_qp()!
961 static int internal_modify_qp(struct ib_qp *ibqp,
962 struct ib_qp_attr *attr,
963 int attr_mask, int smi_reset2init)
965 enum ib_qp_state qp_cur_state, qp_new_state;
966 int cnt, qp_attr_idx, ret = 0;
967 enum ib_qp_statetrans statetrans;
968 struct hcp_modify_qp_control_block *mqpcb;
969 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
970 struct ehca_shca *shca =
971 container_of(ibqp->pd->device, struct ehca_shca, ib_device);
975 int squeue_locked = 0;
976 unsigned long flags = 0;
978 /* do query_qp to obtain current attr values */
979 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
981 ehca_err(ibqp->device, "Could not get zeroed page for mqpcb "
982 "ehca_qp=%p qp_num=%x ", my_qp, ibqp->qp_num);
986 h_ret = hipz_h_query_qp(shca->ipz_hca_handle,
987 my_qp->ipz_qp_handle,
989 mqpcb, my_qp->galpas.kernel);
990 if (h_ret != H_SUCCESS) {
991 ehca_err(ibqp->device, "hipz_h_query_qp() failed "
992 "ehca_qp=%p qp_num=%x h_ret=%lx",
993 my_qp, ibqp->qp_num, h_ret);
994 ret = ehca2ib_return_code(h_ret);
995 goto modify_qp_exit1;
998 qp_cur_state = ehca2ib_qp_state(mqpcb->qp_state);
1000 if (qp_cur_state == -EINVAL) { /* invalid qp state */
1002 ehca_err(ibqp->device, "Invalid current ehca_qp_state=%x "
1003 "ehca_qp=%p qp_num=%x",
1004 mqpcb->qp_state, my_qp, ibqp->qp_num);
1005 goto modify_qp_exit1;
1008 * circumvention to set aqp0 initial state to init
1009 * as expected by IB spec
1011 if (smi_reset2init == 0 &&
1012 ibqp->qp_type == IB_QPT_SMI &&
1013 qp_cur_state == IB_QPS_RESET &&
1014 (attr_mask & IB_QP_STATE) &&
1015 attr->qp_state == IB_QPS_INIT) { /* RESET -> INIT */
1016 struct ib_qp_attr smiqp_attr = {
1017 .qp_state = IB_QPS_INIT,
1018 .port_num = my_qp->init_attr.port_num,
1022 int smiqp_attr_mask = IB_QP_STATE | IB_QP_PORT |
1023 IB_QP_PKEY_INDEX | IB_QP_QKEY;
1024 int smirc = internal_modify_qp(
1025 ibqp, &smiqp_attr, smiqp_attr_mask, 1);
1027 ehca_err(ibqp->device, "SMI RESET -> INIT failed. "
1028 "ehca_modify_qp() rc=%x", smirc);
1030 goto modify_qp_exit1;
1032 qp_cur_state = IB_QPS_INIT;
1033 ehca_dbg(ibqp->device, "SMI RESET -> INIT succeeded");
1035 /* is transmitted current state equal to "real" current state */
1036 if ((attr_mask & IB_QP_CUR_STATE) &&
1037 qp_cur_state != attr->cur_qp_state) {
1039 ehca_err(ibqp->device,
1040 "Invalid IB_QP_CUR_STATE attr->curr_qp_state=%x <>"
1041 " actual cur_qp_state=%x. ehca_qp=%p qp_num=%x",
1042 attr->cur_qp_state, qp_cur_state, my_qp, ibqp->qp_num);
1043 goto modify_qp_exit1;
1046 ehca_dbg(ibqp->device, "ehca_qp=%p qp_num=%x current qp_state=%x "
1047 "new qp_state=%x attribute_mask=%x",
1048 my_qp, ibqp->qp_num, qp_cur_state, attr->qp_state, attr_mask);
1050 qp_new_state = attr_mask & IB_QP_STATE ? attr->qp_state : qp_cur_state;
1051 if (!smi_reset2init &&
1052 !ib_modify_qp_is_ok(qp_cur_state, qp_new_state, ibqp->qp_type,
1055 ehca_err(ibqp->device,
1056 "Invalid qp transition new_state=%x cur_state=%x "
1057 "ehca_qp=%p qp_num=%x attr_mask=%x", qp_new_state,
1058 qp_cur_state, my_qp, ibqp->qp_num, attr_mask);
1059 goto modify_qp_exit1;
1062 mqpcb->qp_state = ib2ehca_qp_state(qp_new_state);
1063 if (mqpcb->qp_state)
1064 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_STATE, 1);
1067 ehca_err(ibqp->device, "Invalid new qp state=%x "
1068 "ehca_qp=%p qp_num=%x",
1069 qp_new_state, my_qp, ibqp->qp_num);
1070 goto modify_qp_exit1;
1073 /* retrieve state transition struct to get req and opt attrs */
1074 statetrans = get_modqp_statetrans(qp_cur_state, qp_new_state);
1075 if (statetrans < 0) {
1077 ehca_err(ibqp->device, "<INVALID STATE CHANGE> qp_cur_state=%x "
1078 "new_qp_state=%x State_xsition=%x ehca_qp=%p "
1079 "qp_num=%x", qp_cur_state, qp_new_state,
1080 statetrans, my_qp, ibqp->qp_num);
1081 goto modify_qp_exit1;
1084 qp_attr_idx = ib2ehcaqptype(ibqp->qp_type);
1086 if (qp_attr_idx < 0) {
1088 ehca_err(ibqp->device,
1089 "Invalid QP type=%x ehca_qp=%p qp_num=%x",
1090 ibqp->qp_type, my_qp, ibqp->qp_num);
1091 goto modify_qp_exit1;
1094 ehca_dbg(ibqp->device,
1095 "ehca_qp=%p qp_num=%x <VALID STATE CHANGE> qp_state_xsit=%x",
1096 my_qp, ibqp->qp_num, statetrans);
1098 /* eHCA2 rev2 and higher require the SEND_GRH_FLAG to be set
1101 if ((my_qp->qp_type == IB_QPT_UD) &&
1102 (my_qp->ext_type != EQPT_LLQP) &&
1103 (statetrans == IB_QPST_INIT2RTR) &&
1104 (shca->hw_level >= 0x22)) {
1105 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1106 mqpcb->send_grh_flag = 1;
1109 /* sqe -> rts: set purge bit of bad wqe before actual trans */
1110 if ((my_qp->qp_type == IB_QPT_UD ||
1111 my_qp->qp_type == IB_QPT_GSI ||
1112 my_qp->qp_type == IB_QPT_SMI) &&
1113 statetrans == IB_QPST_SQE2RTS) {
1114 /* mark next free wqe if kernel */
1115 if (!ibqp->uobject) {
1116 struct ehca_wqe *wqe;
1117 /* lock send queue */
1118 spin_lock_irqsave(&my_qp->spinlock_s, flags);
1120 /* mark next free wqe */
1121 wqe = (struct ehca_wqe *)
1122 ipz_qeit_get(&my_qp->ipz_squeue);
1123 wqe->optype = wqe->wqef = 0xff;
1124 ehca_dbg(ibqp->device, "qp_num=%x next_free_wqe=%p",
1127 ret = prepare_sqe_rts(my_qp, shca, &bad_wqe_cnt);
1129 ehca_err(ibqp->device, "prepare_sqe_rts() failed "
1130 "ehca_qp=%p qp_num=%x ret=%x",
1131 my_qp, ibqp->qp_num, ret);
1132 goto modify_qp_exit2;
1137 * enable RDMA_Atomic_Control if reset->init und reliable con
1138 * this is necessary since gen2 does not provide that flag,
1139 * but pHyp requires it
1141 if (statetrans == IB_QPST_RESET2INIT &&
1142 (ibqp->qp_type == IB_QPT_RC || ibqp->qp_type == IB_QPT_UC)) {
1143 mqpcb->rdma_atomic_ctrl = 3;
1144 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RDMA_ATOMIC_CTRL, 1);
1146 /* circ. pHyp requires #RDMA/Atomic Resp Res for UC INIT -> RTR */
1147 if (statetrans == IB_QPST_INIT2RTR &&
1148 (ibqp->qp_type == IB_QPT_UC) &&
1149 !(attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)) {
1150 mqpcb->rdma_nr_atomic_resp_res = 1; /* default to 1 */
1152 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1155 if (attr_mask & IB_QP_PKEY_INDEX) {
1156 mqpcb->prim_p_key_idx = attr->pkey_index;
1157 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_P_KEY_IDX, 1);
1159 if (attr_mask & IB_QP_PORT) {
1160 if (attr->port_num < 1 || attr->port_num > shca->num_ports) {
1162 ehca_err(ibqp->device, "Invalid port=%x. "
1163 "ehca_qp=%p qp_num=%x num_ports=%x",
1164 attr->port_num, my_qp, ibqp->qp_num,
1166 goto modify_qp_exit2;
1168 mqpcb->prim_phys_port = attr->port_num;
1169 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PRIM_PHYS_PORT, 1);
1171 if (attr_mask & IB_QP_QKEY) {
1172 mqpcb->qkey = attr->qkey;
1173 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_QKEY, 1);
1175 if (attr_mask & IB_QP_AV) {
1176 int ah_mult = ib_rate_to_mult(attr->ah_attr.static_rate);
1177 int ehca_mult = ib_rate_to_mult(shca->sport[my_qp->
1178 init_attr.port_num].rate);
1180 mqpcb->dlid = attr->ah_attr.dlid;
1181 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID, 1);
1182 mqpcb->source_path_bits = attr->ah_attr.src_path_bits;
1183 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS, 1);
1184 mqpcb->service_level = attr->ah_attr.sl;
1185 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL, 1);
1187 if (ah_mult < ehca_mult)
1188 mqpcb->max_static_rate = (ah_mult > 0) ?
1189 ((ehca_mult - 1) / ah_mult) : 0;
1191 mqpcb->max_static_rate = 0;
1192 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE, 1);
1195 * Always supply the GRH flag, even if it's zero, to give the
1196 * hypervisor a clear "yes" or "no" instead of a "perhaps"
1198 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG, 1);
1201 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1202 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1204 if (attr->ah_attr.ah_flags == IB_AH_GRH) {
1205 mqpcb->send_grh_flag = 1;
1207 mqpcb->source_gid_idx = attr->ah_attr.grh.sgid_index;
1209 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX, 1);
1211 for (cnt = 0; cnt < 16; cnt++)
1212 mqpcb->dest_gid.byte[cnt] =
1213 attr->ah_attr.grh.dgid.raw[cnt];
1215 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_GID, 1);
1216 mqpcb->flow_label = attr->ah_attr.grh.flow_label;
1217 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL, 1);
1218 mqpcb->hop_limit = attr->ah_attr.grh.hop_limit;
1219 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT, 1);
1220 mqpcb->traffic_class = attr->ah_attr.grh.traffic_class;
1222 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS, 1);
1226 if (attr_mask & IB_QP_PATH_MTU) {
1227 mqpcb->path_mtu = attr->path_mtu;
1228 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_PATH_MTU, 1);
1230 if (attr_mask & IB_QP_TIMEOUT) {
1231 mqpcb->timeout = attr->timeout;
1232 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_TIMEOUT, 1);
1234 if (attr_mask & IB_QP_RETRY_CNT) {
1235 mqpcb->retry_count = attr->retry_cnt;
1236 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RETRY_COUNT, 1);
1238 if (attr_mask & IB_QP_RNR_RETRY) {
1239 mqpcb->rnr_retry_count = attr->rnr_retry;
1240 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RNR_RETRY_COUNT, 1);
1242 if (attr_mask & IB_QP_RQ_PSN) {
1243 mqpcb->receive_psn = attr->rq_psn;
1244 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_RECEIVE_PSN, 1);
1246 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
1247 mqpcb->rdma_nr_atomic_resp_res = attr->max_dest_rd_atomic < 3 ?
1248 attr->max_dest_rd_atomic : 2;
1250 EHCA_BMASK_SET(MQPCB_MASK_RDMA_NR_ATOMIC_RESP_RES, 1);
1252 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
1253 mqpcb->rdma_atomic_outst_dest_qp = attr->max_rd_atomic < 3 ?
1254 attr->max_rd_atomic : 2;
1257 (MQPCB_MASK_RDMA_ATOMIC_OUTST_DEST_QP, 1);
1259 if (attr_mask & IB_QP_ALT_PATH) {
1260 int ah_mult = ib_rate_to_mult(attr->alt_ah_attr.static_rate);
1261 int ehca_mult = ib_rate_to_mult(
1262 shca->sport[my_qp->init_attr.port_num].rate);
1264 mqpcb->dlid_al = attr->alt_ah_attr.dlid;
1265 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DLID_AL, 1);
1266 mqpcb->source_path_bits_al = attr->alt_ah_attr.src_path_bits;
1268 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_PATH_BITS_AL, 1);
1269 mqpcb->service_level_al = attr->alt_ah_attr.sl;
1270 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SERVICE_LEVEL_AL, 1);
1272 if (ah_mult < ehca_mult)
1273 mqpcb->max_static_rate = (ah_mult > 0) ?
1274 ((ehca_mult - 1) / ah_mult) : 0;
1276 mqpcb->max_static_rate_al = 0;
1278 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_MAX_STATIC_RATE_AL, 1);
1281 * only if GRH is TRUE we might consider SOURCE_GID_IDX
1282 * and DEST_GID otherwise phype will return H_ATTR_PARM!!!
1284 if (attr->alt_ah_attr.ah_flags == IB_AH_GRH) {
1285 mqpcb->send_grh_flag_al = 1 << 31;
1287 EHCA_BMASK_SET(MQPCB_MASK_SEND_GRH_FLAG_AL, 1);
1288 mqpcb->source_gid_idx_al =
1289 attr->alt_ah_attr.grh.sgid_index;
1291 EHCA_BMASK_SET(MQPCB_MASK_SOURCE_GID_IDX_AL, 1);
1293 for (cnt = 0; cnt < 16; cnt++)
1294 mqpcb->dest_gid_al.byte[cnt] =
1295 attr->alt_ah_attr.grh.dgid.raw[cnt];
1298 EHCA_BMASK_SET(MQPCB_MASK_DEST_GID_AL, 1);
1299 mqpcb->flow_label_al = attr->alt_ah_attr.grh.flow_label;
1301 EHCA_BMASK_SET(MQPCB_MASK_FLOW_LABEL_AL, 1);
1302 mqpcb->hop_limit_al = attr->alt_ah_attr.grh.hop_limit;
1304 EHCA_BMASK_SET(MQPCB_MASK_HOP_LIMIT_AL, 1);
1305 mqpcb->traffic_class_al =
1306 attr->alt_ah_attr.grh.traffic_class;
1308 EHCA_BMASK_SET(MQPCB_MASK_TRAFFIC_CLASS_AL, 1);
1312 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
1313 mqpcb->min_rnr_nak_timer_field = attr->min_rnr_timer;
1315 EHCA_BMASK_SET(MQPCB_MASK_MIN_RNR_NAK_TIMER_FIELD, 1);
1318 if (attr_mask & IB_QP_SQ_PSN) {
1319 mqpcb->send_psn = attr->sq_psn;
1320 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_SEND_PSN, 1);
1323 if (attr_mask & IB_QP_DEST_QPN) {
1324 mqpcb->dest_qp_nr = attr->dest_qp_num;
1325 update_mask |= EHCA_BMASK_SET(MQPCB_MASK_DEST_QP_NR, 1);
1328 if (attr_mask & IB_QP_PATH_MIG_STATE) {
1329 mqpcb->path_migration_state = attr->path_mig_state;
1331 EHCA_BMASK_SET(MQPCB_MASK_PATH_MIGRATION_STATE, 1);
1334 if (attr_mask & IB_QP_CAP) {
1335 mqpcb->max_nr_outst_send_wr = attr->cap.max_send_wr+1;
1337 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_SEND_WR, 1);
1338 mqpcb->max_nr_outst_recv_wr = attr->cap.max_recv_wr+1;
1340 EHCA_BMASK_SET(MQPCB_MASK_MAX_NR_OUTST_RECV_WR, 1);
1341 /* no support for max_send/recv_sge yet */
1344 if (ehca_debug_level)
1345 ehca_dmp(mqpcb, 4*70, "qp_num=%x", ibqp->qp_num);
1347 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1348 my_qp->ipz_qp_handle,
1351 mqpcb, my_qp->galpas.kernel);
1353 if (h_ret != H_SUCCESS) {
1354 ret = ehca2ib_return_code(h_ret);
1355 ehca_err(ibqp->device, "hipz_h_modify_qp() failed rc=%lx "
1356 "ehca_qp=%p qp_num=%x", h_ret, my_qp, ibqp->qp_num);
1357 goto modify_qp_exit2;
1360 if ((my_qp->qp_type == IB_QPT_UD ||
1361 my_qp->qp_type == IB_QPT_GSI ||
1362 my_qp->qp_type == IB_QPT_SMI) &&
1363 statetrans == IB_QPST_SQE2RTS) {
1364 /* doorbell to reprocessing wqes */
1365 iosync(); /* serialize GAL register access */
1366 hipz_update_sqa(my_qp, bad_wqe_cnt-1);
1367 ehca_gen_dbg("doorbell for %x wqes", bad_wqe_cnt);
1370 if (statetrans == IB_QPST_RESET2INIT ||
1371 statetrans == IB_QPST_INIT2INIT) {
1372 mqpcb->qp_enable = 1;
1373 mqpcb->qp_state = EHCA_QPS_INIT;
1375 update_mask = EHCA_BMASK_SET(MQPCB_MASK_QP_ENABLE, 1);
1377 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle,
1378 my_qp->ipz_qp_handle,
1382 my_qp->galpas.kernel);
1384 if (h_ret != H_SUCCESS) {
1385 ret = ehca2ib_return_code(h_ret);
1386 ehca_err(ibqp->device, "ENABLE in context of "
1387 "RESET_2_INIT failed! Maybe you didn't get "
1388 "a LID h_ret=%lx ehca_qp=%p qp_num=%x",
1389 h_ret, my_qp, ibqp->qp_num);
1390 goto modify_qp_exit2;
1394 if (statetrans == IB_QPST_ANY2RESET) {
1395 ipz_qeit_reset(&my_qp->ipz_rqueue);
1396 ipz_qeit_reset(&my_qp->ipz_squeue);
1399 if (attr_mask & IB_QP_QKEY)
1400 my_qp->qkey = attr->qkey;
1403 if (squeue_locked) { /* this means: sqe -> rts */
1404 spin_unlock_irqrestore(&my_qp->spinlock_s, flags);
1405 my_qp->sqerr_purgeflag = 1;
1409 ehca_free_fw_ctrlblock(mqpcb);
1414 int ehca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
1415 struct ib_udata *udata)
1417 struct ehca_qp *my_qp = container_of(ibqp, struct ehca_qp, ib_qp);
1418 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1420 u32 cur_pid = current->tgid;
1422 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1423 my_pd->ownpid != cur_pid) {
1424 ehca_err(ibqp->pd->device, "Invalid caller pid=%x ownpid=%x",
1425 cur_pid, my_pd->ownpid);
1429 return internal_modify_qp(ibqp, attr, attr_mask, 0);
1432 int ehca_query_qp(struct ib_qp *qp,
1433 struct ib_qp_attr *qp_attr,
1434 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
1436 struct ehca_qp *my_qp = container_of(qp, struct ehca_qp, ib_qp);
1437 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1439 struct ehca_shca *shca = container_of(qp->device, struct ehca_shca,
1441 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1442 struct hcp_modify_qp_control_block *qpcb;
1443 u32 cur_pid = current->tgid;
1447 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1448 my_pd->ownpid != cur_pid) {
1449 ehca_err(qp->device, "Invalid caller pid=%x ownpid=%x",
1450 cur_pid, my_pd->ownpid);
1454 if (qp_attr_mask & QP_ATTR_QUERY_NOT_SUPPORTED) {
1455 ehca_err(qp->device, "Invalid attribute mask "
1456 "ehca_qp=%p qp_num=%x qp_attr_mask=%x ",
1457 my_qp, qp->qp_num, qp_attr_mask);
1461 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1463 ehca_err(qp->device, "Out of memory for qpcb "
1464 "ehca_qp=%p qp_num=%x", my_qp, qp->qp_num);
1468 h_ret = hipz_h_query_qp(adapter_handle,
1469 my_qp->ipz_qp_handle,
1471 qpcb, my_qp->galpas.kernel);
1473 if (h_ret != H_SUCCESS) {
1474 ret = ehca2ib_return_code(h_ret);
1475 ehca_err(qp->device, "hipz_h_query_qp() failed "
1476 "ehca_qp=%p qp_num=%x h_ret=%lx",
1477 my_qp, qp->qp_num, h_ret);
1478 goto query_qp_exit1;
1481 qp_attr->cur_qp_state = ehca2ib_qp_state(qpcb->qp_state);
1482 qp_attr->qp_state = qp_attr->cur_qp_state;
1484 if (qp_attr->cur_qp_state == -EINVAL) {
1486 ehca_err(qp->device, "Got invalid ehca_qp_state=%x "
1487 "ehca_qp=%p qp_num=%x",
1488 qpcb->qp_state, my_qp, qp->qp_num);
1489 goto query_qp_exit1;
1492 if (qp_attr->qp_state == IB_QPS_SQD)
1493 qp_attr->sq_draining = 1;
1495 qp_attr->qkey = qpcb->qkey;
1496 qp_attr->path_mtu = qpcb->path_mtu;
1497 qp_attr->path_mig_state = qpcb->path_migration_state;
1498 qp_attr->rq_psn = qpcb->receive_psn;
1499 qp_attr->sq_psn = qpcb->send_psn;
1500 qp_attr->min_rnr_timer = qpcb->min_rnr_nak_timer_field;
1501 qp_attr->cap.max_send_wr = qpcb->max_nr_outst_send_wr-1;
1502 qp_attr->cap.max_recv_wr = qpcb->max_nr_outst_recv_wr-1;
1503 /* UD_AV CIRCUMVENTION */
1504 if (my_qp->qp_type == IB_QPT_UD) {
1505 qp_attr->cap.max_send_sge =
1506 qpcb->actual_nr_sges_in_sq_wqe - 2;
1507 qp_attr->cap.max_recv_sge =
1508 qpcb->actual_nr_sges_in_rq_wqe - 2;
1510 qp_attr->cap.max_send_sge =
1511 qpcb->actual_nr_sges_in_sq_wqe;
1512 qp_attr->cap.max_recv_sge =
1513 qpcb->actual_nr_sges_in_rq_wqe;
1516 qp_attr->cap.max_inline_data = my_qp->sq_max_inline_data_size;
1517 qp_attr->dest_qp_num = qpcb->dest_qp_nr;
1519 qp_attr->pkey_index =
1520 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->prim_p_key_idx);
1523 EHCA_BMASK_GET(MQPCB_PRIM_PHYS_PORT, qpcb->prim_phys_port);
1525 qp_attr->timeout = qpcb->timeout;
1526 qp_attr->retry_cnt = qpcb->retry_count;
1527 qp_attr->rnr_retry = qpcb->rnr_retry_count;
1529 qp_attr->alt_pkey_index =
1530 EHCA_BMASK_GET(MQPCB_PRIM_P_KEY_IDX, qpcb->alt_p_key_idx);
1532 qp_attr->alt_port_num = qpcb->alt_phys_port;
1533 qp_attr->alt_timeout = qpcb->timeout_al;
1535 qp_attr->max_dest_rd_atomic = qpcb->rdma_nr_atomic_resp_res;
1536 qp_attr->max_rd_atomic = qpcb->rdma_atomic_outst_dest_qp;
1539 qp_attr->ah_attr.sl = qpcb->service_level;
1541 if (qpcb->send_grh_flag) {
1542 qp_attr->ah_attr.ah_flags = IB_AH_GRH;
1545 qp_attr->ah_attr.static_rate = qpcb->max_static_rate;
1546 qp_attr->ah_attr.dlid = qpcb->dlid;
1547 qp_attr->ah_attr.src_path_bits = qpcb->source_path_bits;
1548 qp_attr->ah_attr.port_num = qp_attr->port_num;
1551 qp_attr->ah_attr.grh.traffic_class = qpcb->traffic_class;
1552 qp_attr->ah_attr.grh.hop_limit = qpcb->hop_limit;
1553 qp_attr->ah_attr.grh.sgid_index = qpcb->source_gid_idx;
1554 qp_attr->ah_attr.grh.flow_label = qpcb->flow_label;
1556 for (cnt = 0; cnt < 16; cnt++)
1557 qp_attr->ah_attr.grh.dgid.raw[cnt] =
1558 qpcb->dest_gid.byte[cnt];
1561 qp_attr->alt_ah_attr.sl = qpcb->service_level_al;
1562 if (qpcb->send_grh_flag_al) {
1563 qp_attr->alt_ah_attr.ah_flags = IB_AH_GRH;
1566 qp_attr->alt_ah_attr.static_rate = qpcb->max_static_rate_al;
1567 qp_attr->alt_ah_attr.dlid = qpcb->dlid_al;
1568 qp_attr->alt_ah_attr.src_path_bits = qpcb->source_path_bits_al;
1571 qp_attr->alt_ah_attr.grh.traffic_class = qpcb->traffic_class_al;
1572 qp_attr->alt_ah_attr.grh.hop_limit = qpcb->hop_limit_al;
1573 qp_attr->alt_ah_attr.grh.sgid_index = qpcb->source_gid_idx_al;
1574 qp_attr->alt_ah_attr.grh.flow_label = qpcb->flow_label_al;
1576 for (cnt = 0; cnt < 16; cnt++)
1577 qp_attr->alt_ah_attr.grh.dgid.raw[cnt] =
1578 qpcb->dest_gid_al.byte[cnt];
1580 /* return init attributes given in ehca_create_qp */
1582 *qp_init_attr = my_qp->init_attr;
1584 if (ehca_debug_level)
1585 ehca_dmp(qpcb, 4*70, "qp_num=%x", qp->qp_num);
1588 ehca_free_fw_ctrlblock(qpcb);
1593 int ehca_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1594 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata)
1596 struct ehca_qp *my_qp =
1597 container_of(ibsrq, struct ehca_qp, ib_srq);
1598 struct ehca_pd *my_pd =
1599 container_of(ibsrq->pd, struct ehca_pd, ib_pd);
1600 struct ehca_shca *shca =
1601 container_of(ibsrq->pd->device, struct ehca_shca, ib_device);
1602 struct hcp_modify_qp_control_block *mqpcb;
1607 u32 cur_pid = current->tgid;
1608 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1609 my_pd->ownpid != cur_pid) {
1610 ehca_err(ibsrq->pd->device, "Invalid caller pid=%x ownpid=%x",
1611 cur_pid, my_pd->ownpid);
1615 mqpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1617 ehca_err(ibsrq->device, "Could not get zeroed page for mqpcb "
1618 "ehca_qp=%p qp_num=%x ", my_qp, my_qp->real_qp_num);
1623 if (attr_mask & IB_SRQ_LIMIT) {
1624 attr_mask &= ~IB_SRQ_LIMIT;
1626 EHCA_BMASK_SET(MQPCB_MASK_CURR_SRQ_LIMIT, 1)
1627 | EHCA_BMASK_SET(MQPCB_MASK_QP_AFF_ASYN_EV_LOG_REG, 1);
1628 mqpcb->curr_srq_limit =
1629 EHCA_BMASK_SET(MQPCB_CURR_SRQ_LIMIT, attr->srq_limit);
1630 mqpcb->qp_aff_asyn_ev_log_reg =
1631 EHCA_BMASK_SET(QPX_AAELOG_RESET_SRQ_LIMIT, 1);
1634 /* by now, all bits in attr_mask should have been cleared */
1636 ehca_err(ibsrq->device, "invalid attribute mask bits set "
1637 "attr_mask=%x", attr_mask);
1639 goto modify_srq_exit0;
1642 if (ehca_debug_level)
1643 ehca_dmp(mqpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1645 h_ret = hipz_h_modify_qp(shca->ipz_hca_handle, my_qp->ipz_qp_handle,
1646 NULL, update_mask, mqpcb,
1647 my_qp->galpas.kernel);
1649 if (h_ret != H_SUCCESS) {
1650 ret = ehca2ib_return_code(h_ret);
1651 ehca_err(ibsrq->device, "hipz_h_modify_qp() failed rc=%lx "
1652 "ehca_qp=%p qp_num=%x",
1653 h_ret, my_qp, my_qp->real_qp_num);
1657 ehca_free_fw_ctrlblock(mqpcb);
1662 int ehca_query_srq(struct ib_srq *srq, struct ib_srq_attr *srq_attr)
1664 struct ehca_qp *my_qp = container_of(srq, struct ehca_qp, ib_srq);
1665 struct ehca_pd *my_pd = container_of(srq->pd, struct ehca_pd, ib_pd);
1666 struct ehca_shca *shca = container_of(srq->device, struct ehca_shca,
1668 struct ipz_adapter_handle adapter_handle = shca->ipz_hca_handle;
1669 struct hcp_modify_qp_control_block *qpcb;
1670 u32 cur_pid = current->tgid;
1674 if (my_pd->ib_pd.uobject && my_pd->ib_pd.uobject->context &&
1675 my_pd->ownpid != cur_pid) {
1676 ehca_err(srq->device, "Invalid caller pid=%x ownpid=%x",
1677 cur_pid, my_pd->ownpid);
1681 qpcb = ehca_alloc_fw_ctrlblock(GFP_KERNEL);
1683 ehca_err(srq->device, "Out of memory for qpcb "
1684 "ehca_qp=%p qp_num=%x", my_qp, my_qp->real_qp_num);
1688 h_ret = hipz_h_query_qp(adapter_handle, my_qp->ipz_qp_handle,
1689 NULL, qpcb, my_qp->galpas.kernel);
1691 if (h_ret != H_SUCCESS) {
1692 ret = ehca2ib_return_code(h_ret);
1693 ehca_err(srq->device, "hipz_h_query_qp() failed "
1694 "ehca_qp=%p qp_num=%x h_ret=%lx",
1695 my_qp, my_qp->real_qp_num, h_ret);
1696 goto query_srq_exit1;
1699 srq_attr->max_wr = qpcb->max_nr_outst_recv_wr - 1;
1700 srq_attr->srq_limit = EHCA_BMASK_GET(
1701 MQPCB_CURR_SRQ_LIMIT, qpcb->curr_srq_limit);
1703 if (ehca_debug_level)
1704 ehca_dmp(qpcb, 4*70, "qp_num=%x", my_qp->real_qp_num);
1707 ehca_free_fw_ctrlblock(qpcb);
1712 static int internal_destroy_qp(struct ib_device *dev, struct ehca_qp *my_qp,
1713 struct ib_uobject *uobject)
1715 struct ehca_shca *shca = container_of(dev, struct ehca_shca, ib_device);
1716 struct ehca_pd *my_pd = container_of(my_qp->ib_qp.pd, struct ehca_pd,
1718 u32 cur_pid = current->tgid;
1719 u32 qp_num = my_qp->real_qp_num;
1723 enum ib_qp_type qp_type;
1724 unsigned long flags;
1727 if (my_qp->mm_count_galpa ||
1728 my_qp->mm_count_rqueue || my_qp->mm_count_squeue) {
1729 ehca_err(dev, "Resources still referenced in "
1730 "user space qp_num=%x", qp_num);
1733 if (my_pd->ownpid != cur_pid) {
1734 ehca_err(dev, "Invalid caller pid=%x ownpid=%x",
1735 cur_pid, my_pd->ownpid);
1740 if (my_qp->send_cq) {
1741 ret = ehca_cq_unassign_qp(my_qp->send_cq, qp_num);
1743 ehca_err(dev, "Couldn't unassign qp from "
1744 "send_cq ret=%x qp_num=%x cq_num=%x", ret,
1745 qp_num, my_qp->send_cq->cq_number);
1750 write_lock_irqsave(&ehca_qp_idr_lock, flags);
1751 idr_remove(&ehca_qp_idr, my_qp->token);
1752 write_unlock_irqrestore(&ehca_qp_idr_lock, flags);
1754 h_ret = hipz_h_destroy_qp(shca->ipz_hca_handle, my_qp);
1755 if (h_ret != H_SUCCESS) {
1756 ehca_err(dev, "hipz_h_destroy_qp() failed rc=%lx "
1757 "ehca_qp=%p qp_num=%x", h_ret, my_qp, qp_num);
1758 return ehca2ib_return_code(h_ret);
1761 port_num = my_qp->init_attr.port_num;
1762 qp_type = my_qp->init_attr.qp_type;
1764 /* no support for IB_QPT_SMI yet */
1765 if (qp_type == IB_QPT_GSI) {
1766 struct ib_event event;
1767 ehca_info(dev, "device %s: port %x is inactive.",
1768 shca->ib_device.name, port_num);
1769 event.device = &shca->ib_device;
1770 event.event = IB_EVENT_PORT_ERR;
1771 event.element.port_num = port_num;
1772 shca->sport[port_num - 1].port_state = IB_PORT_DOWN;
1773 ib_dispatch_event(&event);
1777 ipz_queue_dtor(my_pd, &my_qp->ipz_rqueue);
1779 ipz_queue_dtor(my_pd, &my_qp->ipz_squeue);
1780 kmem_cache_free(qp_cache, my_qp);
1784 int ehca_destroy_qp(struct ib_qp *qp)
1786 return internal_destroy_qp(qp->device,
1787 container_of(qp, struct ehca_qp, ib_qp),
1791 int ehca_destroy_srq(struct ib_srq *srq)
1793 return internal_destroy_qp(srq->device,
1794 container_of(srq, struct ehca_qp, ib_srq),
1798 int ehca_init_qp_cache(void)
1800 qp_cache = kmem_cache_create("ehca_cache_qp",
1801 sizeof(struct ehca_qp), 0,
1809 void ehca_cleanup_qp_cache(void)
1812 kmem_cache_destroy(qp_cache);