2 * linux/drivers/ide/pci/sl82c105.c
4 * SL82C105/Winbond 553 IDE driver
8 * Drive tuning added from Rebel.com's kernel sources
9 * -- Russell King (15/11/98) linux@arm.linux.org.uk
11 * Merge in Russell's HW workarounds, fix various problems
12 * with the timing registers setup.
13 * -- Benjamin Herrenschmidt (01/11/03) benh@kernel.crashing.org
15 * Copyright (C) 2006-2007 MontaVista Software, Inc. <source@mvista.com>
18 #include <linux/types.h>
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/timer.h>
23 #include <linux/ioport.h>
24 #include <linux/interrupt.h>
25 #include <linux/blkdev.h>
26 #include <linux/hdreg.h>
27 #include <linux/pci.h>
28 #include <linux/ide.h>
36 #define DBG(arg) printk arg
41 * SL82C105 PCI config register 0x40 bits.
43 #define CTRL_IDE_IRQB (1 << 30)
44 #define CTRL_IDE_IRQA (1 << 28)
45 #define CTRL_LEGIRQ (1 << 11)
46 #define CTRL_P1F16 (1 << 5)
47 #define CTRL_P1EN (1 << 4)
48 #define CTRL_P0F16 (1 << 1)
49 #define CTRL_P0EN (1 << 0)
52 * Convert a PIO mode and cycle time to the required on/off times
53 * for the interface. This has protection against runaway timings.
55 static unsigned int get_pio_timings(ide_pio_data_t *p)
57 unsigned int cmd_on, cmd_off;
59 cmd_on = (ide_pio_timings[p->pio_mode].active_time + 29) / 30;
60 cmd_off = (p->cycle_time - 30 * cmd_on + 29) / 30;
68 return (cmd_on - 1) << 8 | (cmd_off - 1) | (p->use_iordy ? 0x40 : 0x00);
72 * Configure the chipset for PIO mode.
74 static u8 sl82c105_tune_pio(ide_drive_t *drive, u8 pio)
76 struct pci_dev *dev = HWIF(drive)->pci_dev;
77 int reg = 0x44 + drive->dn * 4;
81 DBG(("sl82c105_tune_pio(drive:%s, pio:%u)\n", drive->name, pio));
83 pio = ide_get_best_pio_mode(drive, pio, 5, &p);
85 drv_ctrl = get_pio_timings(&p);
88 * Store the PIO timings so that we can restore them
89 * in case DMA will be turned off...
91 drive->drive_data &= 0xffff0000;
92 drive->drive_data |= drv_ctrl;
94 if (!drive->using_dma) {
96 * If we are actually using MW DMA, then we can not
97 * reprogram the interface drive control register.
99 pci_write_config_word(dev, reg, drv_ctrl);
100 pci_read_config_word (dev, reg, &drv_ctrl);
103 printk(KERN_DEBUG "%s: selected %s (%dns) (%04X)\n", drive->name,
104 ide_xfer_verbose(pio + XFER_PIO_0), p.cycle_time, drv_ctrl);
110 * Configure the drive and chipset for a new transfer speed.
112 static int sl82c105_tune_chipset(ide_drive_t *drive, u8 speed)
114 static u16 mwdma_timings[] = {0x0707, 0x0201, 0x0200};
117 DBG(("sl82c105_tune_chipset(drive:%s, speed:%s)\n",
118 drive->name, ide_xfer_verbose(speed)));
120 speed = ide_rate_filter(drive, speed);
126 drv_ctrl = mwdma_timings[speed - XFER_MW_DMA_0];
129 * Store the DMA timings so that we can actually program
130 * them when DMA will be turned on...
132 drive->drive_data &= 0x0000ffff;
133 drive->drive_data |= (unsigned long)drv_ctrl << 16;
136 * If we are already using DMA, we just reprogram
137 * the drive control register.
139 if (drive->using_dma) {
140 struct pci_dev *dev = HWIF(drive)->pci_dev;
141 int reg = 0x44 + drive->dn * 4;
143 pci_write_config_word(dev, reg, drv_ctrl);
152 (void) sl82c105_tune_pio(drive, speed - XFER_PIO_0);
158 return ide_config_drive_speed(drive, speed);
162 * Configure the drive for DMA.
164 static int config_for_dma(ide_drive_t *drive)
166 u8 speed = ide_max_dma_mode(drive);
168 DBG(("config_for_dma(drive:%s)\n", drive->name));
170 if (!speed || sl82c105_tune_chipset(drive, speed))
173 return ide_dma_enable(drive);
177 * Check to see if the drive and chipset are capable of DMA mode.
179 static int sl82c105_ide_dma_check(ide_drive_t *drive)
181 DBG(("sl82c105_ide_dma_check(drive:%s)\n", drive->name));
183 if (ide_use_dma(drive) && config_for_dma(drive))
190 * The SL82C105 holds off all IDE interrupts while in DMA mode until
191 * all DMA activity is completed. Sometimes this causes problems (eg,
192 * when the drive wants to report an error condition).
194 * 0x7e is a "chip testing" register. Bit 2 resets the DMA controller
195 * state machine. We need to kick this to work around various bugs.
197 static inline void sl82c105_reset_host(struct pci_dev *dev)
201 pci_read_config_word(dev, 0x7e, &val);
202 pci_write_config_word(dev, 0x7e, val | (1 << 2));
203 pci_write_config_word(dev, 0x7e, val & ~(1 << 2));
207 * If we get an IRQ timeout, it might be that the DMA state machine
208 * got confused. Fix from Todd Inglett. Details from Winbond.
210 * This function is called when the IDE timer expires, the drive
211 * indicates that it is READY, and we were waiting for DMA to complete.
213 static int sl82c105_ide_dma_lostirq(ide_drive_t *drive)
215 ide_hwif_t *hwif = HWIF(drive);
216 struct pci_dev *dev = hwif->pci_dev;
217 u32 val, mask = hwif->channel ? CTRL_IDE_IRQB : CTRL_IDE_IRQA;
220 printk("sl82c105: lost IRQ, resetting host\n");
223 * Check the raw interrupt from the drive.
225 pci_read_config_dword(dev, 0x40, &val);
227 printk("sl82c105: drive was requesting IRQ, but host lost it\n");
230 * Was DMA enabled? If so, disable it - we're resetting the
231 * host. The IDE layer will be handling the drive for us.
233 dma_cmd = inb(hwif->dma_command);
235 outb(dma_cmd & ~1, hwif->dma_command);
236 printk("sl82c105: DMA was enabled\n");
239 sl82c105_reset_host(dev);
241 /* __ide_dma_lostirq would return 1, so we do as well */
246 * ATAPI devices can cause the SL82C105 DMA state machine to go gaga.
247 * Winbond recommend that the DMA state machine is reset prior to
248 * setting the bus master DMA enable bit.
250 * The generic IDE core will have disabled the BMEN bit before this
251 * function is called.
253 static void sl82c105_dma_start(ide_drive_t *drive)
255 ide_hwif_t *hwif = HWIF(drive);
256 struct pci_dev *dev = hwif->pci_dev;
258 sl82c105_reset_host(dev);
259 ide_dma_start(drive);
262 static int sl82c105_ide_dma_timeout(ide_drive_t *drive)
264 ide_hwif_t *hwif = HWIF(drive);
265 struct pci_dev *dev = hwif->pci_dev;
267 DBG(("sl82c105_ide_dma_timeout(drive:%s)\n", drive->name));
269 sl82c105_reset_host(dev);
270 return __ide_dma_timeout(drive);
273 static int sl82c105_ide_dma_on(ide_drive_t *drive)
275 struct pci_dev *dev = HWIF(drive)->pci_dev;
276 int rc, reg = 0x44 + drive->dn * 4;
278 DBG(("sl82c105_ide_dma_on(drive:%s)\n", drive->name));
280 rc = __ide_dma_on(drive);
282 pci_write_config_word(dev, reg, drive->drive_data >> 16);
284 printk(KERN_INFO "%s: DMA enabled\n", drive->name);
289 static void sl82c105_dma_off_quietly(ide_drive_t *drive)
291 struct pci_dev *dev = HWIF(drive)->pci_dev;
292 int reg = 0x44 + drive->dn * 4;
294 DBG(("sl82c105_dma_off_quietly(drive:%s)\n", drive->name));
296 pci_write_config_word(dev, reg, drive->drive_data);
298 ide_dma_off_quietly(drive);
302 * Ok, that is nasty, but we must make sure the DMA timings
303 * won't be used for a PIO access. The solution here is
304 * to make sure the 16 bits mode is diabled on the channel
305 * when DMA is enabled, thus causing the chip to use PIO0
306 * timings for those operations.
308 static void sl82c105_selectproc(ide_drive_t *drive)
310 ide_hwif_t *hwif = HWIF(drive);
311 struct pci_dev *dev = hwif->pci_dev;
314 //DBG(("sl82c105_selectproc(drive:%s)\n", drive->name));
316 mask = hwif->channel ? CTRL_P1F16 : CTRL_P0F16;
317 old = val = (u32)pci_get_drvdata(dev);
318 if (drive->using_dma)
323 pci_write_config_dword(dev, 0x40, val);
324 pci_set_drvdata(dev, (void *)val);
329 * ATA reset will clear the 16 bits mode in the control
330 * register, we need to update our cache
332 static void sl82c105_resetproc(ide_drive_t *drive)
334 struct pci_dev *dev = HWIF(drive)->pci_dev;
337 DBG(("sl82c105_resetproc(drive:%s)\n", drive->name));
339 pci_read_config_dword(dev, 0x40, &val);
340 pci_set_drvdata(dev, (void *)val);
344 * We only deal with PIO mode here - DMA mode 'using_dma' is not
345 * initialised at the point that this function is called.
347 static void sl82c105_tune_drive(ide_drive_t *drive, u8 pio)
349 DBG(("sl82c105_tune_drive(drive:%s, pio:%u)\n", drive->name, pio));
351 pio = sl82c105_tune_pio(drive, pio);
352 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
356 * Return the revision of the Winbond bridge
357 * which this function is part of.
359 static unsigned int sl82c105_bridge_revision(struct pci_dev *dev)
361 struct pci_dev *bridge;
365 * The bridge should be part of the same device, but function 0.
367 bridge = pci_find_slot(dev->bus->number,
368 PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
373 * Make sure it is a Winbond 553 and is an ISA bridge.
375 if (bridge->vendor != PCI_VENDOR_ID_WINBOND ||
376 bridge->device != PCI_DEVICE_ID_WINBOND_83C553 ||
377 bridge->class >> 8 != PCI_CLASS_BRIDGE_ISA)
381 * We need to find function 0's revision, not function 1
383 pci_read_config_byte(bridge, PCI_REVISION_ID, &rev);
389 * Enable the PCI device
391 * --BenH: It's arch fixup code that should enable channels that
392 * have not been enabled by firmware. I decided we can still enable
393 * channel 0 here at least, but channel 1 has to be enabled by
394 * firmware or arch code. We still set both to 16 bits mode.
396 static unsigned int __devinit init_chipset_sl82c105(struct pci_dev *dev, const char *msg)
400 DBG(("init_chipset_sl82c105()\n"));
402 pci_read_config_dword(dev, 0x40, &val);
403 val |= CTRL_P0EN | CTRL_P0F16 | CTRL_P1F16;
404 pci_write_config_dword(dev, 0x40, val);
405 pci_set_drvdata(dev, (void *)val);
411 * Initialise IDE channel
413 static void __devinit init_hwif_sl82c105(ide_hwif_t *hwif)
417 DBG(("init_hwif_sl82c105(hwif: ide%d)\n", hwif->index));
419 hwif->tuneproc = &sl82c105_tune_drive;
420 hwif->speedproc = &sl82c105_tune_chipset;
421 hwif->selectproc = &sl82c105_selectproc;
422 hwif->resetproc = &sl82c105_resetproc;
425 * We support 32-bit I/O on this interface, and
426 * it doesn't have problems with interrupts.
428 hwif->drives[0].io_32bit = hwif->drives[1].io_32bit = 1;
429 hwif->drives[0].unmask = hwif->drives[1].unmask = 1;
432 * We always autotune PIO, this is done before DMA is checked,
433 * so there's no risk of accidentally disabling DMA
435 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
440 rev = sl82c105_bridge_revision(hwif->pci_dev);
443 * Never ever EVER under any circumstances enable
444 * DMA when the bridge is this old.
446 printk(" %s: Winbond W83C553 bridge revision %d, "
447 "BM-DMA disabled\n", hwif->name, rev);
452 hwif->mwdma_mask = 0x07;
454 hwif->ide_dma_check = &sl82c105_ide_dma_check;
455 hwif->ide_dma_on = &sl82c105_ide_dma_on;
456 hwif->dma_off_quietly = &sl82c105_dma_off_quietly;
457 hwif->ide_dma_lostirq = &sl82c105_ide_dma_lostirq;
458 hwif->dma_start = &sl82c105_dma_start;
459 hwif->ide_dma_timeout = &sl82c105_ide_dma_timeout;
463 hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
466 hwif->serialized = hwif->mate->serialized = 1;
469 static ide_pci_device_t sl82c105_chipset __devinitdata = {
471 .init_chipset = init_chipset_sl82c105,
472 .init_hwif = init_hwif_sl82c105,
474 .autodma = NOAUTODMA,
475 .enablebits = {{0x40,0x01,0x01}, {0x40,0x10,0x10}},
476 .bootable = ON_BOARD,
479 static int __devinit sl82c105_init_one(struct pci_dev *dev, const struct pci_device_id *id)
481 return ide_setup_pci_device(dev, &sl82c105_chipset);
484 static struct pci_device_id sl82c105_pci_tbl[] = {
485 { PCI_DEVICE(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105), 0},
488 MODULE_DEVICE_TABLE(pci, sl82c105_pci_tbl);
490 static struct pci_driver driver = {
491 .name = "W82C105_IDE",
492 .id_table = sl82c105_pci_tbl,
493 .probe = sl82c105_init_one,
496 static int __init sl82c105_ide_init(void)
498 return ide_pci_register_driver(&driver);
501 module_init(sl82c105_ide_init);
503 MODULE_DESCRIPTION("PCI driver module for W82C105 IDE");
504 MODULE_LICENSE("GPL");