2 * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
3 * Copyright (C) 2003 Red Hat <alan@redhat.com>
4 * Copyright (C) 2007 MontaVista Software, Inc.
5 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
7 * May be copied or modified under the terms of the GNU General Public License
9 * Documentation for CMD680:
10 * http://gkernel.sourceforge.net/specs/sii/sii-0680a-v1.31.pdf.bz2
12 * Documentation for SiI 3112:
13 * http://gkernel.sourceforge.net/specs/sii/3112A_SiI-DS-0095-B2.pdf.bz2
15 * Errata and other documentation only available under NDA.
19 * If you are using Marvell SATA-IDE adapters with Maxtor drives
20 * ensure the system is set up for ATA100/UDMA5 not UDMA6.
22 * If you are using WD drives with SATA bridges you must set the
23 * drive to "Single". "Master" will hang
25 * If you have strange problems with nVidia chipset systems please
26 * see the SI support documentation and update your system BIOS
29 * The Dell DRAC4 has some interesting features including effectively hot
30 * unplugging/replugging the virtual CD interface when the DRAC is reset.
31 * This often causes drivers/ide/siimage to panic but is ok with the rather
32 * smarter code in libata.
39 #include <linux/types.h>
40 #include <linux/module.h>
41 #include <linux/pci.h>
42 #include <linux/hdreg.h>
43 #include <linux/ide.h>
44 #include <linux/init.h>
49 * pdev_is_sata - check if device is SATA
50 * @pdev: PCI device to check
52 * Returns true if this is a SATA controller
55 static int pdev_is_sata(struct pci_dev *pdev)
57 #ifdef CONFIG_BLK_DEV_IDE_SATA
58 switch(pdev->device) {
59 case PCI_DEVICE_ID_SII_3112:
60 case PCI_DEVICE_ID_SII_1210SA:
62 case PCI_DEVICE_ID_SII_680:
71 * is_sata - check if hwif is SATA
72 * @hwif: interface to check
74 * Returns true if this is a SATA controller
77 static inline int is_sata(ide_hwif_t *hwif)
79 return pdev_is_sata(to_pci_dev(hwif->dev));
83 * siimage_selreg - return register base
87 * Turn a config register offset into the right address in either
88 * PCI space or MMIO space to access the control register in question
89 * Thankfully this is a configuration operation so isnt performance
93 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
95 unsigned long base = (unsigned long)hwif->hwif_data;
98 base += (hwif->channel << 6);
100 base += (hwif->channel << 4);
105 * siimage_seldev - return register base
109 * Turn a config register offset into the right address in either
110 * PCI space or MMIO space to access the control register in question
111 * including accounting for the unit shift.
114 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
116 ide_hwif_t *hwif = HWIF(drive);
117 unsigned long base = (unsigned long)hwif->hwif_data;
120 base += (hwif->channel << 6);
122 base += (hwif->channel << 4);
123 base |= drive->select.b.unit << drive->select.b.unit;
128 * sil_udma_filter - compute UDMA mask
131 * Compute the available UDMA speeds for the device on the interface.
133 * For the CMD680 this depends on the clocking mode (scsc), for the
134 * SI3112 SATA controller life is a bit simpler.
137 static u8 sil_pata_udma_filter(ide_drive_t *drive)
139 ide_hwif_t *hwif = drive->hwif;
140 struct pci_dev *dev = to_pci_dev(hwif->dev);
141 unsigned long base = (unsigned long) hwif->hwif_data;
142 u8 mask = 0, scsc = 0;
145 scsc = hwif->INB(base + 0x4A);
147 pci_read_config_byte(dev, 0x8A, &scsc);
149 if ((scsc & 0x30) == 0x10) /* 133 */
151 else if ((scsc & 0x30) == 0x20) /* 2xPCI */
153 else if ((scsc & 0x30) == 0x00) /* 100 */
155 else /* Disabled ? */
161 static u8 sil_sata_udma_filter(ide_drive_t *drive)
163 return strstr(drive->id->model, "Maxtor") ? ATA_UDMA5 : ATA_UDMA6;
167 * sil_set_pio_mode - set host controller for PIO mode
169 * @pio: PIO mode number
171 * Load the timing settings for this device mode into the
172 * controller. If we are in PIO mode 3 or 4 turn on IORDY
173 * monitoring (bit 9). The TF timing is bits 31:16
176 static void sil_set_pio_mode(ide_drive_t *drive, u8 pio)
178 const u16 tf_speed[] = { 0x328a, 0x2283, 0x1281, 0x10c3, 0x10c1 };
179 const u16 data_speed[] = { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
181 ide_hwif_t *hwif = HWIF(drive);
182 ide_drive_t *pair = ide_get_paired_drive(drive);
185 unsigned long addr = siimage_seldev(drive, 0x04);
186 unsigned long tfaddr = siimage_selreg(hwif, 0x02);
187 unsigned long base = (unsigned long)hwif->hwif_data;
189 u8 addr_mask = hwif->channel ? (hwif->mmio ? 0xF4 : 0x84)
190 : (hwif->mmio ? 0xB4 : 0x80);
192 u8 unit = drive->select.b.unit;
194 /* trim *taskfile* PIO to the slowest of the master/slave */
196 u8 pair_pio = ide_get_best_pio_mode(pair, 255, 4);
198 if (pair_pio < tf_pio)
202 /* cheat for now and use the docs */
203 speedp = data_speed[pio];
204 speedt = tf_speed[tf_pio];
207 hwif->OUTW(speedp, addr);
208 hwif->OUTW(speedt, tfaddr);
209 /* Now set up IORDY */
211 hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
213 hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
215 mode = hwif->INB(base + addr_mask);
216 mode &= ~(unit ? 0x30 : 0x03);
217 mode |= (unit ? 0x10 : 0x01);
218 hwif->OUTB(mode, base + addr_mask);
220 struct pci_dev *dev = to_pci_dev(hwif->dev);
222 pci_write_config_word(dev, addr, speedp);
223 pci_write_config_word(dev, tfaddr, speedt);
224 pci_read_config_word(dev, tfaddr - 2, &speedp);
226 /* Set IORDY for mode 3 or 4 */
229 pci_write_config_word(dev, tfaddr - 2, speedp);
231 pci_read_config_byte(dev, addr_mask, &mode);
232 mode &= ~(unit ? 0x30 : 0x03);
233 mode |= (unit ? 0x10 : 0x01);
234 pci_write_config_byte(dev, addr_mask, mode);
239 * sil_set_dma_mode - set host controller for DMA mode
243 * Tune the SiI chipset for the desired DMA mode.
246 static void sil_set_dma_mode(ide_drive_t *drive, const u8 speed)
248 u8 ultra6[] = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
249 u8 ultra5[] = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
250 u16 dma[] = { 0x2208, 0x10C2, 0x10C1 };
252 ide_hwif_t *hwif = HWIF(drive);
253 struct pci_dev *dev = to_pci_dev(hwif->dev);
254 u16 ultra = 0, multi = 0;
255 u8 mode = 0, unit = drive->select.b.unit;
256 unsigned long base = (unsigned long)hwif->hwif_data;
257 u8 scsc = 0, addr_mask = ((hwif->channel) ?
258 ((hwif->mmio) ? 0xF4 : 0x84) :
259 ((hwif->mmio) ? 0xB4 : 0x80));
261 unsigned long ma = siimage_seldev(drive, 0x08);
262 unsigned long ua = siimage_seldev(drive, 0x0C);
265 scsc = hwif->INB(base + 0x4A);
266 mode = hwif->INB(base + addr_mask);
267 multi = hwif->INW(ma);
268 ultra = hwif->INW(ua);
270 pci_read_config_byte(dev, 0x8A, &scsc);
271 pci_read_config_byte(dev, addr_mask, &mode);
272 pci_read_config_word(dev, ma, &multi);
273 pci_read_config_word(dev, ua, &ultra);
276 mode &= ~((unit) ? 0x30 : 0x03);
278 scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
280 scsc = is_sata(hwif) ? 1 : scsc;
282 if (speed >= XFER_UDMA_0) {
284 ultra |= (scsc ? ultra6[speed - XFER_UDMA_0] :
285 ultra5[speed - XFER_UDMA_0]);
286 mode |= (unit ? 0x30 : 0x03);
288 multi = dma[speed - XFER_MW_DMA_0];
289 mode |= (unit ? 0x20 : 0x02);
293 hwif->OUTB(mode, base + addr_mask);
294 hwif->OUTW(multi, ma);
295 hwif->OUTW(ultra, ua);
297 pci_write_config_byte(dev, addr_mask, mode);
298 pci_write_config_word(dev, ma, multi);
299 pci_write_config_word(dev, ua, ultra);
303 /* returns 1 if dma irq issued, 0 otherwise */
304 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
306 ide_hwif_t *hwif = HWIF(drive);
307 struct pci_dev *dev = to_pci_dev(hwif->dev);
309 unsigned long addr = siimage_selreg(hwif, 1);
311 /* return 1 if INTR asserted */
312 if ((hwif->INB(hwif->dma_status) & 4) == 4)
315 /* return 1 if Device INTR asserted */
316 pci_read_config_byte(dev, addr, &dma_altstat);
318 return 0; //return 1;
323 * siimage_mmio_ide_dma_test_irq - check we caused an IRQ
324 * @drive: drive we are testing
326 * Check if we caused an IDE DMA interrupt. We may also have caused
327 * SATA status interrupts, if so we clean them up and continue.
330 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
332 ide_hwif_t *hwif = HWIF(drive);
333 unsigned long addr = siimage_selreg(hwif, 0x1);
335 if (SATA_ERROR_REG) {
336 unsigned long base = (unsigned long)hwif->hwif_data;
338 u32 ext_stat = readl((void __iomem *)(base + 0x10));
340 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
341 u32 sata_error = readl((void __iomem *)SATA_ERROR_REG);
342 writel(sata_error, (void __iomem *)SATA_ERROR_REG);
343 watchdog = (sata_error & 0x00680000) ? 1 : 0;
344 printk(KERN_WARNING "%s: sata_error = 0x%08x, "
345 "watchdog = %d, %s\n",
346 drive->name, sata_error, watchdog,
350 watchdog = (ext_stat & 0x8000) ? 1 : 0;
354 if (!(ext_stat & 0x0404) && !watchdog)
358 /* return 1 if INTR asserted */
359 if ((readb((void __iomem *)hwif->dma_status) & 0x04) == 0x04)
362 /* return 1 if Device INTR asserted */
363 if ((readb((void __iomem *)addr) & 8) == 8)
364 return 0; //return 1;
370 * sil_sata_busproc - bus isolation IOCTL
371 * @drive: drive to isolate/restore
372 * @state: bus state to set
374 * Used by the SII3112 to handle bus isolation. As this is a
375 * SATA controller the work required is quite limited, we
376 * just have to clean up the statistics
379 static int sil_sata_busproc(ide_drive_t * drive, int state)
381 ide_hwif_t *hwif = HWIF(drive);
382 struct pci_dev *dev = to_pci_dev(hwif->dev);
384 unsigned long addr = siimage_selreg(hwif, 0);
387 stat_config = readl((void __iomem *)addr);
389 pci_read_config_dword(dev, addr, &stat_config);
393 hwif->drives[0].failures = 0;
394 hwif->drives[1].failures = 0;
397 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
398 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
400 case BUSSTATE_TRISTATE:
401 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
402 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
407 hwif->bus_state = state;
412 * sil_sata_reset_poll - wait for SATA reset
413 * @drive: drive we are resetting
415 * Poll the SATA phy and see whether it has come back from the dead
419 static int sil_sata_reset_poll(ide_drive_t *drive)
421 if (SATA_STATUS_REG) {
422 ide_hwif_t *hwif = HWIF(drive);
424 /* SATA_STATUS_REG is valid only when in MMIO mode */
425 if ((readl((void __iomem *)SATA_STATUS_REG) & 0x03) != 0x03) {
426 printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
427 hwif->name, readl((void __iomem *)SATA_STATUS_REG));
428 HWGROUP(drive)->polling = 0;
437 * sil_sata_pre_reset - reset hook
438 * @drive: IDE device being reset
440 * For the SATA devices we need to handle recalibration/geometry
444 static void sil_sata_pre_reset(ide_drive_t *drive)
446 if (drive->media == ide_disk) {
447 drive->special.b.set_geometry = 0;
448 drive->special.b.recalibrate = 0;
453 * proc_reports_siimage - add siimage controller to proc
455 * @clocking: SCSC value
456 * @name: controller name
458 * Report the clocking mode of the controller and add it to
459 * the /proc interface layer
462 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
464 if (!pdev_is_sata(dev)) {
465 printk(KERN_INFO "%s: BASE CLOCK ", name);
468 case 0x03: printk("DISABLED!\n"); break;
469 case 0x02: printk("== 2X PCI\n"); break;
470 case 0x01: printk("== 133\n"); break;
471 case 0x00: printk("== 100\n"); break;
477 * setup_mmio_siimage - switch an SI controller into MMIO
478 * @dev: PCI device we are configuring
481 * Attempt to put the device into mmio mode. There are some slight
482 * complications here with certain systems where the mmio bar isnt
483 * mapped so we have to be sure we can fall back to I/O.
486 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
488 unsigned long bar5 = pci_resource_start(dev, 5);
489 unsigned long barsize = pci_resource_len(dev, 5);
491 void __iomem *ioaddr;
495 * Drop back to PIO if we can't map the mmio. Some
496 * systems seem to get terminally confused in the PCI
500 if(!request_mem_region(bar5, barsize, name))
502 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
506 ioaddr = ioremap(bar5, barsize);
510 release_mem_region(bar5, barsize);
515 pci_set_drvdata(dev, (void *) ioaddr);
517 if (pdev_is_sata(dev)) {
518 /* make sure IDE0/1 interrupts are not masked */
519 irq_mask = (1 << 22) | (1 << 23);
520 tmp = readl(ioaddr + 0x48);
521 if (tmp & irq_mask) {
523 writel(tmp, ioaddr + 0x48);
524 readl(ioaddr + 0x48); /* flush */
526 writel(0, ioaddr + 0x148);
527 writel(0, ioaddr + 0x1C8);
530 writeb(0, ioaddr + 0xB4);
531 writeb(0, ioaddr + 0xF4);
532 tmpbyte = readb(ioaddr + 0x4A);
534 switch(tmpbyte & 0x30) {
536 /* In 100 MHz clocking, try and switch to 133 */
537 writeb(tmpbyte|0x10, ioaddr + 0x4A);
540 /* On 133Mhz clocking */
543 /* On PCIx2 clocking */
546 /* Clocking is disabled */
547 /* 133 clock attempt to force it on */
548 writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
552 writeb( 0x72, ioaddr + 0xA1);
553 writew( 0x328A, ioaddr + 0xA2);
554 writel(0x62DD62DD, ioaddr + 0xA4);
555 writel(0x43924392, ioaddr + 0xA8);
556 writel(0x40094009, ioaddr + 0xAC);
557 writeb( 0x72, ioaddr + 0xE1);
558 writew( 0x328A, ioaddr + 0xE2);
559 writel(0x62DD62DD, ioaddr + 0xE4);
560 writel(0x43924392, ioaddr + 0xE8);
561 writel(0x40094009, ioaddr + 0xEC);
563 if (pdev_is_sata(dev)) {
564 writel(0xFFFF0000, ioaddr + 0x108);
565 writel(0xFFFF0000, ioaddr + 0x188);
566 writel(0x00680000, ioaddr + 0x148);
567 writel(0x00680000, ioaddr + 0x1C8);
570 tmpbyte = readb(ioaddr + 0x4A);
572 proc_reports_siimage(dev, (tmpbyte>>4), name);
577 * init_chipset_siimage - set up an SI device
581 * Perform the initial PCI set up for this device. Attempt to switch
582 * to 133MHz clocking if the system isn't already set up to do it.
585 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
587 u8 rev = dev->revision, tmpbyte = 0, BA5_EN = 0;
589 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, rev ? 1 : 255);
591 pci_read_config_byte(dev, 0x8A, &BA5_EN);
592 if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
593 if (setup_mmio_siimage(dev, name)) {
598 pci_write_config_byte(dev, 0x80, 0x00);
599 pci_write_config_byte(dev, 0x84, 0x00);
600 pci_read_config_byte(dev, 0x8A, &tmpbyte);
601 switch(tmpbyte & 0x30) {
603 /* 133 clock attempt to force it on */
604 pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
606 /* if clocking is disabled */
607 /* 133 clock attempt to force it on */
608 pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
613 /* BIOS set PCI x2 clocking */
617 pci_read_config_byte(dev, 0x8A, &tmpbyte);
619 pci_write_config_byte(dev, 0xA1, 0x72);
620 pci_write_config_word(dev, 0xA2, 0x328A);
621 pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
622 pci_write_config_dword(dev, 0xA8, 0x43924392);
623 pci_write_config_dword(dev, 0xAC, 0x40094009);
624 pci_write_config_byte(dev, 0xB1, 0x72);
625 pci_write_config_word(dev, 0xB2, 0x328A);
626 pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
627 pci_write_config_dword(dev, 0xB8, 0x43924392);
628 pci_write_config_dword(dev, 0xBC, 0x40094009);
630 proc_reports_siimage(dev, (tmpbyte>>4), name);
635 * init_mmio_iops_siimage - set up the iops for MMIO
636 * @hwif: interface to set up
638 * The basic setup here is fairly simple, we can use standard MMIO
639 * operations. However we do have to set the taskfile register offsets
640 * by hand as there isnt a standard defined layout for them this
643 * The hardware supports buffered taskfiles and also some rather nice
644 * extended PRD tables. For better SI3112 support use the libata driver
647 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
649 struct pci_dev *dev = to_pci_dev(hwif->dev);
650 void *addr = pci_get_drvdata(dev);
651 u8 ch = hwif->channel;
656 * Fill in the basic HWIF bits
659 default_hwif_mmiops(hwif);
660 hwif->hwif_data = addr;
663 * Now set up the hw. We have to do this ourselves as
664 * the MMIO layout isnt the same as the standard port
668 memset(&hw, 0, sizeof(hw_regs_t));
670 base = (unsigned long)addr;
677 * The buffered task file doesn't have status/control
678 * so we can't currently use it sanely since we want to
681 hw.io_ports[IDE_DATA_OFFSET] = base;
682 hw.io_ports[IDE_ERROR_OFFSET] = base + 1;
683 hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
684 hw.io_ports[IDE_SECTOR_OFFSET] = base + 3;
685 hw.io_ports[IDE_LCYL_OFFSET] = base + 4;
686 hw.io_ports[IDE_HCYL_OFFSET] = base + 5;
687 hw.io_ports[IDE_SELECT_OFFSET] = base + 6;
688 hw.io_ports[IDE_STATUS_OFFSET] = base + 7;
689 hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
691 hw.io_ports[IDE_IRQ_OFFSET] = 0;
693 if (pdev_is_sata(dev)) {
694 base = (unsigned long)addr;
697 hwif->sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
698 hwif->sata_scr[SATA_ERROR_OFFSET] = base + 0x108;
699 hwif->sata_scr[SATA_CONTROL_OFFSET] = base + 0x100;
700 hwif->sata_misc[SATA_MISC_OFFSET] = base + 0x140;
701 hwif->sata_misc[SATA_PHY_OFFSET] = base + 0x144;
702 hwif->sata_misc[SATA_IEN_OFFSET] = base + 0x148;
705 memcpy(hwif->io_ports, hw.io_ports, sizeof(hwif->io_ports));
707 hwif->irq = dev->irq;
709 hwif->dma_base = (unsigned long)addr + (ch ? 0x08 : 0x00);
714 static int is_dev_seagate_sata(ide_drive_t *drive)
716 const char *s = &drive->id->model[0];
719 len = strnlen(s, sizeof(drive->id->model));
721 if ((len > 4) && (!memcmp(s, "ST", 2))) {
722 if ((!memcmp(s + len - 2, "AS", 2)) ||
723 (!memcmp(s + len - 3, "ASL", 3))) {
724 printk(KERN_INFO "%s: applying pessimistic Seagate "
725 "errata fix\n", drive->name);
733 * sil_quirkproc - post probe fixups
736 * Called after drive probe we use this to decide whether the
737 * Seagate fixup must be applied. This used to be in init_iops but
738 * that can occur before we know what drives are present.
741 static void __devinit sil_quirkproc(ide_drive_t *drive)
743 ide_hwif_t *hwif = drive->hwif;
745 /* Try and raise the rqsize */
746 if (!is_sata(hwif) || !is_dev_seagate_sata(drive))
751 * init_iops_siimage - set up iops
752 * @hwif: interface to set up
754 * Do the basic setup for the SIIMAGE hardware interface
755 * and then do the MMIO setup if we can. This is the first
756 * look in we get for setting up the hwif so that we
757 * can get the iops right before using them.
760 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
762 struct pci_dev *dev = to_pci_dev(hwif->dev);
764 hwif->hwif_data = NULL;
766 /* Pessimal until we finish probing */
769 if (pci_get_drvdata(dev) == NULL)
772 init_mmio_iops_siimage(hwif);
776 * ata66_siimage - check for 80 pin cable
777 * @hwif: interface to check
779 * Check for the presence of an ATA66 capable cable on the
783 static u8 __devinit ata66_siimage(ide_hwif_t *hwif)
785 struct pci_dev *dev = to_pci_dev(hwif->dev);
786 unsigned long addr = siimage_selreg(hwif, 0);
789 if (pci_get_drvdata(dev) == NULL)
790 pci_read_config_byte(dev, addr, &ata66);
792 ata66 = hwif->INB(addr);
794 return (ata66 & 0x01) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
798 * init_hwif_siimage - set up hwif structs
799 * @hwif: interface to set up
801 * We do the basic set up of the interface structure. The SIIMAGE
802 * requires several custom handlers so we override the default
803 * ide DMA handlers appropriately
806 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
808 u8 sata = is_sata(hwif);
810 hwif->set_pio_mode = &sil_set_pio_mode;
811 hwif->set_dma_mode = &sil_set_dma_mode;
812 hwif->quirkproc = &sil_quirkproc;
815 static int first = 1;
817 hwif->busproc = &sil_sata_busproc;
818 hwif->reset_poll = &sil_sata_reset_poll;
819 hwif->pre_reset = &sil_sata_pre_reset;
820 hwif->udma_filter = &sil_sata_udma_filter;
823 printk(KERN_INFO "siimage: For full SATA support you should use the libata sata_sil module.\n");
827 hwif->udma_filter = &sil_pata_udma_filter;
829 hwif->cable_detect = ata66_siimage;
831 if (hwif->dma_base == 0)
835 hwif->host_flags |= IDE_HFLAG_NO_ATAPI_DMA;
838 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
840 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
844 #define DECLARE_SII_DEV(name_str) \
847 .init_chipset = init_chipset_siimage, \
848 .init_iops = init_iops_siimage, \
849 .init_hwif = init_hwif_siimage, \
850 .host_flags = IDE_HFLAG_BOOTABLE, \
851 .pio_mask = ATA_PIO4, \
852 .mwdma_mask = ATA_MWDMA2, \
853 .udma_mask = ATA_UDMA6, \
856 static const struct ide_port_info siimage_chipsets[] __devinitdata = {
857 /* 0 */ DECLARE_SII_DEV("SiI680"),
858 /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
859 /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
863 * siimage_init_one - pci layer discovery entry
865 * @id: ident table entry
867 * Called by the PCI code when it finds an SI680 or SI3112 controller.
868 * We then use the IDE PCI generic helper to do most of the work.
871 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
873 return ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
876 static const struct pci_device_id siimage_pci_tbl[] = {
877 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), 0 },
878 #ifdef CONFIG_BLK_DEV_IDE_SATA
879 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_3112), 1 },
880 { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_1210SA), 2 },
884 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
886 static struct pci_driver driver = {
888 .id_table = siimage_pci_tbl,
889 .probe = siimage_init_one,
892 static int __init siimage_ide_init(void)
894 return ide_pci_register_driver(&driver);
897 module_init(siimage_ide_init);
899 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
900 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
901 MODULE_LICENSE("GPL");