drivers/ide/pci/sgiioc4.c

   1 /*
   2  * Copyright (c) 2003-2006 Silicon Graphics, Inc.  All Rights Reserved.
   3  * Copyright (C) 2008 MontaVista Software, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License
   7  * as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it would be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  12  *
  13  * You should have received a copy of the GNU General Public
  14  * License along with this program; if not, write the Free Software
  15  * Foundation, Inc., 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  16  *
  17  * For further information regarding this notice, see:
  18  *
  19  * http://oss.sgi.com/projects/GenInfo/NoticeExplan
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/types.h>
  24 #include <linux/pci.h>
  25 #include <linux/delay.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/ioport.h>
  29 #include <linux/blkdev.h>
  30 #include <linux/scatterlist.h>
  31 #include <linux/ioc4.h>
  32 #include <asm/io.h>
  33
  34 #include <linux/ide.h>
  35
  36 #define DRV_NAME "SGIIOC4"
  37
  38 /* IOC4 Specific Definitions */
  39 #define IOC4_CMD_OFFSET         0x100
  40 #define IOC4_CTRL_OFFSET        0x120
  41 #define IOC4_DMA_OFFSET         0x140
  42 #define IOC4_INTR_OFFSET        0x0
  43
  44 #define IOC4_TIMING             0x00
  45 #define IOC4_DMA_PTR_L          0x01
  46 #define IOC4_DMA_PTR_H          0x02
  47 #define IOC4_DMA_ADDR_L         0x03
  48 #define IOC4_DMA_ADDR_H         0x04
  49 #define IOC4_BC_DEV             0x05
  50 #define IOC4_BC_MEM             0x06
  51 #define IOC4_DMA_CTRL           0x07
  52 #define IOC4_DMA_END_ADDR       0x08
  53
  54 /* Bits in the IOC4 Control/Status Register */
  55 #define IOC4_S_DMA_START        0x01
  56 #define IOC4_S_DMA_STOP         0x02
  57 #define IOC4_S_DMA_DIR          0x04
  58 #define IOC4_S_DMA_ACTIVE       0x08
  59 #define IOC4_S_DMA_ERROR        0x10
  60 #define IOC4_ATA_MEMERR         0x02
  61
  62 /* Read/Write Directions */
  63 #define IOC4_DMA_WRITE          0x04
  64 #define IOC4_DMA_READ           0x00
  65
  66 /* Interrupt Register Offsets */
  67 #define IOC4_INTR_REG           0x03
  68 #define IOC4_INTR_SET           0x05
  69 #define IOC4_INTR_CLEAR         0x07
  70
  71 #define IOC4_IDE_CACHELINE_SIZE 128
  72 #define IOC4_CMD_CTL_BLK_SIZE   0x20
  73 #define IOC4_SUPPORTED_FIRMWARE_REV 46
  74
  75 typedef struct {
  76         u32 timing_reg0;
  77         u32 timing_reg1;
  78         u32 low_mem_ptr;
  79         u32 high_mem_ptr;
  80         u32 low_mem_addr;
  81         u32 high_mem_addr;
  82         u32 dev_byte_count;
  83         u32 mem_byte_count;
  84         u32 status;
  85 } ioc4_dma_regs_t;
  86
  87 /* Each Physical Region Descriptor Entry size is 16 bytes (2 * 64 bits) */
  88 /* IOC4 has only 1 IDE channel */
  89 #define IOC4_PRD_BYTES       16
  90 #define IOC4_PRD_ENTRIES     (PAGE_SIZE /(4*IOC4_PRD_BYTES))
  91
  92
  93 static void
  94 sgiioc4_init_hwif_ports(hw_regs_t * hw, unsigned long data_port,
  95                         unsigned long ctrl_port, unsigned long irq_port)
  96 {
  97         unsigned long reg = data_port;
  98         int i;
  99
 100         /* Registers are word (32 bit) aligned */
 101         for (i = 0; i <= 7; i++)
 102                 hw->io_ports_array[i] = reg + i * 4;
 103
 104         if (ctrl_port)
 105                 hw->io_ports.ctl_addr = ctrl_port;
 106
 107         if (irq_port)
 108                 hw->io_ports.irq_addr = irq_port;
 109 }
 110
 111 static void
 112 sgiioc4_maskproc(ide_drive_t * drive, int mask)
 113 {
 114         writeb(ATA_DEVCTL_OBS | (mask ? 2 : 0),
 115                (void __iomem *)drive->hwif->io_ports.ctl_addr);
 116 }
 117
 118 static int
 119 sgiioc4_checkirq(ide_hwif_t * hwif)
 120 {
 121         unsigned long intr_addr =
 122                 hwif->io_ports.irq_addr + IOC4_INTR_REG * 4;
 123
 124         if ((u8)readl((void __iomem *)intr_addr) & 0x03)
 125                 return 1;
 126
 127         return 0;
 128 }
 129
 130 static u8 sgiioc4_read_status(ide_hwif_t *);
 131
 132 static int
 133 sgiioc4_clearirq(ide_drive_t * drive)
 134 {
 135         u32 intr_reg;
 136         ide_hwif_t *hwif = HWIF(drive);
 137         struct ide_io_ports *io_ports = &hwif->io_ports;
 138         unsigned long other_ir = io_ports->irq_addr + (IOC4_INTR_REG << 2);
 139
 140         /* Code to check for PCI error conditions */
 141         intr_reg = readl((void __iomem *)other_ir);
 142         if (intr_reg & 0x03) { /* Valid IOC4-IDE interrupt */
 143                 /*
 144                  * Using sgiioc4_read_status to read the Status register has a
 145                  * side effect of clearing the interrupt.  The first read should
 146                  * clear it if it is set.  The second read should return
 147                  * a "clear" status if it got cleared.  If not, then spin
 148                  * for a bit trying to clear it.
 149                  */
 150                 u8 stat = sgiioc4_read_status(hwif);
 151                 int count = 0;
 152
 153                 stat = sgiioc4_read_status(hwif);
 154                 while ((stat & ATA_BUSY) && (count++ < 100)) {
 155                         udelay(1);
 156                         stat = sgiioc4_read_status(hwif);
 157                 }
 158
 159                 if (intr_reg & 0x02) {
 160                         struct pci_dev *dev = to_pci_dev(hwif->dev);
 161                         /* Error when transferring DMA data on PCI bus */
 162                         u32 pci_err_addr_low, pci_err_addr_high,
 163                             pci_stat_cmd_reg;
 164
 165                         pci_err_addr_low =
 166                                 readl((void __iomem *)io_ports->irq_addr);
 167                         pci_err_addr_high =
 168                                 readl((void __iomem *)(io_ports->irq_addr + 4));
 169                         pci_read_config_dword(dev, PCI_COMMAND,
 170                                               &pci_stat_cmd_reg);
 171                         printk(KERN_ERR
 172                                "%s(%s) : PCI Bus Error when doing DMA:"
 173                                    " status-cmd reg is 0x%x\n",
 174                                __func__, drive->name, pci_stat_cmd_reg);
 175                         printk(KERN_ERR
 176                                "%s(%s) : PCI Error Address is 0x%x%x\n",
 177                                __func__, drive->name,
 178                                pci_err_addr_high, pci_err_addr_low);
 179                         /* Clear the PCI Error indicator */
 180                         pci_write_config_dword(dev, PCI_COMMAND, 0x00000146);
 181                 }
 182
 183                 /* Clear the Interrupt, Error bits on the IOC4 */
 184                 writel(0x03, (void __iomem *)other_ir);
 185
 186                 intr_reg = readl((void __iomem *)other_ir);
 187         }
 188
 189         return intr_reg & 3;
 190 }
 191
 192 static void sgiioc4_dma_start(ide_drive_t *drive)
 193 {
 194         ide_hwif_t *hwif = HWIF(drive);
 195         unsigned long ioc4_dma_addr = hwif->dma_base + IOC4_DMA_CTRL * 4;
 196         unsigned int reg = readl((void __iomem *)ioc4_dma_addr);
 197         unsigned int temp_reg = reg | IOC4_S_DMA_START;
 198
 199         writel(temp_reg, (void __iomem *)ioc4_dma_addr);
 200 }
 201
 202 static u32
 203 sgiioc4_ide_dma_stop(ide_hwif_t *hwif, u64 dma_base)
 204 {
 205         unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 206         u32     ioc4_dma;
 207         int     count;
 208
 209         count = 0;
 210         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 211         while ((ioc4_dma & IOC4_S_DMA_STOP) && (count++ < 200)) {
 212                 udelay(1);
 213                 ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 214         }
 215         return ioc4_dma;
 216 }
 217
 218 /* Stops the IOC4 DMA Engine */
 219 static int sgiioc4_dma_end(ide_drive_t *drive)
 220 {
 221         u32 ioc4_dma, bc_dev, bc_mem, num, valid = 0, cnt = 0;
 222         ide_hwif_t *hwif = HWIF(drive);
 223         unsigned long dma_base = hwif->dma_base;
 224         int dma_stat = 0;
 225         unsigned long *ending_dma = ide_get_hwifdata(hwif);
 226
 227         writel(IOC4_S_DMA_STOP, (void __iomem *)(dma_base + IOC4_DMA_CTRL * 4));
 228
 229         ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 230
 231         if (ioc4_dma & IOC4_S_DMA_STOP) {
 232                 printk(KERN_ERR
 233                        "%s(%s): IOC4 DMA STOP bit is still 1 :"
 234                        "ioc4_dma_reg 0x%x\n",
 235                        __func__, drive->name, ioc4_dma);
 236                 dma_stat = 1;
 237         }
 238
 239         /*
 240          * The IOC4 will DMA 1's to the ending dma area to indicate that
 241          * previous data DMA is complete.  This is necessary because of relaxed
 242          * ordering between register reads and DMA writes on the Altix.
 243          */
 244         while ((cnt++ < 200) && (!valid)) {
 245                 for (num = 0; num < 16; num++) {
 246                         if (ending_dma[num]) {
 247                                 valid = 1;
 248                                 break;
 249                         }
 250                 }
 251                 udelay(1);
 252         }
 253         if (!valid) {
 254                 printk(KERN_ERR "%s(%s) : DMA incomplete\n", __func__,
 255                        drive->name);
 256                 dma_stat = 1;
 257         }
 258
 259         bc_dev = readl((void __iomem *)(dma_base + IOC4_BC_DEV * 4));
 260         bc_mem = readl((void __iomem *)(dma_base + IOC4_BC_MEM * 4));
 261
 262         if ((bc_dev & 0x01FF) || (bc_mem & 0x1FF)) {
 263                 if (bc_dev > bc_mem + 8) {
 264                         printk(KERN_ERR
 265                                "%s(%s): WARNING!! byte_count_dev %d "
 266                                "!= byte_count_mem %d\n",
 267                                __func__, drive->name, bc_dev, bc_mem);
 268                 }
 269         }
 270
 271         drive->waiting_for_dma = 0;
 272         ide_destroy_dmatable(drive);
 273
 274         return dma_stat;
 275 }
 276
 277 static void sgiioc4_set_dma_mode(ide_drive_t *drive, const u8 speed)
 278 {
 279 }
 280
 281 /* returns 1 if dma irq issued, 0 otherwise */
 282 static int sgiioc4_dma_test_irq(ide_drive_t *drive)
 283 {
 284         return sgiioc4_checkirq(HWIF(drive));
 285 }
 286
 287 static void sgiioc4_dma_host_set(ide_drive_t *drive, int on)
 288 {
 289         if (!on)
 290                 sgiioc4_clearirq(drive);
 291 }
 292
 293 static void
 294 sgiioc4_resetproc(ide_drive_t * drive)
 295 {
 296         sgiioc4_dma_end(drive);
 297         sgiioc4_clearirq(drive);
 298 }
 299
 300 static void
 301 sgiioc4_dma_lost_irq(ide_drive_t * drive)
 302 {
 303         sgiioc4_resetproc(drive);
 304
 305         ide_dma_lost_irq(drive);
 306 }
 307
 308 static u8 sgiioc4_read_status(ide_hwif_t *hwif)
 309 {
 310         unsigned long port = hwif->io_ports.status_addr;
 311         u8 reg = (u8) readb((void __iomem *) port);
 312
 313         if ((port & 0xFFF) == 0x11C) {  /* Status register of IOC4 */
 314                 if (!(reg & ATA_BUSY)) { /* Not busy... check for interrupt */
 315                         unsigned long other_ir = port - 0x110;
 316                         unsigned int intr_reg = (u32) readl((void __iomem *) other_ir);
 317
 318                         /* Clear the Interrupt, Error bits on the IOC4 */
 319                         if (intr_reg & 0x03) {
 320                                 writel(0x03, (void __iomem *) other_ir);
 321                                 intr_reg = (u32) readl((void __iomem *) other_ir);
 322                         }
 323                 }
 324         }
 325
 326         return reg;
 327 }
 328
 329 /* Creates a dma map for the scatter-gather list entries */
 330 static int __devinit
 331 ide_dma_sgiioc4(ide_hwif_t *hwif, const struct ide_port_info *d)
 332 {
 333         struct pci_dev *dev = to_pci_dev(hwif->dev);
 334         unsigned long dma_base = pci_resource_start(dev, 0) + IOC4_DMA_OFFSET;
 335         void __iomem *virt_dma_base;
 336         int num_ports = sizeof (ioc4_dma_regs_t);
 337         void *pad;
 338
 339         if (dma_base == 0)
 340                 return -1;
 341
 342         printk(KERN_INFO "    %s: MMIO-DMA\n", hwif->name);
 343
 344         if (request_mem_region(dma_base, num_ports, hwif->name) == NULL) {
 345                 printk(KERN_ERR "%s(%s) -- ERROR: addresses 0x%08lx to 0x%08lx "
 346                        "already in use\n", __func__, hwif->name,
 347                        dma_base, dma_base + num_ports - 1);
 348                 return -1;
 349         }
 350
 351         virt_dma_base = ioremap(dma_base, num_ports);
 352         if (virt_dma_base == NULL) {
 353                 printk(KERN_ERR "%s(%s) -- ERROR: unable to map addresses "
 354                        "0x%lx to 0x%lx\n", __func__, hwif->name,
 355                        dma_base, dma_base + num_ports - 1);
 356                 goto dma_remap_failure;
 357         }
 358         hwif->dma_base = (unsigned long) virt_dma_base;
 359
 360         hwif->dmatable_cpu = pci_alloc_consistent(dev,
 361                                           IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 362                                           &hwif->dmatable_dma);
 363
 364         if (!hwif->dmatable_cpu)
 365                 goto dma_pci_alloc_failure;
 366
 367         hwif->sg_max_nents = IOC4_PRD_ENTRIES;
 368
 369         pad = pci_alloc_consistent(dev, IOC4_IDE_CACHELINE_SIZE,
 370                                    (dma_addr_t *)&hwif->extra_base);
 371         if (pad) {
 372                 ide_set_hwifdata(hwif, pad);
 373                 return 0;
 374         }
 375
 376         pci_free_consistent(dev, IOC4_PRD_ENTRIES * IOC4_PRD_BYTES,
 377                             hwif->dmatable_cpu, hwif->dmatable_dma);
 378         printk(KERN_ERR "%s(%s) -- ERROR: Unable to allocate DMA maps\n",
 379                __func__, hwif->name);
 380         printk(KERN_INFO "%s: changing from DMA to PIO mode", hwif->name);
 381
 382 dma_pci_alloc_failure:
 383         iounmap(virt_dma_base);
 384
 385 dma_remap_failure:
 386         release_mem_region(dma_base, num_ports);
 387
 388         return -1;
 389 }
 390
 391 /* Initializes the IOC4 DMA Engine */
 392 static void
 393 sgiioc4_configure_for_dma(int dma_direction, ide_drive_t * drive)
 394 {
 395         u32 ioc4_dma;
 396         ide_hwif_t *hwif = HWIF(drive);
 397         unsigned long dma_base = hwif->dma_base;
 398         unsigned long ioc4_dma_addr = dma_base + IOC4_DMA_CTRL * 4;
 399         u32 dma_addr, ending_dma_addr;
 400
 401         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 402
 403         if (ioc4_dma & IOC4_S_DMA_ACTIVE) {
 404                 printk(KERN_WARNING
 405                         "%s(%s):Warning!! DMA from previous transfer was still active\n",
 406                        __func__, drive->name);
 407                 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 408                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 409
 410                 if (ioc4_dma & IOC4_S_DMA_STOP)
 411                         printk(KERN_ERR
 412                                "%s(%s) : IOC4 Dma STOP bit is still 1\n",
 413                                __func__, drive->name);
 414         }
 415
 416         ioc4_dma = readl((void __iomem *)ioc4_dma_addr);
 417         if (ioc4_dma & IOC4_S_DMA_ERROR) {
 418                 printk(KERN_WARNING
 419                        "%s(%s) : Warning!! - DMA Error during Previous"
 420                        " transfer | status 0x%x\n",
 421                        __func__, drive->name, ioc4_dma);
 422                 writel(IOC4_S_DMA_STOP, (void __iomem *)ioc4_dma_addr);
 423                 ioc4_dma = sgiioc4_ide_dma_stop(hwif, dma_base);
 424
 425                 if (ioc4_dma & IOC4_S_DMA_STOP)
 426                         printk(KERN_ERR
 427                                "%s(%s) : IOC4 DMA STOP bit is still 1\n",
 428                                __func__, drive->name);
 429         }
 430
 431         /* Address of the Scatter Gather List */
 432         dma_addr = cpu_to_le32(hwif->dmatable_dma);
 433         writel(dma_addr, (void __iomem *)(dma_base + IOC4_DMA_PTR_L * 4));
 434
 435         /* Address of the Ending DMA */
 436         memset(ide_get_hwifdata(hwif), 0, IOC4_IDE_CACHELINE_SIZE);
 437         ending_dma_addr = cpu_to_le32(hwif->extra_base);
 438         writel(ending_dma_addr, (void __iomem *)(dma_base + IOC4_DMA_END_ADDR * 4));
 439
 440         writel(dma_direction, (void __iomem *)ioc4_dma_addr);
 441         drive->waiting_for_dma = 1;
 442 }
 443
 444 /* IOC4 Scatter Gather list Format                                       */
 445 /* 128 Bit entries to support 64 bit addresses in the future             */
 446 /* The Scatter Gather list Entry should be in the BIG-ENDIAN Format      */
 447 /* --------------------------------------------------------------------- */
 448 /* | Upper 32 bits - Zero           |           Lower 32 bits- address | */
 449 /* --------------------------------------------------------------------- */
 450 /* | Upper 32 bits - Zero           |EOL| 15 unused     | 16 Bit Length| */
 451 /* --------------------------------------------------------------------- */
 452 /* Creates the scatter gather list, DMA Table */
 453 static unsigned int
 454 sgiioc4_build_dma_table(ide_drive_t * drive, struct request *rq, int ddir)
 455 {
 456         ide_hwif_t *hwif = HWIF(drive);
 457         unsigned int *table = hwif->dmatable_cpu;
 458         unsigned int count = 0, i = 1;
 459         struct scatterlist *sg;
 460
 461         hwif->sg_nents = i = ide_build_sglist(drive, rq);
 462
 463         if (!i)
 464                 return 0;       /* sglist of length Zero */
 465
 466         sg = hwif->sg_table;
 467         while (i && sg_dma_len(sg)) {
 468                 dma_addr_t cur_addr;
 469                 int cur_len;
 470                 cur_addr = sg_dma_address(sg);
 471                 cur_len = sg_dma_len(sg);
 472
 473                 while (cur_len) {
 474                         if (count++ >= IOC4_PRD_ENTRIES) {
 475                                 printk(KERN_WARNING
 476                                        "%s: DMA table too small\n",
 477                                        drive->name);
 478                                 goto use_pio_instead;
 479                         } else {
 480                                 u32 bcount =
 481                                     0x10000 - (cur_addr & 0xffff);
 482
 483                                 if (bcount > cur_len)
 484                                         bcount = cur_len;
 485
 486                                 /* put the addr, length in
 487                                  * the IOC4 dma-table format */
 488                                 *table = 0x0;
 489                                 table++;
 490                                 *table = cpu_to_be32(cur_addr);
 491                                 table++;
 492                                 *table = 0x0;
 493                                 table++;
 494
 495                                 *table = cpu_to_be32(bcount);
 496                                 table++;
 497
 498                                 cur_addr += bcount;
 499                                 cur_len -= bcount;
 500                         }
 501                 }
 502
 503                 sg = sg_next(sg);
 504                 i--;
 505         }
 506
 507         if (count) {
 508                 table--;
 509                 *table |= cpu_to_be32(0x80000000);
 510                 return count;
 511         }
 512
 513 use_pio_instead:
 514         ide_destroy_dmatable(drive);
 515
 516         return 0;               /* revert to PIO for this request */
 517 }
 518
 519 static int sgiioc4_dma_setup(ide_drive_t *drive)
 520 {
 521         struct request *rq = HWGROUP(drive)->rq;
 522         unsigned int count = 0;
 523         int ddir;
 524
 525         if (rq_data_dir(rq))
 526                 ddir = PCI_DMA_TODEVICE;
 527         else
 528                 ddir = PCI_DMA_FROMDEVICE;
 529
 530         if (!(count = sgiioc4_build_dma_table(drive, rq, ddir))) {
 531                 /* try PIO instead of DMA */
 532                 ide_map_sg(drive, rq);
 533                 return 1;
 534         }
 535
 536         if (rq_data_dir(rq))
 537                 /* Writes TO the IOC4 FROM Main Memory */
 538                 ddir = IOC4_DMA_READ;
 539         else
 540                 /* Writes FROM the IOC4 TO Main Memory */
 541                 ddir = IOC4_DMA_WRITE;
 542
 543         sgiioc4_configure_for_dma(ddir, drive);
 544
 545         return 0;
 546 }
 547
 548 static const struct ide_tp_ops sgiioc4_tp_ops = {
 549         .exec_command           = ide_exec_command,
 550         .read_status            = sgiioc4_read_status,
 551         .read_altstatus         = ide_read_altstatus,
 552         .read_sff_dma_status    = ide_read_sff_dma_status,
 553
 554         .set_irq                = ide_set_irq,
 555
 556         .tf_load                = ide_tf_load,
 557         .tf_read                = ide_tf_read,
 558
 559         .input_data             = ide_input_data,
 560         .output_data            = ide_output_data,
 561 };
 562
 563 static const struct ide_port_ops sgiioc4_port_ops = {
 564         .set_dma_mode           = sgiioc4_set_dma_mode,
 565         /* reset DMA engine, clear IRQs */
 566         .resetproc              = sgiioc4_resetproc,
 567         /* mask on/off NIEN register */
 568         .maskproc               = sgiioc4_maskproc,
 569 };
 570
 571 static const struct ide_dma_ops sgiioc4_dma_ops = {
 572         .dma_host_set           = sgiioc4_dma_host_set,
 573         .dma_setup              = sgiioc4_dma_setup,
 574         .dma_start              = sgiioc4_dma_start,
 575         .dma_end                = sgiioc4_dma_end,
 576         .dma_test_irq           = sgiioc4_dma_test_irq,
 577         .dma_lost_irq           = sgiioc4_dma_lost_irq,
 578         .dma_timeout            = ide_dma_timeout,
 579 };
 580
 581 static const struct ide_port_info sgiioc4_port_info __devinitdata = {
 582         .name                   = DRV_NAME,
 583         .chipset                = ide_pci,
 584         .init_dma               = ide_dma_sgiioc4,
 585         .tp_ops                 = &sgiioc4_tp_ops,
 586         .port_ops               = &sgiioc4_port_ops,
 587         .dma_ops                = &sgiioc4_dma_ops,
 588         .host_flags             = IDE_HFLAG_MMIO,
 589         .mwdma_mask             = ATA_MWDMA2_ONLY,
 590 };
 591
 592 static int __devinit
 593 sgiioc4_ide_setup_pci_device(struct pci_dev *dev)
 594 {
 595         unsigned long cmd_base, irqport;
 596         unsigned long bar0, cmd_phys_base, ctl;
 597         void __iomem *virt_base;
 598         struct ide_host *host;
 599         hw_regs_t hw, *hws[] = { &hw, NULL, NULL, NULL };
 600         struct ide_port_info d = sgiioc4_port_info;
 601         int rc;
 602
 603         /*  Get the CmdBlk and CtrlBlk Base Registers */
 604         bar0 = pci_resource_start(dev, 0);
 605         virt_base = ioremap(bar0, pci_resource_len(dev, 0));
 606         if (virt_base == NULL) {
 607                 printk(KERN_ERR "%s: Unable to remap BAR 0 address: 0x%lx\n",
 608                                 DRV_NAME, bar0);
 609                 return -ENOMEM;
 610         }
 611         cmd_base = (unsigned long) virt_base + IOC4_CMD_OFFSET;
 612         ctl = (unsigned long) virt_base + IOC4_CTRL_OFFSET;
 613         irqport = (unsigned long) virt_base + IOC4_INTR_OFFSET;
 614
 615         cmd_phys_base = bar0 + IOC4_CMD_OFFSET;
 616         if (request_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE,
 617                                DRV_NAME) == NULL) {
 618                 printk(KERN_ERR "%s %s -- ERROR: addresses 0x%08lx to 0x%08lx "
 619                        "already in use\n", DRV_NAME, pci_name(dev),
 620                        cmd_phys_base, cmd_phys_base + IOC4_CMD_CTL_BLK_SIZE);
 621                 return -EBUSY;
 622         }
 623
 624         /* Initialize the IO registers */
 625         memset(&hw, 0, sizeof(hw));
 626         sgiioc4_init_hwif_ports(&hw, cmd_base, ctl, irqport);
 627         hw.irq = dev->irq;
 628         hw.chipset = ide_pci;
 629         hw.dev = &dev->dev;
 630
 631         /* Initializing chipset IRQ Registers */
 632         writel(0x03, (void __iomem *)(irqport + IOC4_INTR_SET * 4));
 633
 634         host = ide_host_alloc(&d, hws);
 635         if (host == NULL) {
 636                 rc = -ENOMEM;
 637                 goto err;
 638         }
 639
 640         rc = ide_host_register(host, &d, hws);
 641         if (rc)
 642                 goto err_free;
 643
 644         return 0;
 645 err_free:
 646         ide_host_free(host);
 647 err:
 648         release_mem_region(cmd_phys_base, IOC4_CMD_CTL_BLK_SIZE);
 649         iounmap(virt_base);
 650         return rc;
 651 }
 652
 653 static unsigned int __devinit
 654 pci_init_sgiioc4(struct pci_dev *dev)
 655 {
 656         int ret;
 657
 658         printk(KERN_INFO "%s: IDE controller at PCI slot %s, revision %d\n",
 659                          DRV_NAME, pci_name(dev), dev->revision);
 660
 661         if (dev->revision < IOC4_SUPPORTED_FIRMWARE_REV) {
 662                 printk(KERN_ERR "Skipping %s IDE controller in slot %s: "
 663                                 "firmware is obsolete - please upgrade to "
 664                                 "revision46 or higher\n",
 665                                 DRV_NAME, pci_name(dev));
 666                 ret = -EAGAIN;
 667                 goto out;
 668         }
 669         ret = sgiioc4_ide_setup_pci_device(dev);
 670 out:
 671         return ret;
 672 }
 673
 674 int
 675 ioc4_ide_attach_one(struct ioc4_driver_data *idd)
 676 {
 677         /* PCI-RT does not bring out IDE connection.
 678          * Do not attach to this particular IOC4.
 679          */
 680         if (idd->idd_variant == IOC4_VARIANT_PCI_RT)
 681                 return 0;
 682
 683         return pci_init_sgiioc4(idd->idd_pdev);
 684 }
 685
 686 static struct ioc4_submodule ioc4_ide_submodule = {
 687         .is_name = "IOC4_ide",
 688         .is_owner = THIS_MODULE,
 689         .is_probe = ioc4_ide_attach_one,
 690 /*      .is_remove = ioc4_ide_remove_one,       */
 691 };
 692
 693 static int __init ioc4_ide_init(void)
 694 {
 695         return ioc4_register_submodule(&ioc4_ide_submodule);
 696 }
 697
 698 late_initcall(ioc4_ide_init); /* Call only after IDE init is done */
 699
 700 MODULE_AUTHOR("Aniket Malatpure/Jeremy Higdon");
 701 MODULE_DESCRIPTION("IDE PCI driver module for SGI IOC4 Base-IO Card");
 702 MODULE_LICENSE("GPL");