drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *
   7  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   8  *  compiled into the kernel if you have more than one card installed.
   9  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  10  *  safe chipset tuning, including this support is harmless
  11  *
  12  *  Promise Ultra66 cards with BIOS v1.11 this
  13  *  compiled into the kernel if you have more than one card installed.
  14  *
  15  *  Promise Ultra100 cards.
  16  *
  17  *  The latest chipset code will support the following ::
  18  *  Three Ultra33 controllers and 12 drives.
  19  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  20  *  The 8/4 ratio is a BIOS code limit by promise.
  21  *
  22  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  23  *
  24  */
  25
  26 /*
  27  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  28  *  Author: Frank Tiernan (frankt@promise.com)
  29  *  Released under terms of General Public License
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #define PDC202XX_DEBUG_DRIVE_INFO       0
  50
  51 static const char *pdc_quirk_drives[] = {
  52         "QUANTUM FIREBALLlct08 08",
  53         "QUANTUM FIREBALLP KA6.4",
  54         "QUANTUM FIREBALLP KA9.1",
  55         "QUANTUM FIREBALLP LM20.4",
  56         "QUANTUM FIREBALLP KX13.6",
  57         "QUANTUM FIREBALLP KX20.5",
  58         "QUANTUM FIREBALLP KX27.3",
  59         "QUANTUM FIREBALLP LM20.5",
  60         NULL
  61 };
  62
  63 /* A Register */
  64 #define SYNC_ERRDY_EN   0xC0
  65
  66 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  67 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  68 #define IORDY_EN        0x20    /* PIO: IOREADY */
  69 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  70
  71 #define PA3             0x08    /* PIO"A" timing */
  72 #define PA2             0x04    /* PIO"A" timing */
  73 #define PA1             0x02    /* PIO"A" timing */
  74 #define PA0             0x01    /* PIO"A" timing */
  75
  76 /* B Register */
  77
  78 #define MB2             0x80    /* DMA"B" timing */
  79 #define MB1             0x40    /* DMA"B" timing */
  80 #define MB0             0x20    /* DMA"B" timing */
  81
  82 #define PB4             0x10    /* PIO_FORCE 1:0 */
  83
  84 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  85 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  86 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  87 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  88
  89 /* C Register */
  90 #define IORDYp_NO_SPEED 0x4F
  91 #define SPEED_DIS       0x0F
  92
  93 #define DMARQp          0x80
  94 #define IORDYp          0x40
  95 #define DMAR_EN         0x20
  96 #define DMAW_EN         0x10
  97
  98 #define MC3             0x08    /* DMA"C" timing */
  99 #define MC2             0x04    /* DMA"C" timing */
 100 #define MC1             0x02    /* DMA"C" timing */
 101 #define MC0             0x01    /* DMA"C" timing */
 102
 103 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 104 {
 105         ide_hwif_t *hwif        = HWIF(drive);
 106         struct pci_dev *dev     = hwif->pci_dev;
 107         u8 drive_pci            = 0x60 + (drive->dn << 2);
 108         u8 speed                = ide_rate_filter(drive, xferspeed);
 109
 110         u32                     drive_conf;
 111         u8                      AP, BP, CP, DP;
 112         u8                      TA = 0, TB = 0, TC = 0;
 113
 114         if (drive->media != ide_disk &&
 115                 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
 116                 return -1;
 117
 118         pci_read_config_dword(dev, drive_pci, &drive_conf);
 119         pci_read_config_byte(dev, (drive_pci), &AP);
 120         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 121         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 122         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 123
 124         if (speed < XFER_SW_DMA_0) {
 125                 if ((AP & 0x0F) || (BP & 0x07)) {
 126                         /* clear PIO modes of lower 8421 bits of A Register */
 127                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 128                         pci_read_config_byte(dev, (drive_pci), &AP);
 129
 130                         /* clear PIO modes of lower 421 bits of B Register */
 131                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 132                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 133
 134                         pci_read_config_byte(dev, (drive_pci), &AP);
 135                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 136                 }
 137         } else {
 138                 if ((BP & 0xF0) && (CP & 0x0F)) {
 139                         /* clear DMA modes of upper 842 bits of B Register */
 140                         /* clear PIO forced mode upper 1 bit of B Register */
 141                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 142                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 143
 144                         /* clear DMA modes of lower 8421 bits of C Register */
 145                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 146                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 147                 }
 148         }
 149
 150         pci_read_config_byte(dev, (drive_pci), &AP);
 151         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 152         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 153
 154         switch(speed) {
 155                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 156                 case XFER_UDMA_5:
 157                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 158                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 159                 case XFER_UDMA_3:
 160                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 161                 case XFER_UDMA_0:
 162                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 163                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 164                 case XFER_MW_DMA_0:
 165                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 166                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 167                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 168                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 169                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 170                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 171                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 172                 case XFER_PIO_0:
 173                 default:                TA = 0x09; TB = 0x13; break;
 174         }
 175
 176         if (speed < XFER_SW_DMA_0) {
 177                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 178                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 179         } else {
 180                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 181                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 182         }
 183
 184 #if PDC202XX_DEBUG_DRIVE_INFO
 185         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 186                 drive->name, ide_xfer_verbose(speed),
 187                 drive->dn, drive_conf);
 188                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 189         printk("0x%08x\n", drive_conf);
 190 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 191
 192         return (ide_config_drive_speed(drive, speed));
 193 }
 194
 195
 196 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
 197 {
 198         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 199         pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
 200 }
 201
 202 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 203 {
 204         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 205         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 206         return (CIS & mask) ? 1 : 0;
 207 }
 208
 209 /*
 210  * Set the control register to use the 66MHz system
 211  * clock for UDMA 3/4/5 mode operation when necessary.
 212  *
 213  * It may also be possible to leave the 66MHz clock on
 214  * and readjust the timing parameters.
 215  */
 216 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 217 {
 218         unsigned long clock_reg = hwif->dma_master + 0x11;
 219         u8 clock = inb(clock_reg);
 220
 221         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 222 }
 223
 224 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 225 {
 226         unsigned long clock_reg = hwif->dma_master + 0x11;
 227         u8 clock = inb(clock_reg);
 228
 229         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 230 }
 231
 232 static int config_chipset_for_dma (ide_drive_t *drive)
 233 {
 234         struct hd_driveid *id   = drive->id;
 235         ide_hwif_t *hwif        = HWIF(drive);
 236         struct pci_dev *dev     = hwif->pci_dev;
 237         u32 drive_conf          = 0;
 238         u8 drive_pci            = 0x60 + (drive->dn << 2);
 239         u8 test1 = 0, test2 = 0, speed = -1;
 240         u8 AP = 0;
 241
 242         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 243                 pdc_old_disable_66MHz_clock(drive->hwif);
 244
 245         drive_pci = 0x60 + (drive->dn << 2);
 246         pci_read_config_dword(dev, drive_pci, &drive_conf);
 247         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 248                 goto chipset_is_set;
 249
 250         pci_read_config_byte(dev, drive_pci, &test1);
 251         if (!(test1 & SYNC_ERRDY_EN)) {
 252                 if (drive->select.b.unit & 0x01) {
 253                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 254                         if ((test2 & SYNC_ERRDY_EN) &&
 255                             !(test1 & SYNC_ERRDY_EN)) {
 256                                 pci_write_config_byte(dev, drive_pci,
 257                                         test1|SYNC_ERRDY_EN);
 258                         }
 259                 } else {
 260                         pci_write_config_byte(dev, drive_pci,
 261                                 test1|SYNC_ERRDY_EN);
 262                 }
 263         }
 264
 265 chipset_is_set:
 266
 267         pci_read_config_byte(dev, (drive_pci), &AP);
 268         if (id->capability & 4) /* IORDY_EN */
 269                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 270         pci_read_config_byte(dev, (drive_pci), &AP);
 271         if (drive->media == ide_disk)   /* PREFETCH_EN */
 272                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 273
 274         speed = ide_max_dma_mode(drive);
 275
 276         if (!(speed)) {
 277                 /* restore original pci-config space */
 278                 pci_write_config_dword(dev, drive_pci, drive_conf);
 279                 return 0;
 280         }
 281
 282         (void) hwif->speedproc(drive, speed);
 283         return ide_dma_enable(drive);
 284 }
 285
 286 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 287 {
 288         drive->init_speed = 0;
 289
 290         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 291                 return 0;
 292
 293         if (ide_use_fast_pio(drive))
 294                 pdc202xx_tune_drive(drive, 255);
 295
 296         return -1;
 297 }
 298
 299 static int pdc202xx_quirkproc (ide_drive_t *drive)
 300 {
 301         const char **list, *model = drive->id->model;
 302
 303         for (list = pdc_quirk_drives; *list != NULL; list++)
 304                 if (strstr(model, *list) != NULL)
 305                         return 2;
 306         return 0;
 307 }
 308
 309 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 310 {
 311         if (drive->current_speed > XFER_UDMA_2)
 312                 pdc_old_enable_66MHz_clock(drive->hwif);
 313         if (drive->media != ide_disk || drive->addressing == 1) {
 314                 struct request *rq      = HWGROUP(drive)->rq;
 315                 ide_hwif_t *hwif        = HWIF(drive);
 316                 unsigned long high_16   = hwif->dma_master;
 317                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 318                 u32 word_count  = 0;
 319                 u8 clock = inb(high_16 + 0x11);
 320
 321                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 322                 word_count = (rq->nr_sectors << 8);
 323                 word_count = (rq_data_dir(rq) == READ) ?
 324                                         word_count | 0x05000000 :
 325                                         word_count | 0x06000000;
 326                 outl(word_count, atapi_reg);
 327         }
 328         ide_dma_start(drive);
 329 }
 330
 331 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 332 {
 333         if (drive->media != ide_disk || drive->addressing == 1) {
 334                 ide_hwif_t *hwif        = HWIF(drive);
 335                 unsigned long high_16   = hwif->dma_master;
 336                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 337                 u8 clock                = 0;
 338
 339                 outl(0, atapi_reg); /* zero out extra */
 340                 clock = inb(high_16 + 0x11);
 341                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 342         }
 343         if (drive->current_speed > XFER_UDMA_2)
 344                 pdc_old_disable_66MHz_clock(drive->hwif);
 345         return __ide_dma_end(drive);
 346 }
 347
 348 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 349 {
 350         ide_hwif_t *hwif        = HWIF(drive);
 351         unsigned long high_16   = hwif->dma_master;
 352         u8 dma_stat             = inb(hwif->dma_status);
 353         u8 sc1d                 = inb(high_16 + 0x001d);
 354
 355         if (hwif->channel) {
 356                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 357                 if ((sc1d & 0x50) == 0x50)
 358                         goto somebody_else;
 359                 else if ((sc1d & 0x40) == 0x40)
 360                         return (dma_stat & 4) == 4;
 361         } else {
 362                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 363                 if ((sc1d & 0x05) == 0x05)
 364                         goto somebody_else;
 365                 else if ((sc1d & 0x04) == 0x04)
 366                         return (dma_stat & 4) == 4;
 367         }
 368 somebody_else:
 369         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 370 }
 371
 372 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 373 {
 374         if (HWIF(drive)->resetproc != NULL)
 375                 HWIF(drive)->resetproc(drive);
 376         return __ide_dma_lostirq(drive);
 377 }
 378
 379 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 380 {
 381         if (HWIF(drive)->resetproc != NULL)
 382                 HWIF(drive)->resetproc(drive);
 383         return __ide_dma_timeout(drive);
 384 }
 385
 386 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 387 {
 388         unsigned long high_16   = hwif->dma_master;
 389         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 390
 391         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 392         mdelay(100);
 393         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 394         mdelay(2000);   /* 2 seconds ?! */
 395
 396         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 397                 hwif->channel ? "Secondary" : "Primary");
 398 }
 399
 400 static void pdc202xx_reset (ide_drive_t *drive)
 401 {
 402         ide_hwif_t *hwif        = HWIF(drive);
 403         ide_hwif_t *mate        = hwif->mate;
 404
 405         pdc202xx_reset_host(hwif);
 406         pdc202xx_reset_host(mate);
 407         pdc202xx_tune_drive(drive, 255);
 408 }
 409
 410 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 411                                                         const char *name)
 412 {
 413         /* This doesn't appear needed */
 414         if (dev->resource[PCI_ROM_RESOURCE].start) {
 415                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 416                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 417                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 418                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 419         }
 420
 421         return dev->irq;
 422 }
 423
 424 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 425 {
 426         struct pci_dev *dev = hwif->pci_dev;
 427
 428         /* PDC20265 has problems with large LBA48 requests */
 429         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 430             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 431                 hwif->rqsize = 256;
 432
 433         hwif->autodma = 0;
 434         hwif->tuneproc  = &pdc202xx_tune_drive;
 435         hwif->quirkproc = &pdc202xx_quirkproc;
 436
 437         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 438                 hwif->resetproc = &pdc202xx_reset;
 439
 440         hwif->speedproc = &pdc202xx_tune_chipset;
 441
 442         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 443
 444         hwif->ultra_mask = hwif->cds->udma_mask;
 445         hwif->mwdma_mask = 0x07;
 446         hwif->swdma_mask = 0x07;
 447         hwif->atapi_dma = 1;
 448
 449         hwif->err_stops_fifo = 1;
 450
 451         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 452         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 453         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 454
 455         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 456                 if (!(hwif->udma_four))
 457                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 458                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 459                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 460         }
 461         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 462
 463         if (!noautodma)
 464                 hwif->autodma = 1;
 465         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 466 }
 467
 468 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 469 {
 470         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 471
 472         if (hwif->channel) {
 473                 ide_setup_dma(hwif, dmabase, 8);
 474                 return;
 475         }
 476
 477         udma_speed_flag = inb(dmabase | 0x1f);
 478         primary_mode    = inb(dmabase | 0x1a);
 479         secondary_mode  = inb(dmabase | 0x1b);
 480         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 481                 "Primary %s Mode " \
 482                 "Secondary %s Mode.\n", hwif->cds->name,
 483                 (udma_speed_flag & 1) ? "EN" : "DIS",
 484                 (primary_mode & 1) ? "MASTER" : "PCI",
 485                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 486
 487 #ifdef CONFIG_PDC202XX_BURST
 488         if (!(udma_speed_flag & 1)) {
 489                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 490                         hwif->cds->name, udma_speed_flag,
 491                         (udma_speed_flag|1));
 492                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 493                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 494         }
 495 #endif /* CONFIG_PDC202XX_BURST */
 496
 497         ide_setup_dma(hwif, dmabase, 8);
 498 }
 499
 500 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 501                                            ide_pci_device_t *d)
 502 {
 503         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 504                 u8 irq = 0, irq2 = 0;
 505                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 506                 /* 0xbc */
 507                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 508                 if (irq != irq2) {
 509                         pci_write_config_byte(dev,
 510                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 511                         printk(KERN_INFO "%s: pci-config space interrupt "
 512                                 "mirror fixed.\n", d->name);
 513                 }
 514         }
 515         return ide_setup_pci_device(dev, d);
 516 }
 517
 518 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 519                                          ide_pci_device_t *d)
 520 {
 521         if ((dev->bus->self) &&
 522             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 523             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 524              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 525                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 526                         "attached to I2O RAID controller.\n");
 527                 return -ENODEV;
 528         }
 529         return ide_setup_pci_device(dev, d);
 530 }
 531
 532 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 533                                          ide_pci_device_t *d)
 534 {
 535         return ide_setup_pci_device(dev, d);
 536 }
 537
 538 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 539         {       /* 0 */
 540                 .name           = "PDC20246",
 541                 .init_setup     = init_setup_pdc202ata4,
 542                 .init_chipset   = init_chipset_pdc202xx,
 543                 .init_hwif      = init_hwif_pdc202xx,
 544                 .init_dma       = init_dma_pdc202xx,
 545                 .channels       = 2,
 546                 .autodma        = AUTODMA,
 547                 .bootable       = OFF_BOARD,
 548                 .extra          = 16,
 549                 .udma_mask      = 0x07, /* udma0-2 */
 550         },{     /* 1 */
 551                 .name           = "PDC20262",
 552                 .init_setup     = init_setup_pdc202ata4,
 553                 .init_chipset   = init_chipset_pdc202xx,
 554                 .init_hwif      = init_hwif_pdc202xx,
 555                 .init_dma       = init_dma_pdc202xx,
 556                 .channels       = 2,
 557                 .autodma        = AUTODMA,
 558                 .bootable       = OFF_BOARD,
 559                 .extra          = 48,
 560                 .udma_mask      = 0x1f, /* udma0-4 */
 561         },{     /* 2 */
 562                 .name           = "PDC20263",
 563                 .init_setup     = init_setup_pdc202ata4,
 564                 .init_chipset   = init_chipset_pdc202xx,
 565                 .init_hwif      = init_hwif_pdc202xx,
 566                 .init_dma       = init_dma_pdc202xx,
 567                 .channels       = 2,
 568                 .autodma        = AUTODMA,
 569                 .bootable       = OFF_BOARD,
 570                 .extra          = 48,
 571                 .udma_mask      = 0x1f, /* udma0-4 */
 572         },{     /* 3 */
 573                 .name           = "PDC20265",
 574                 .init_setup     = init_setup_pdc20265,
 575                 .init_chipset   = init_chipset_pdc202xx,
 576                 .init_hwif      = init_hwif_pdc202xx,
 577                 .init_dma       = init_dma_pdc202xx,
 578                 .channels       = 2,
 579                 .autodma        = AUTODMA,
 580                 .bootable       = OFF_BOARD,
 581                 .extra          = 48,
 582                 .udma_mask      = 0x3f, /* udma0-5 */
 583         },{     /* 4 */
 584                 .name           = "PDC20267",
 585                 .init_setup     = init_setup_pdc202xx,
 586                 .init_chipset   = init_chipset_pdc202xx,
 587                 .init_hwif      = init_hwif_pdc202xx,
 588                 .init_dma       = init_dma_pdc202xx,
 589                 .channels       = 2,
 590                 .autodma        = AUTODMA,
 591                 .bootable       = OFF_BOARD,
 592                 .extra          = 48,
 593                 .udma_mask      = 0x3f, /* udma0-5 */
 594         }
 595 };
 596
 597 /**
 598  *      pdc202xx_init_one       -       called when a PDC202xx is found
 599  *      @dev: the pdc202xx device
 600  *      @id: the matching pci id
 601  *
 602  *      Called when the PCI registration layer (or the IDE initialization)
 603  *      finds a device matching our IDE device tables.
 604  */
 605
 606 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 607 {
 608         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 609
 610         return d->init_setup(dev, d);
 611 }
 612
 613 static struct pci_device_id pdc202xx_pci_tbl[] = {
 614         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 615         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 616         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 617         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 618         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 619         { 0, },
 620 };
 621 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 622
 623 static struct pci_driver driver = {
 624         .name           = "Promise_Old_IDE",
 625         .id_table       = pdc202xx_pci_tbl,
 626         .probe          = pdc202xx_init_one,
 627 };
 628
 629 static int __init pdc202xx_ide_init(void)
 630 {
 631         return ide_pci_register_driver(&driver);
 632 }
 633
 634 module_init(pdc202xx_ide_init);
 635
 636 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 637 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 638 MODULE_LICENSE("GPL");