drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.51    Jul 27, 2007
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *  Copyright (C) 2007                  Bartlomiej Zolnierkiewicz
   7  *
   8  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   9  *  compiled into the kernel if you have more than one card installed.
  10  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  11  *  safe chipset tuning, including this support is harmless
  12  *
  13  *  Promise Ultra66 cards with BIOS v1.11 this
  14  *  compiled into the kernel if you have more than one card installed.
  15  *
  16  *  Promise Ultra100 cards.
  17  *
  18  *  The latest chipset code will support the following ::
  19  *  Three Ultra33 controllers and 12 drives.
  20  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  21  *  The 8/4 ratio is a BIOS code limit by promise.
  22  *
  23  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  24  *
  25  */
  26
  27 /*
  28  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  29  *  Author: Frank Tiernan (frankt@promise.com)
  30  *  Released under terms of General Public License
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/delay.h>
  37 #include <linux/timer.h>
  38 #include <linux/mm.h>
  39 #include <linux/ioport.h>
  40 #include <linux/blkdev.h>
  41 #include <linux/hdreg.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/pci.h>
  44 #include <linux/init.h>
  45 #include <linux/ide.h>
  46
  47 #include <asm/io.h>
  48 #include <asm/irq.h>
  49
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
  65
  66 static int pdc202xx_tune_chipset(ide_drive_t *drive, const u8 speed)
  67 {
  68         ide_hwif_t *hwif        = HWIF(drive);
  69         struct pci_dev *dev     = hwif->pci_dev;
  70         u8 drive_pci            = 0x60 + (drive->dn << 2);
  71
  72         u8                      AP = 0, BP = 0, CP = 0;
  73         u8                      TA = 0, TB = 0, TC = 0;
  74
  75 #if PDC202XX_DEBUG_DRIVE_INFO
  76         u32                     drive_conf = 0;
  77         pci_read_config_dword(dev, drive_pci, &drive_conf);
  78 #endif
  79
  80         /*
  81          * TODO: do this once per channel
  82          */
  83         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
  84                 pdc_old_disable_66MHz_clock(hwif);
  85
  86         pci_read_config_byte(dev, drive_pci,     &AP);
  87         pci_read_config_byte(dev, drive_pci + 1, &BP);
  88         pci_read_config_byte(dev, drive_pci + 2, &CP);
  89
  90         switch(speed) {
  91                 case XFER_UDMA_5:
  92                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
  93                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
  94                 case XFER_UDMA_3:
  95                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
  96                 case XFER_UDMA_0:
  97                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
  98                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
  99                 case XFER_MW_DMA_0:     TB = 0xE0; TC = 0x0F; break;
 100                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 101                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 102                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 103                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 104                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 105                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 106                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 107                 case XFER_PIO_0:
 108                 default:                TA = 0x09; TB = 0x13; break;
 109         }
 110
 111         if (speed < XFER_SW_DMA_0) {
 112                 /*
 113                  * preserve SYNC_INT / ERDDY_EN bits while clearing
 114                  * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
 115                  */
 116                 AP &= ~0x3f;
 117                 if (drive->id->capability & 4)
 118                         AP |= 0x20;     /* set IORDY_EN bit */
 119                 if (drive->media == ide_disk)
 120                         AP |= 0x10;     /* set Prefetch_EN bit */
 121                 /* clear PB[4:0] bits of register B */
 122                 BP &= ~0x1f;
 123                 pci_write_config_byte(dev, drive_pci,     AP | TA);
 124                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 125         } else {
 126                 /* clear MB[2:0] bits of register B */
 127                 BP &= ~0xe0;
 128                 /* clear MC[3:0] bits of register C */
 129                 CP &= ~0x0f;
 130                 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
 131                 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
 132         }
 133
 134 #if PDC202XX_DEBUG_DRIVE_INFO
 135         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 136                 drive->name, ide_xfer_verbose(speed),
 137                 drive->dn, drive_conf);
 138         pci_read_config_dword(dev, drive_pci, &drive_conf);
 139         printk("0x%08x\n", drive_conf);
 140 #endif
 141
 142         return ide_config_drive_speed(drive, speed);
 143 }
 144
 145 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
 146 {
 147         pio = ide_get_best_pio_mode(drive, pio, 4);
 148         pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
 149 }
 150
 151 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 152 {
 153         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 154
 155         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 156
 157         return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
 158 }
 159
 160 /*
 161  * Set the control register to use the 66MHz system
 162  * clock for UDMA 3/4/5 mode operation when necessary.
 163  *
 164  * FIXME: this register is shared by both channels, some locking is needed
 165  *
 166  * It may also be possible to leave the 66MHz clock on
 167  * and readjust the timing parameters.
 168  */
 169 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 170 {
 171         unsigned long clock_reg = hwif->dma_master + 0x11;
 172         u8 clock = inb(clock_reg);
 173
 174         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 175 }
 176
 177 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 178 {
 179         unsigned long clock_reg = hwif->dma_master + 0x11;
 180         u8 clock = inb(clock_reg);
 181
 182         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 183 }
 184
 185 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 186 {
 187         drive->init_speed = 0;
 188
 189         if (ide_tune_dma(drive))
 190                 return 0;
 191
 192         if (ide_use_fast_pio(drive))
 193                 pdc202xx_tune_drive(drive, 255);
 194
 195         return -1;
 196 }
 197
 198 static int pdc202xx_quirkproc (ide_drive_t *drive)
 199 {
 200         const char **list, *model = drive->id->model;
 201
 202         for (list = pdc_quirk_drives; *list != NULL; list++)
 203                 if (strstr(model, *list) != NULL)
 204                         return 2;
 205         return 0;
 206 }
 207
 208 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 209 {
 210         if (drive->current_speed > XFER_UDMA_2)
 211                 pdc_old_enable_66MHz_clock(drive->hwif);
 212         if (drive->media != ide_disk || drive->addressing == 1) {
 213                 struct request *rq      = HWGROUP(drive)->rq;
 214                 ide_hwif_t *hwif        = HWIF(drive);
 215                 unsigned long high_16   = hwif->dma_master;
 216                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 217                 u32 word_count  = 0;
 218                 u8 clock = inb(high_16 + 0x11);
 219
 220                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 221                 word_count = (rq->nr_sectors << 8);
 222                 word_count = (rq_data_dir(rq) == READ) ?
 223                                         word_count | 0x05000000 :
 224                                         word_count | 0x06000000;
 225                 outl(word_count, atapi_reg);
 226         }
 227         ide_dma_start(drive);
 228 }
 229
 230 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 231 {
 232         if (drive->media != ide_disk || drive->addressing == 1) {
 233                 ide_hwif_t *hwif        = HWIF(drive);
 234                 unsigned long high_16   = hwif->dma_master;
 235                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 236                 u8 clock                = 0;
 237
 238                 outl(0, atapi_reg); /* zero out extra */
 239                 clock = inb(high_16 + 0x11);
 240                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 241         }
 242         if (drive->current_speed > XFER_UDMA_2)
 243                 pdc_old_disable_66MHz_clock(drive->hwif);
 244         return __ide_dma_end(drive);
 245 }
 246
 247 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 248 {
 249         ide_hwif_t *hwif        = HWIF(drive);
 250         unsigned long high_16   = hwif->dma_master;
 251         u8 dma_stat             = inb(hwif->dma_status);
 252         u8 sc1d                 = inb(high_16 + 0x001d);
 253
 254         if (hwif->channel) {
 255                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 256                 if ((sc1d & 0x50) == 0x50)
 257                         goto somebody_else;
 258                 else if ((sc1d & 0x40) == 0x40)
 259                         return (dma_stat & 4) == 4;
 260         } else {
 261                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 262                 if ((sc1d & 0x05) == 0x05)
 263                         goto somebody_else;
 264                 else if ((sc1d & 0x04) == 0x04)
 265                         return (dma_stat & 4) == 4;
 266         }
 267 somebody_else:
 268         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 269 }
 270
 271 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
 272 {
 273         ide_hwif_t *hwif = HWIF(drive);
 274
 275         if (hwif->resetproc != NULL)
 276                 hwif->resetproc(drive);
 277
 278         ide_dma_lost_irq(drive);
 279 }
 280
 281 static void pdc202xx_dma_timeout(ide_drive_t *drive)
 282 {
 283         ide_hwif_t *hwif = HWIF(drive);
 284
 285         if (hwif->resetproc != NULL)
 286                 hwif->resetproc(drive);
 287
 288         ide_dma_timeout(drive);
 289 }
 290
 291 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 292 {
 293         unsigned long high_16   = hwif->dma_master;
 294         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 295
 296         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 297         mdelay(100);
 298         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 299         mdelay(2000);   /* 2 seconds ?! */
 300
 301         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 302                 hwif->channel ? "Secondary" : "Primary");
 303 }
 304
 305 static void pdc202xx_reset (ide_drive_t *drive)
 306 {
 307         ide_hwif_t *hwif        = HWIF(drive);
 308         ide_hwif_t *mate        = hwif->mate;
 309
 310         pdc202xx_reset_host(hwif);
 311         pdc202xx_reset_host(mate);
 312         pdc202xx_tune_drive(drive, 255);
 313 }
 314
 315 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 316                                                         const char *name)
 317 {
 318         return dev->irq;
 319 }
 320
 321 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 322 {
 323         struct pci_dev *dev = hwif->pci_dev;
 324
 325         /* PDC20265 has problems with large LBA48 requests */
 326         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 327             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 328                 hwif->rqsize = 256;
 329
 330         hwif->autodma = 0;
 331         hwif->tuneproc  = &pdc202xx_tune_drive;
 332         hwif->quirkproc = &pdc202xx_quirkproc;
 333
 334         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 335                 hwif->resetproc = &pdc202xx_reset;
 336
 337         hwif->speedproc = &pdc202xx_tune_chipset;
 338
 339         hwif->err_stops_fifo = 1;
 340
 341         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 342
 343         if (hwif->dma_base == 0)
 344                 return;
 345
 346         hwif->ultra_mask = hwif->cds->udma_mask;
 347         hwif->mwdma_mask = 0x07;
 348         hwif->swdma_mask = 0x07;
 349         hwif->atapi_dma = 1;
 350
 351         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 352         hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
 353         hwif->dma_timeout = &pdc202xx_dma_timeout;
 354
 355         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 356                 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
 357                         hwif->cbl = pdc202xx_old_cable_detect(hwif);
 358
 359                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 360                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 361         }
 362         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 363
 364         if (!noautodma)
 365                 hwif->autodma = 1;
 366         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 367 }
 368
 369 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 370 {
 371         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 372
 373         if (hwif->channel) {
 374                 ide_setup_dma(hwif, dmabase, 8);
 375                 return;
 376         }
 377
 378         udma_speed_flag = inb(dmabase | 0x1f);
 379         primary_mode    = inb(dmabase | 0x1a);
 380         secondary_mode  = inb(dmabase | 0x1b);
 381         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 382                 "Primary %s Mode " \
 383                 "Secondary %s Mode.\n", hwif->cds->name,
 384                 (udma_speed_flag & 1) ? "EN" : "DIS",
 385                 (primary_mode & 1) ? "MASTER" : "PCI",
 386                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 387
 388 #ifdef CONFIG_PDC202XX_BURST
 389         if (!(udma_speed_flag & 1)) {
 390                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 391                         hwif->cds->name, udma_speed_flag,
 392                         (udma_speed_flag|1));
 393                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 394                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 395         }
 396 #endif /* CONFIG_PDC202XX_BURST */
 397
 398         ide_setup_dma(hwif, dmabase, 8);
 399 }
 400
 401 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 402                                            ide_pci_device_t *d)
 403 {
 404         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 405                 u8 irq = 0, irq2 = 0;
 406                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 407                 /* 0xbc */
 408                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 409                 if (irq != irq2) {
 410                         pci_write_config_byte(dev,
 411                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 412                         printk(KERN_INFO "%s: pci-config space interrupt "
 413                                 "mirror fixed.\n", d->name);
 414                 }
 415         }
 416         return ide_setup_pci_device(dev, d);
 417 }
 418
 419 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 420                                          ide_pci_device_t *d)
 421 {
 422         if ((dev->bus->self) &&
 423             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 424             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 425              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 426                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 427                         "attached to I2O RAID controller.\n");
 428                 return -ENODEV;
 429         }
 430         return ide_setup_pci_device(dev, d);
 431 }
 432
 433 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 434                                          ide_pci_device_t *d)
 435 {
 436         return ide_setup_pci_device(dev, d);
 437 }
 438
 439 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 440         {       /* 0 */
 441                 .name           = "PDC20246",
 442                 .init_setup     = init_setup_pdc202ata4,
 443                 .init_chipset   = init_chipset_pdc202xx,
 444                 .init_hwif      = init_hwif_pdc202xx,
 445                 .init_dma       = init_dma_pdc202xx,
 446                 .autodma        = AUTODMA,
 447                 .bootable       = OFF_BOARD,
 448                 .extra          = 16,
 449                 .pio_mask       = ATA_PIO4,
 450                 .udma_mask      = 0x07, /* udma0-2 */
 451         },{     /* 1 */
 452                 .name           = "PDC20262",
 453                 .init_setup     = init_setup_pdc202ata4,
 454                 .init_chipset   = init_chipset_pdc202xx,
 455                 .init_hwif      = init_hwif_pdc202xx,
 456                 .init_dma       = init_dma_pdc202xx,
 457                 .autodma        = AUTODMA,
 458                 .bootable       = OFF_BOARD,
 459                 .extra          = 48,
 460                 .pio_mask       = ATA_PIO4,
 461                 .udma_mask      = 0x1f, /* udma0-4 */
 462         },{     /* 2 */
 463                 .name           = "PDC20263",
 464                 .init_setup     = init_setup_pdc202ata4,
 465                 .init_chipset   = init_chipset_pdc202xx,
 466                 .init_hwif      = init_hwif_pdc202xx,
 467                 .init_dma       = init_dma_pdc202xx,
 468                 .autodma        = AUTODMA,
 469                 .bootable       = OFF_BOARD,
 470                 .extra          = 48,
 471                 .pio_mask       = ATA_PIO4,
 472                 .udma_mask      = 0x1f, /* udma0-4 */
 473         },{     /* 3 */
 474                 .name           = "PDC20265",
 475                 .init_setup     = init_setup_pdc20265,
 476                 .init_chipset   = init_chipset_pdc202xx,
 477                 .init_hwif      = init_hwif_pdc202xx,
 478                 .init_dma       = init_dma_pdc202xx,
 479                 .autodma        = AUTODMA,
 480                 .bootable       = OFF_BOARD,
 481                 .extra          = 48,
 482                 .pio_mask       = ATA_PIO4,
 483                 .udma_mask      = 0x3f, /* udma0-5 */
 484         },{     /* 4 */
 485                 .name           = "PDC20267",
 486                 .init_setup     = init_setup_pdc202xx,
 487                 .init_chipset   = init_chipset_pdc202xx,
 488                 .init_hwif      = init_hwif_pdc202xx,
 489                 .init_dma       = init_dma_pdc202xx,
 490                 .autodma        = AUTODMA,
 491                 .bootable       = OFF_BOARD,
 492                 .extra          = 48,
 493                 .pio_mask       = ATA_PIO4,
 494                 .udma_mask      = 0x3f, /* udma0-5 */
 495         }
 496 };
 497
 498 /**
 499  *      pdc202xx_init_one       -       called when a PDC202xx is found
 500  *      @dev: the pdc202xx device
 501  *      @id: the matching pci id
 502  *
 503  *      Called when the PCI registration layer (or the IDE initialization)
 504  *      finds a device matching our IDE device tables.
 505  */
 506
 507 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 508 {
 509         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 510
 511         return d->init_setup(dev, d);
 512 }
 513
 514 static struct pci_device_id pdc202xx_pci_tbl[] = {
 515         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 516         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 517         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 518         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 519         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 520         { 0, },
 521 };
 522 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 523
 524 static struct pci_driver driver = {
 525         .name           = "Promise_Old_IDE",
 526         .id_table       = pdc202xx_pci_tbl,
 527         .probe          = pdc202xx_init_one,
 528 };
 529
 530 static int __init pdc202xx_ide_init(void)
 531 {
 532         return ide_pci_register_driver(&driver);
 533 }
 534
 535 module_init(pdc202xx_ide_init);
 536
 537 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 538 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 539 MODULE_LICENSE("GPL");