2 * linux/drivers/ide/pci/pdc202xx_old.c Version 0.52 Aug 27, 2007
4 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
5 * Copyright (C) 2006-2007 MontaVista Software, Inc.
6 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz
8 * Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
9 * compiled into the kernel if you have more than one card installed.
10 * Note that BIOS v1.29 is reported to fix the problem. Since this is
11 * safe chipset tuning, including this support is harmless
13 * Promise Ultra66 cards with BIOS v1.11 this
14 * compiled into the kernel if you have more than one card installed.
16 * Promise Ultra100 cards.
18 * The latest chipset code will support the following ::
19 * Three Ultra33 controllers and 12 drives.
20 * 8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
21 * The 8/4 ratio is a BIOS code limit by promise.
23 * UNLESS you enable "CONFIG_PDC202XX_BURST"
28 * Portions Copyright (C) 1999 Promise Technology, Inc.
29 * Author: Frank Tiernan (frankt@promise.com)
30 * Released under terms of General Public License
33 #include <linux/types.h>
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/timer.h>
39 #include <linux/ioport.h>
40 #include <linux/blkdev.h>
41 #include <linux/hdreg.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/init.h>
45 #include <linux/ide.h>
50 #define PDC202XX_DEBUG_DRIVE_INFO 0
52 static const char *pdc_quirk_drives[] = {
53 "QUANTUM FIREBALLlct08 08",
54 "QUANTUM FIREBALLP KA6.4",
55 "QUANTUM FIREBALLP KA9.1",
56 "QUANTUM FIREBALLP LM20.4",
57 "QUANTUM FIREBALLP KX13.6",
58 "QUANTUM FIREBALLP KX20.5",
59 "QUANTUM FIREBALLP KX27.3",
60 "QUANTUM FIREBALLP LM20.5",
64 static void pdc_old_disable_66MHz_clock(ide_hwif_t *);
66 static void pdc202xx_set_mode(ide_drive_t *drive, const u8 speed)
68 ide_hwif_t *hwif = HWIF(drive);
69 struct pci_dev *dev = hwif->pci_dev;
70 u8 drive_pci = 0x60 + (drive->dn << 2);
72 u8 AP = 0, BP = 0, CP = 0;
73 u8 TA = 0, TB = 0, TC = 0;
75 #if PDC202XX_DEBUG_DRIVE_INFO
77 pci_read_config_dword(dev, drive_pci, &drive_conf);
81 * TODO: do this once per channel
83 if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
84 pdc_old_disable_66MHz_clock(hwif);
86 pci_read_config_byte(dev, drive_pci, &AP);
87 pci_read_config_byte(dev, drive_pci + 1, &BP);
88 pci_read_config_byte(dev, drive_pci + 2, &CP);
92 case XFER_UDMA_4: TB = 0x20; TC = 0x01; break;
93 case XFER_UDMA_2: TB = 0x20; TC = 0x01; break;
95 case XFER_UDMA_1: TB = 0x40; TC = 0x02; break;
97 case XFER_MW_DMA_2: TB = 0x60; TC = 0x03; break;
98 case XFER_MW_DMA_1: TB = 0x60; TC = 0x04; break;
99 case XFER_MW_DMA_0: TB = 0xE0; TC = 0x0F; break;
100 case XFER_PIO_4: TA = 0x01; TB = 0x04; break;
101 case XFER_PIO_3: TA = 0x02; TB = 0x06; break;
102 case XFER_PIO_2: TA = 0x03; TB = 0x08; break;
103 case XFER_PIO_1: TA = 0x05; TB = 0x0C; break;
105 default: TA = 0x09; TB = 0x13; break;
108 if (speed < XFER_SW_DMA_0) {
110 * preserve SYNC_INT / ERDDY_EN bits while clearing
111 * Prefetch_EN / IORDY_EN / PA[3:0] bits of register A
114 if (drive->id->capability & 4)
115 AP |= 0x20; /* set IORDY_EN bit */
116 if (drive->media == ide_disk)
117 AP |= 0x10; /* set Prefetch_EN bit */
118 /* clear PB[4:0] bits of register B */
120 pci_write_config_byte(dev, drive_pci, AP | TA);
121 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
123 /* clear MB[2:0] bits of register B */
125 /* clear MC[3:0] bits of register C */
127 pci_write_config_byte(dev, drive_pci + 1, BP | TB);
128 pci_write_config_byte(dev, drive_pci + 2, CP | TC);
131 #if PDC202XX_DEBUG_DRIVE_INFO
132 printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
133 drive->name, ide_xfer_verbose(speed),
134 drive->dn, drive_conf);
135 pci_read_config_dword(dev, drive_pci, &drive_conf);
136 printk("0x%08x\n", drive_conf);
140 static void pdc202xx_set_pio_mode(ide_drive_t *drive, const u8 pio)
142 pdc202xx_set_mode(drive, XFER_PIO_0 + pio);
145 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
147 u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
149 pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
151 return (CIS & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
155 * Set the control register to use the 66MHz system
156 * clock for UDMA 3/4/5 mode operation when necessary.
158 * FIXME: this register is shared by both channels, some locking is needed
160 * It may also be possible to leave the 66MHz clock on
161 * and readjust the timing parameters.
163 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
165 unsigned long clock_reg = hwif->dma_master + 0x11;
166 u8 clock = inb(clock_reg);
168 outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
171 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
173 unsigned long clock_reg = hwif->dma_master + 0x11;
174 u8 clock = inb(clock_reg);
176 outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
179 static int pdc202xx_quirkproc (ide_drive_t *drive)
181 const char **list, *model = drive->id->model;
183 for (list = pdc_quirk_drives; *list != NULL; list++)
184 if (strstr(model, *list) != NULL)
189 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
191 if (drive->current_speed > XFER_UDMA_2)
192 pdc_old_enable_66MHz_clock(drive->hwif);
193 if (drive->media != ide_disk || drive->addressing == 1) {
194 struct request *rq = HWGROUP(drive)->rq;
195 ide_hwif_t *hwif = HWIF(drive);
196 unsigned long high_16 = hwif->dma_master;
197 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
199 u8 clock = inb(high_16 + 0x11);
201 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
202 word_count = (rq->nr_sectors << 8);
203 word_count = (rq_data_dir(rq) == READ) ?
204 word_count | 0x05000000 :
205 word_count | 0x06000000;
206 outl(word_count, atapi_reg);
208 ide_dma_start(drive);
211 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
213 if (drive->media != ide_disk || drive->addressing == 1) {
214 ide_hwif_t *hwif = HWIF(drive);
215 unsigned long high_16 = hwif->dma_master;
216 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
219 outl(0, atapi_reg); /* zero out extra */
220 clock = inb(high_16 + 0x11);
221 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
223 if (drive->current_speed > XFER_UDMA_2)
224 pdc_old_disable_66MHz_clock(drive->hwif);
225 return __ide_dma_end(drive);
228 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
230 ide_hwif_t *hwif = HWIF(drive);
231 unsigned long high_16 = hwif->dma_master;
232 u8 dma_stat = inb(hwif->dma_status);
233 u8 sc1d = inb(high_16 + 0x001d);
236 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
237 if ((sc1d & 0x50) == 0x50)
239 else if ((sc1d & 0x40) == 0x40)
240 return (dma_stat & 4) == 4;
242 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
243 if ((sc1d & 0x05) == 0x05)
245 else if ((sc1d & 0x04) == 0x04)
246 return (dma_stat & 4) == 4;
249 return (dma_stat & 4) == 4; /* return 1 if INTR asserted */
252 static void pdc202xx_dma_lost_irq(ide_drive_t *drive)
254 ide_hwif_t *hwif = HWIF(drive);
256 if (hwif->resetproc != NULL)
257 hwif->resetproc(drive);
259 ide_dma_lost_irq(drive);
262 static void pdc202xx_dma_timeout(ide_drive_t *drive)
264 ide_hwif_t *hwif = HWIF(drive);
266 if (hwif->resetproc != NULL)
267 hwif->resetproc(drive);
269 ide_dma_timeout(drive);
272 static void pdc202xx_reset_host (ide_hwif_t *hwif)
274 unsigned long high_16 = hwif->dma_master;
275 u8 udma_speed_flag = inb(high_16 | 0x001f);
277 outb(udma_speed_flag | 0x10, high_16 | 0x001f);
279 outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
280 mdelay(2000); /* 2 seconds ?! */
282 printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
283 hwif->channel ? "Secondary" : "Primary");
286 static void pdc202xx_reset (ide_drive_t *drive)
288 ide_hwif_t *hwif = HWIF(drive);
289 ide_hwif_t *mate = hwif->mate;
291 pdc202xx_reset_host(hwif);
292 pdc202xx_reset_host(mate);
294 ide_set_max_pio(drive);
297 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
303 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
305 struct pci_dev *dev = hwif->pci_dev;
307 /* PDC20265 has problems with large LBA48 requests */
308 if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
309 (dev->device == PCI_DEVICE_ID_PROMISE_20265))
312 hwif->set_pio_mode = &pdc202xx_set_pio_mode;
313 hwif->set_dma_mode = &pdc202xx_set_mode;
315 hwif->quirkproc = &pdc202xx_quirkproc;
317 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
318 hwif->resetproc = &pdc202xx_reset;
320 hwif->err_stops_fifo = 1;
322 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
324 if (hwif->dma_base == 0)
327 hwif->dma_lost_irq = &pdc202xx_dma_lost_irq;
328 hwif->dma_timeout = &pdc202xx_dma_timeout;
330 if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
331 if (hwif->cbl != ATA_CBL_PATA40_SHORT)
332 hwif->cbl = pdc202xx_old_cable_detect(hwif);
334 hwif->dma_start = &pdc202xx_old_ide_dma_start;
335 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
337 hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
340 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
342 u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
345 ide_setup_dma(hwif, dmabase, 8);
349 udma_speed_flag = inb(dmabase | 0x1f);
350 primary_mode = inb(dmabase | 0x1a);
351 secondary_mode = inb(dmabase | 0x1b);
352 printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
354 "Secondary %s Mode.\n", hwif->cds->name,
355 (udma_speed_flag & 1) ? "EN" : "DIS",
356 (primary_mode & 1) ? "MASTER" : "PCI",
357 (secondary_mode & 1) ? "MASTER" : "PCI" );
359 #ifdef CONFIG_PDC202XX_BURST
360 if (!(udma_speed_flag & 1)) {
361 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
362 hwif->cds->name, udma_speed_flag,
363 (udma_speed_flag|1));
364 outb(udma_speed_flag | 1, dmabase | 0x1f);
365 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
367 #endif /* CONFIG_PDC202XX_BURST */
369 ide_setup_dma(hwif, dmabase, 8);
372 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
375 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
376 u8 irq = 0, irq2 = 0;
377 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
379 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
381 pci_write_config_byte(dev,
382 (PCI_INTERRUPT_LINE)|0x80, irq); /* 0xbc */
383 printk(KERN_INFO "%s: pci-config space interrupt "
384 "mirror fixed.\n", d->name);
387 return ide_setup_pci_device(dev, d);
390 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
393 if ((dev->bus->self) &&
394 (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
395 ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
396 (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
397 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
398 "attached to I2O RAID controller.\n");
401 return ide_setup_pci_device(dev, d);
404 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
407 return ide_setup_pci_device(dev, d);
410 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
413 .init_setup = init_setup_pdc202ata4,
414 .init_chipset = init_chipset_pdc202xx,
415 .init_hwif = init_hwif_pdc202xx,
416 .init_dma = init_dma_pdc202xx,
418 .host_flags = IDE_HFLAG_OFF_BOARD,
419 .pio_mask = ATA_PIO4,
420 .mwdma_mask = ATA_MWDMA2,
421 .udma_mask = ATA_UDMA2,
424 .init_setup = init_setup_pdc202ata4,
425 .init_chipset = init_chipset_pdc202xx,
426 .init_hwif = init_hwif_pdc202xx,
427 .init_dma = init_dma_pdc202xx,
429 .host_flags = IDE_HFLAG_OFF_BOARD,
430 .pio_mask = ATA_PIO4,
431 .mwdma_mask = ATA_MWDMA2,
432 .udma_mask = ATA_UDMA4,
435 .init_setup = init_setup_pdc202ata4,
436 .init_chipset = init_chipset_pdc202xx,
437 .init_hwif = init_hwif_pdc202xx,
438 .init_dma = init_dma_pdc202xx,
440 .host_flags = IDE_HFLAG_OFF_BOARD,
441 .pio_mask = ATA_PIO4,
442 .mwdma_mask = ATA_MWDMA2,
443 .udma_mask = ATA_UDMA4,
446 .init_setup = init_setup_pdc20265,
447 .init_chipset = init_chipset_pdc202xx,
448 .init_hwif = init_hwif_pdc202xx,
449 .init_dma = init_dma_pdc202xx,
451 .host_flags = IDE_HFLAG_OFF_BOARD,
452 .pio_mask = ATA_PIO4,
453 .mwdma_mask = ATA_MWDMA2,
454 .udma_mask = ATA_UDMA5,
457 .init_setup = init_setup_pdc202xx,
458 .init_chipset = init_chipset_pdc202xx,
459 .init_hwif = init_hwif_pdc202xx,
460 .init_dma = init_dma_pdc202xx,
462 .host_flags = IDE_HFLAG_OFF_BOARD,
463 .pio_mask = ATA_PIO4,
464 .mwdma_mask = ATA_MWDMA2,
465 .udma_mask = ATA_UDMA5,
470 * pdc202xx_init_one - called when a PDC202xx is found
471 * @dev: the pdc202xx device
472 * @id: the matching pci id
474 * Called when the PCI registration layer (or the IDE initialization)
475 * finds a device matching our IDE device tables.
478 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
480 ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
482 return d->init_setup(dev, d);
485 static const struct pci_device_id pdc202xx_pci_tbl[] = {
486 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
487 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
488 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 2 },
489 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 3 },
490 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 4 },
493 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
495 static struct pci_driver driver = {
496 .name = "Promise_Old_IDE",
497 .id_table = pdc202xx_pci_tbl,
498 .probe = pdc202xx_init_one,
501 static int __init pdc202xx_ide_init(void)
503 return ide_pci_register_driver(&driver);
506 module_init(pdc202xx_ide_init);
508 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
509 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
510 MODULE_LICENSE("GPL");