drivers/ide/pci/pdc202xx_old.c

   1 /*
   2  *  linux/drivers/ide/pci/pdc202xx_old.c        Version 0.36    Sept 11, 2002
   3  *
   4  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
   5  *  Copyright (C) 2006-2007             MontaVista Software, Inc.
   6  *
   7  *  Promise Ultra33 cards with BIOS v1.20 through 1.28 will need this
   8  *  compiled into the kernel if you have more than one card installed.
   9  *  Note that BIOS v1.29 is reported to fix the problem.  Since this is
  10  *  safe chipset tuning, including this support is harmless
  11  *
  12  *  Promise Ultra66 cards with BIOS v1.11 this
  13  *  compiled into the kernel if you have more than one card installed.
  14  *
  15  *  Promise Ultra100 cards.
  16  *
  17  *  The latest chipset code will support the following ::
  18  *  Three Ultra33 controllers and 12 drives.
  19  *  8 are UDMA supported and 4 are limited to DMA mode 2 multi-word.
  20  *  The 8/4 ratio is a BIOS code limit by promise.
  21  *
  22  *  UNLESS you enable "CONFIG_PDC202XX_BURST"
  23  *
  24  */
  25
  26 /*
  27  *  Portions Copyright (C) 1999 Promise Technology, Inc.
  28  *  Author: Frank Tiernan (frankt@promise.com)
  29  *  Released under terms of General Public License
  30  */
  31
  32 #include <linux/types.h>
  33 #include <linux/module.h>
  34 #include <linux/kernel.h>
  35 #include <linux/delay.h>
  36 #include <linux/timer.h>
  37 #include <linux/mm.h>
  38 #include <linux/ioport.h>
  39 #include <linux/blkdev.h>
  40 #include <linux/hdreg.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/pci.h>
  43 #include <linux/init.h>
  44 #include <linux/ide.h>
  45
  46 #include <asm/io.h>
  47 #include <asm/irq.h>
  48
  49 #define PDC202_DEBUG_CABLE              0
  50 #define PDC202XX_DEBUG_DRIVE_INFO       0
  51
  52 static const char *pdc_quirk_drives[] = {
  53         "QUANTUM FIREBALLlct08 08",
  54         "QUANTUM FIREBALLP KA6.4",
  55         "QUANTUM FIREBALLP KA9.1",
  56         "QUANTUM FIREBALLP LM20.4",
  57         "QUANTUM FIREBALLP KX13.6",
  58         "QUANTUM FIREBALLP KX20.5",
  59         "QUANTUM FIREBALLP KX27.3",
  60         "QUANTUM FIREBALLP LM20.5",
  61         NULL
  62 };
  63
  64 /* A Register */
  65 #define SYNC_ERRDY_EN   0xC0
  66
  67 #define SYNC_IN         0x80    /* control bit, different for master vs. slave drives */
  68 #define ERRDY_EN        0x40    /* control bit, different for master vs. slave drives */
  69 #define IORDY_EN        0x20    /* PIO: IOREADY */
  70 #define PREFETCH_EN     0x10    /* PIO: PREFETCH */
  71
  72 #define PA3             0x08    /* PIO"A" timing */
  73 #define PA2             0x04    /* PIO"A" timing */
  74 #define PA1             0x02    /* PIO"A" timing */
  75 #define PA0             0x01    /* PIO"A" timing */
  76
  77 /* B Register */
  78
  79 #define MB2             0x80    /* DMA"B" timing */
  80 #define MB1             0x40    /* DMA"B" timing */
  81 #define MB0             0x20    /* DMA"B" timing */
  82
  83 #define PB4             0x10    /* PIO_FORCE 1:0 */
  84
  85 #define PB3             0x08    /* PIO"B" timing */     /* PIO flow Control mode */
  86 #define PB2             0x04    /* PIO"B" timing */     /* PIO 4 */
  87 #define PB1             0x02    /* PIO"B" timing */     /* PIO 3 half */
  88 #define PB0             0x01    /* PIO"B" timing */     /* PIO 3 other half */
  89
  90 /* C Register */
  91 #define IORDYp_NO_SPEED 0x4F
  92 #define SPEED_DIS       0x0F
  93
  94 #define DMARQp          0x80
  95 #define IORDYp          0x40
  96 #define DMAR_EN         0x20
  97 #define DMAW_EN         0x10
  98
  99 #define MC3             0x08    /* DMA"C" timing */
 100 #define MC2             0x04    /* DMA"C" timing */
 101 #define MC1             0x02    /* DMA"C" timing */
 102 #define MC0             0x01    /* DMA"C" timing */
 103
 104 static u8 pdc202xx_ratemask (ide_drive_t *drive)
 105 {
 106         u8 mode;
 107
 108         switch(HWIF(drive)->pci_dev->device) {
 109                 case PCI_DEVICE_ID_PROMISE_20267:
 110                 case PCI_DEVICE_ID_PROMISE_20265:
 111                         mode = 3;
 112                         break;
 113                 case PCI_DEVICE_ID_PROMISE_20263:
 114                 case PCI_DEVICE_ID_PROMISE_20262:
 115                         mode = 2;
 116                         break;
 117                 case PCI_DEVICE_ID_PROMISE_20246:
 118                         return 1;
 119                 default:
 120                         return 0;
 121         }
 122         if (!eighty_ninty_three(drive))
 123                 mode = min(mode, (u8)1);
 124         return mode;
 125 }
 126
 127 static int pdc202xx_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 128 {
 129         ide_hwif_t *hwif        = HWIF(drive);
 130         struct pci_dev *dev     = hwif->pci_dev;
 131         u8 drive_pci            = 0x60 + (drive->dn << 2);
 132         u8 speed        = ide_rate_filter(pdc202xx_ratemask(drive), xferspeed);
 133
 134         u32                     drive_conf;
 135         u8                      AP, BP, CP, DP;
 136         u8                      TA = 0, TB = 0, TC = 0;
 137
 138         if (drive->media != ide_disk &&
 139                 drive->media != ide_cdrom && speed < XFER_SW_DMA_0)
 140                 return -1;
 141
 142         pci_read_config_dword(dev, drive_pci, &drive_conf);
 143         pci_read_config_byte(dev, (drive_pci), &AP);
 144         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 145         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 146         pci_read_config_byte(dev, (drive_pci)|0x03, &DP);
 147
 148         if (speed < XFER_SW_DMA_0) {
 149                 if ((AP & 0x0F) || (BP & 0x07)) {
 150                         /* clear PIO modes of lower 8421 bits of A Register */
 151                         pci_write_config_byte(dev, (drive_pci), AP &~0x0F);
 152                         pci_read_config_byte(dev, (drive_pci), &AP);
 153
 154                         /* clear PIO modes of lower 421 bits of B Register */
 155                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0x07);
 156                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 157
 158                         pci_read_config_byte(dev, (drive_pci), &AP);
 159                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 160                 }
 161         } else {
 162                 if ((BP & 0xF0) && (CP & 0x0F)) {
 163                         /* clear DMA modes of upper 842 bits of B Register */
 164                         /* clear PIO forced mode upper 1 bit of B Register */
 165                         pci_write_config_byte(dev, (drive_pci)|0x01, BP &~0xF0);
 166                         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 167
 168                         /* clear DMA modes of lower 8421 bits of C Register */
 169                         pci_write_config_byte(dev, (drive_pci)|0x02, CP &~0x0F);
 170                         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 171                 }
 172         }
 173
 174         pci_read_config_byte(dev, (drive_pci), &AP);
 175         pci_read_config_byte(dev, (drive_pci)|0x01, &BP);
 176         pci_read_config_byte(dev, (drive_pci)|0x02, &CP);
 177
 178         switch(speed) {
 179                 case XFER_UDMA_6:       speed = XFER_UDMA_5;
 180                 case XFER_UDMA_5:
 181                 case XFER_UDMA_4:       TB = 0x20; TC = 0x01; break;
 182                 case XFER_UDMA_2:       TB = 0x20; TC = 0x01; break;
 183                 case XFER_UDMA_3:
 184                 case XFER_UDMA_1:       TB = 0x40; TC = 0x02; break;
 185                 case XFER_UDMA_0:
 186                 case XFER_MW_DMA_2:     TB = 0x60; TC = 0x03; break;
 187                 case XFER_MW_DMA_1:     TB = 0x60; TC = 0x04; break;
 188                 case XFER_MW_DMA_0:
 189                 case XFER_SW_DMA_2:     TB = 0x60; TC = 0x05; break;
 190                 case XFER_SW_DMA_1:     TB = 0x80; TC = 0x06; break;
 191                 case XFER_SW_DMA_0:     TB = 0xC0; TC = 0x0B; break;
 192                 case XFER_PIO_4:        TA = 0x01; TB = 0x04; break;
 193                 case XFER_PIO_3:        TA = 0x02; TB = 0x06; break;
 194                 case XFER_PIO_2:        TA = 0x03; TB = 0x08; break;
 195                 case XFER_PIO_1:        TA = 0x05; TB = 0x0C; break;
 196                 case XFER_PIO_0:
 197                 default:                TA = 0x09; TB = 0x13; break;
 198         }
 199
 200         if (speed < XFER_SW_DMA_0) {
 201                 pci_write_config_byte(dev, (drive_pci), AP|TA);
 202                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 203         } else {
 204                 pci_write_config_byte(dev, (drive_pci)|0x01, BP|TB);
 205                 pci_write_config_byte(dev, (drive_pci)|0x02, CP|TC);
 206         }
 207
 208 #if PDC202XX_DEBUG_DRIVE_INFO
 209         printk(KERN_DEBUG "%s: %s drive%d 0x%08x ",
 210                 drive->name, ide_xfer_verbose(speed),
 211                 drive->dn, drive_conf);
 212                 pci_read_config_dword(dev, drive_pci, &drive_conf);
 213         printk("0x%08x\n", drive_conf);
 214 #endif /* PDC202XX_DEBUG_DRIVE_INFO */
 215
 216         return (ide_config_drive_speed(drive, speed));
 217 }
 218
 219
 220 static void pdc202xx_tune_drive(ide_drive_t *drive, u8 pio)
 221 {
 222         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 223         pdc202xx_tune_chipset(drive, XFER_PIO_0 + pio);
 224 }
 225
 226 static u8 pdc202xx_old_cable_detect (ide_hwif_t *hwif)
 227 {
 228         u16 CIS = 0, mask = (hwif->channel) ? (1<<11) : (1<<10);
 229         pci_read_config_word(hwif->pci_dev, 0x50, &CIS);
 230         return (CIS & mask) ? 1 : 0;
 231 }
 232
 233 /*
 234  * Set the control register to use the 66MHz system
 235  * clock for UDMA 3/4/5 mode operation when necessary.
 236  *
 237  * It may also be possible to leave the 66MHz clock on
 238  * and readjust the timing parameters.
 239  */
 240 static void pdc_old_enable_66MHz_clock(ide_hwif_t *hwif)
 241 {
 242         unsigned long clock_reg = hwif->dma_master + 0x11;
 243         u8 clock = inb(clock_reg);
 244
 245         outb(clock | (hwif->channel ? 0x08 : 0x02), clock_reg);
 246 }
 247
 248 static void pdc_old_disable_66MHz_clock(ide_hwif_t *hwif)
 249 {
 250         unsigned long clock_reg = hwif->dma_master + 0x11;
 251         u8 clock = inb(clock_reg);
 252
 253         outb(clock & ~(hwif->channel ? 0x08 : 0x02), clock_reg);
 254 }
 255
 256 static int config_chipset_for_dma (ide_drive_t *drive)
 257 {
 258         struct hd_driveid *id   = drive->id;
 259         ide_hwif_t *hwif        = HWIF(drive);
 260         struct pci_dev *dev     = hwif->pci_dev;
 261         u32 drive_conf          = 0;
 262         u8 drive_pci            = 0x60 + (drive->dn << 2);
 263         u8 test1 = 0, test2 = 0, speed = -1;
 264         u8 AP = 0, cable = 0;
 265
 266         u8 ultra_66             = ((id->dma_ultra & 0x0010) ||
 267                                    (id->dma_ultra & 0x0008)) ? 1 : 0;
 268
 269         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 270                 cable = pdc202xx_old_cable_detect(hwif);
 271         else
 272                 ultra_66 = 0;
 273
 274         if (ultra_66 && cable) {
 275                 printk(KERN_WARNING "Warning: %s channel requires an 80-pin cable for operation.\n", hwif->channel ? "Secondary":"Primary");
 276                 printk(KERN_WARNING "%s reduced to Ultra33 mode.\n", drive->name);
 277         }
 278
 279         if (dev->device != PCI_DEVICE_ID_PROMISE_20246)
 280                 pdc_old_disable_66MHz_clock(drive->hwif);
 281
 282         drive_pci = 0x60 + (drive->dn << 2);
 283         pci_read_config_dword(dev, drive_pci, &drive_conf);
 284         if ((drive_conf != 0x004ff304) && (drive_conf != 0x004ff3c4))
 285                 goto chipset_is_set;
 286
 287         pci_read_config_byte(dev, drive_pci, &test1);
 288         if (!(test1 & SYNC_ERRDY_EN)) {
 289                 if (drive->select.b.unit & 0x01) {
 290                         pci_read_config_byte(dev, drive_pci - 4, &test2);
 291                         if ((test2 & SYNC_ERRDY_EN) &&
 292                             !(test1 & SYNC_ERRDY_EN)) {
 293                                 pci_write_config_byte(dev, drive_pci,
 294                                         test1|SYNC_ERRDY_EN);
 295                         }
 296                 } else {
 297                         pci_write_config_byte(dev, drive_pci,
 298                                 test1|SYNC_ERRDY_EN);
 299                 }
 300         }
 301
 302 chipset_is_set:
 303
 304         pci_read_config_byte(dev, (drive_pci), &AP);
 305         if (id->capability & 4) /* IORDY_EN */
 306                 pci_write_config_byte(dev, (drive_pci), AP|IORDY_EN);
 307         pci_read_config_byte(dev, (drive_pci), &AP);
 308         if (drive->media == ide_disk)   /* PREFETCH_EN */
 309                 pci_write_config_byte(dev, (drive_pci), AP|PREFETCH_EN);
 310
 311         speed = ide_dma_speed(drive, pdc202xx_ratemask(drive));
 312
 313         if (!(speed)) {
 314                 /* restore original pci-config space */
 315                 pci_write_config_dword(dev, drive_pci, drive_conf);
 316                 return 0;
 317         }
 318
 319         (void) hwif->speedproc(drive, speed);
 320         return ide_dma_enable(drive);
 321 }
 322
 323 static int pdc202xx_config_drive_xfer_rate (ide_drive_t *drive)
 324 {
 325         ide_hwif_t *hwif        = HWIF(drive);
 326
 327         drive->init_speed = 0;
 328
 329         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 330                 return hwif->ide_dma_on(drive);
 331
 332         if (ide_use_fast_pio(drive)) {
 333                 pdc202xx_tune_drive(drive, 255);
 334                 return hwif->ide_dma_off_quietly(drive);
 335         }
 336         /* IORDY not supported */
 337         return 0;
 338 }
 339
 340 static int pdc202xx_quirkproc (ide_drive_t *drive)
 341 {
 342         const char **list, *model = drive->id->model;
 343
 344         for (list = pdc_quirk_drives; *list != NULL; list++)
 345                 if (strstr(model, *list) != NULL)
 346                         return 2;
 347         return 0;
 348 }
 349
 350 static void pdc202xx_old_ide_dma_start(ide_drive_t *drive)
 351 {
 352         if (drive->current_speed > XFER_UDMA_2)
 353                 pdc_old_enable_66MHz_clock(drive->hwif);
 354         if (drive->media != ide_disk || drive->addressing == 1) {
 355                 struct request *rq      = HWGROUP(drive)->rq;
 356                 ide_hwif_t *hwif        = HWIF(drive);
 357                 unsigned long high_16   = hwif->dma_master;
 358                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 359                 u32 word_count  = 0;
 360                 u8 clock = inb(high_16 + 0x11);
 361
 362                 outb(clock | (hwif->channel ? 0x08 : 0x02), high_16 + 0x11);
 363                 word_count = (rq->nr_sectors << 8);
 364                 word_count = (rq_data_dir(rq) == READ) ?
 365                                         word_count | 0x05000000 :
 366                                         word_count | 0x06000000;
 367                 outl(word_count, atapi_reg);
 368         }
 369         ide_dma_start(drive);
 370 }
 371
 372 static int pdc202xx_old_ide_dma_end(ide_drive_t *drive)
 373 {
 374         if (drive->media != ide_disk || drive->addressing == 1) {
 375                 ide_hwif_t *hwif        = HWIF(drive);
 376                 unsigned long high_16   = hwif->dma_master;
 377                 unsigned long atapi_reg = high_16 + (hwif->channel ? 0x24 : 0x20);
 378                 u8 clock                = 0;
 379
 380                 outl(0, atapi_reg); /* zero out extra */
 381                 clock = inb(high_16 + 0x11);
 382                 outb(clock & ~(hwif->channel ? 0x08:0x02), high_16 + 0x11);
 383         }
 384         if (drive->current_speed > XFER_UDMA_2)
 385                 pdc_old_disable_66MHz_clock(drive->hwif);
 386         return __ide_dma_end(drive);
 387 }
 388
 389 static int pdc202xx_old_ide_dma_test_irq(ide_drive_t *drive)
 390 {
 391         ide_hwif_t *hwif        = HWIF(drive);
 392         unsigned long high_16   = hwif->dma_master;
 393         u8 dma_stat             = inb(hwif->dma_status);
 394         u8 sc1d                 = inb(high_16 + 0x001d);
 395
 396         if (hwif->channel) {
 397                 /* bit7: Error, bit6: Interrupting, bit5: FIFO Full, bit4: FIFO Empty */
 398                 if ((sc1d & 0x50) == 0x50)
 399                         goto somebody_else;
 400                 else if ((sc1d & 0x40) == 0x40)
 401                         return (dma_stat & 4) == 4;
 402         } else {
 403                 /* bit3: Error, bit2: Interrupting, bit1: FIFO Full, bit0: FIFO Empty */
 404                 if ((sc1d & 0x05) == 0x05)
 405                         goto somebody_else;
 406                 else if ((sc1d & 0x04) == 0x04)
 407                         return (dma_stat & 4) == 4;
 408         }
 409 somebody_else:
 410         return (dma_stat & 4) == 4;     /* return 1 if INTR asserted */
 411 }
 412
 413 static int pdc202xx_ide_dma_lostirq(ide_drive_t *drive)
 414 {
 415         if (HWIF(drive)->resetproc != NULL)
 416                 HWIF(drive)->resetproc(drive);
 417         return __ide_dma_lostirq(drive);
 418 }
 419
 420 static int pdc202xx_ide_dma_timeout(ide_drive_t *drive)
 421 {
 422         if (HWIF(drive)->resetproc != NULL)
 423                 HWIF(drive)->resetproc(drive);
 424         return __ide_dma_timeout(drive);
 425 }
 426
 427 static void pdc202xx_reset_host (ide_hwif_t *hwif)
 428 {
 429         unsigned long high_16   = hwif->dma_master;
 430         u8 udma_speed_flag      = inb(high_16 | 0x001f);
 431
 432         outb(udma_speed_flag | 0x10, high_16 | 0x001f);
 433         mdelay(100);
 434         outb(udma_speed_flag & ~0x10, high_16 | 0x001f);
 435         mdelay(2000);   /* 2 seconds ?! */
 436
 437         printk(KERN_WARNING "PDC202XX: %s channel reset.\n",
 438                 hwif->channel ? "Secondary" : "Primary");
 439 }
 440
 441 static void pdc202xx_reset (ide_drive_t *drive)
 442 {
 443         ide_hwif_t *hwif        = HWIF(drive);
 444         ide_hwif_t *mate        = hwif->mate;
 445
 446         pdc202xx_reset_host(hwif);
 447         pdc202xx_reset_host(mate);
 448         pdc202xx_tune_drive(drive, 255);
 449 }
 450
 451 static unsigned int __devinit init_chipset_pdc202xx(struct pci_dev *dev,
 452                                                         const char *name)
 453 {
 454         /* This doesn't appear needed */
 455         if (dev->resource[PCI_ROM_RESOURCE].start) {
 456                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
 457                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
 458                 printk(KERN_INFO "%s: ROM enabled at 0x%08lx\n", name,
 459                         (unsigned long)dev->resource[PCI_ROM_RESOURCE].start);
 460         }
 461
 462         return dev->irq;
 463 }
 464
 465 static void __devinit init_hwif_pdc202xx(ide_hwif_t *hwif)
 466 {
 467         struct pci_dev *dev = hwif->pci_dev;
 468
 469         /* PDC20265 has problems with large LBA48 requests */
 470         if ((dev->device == PCI_DEVICE_ID_PROMISE_20267) ||
 471             (dev->device == PCI_DEVICE_ID_PROMISE_20265))
 472                 hwif->rqsize = 256;
 473
 474         hwif->autodma = 0;
 475         hwif->tuneproc  = &pdc202xx_tune_drive;
 476         hwif->quirkproc = &pdc202xx_quirkproc;
 477
 478         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246)
 479                 hwif->resetproc = &pdc202xx_reset;
 480
 481         hwif->speedproc = &pdc202xx_tune_chipset;
 482
 483         hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
 484
 485         hwif->ultra_mask = 0x3f;
 486         hwif->mwdma_mask = 0x07;
 487         hwif->swdma_mask = 0x07;
 488         hwif->atapi_dma = 1;
 489
 490         hwif->err_stops_fifo = 1;
 491
 492         hwif->ide_dma_check = &pdc202xx_config_drive_xfer_rate;
 493         hwif->ide_dma_lostirq = &pdc202xx_ide_dma_lostirq;
 494         hwif->ide_dma_timeout = &pdc202xx_ide_dma_timeout;
 495
 496         if (hwif->pci_dev->device != PCI_DEVICE_ID_PROMISE_20246) {
 497                 if (!(hwif->udma_four))
 498                         hwif->udma_four = (pdc202xx_old_cable_detect(hwif)) ? 0 : 1;
 499                 hwif->dma_start = &pdc202xx_old_ide_dma_start;
 500                 hwif->ide_dma_end = &pdc202xx_old_ide_dma_end;
 501         }
 502         hwif->ide_dma_test_irq = &pdc202xx_old_ide_dma_test_irq;
 503
 504         if (!noautodma)
 505                 hwif->autodma = 1;
 506         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
 507 #if PDC202_DEBUG_CABLE
 508         printk(KERN_DEBUG "%s: %s-pin cable\n",
 509                 hwif->name, hwif->udma_four ? "80" : "40");
 510 #endif /* PDC202_DEBUG_CABLE */
 511 }
 512
 513 static void __devinit init_dma_pdc202xx(ide_hwif_t *hwif, unsigned long dmabase)
 514 {
 515         u8 udma_speed_flag = 0, primary_mode = 0, secondary_mode = 0;
 516
 517         if (hwif->channel) {
 518                 ide_setup_dma(hwif, dmabase, 8);
 519                 return;
 520         }
 521
 522         udma_speed_flag = inb(dmabase | 0x1f);
 523         primary_mode    = inb(dmabase | 0x1a);
 524         secondary_mode  = inb(dmabase | 0x1b);
 525         printk(KERN_INFO "%s: (U)DMA Burst Bit %sABLED " \
 526                 "Primary %s Mode " \
 527                 "Secondary %s Mode.\n", hwif->cds->name,
 528                 (udma_speed_flag & 1) ? "EN" : "DIS",
 529                 (primary_mode & 1) ? "MASTER" : "PCI",
 530                 (secondary_mode & 1) ? "MASTER" : "PCI" );
 531
 532 #ifdef CONFIG_PDC202XX_BURST
 533         if (!(udma_speed_flag & 1)) {
 534                 printk(KERN_INFO "%s: FORCING BURST BIT 0x%02x->0x%02x ",
 535                         hwif->cds->name, udma_speed_flag,
 536                         (udma_speed_flag|1));
 537                 outb(udma_speed_flag | 1, dmabase | 0x1f);
 538                 printk("%sACTIVE\n", (inb(dmabase | 0x1f) & 1) ? "" : "IN");
 539         }
 540 #endif /* CONFIG_PDC202XX_BURST */
 541
 542         ide_setup_dma(hwif, dmabase, 8);
 543 }
 544
 545 static int __devinit init_setup_pdc202ata4(struct pci_dev *dev,
 546                                            ide_pci_device_t *d)
 547 {
 548         if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE) {
 549                 u8 irq = 0, irq2 = 0;
 550                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 551                 /* 0xbc */
 552                 pci_read_config_byte(dev, (PCI_INTERRUPT_LINE)|0x80, &irq2);
 553                 if (irq != irq2) {
 554                         pci_write_config_byte(dev,
 555                                 (PCI_INTERRUPT_LINE)|0x80, irq);     /* 0xbc */
 556                         printk(KERN_INFO "%s: pci-config space interrupt "
 557                                 "mirror fixed.\n", d->name);
 558                 }
 559         }
 560         return ide_setup_pci_device(dev, d);
 561 }
 562
 563 static int __devinit init_setup_pdc20265(struct pci_dev *dev,
 564                                          ide_pci_device_t *d)
 565 {
 566         if ((dev->bus->self) &&
 567             (dev->bus->self->vendor == PCI_VENDOR_ID_INTEL) &&
 568             ((dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960) ||
 569              (dev->bus->self->device == PCI_DEVICE_ID_INTEL_I960RM))) {
 570                 printk(KERN_INFO "ide: Skipping Promise PDC20265 "
 571                         "attached to I2O RAID controller.\n");
 572                 return -ENODEV;
 573         }
 574         return ide_setup_pci_device(dev, d);
 575 }
 576
 577 static int __devinit init_setup_pdc202xx(struct pci_dev *dev,
 578                                          ide_pci_device_t *d)
 579 {
 580         return ide_setup_pci_device(dev, d);
 581 }
 582
 583 static ide_pci_device_t pdc202xx_chipsets[] __devinitdata = {
 584         {       /* 0 */
 585                 .name           = "PDC20246",
 586                 .init_setup     = init_setup_pdc202ata4,
 587                 .init_chipset   = init_chipset_pdc202xx,
 588                 .init_hwif      = init_hwif_pdc202xx,
 589                 .init_dma       = init_dma_pdc202xx,
 590                 .channels       = 2,
 591                 .autodma        = AUTODMA,
 592                 .bootable       = OFF_BOARD,
 593                 .extra          = 16,
 594         },{     /* 1 */
 595                 .name           = "PDC20262",
 596                 .init_setup     = init_setup_pdc202ata4,
 597                 .init_chipset   = init_chipset_pdc202xx,
 598                 .init_hwif      = init_hwif_pdc202xx,
 599                 .init_dma       = init_dma_pdc202xx,
 600                 .channels       = 2,
 601                 .autodma        = AUTODMA,
 602                 .bootable       = OFF_BOARD,
 603                 .extra          = 48,
 604         },{     /* 2 */
 605                 .name           = "PDC20263",
 606                 .init_setup     = init_setup_pdc202ata4,
 607                 .init_chipset   = init_chipset_pdc202xx,
 608                 .init_hwif      = init_hwif_pdc202xx,
 609                 .init_dma       = init_dma_pdc202xx,
 610                 .channels       = 2,
 611                 .autodma        = AUTODMA,
 612                 .bootable       = OFF_BOARD,
 613                 .extra          = 48,
 614         },{     /* 3 */
 615                 .name           = "PDC20265",
 616                 .init_setup     = init_setup_pdc20265,
 617                 .init_chipset   = init_chipset_pdc202xx,
 618                 .init_hwif      = init_hwif_pdc202xx,
 619                 .init_dma       = init_dma_pdc202xx,
 620                 .channels       = 2,
 621                 .autodma        = AUTODMA,
 622                 .bootable       = OFF_BOARD,
 623                 .extra          = 48,
 624         },{     /* 4 */
 625                 .name           = "PDC20267",
 626                 .init_setup     = init_setup_pdc202xx,
 627                 .init_chipset   = init_chipset_pdc202xx,
 628                 .init_hwif      = init_hwif_pdc202xx,
 629                 .init_dma       = init_dma_pdc202xx,
 630                 .channels       = 2,
 631                 .autodma        = AUTODMA,
 632                 .bootable       = OFF_BOARD,
 633                 .extra          = 48,
 634         }
 635 };
 636
 637 /**
 638  *      pdc202xx_init_one       -       called when a PDC202xx is found
 639  *      @dev: the pdc202xx device
 640  *      @id: the matching pci id
 641  *
 642  *      Called when the PCI registration layer (or the IDE initialization)
 643  *      finds a device matching our IDE device tables.
 644  */
 645
 646 static int __devinit pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 647 {
 648         ide_pci_device_t *d = &pdc202xx_chipsets[id->driver_data];
 649
 650         return d->init_setup(dev, d);
 651 }
 652
 653 static struct pci_device_id pdc202xx_pci_tbl[] = {
 654         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20246, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 655         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20262, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 656         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 657         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20265, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 658         { PCI_VENDOR_ID_PROMISE, PCI_DEVICE_ID_PROMISE_20267, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 659         { 0, },
 660 };
 661 MODULE_DEVICE_TABLE(pci, pdc202xx_pci_tbl);
 662
 663 static struct pci_driver driver = {
 664         .name           = "Promise_Old_IDE",
 665         .id_table       = pdc202xx_pci_tbl,
 666         .probe          = pdc202xx_init_one,
 667 };
 668
 669 static int __init pdc202xx_ide_init(void)
 670 {
 671         return ide_pci_register_driver(&driver);
 672 }
 673
 674 module_init(pdc202xx_ide_init);
 675
 676 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan");
 677 MODULE_DESCRIPTION("PCI driver module for older Promise IDE");
 678 MODULE_LICENSE("GPL");