drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.44    May 20, 2006
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
  66  *   as the ATA clock being used does not allow for this speed anyway
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  71  *   HPT37x chip family; save space by introducing the separate transfer mode
  72  *   table in which the mode lookup is done
  73  * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  74  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
  75  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  76  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  77  * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  78  *   they tamper with its fields
  79  * - prefix the driver startup messages with the real chip name
  80  * - claim the extra 240 bytes of I/O space for all chips
  81  * - optimize the rate masking/filtering and the drive list lookup code
  82  *              <source@mvista.com>
  83  *
  84  */
  85
  86
  87 #include <linux/types.h>
  88 #include <linux/module.h>
  89 #include <linux/kernel.h>
  90 #include <linux/delay.h>
  91 #include <linux/timer.h>
  92 #include <linux/mm.h>
  93 #include <linux/ioport.h>
  94 #include <linux/blkdev.h>
  95 #include <linux/hdreg.h>
  96
  97 #include <linux/interrupt.h>
  98 #include <linux/pci.h>
  99 #include <linux/init.h>
 100 #include <linux/ide.h>
 101
 102 #include <asm/uaccess.h>
 103 #include <asm/io.h>
 104 #include <asm/irq.h>
 105
 106 /* various tuning parameters */
 107 #define HPT_RESET_STATE_ENGINE
 108 #undef  HPT_DELAY_INTERRUPT
 109 #define HPT_SERIALIZE_IO        0
 110
 111 static const char *quirk_drives[] = {
 112         "QUANTUM FIREBALLlct08 08",
 113         "QUANTUM FIREBALLP KA6.4",
 114         "QUANTUM FIREBALLP LM20.4",
 115         "QUANTUM FIREBALLP LM20.5",
 116         NULL
 117 };
 118
 119 static const char *bad_ata100_5[] = {
 120         "IBM-DTLA-307075",
 121         "IBM-DTLA-307060",
 122         "IBM-DTLA-307045",
 123         "IBM-DTLA-307030",
 124         "IBM-DTLA-307020",
 125         "IBM-DTLA-307015",
 126         "IBM-DTLA-305040",
 127         "IBM-DTLA-305030",
 128         "IBM-DTLA-305020",
 129         "IC35L010AVER07-0",
 130         "IC35L020AVER07-0",
 131         "IC35L030AVER07-0",
 132         "IC35L040AVER07-0",
 133         "IC35L060AVER07-0",
 134         "WDC AC310200R",
 135         NULL
 136 };
 137
 138 static const char *bad_ata66_4[] = {
 139         "IBM-DTLA-307075",
 140         "IBM-DTLA-307060",
 141         "IBM-DTLA-307045",
 142         "IBM-DTLA-307030",
 143         "IBM-DTLA-307020",
 144         "IBM-DTLA-307015",
 145         "IBM-DTLA-305040",
 146         "IBM-DTLA-305030",
 147         "IBM-DTLA-305020",
 148         "IC35L010AVER07-0",
 149         "IC35L020AVER07-0",
 150         "IC35L030AVER07-0",
 151         "IC35L040AVER07-0",
 152         "IC35L060AVER07-0",
 153         "WDC AC310200R",
 154         NULL
 155 };
 156
 157 static const char *bad_ata66_3[] = {
 158         "WDC AC310200R",
 159         NULL
 160 };
 161
 162 static const char *bad_ata33[] = {
 163         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 164         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 165         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 166         "Maxtor 90510D4",
 167         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 168         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 169         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 170         NULL
 171 };
 172
 173 static u8 xfer_speeds[] = {
 174         XFER_UDMA_6,
 175         XFER_UDMA_5,
 176         XFER_UDMA_4,
 177         XFER_UDMA_3,
 178         XFER_UDMA_2,
 179         XFER_UDMA_1,
 180         XFER_UDMA_0,
 181
 182         XFER_MW_DMA_2,
 183         XFER_MW_DMA_1,
 184         XFER_MW_DMA_0,
 185
 186         XFER_PIO_4,
 187         XFER_PIO_3,
 188         XFER_PIO_2,
 189         XFER_PIO_1,
 190         XFER_PIO_0
 191 };
 192
 193 /* Key for bus clock timings
 194  * 36x   37x
 195  * bits  bits
 196  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 197  *              cycles = value + 1
 198  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 199  *              cycles = value + 1
 200  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 201  *              register access.
 202  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 203  *              register access.
 204  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 205  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 206  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 207  *              MW DMA xfer.
 208  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 209  *              task file register access.
 210  * 28    28     UDMA enable.
 211  * 29    29     DMA  enable.
 212  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 213  *              PIO xfer.
 214  * 31    31     FIFO enable.
 215  */
 216
 217 static u32 forty_base_hpt36x[] = {
 218         /* XFER_UDMA_6 */       0x900fd943,
 219         /* XFER_UDMA_5 */       0x900fd943,
 220         /* XFER_UDMA_4 */       0x900fd943,
 221         /* XFER_UDMA_3 */       0x900ad943,
 222         /* XFER_UDMA_2 */       0x900bd943,
 223         /* XFER_UDMA_1 */       0x9008d943,
 224         /* XFER_UDMA_0 */       0x9008d943,
 225
 226         /* XFER_MW_DMA_2 */     0xa008d943,
 227         /* XFER_MW_DMA_1 */     0xa010d955,
 228         /* XFER_MW_DMA_0 */     0xa010d9fc,
 229
 230         /* XFER_PIO_4 */        0xc008d963,
 231         /* XFER_PIO_3 */        0xc010d974,
 232         /* XFER_PIO_2 */        0xc010d997,
 233         /* XFER_PIO_1 */        0xc010d9c7,
 234         /* XFER_PIO_0 */        0xc018d9d9
 235 };
 236
 237 static u32 thirty_three_base_hpt36x[] = {
 238         /* XFER_UDMA_6 */       0x90c9a731,
 239         /* XFER_UDMA_5 */       0x90c9a731,
 240         /* XFER_UDMA_4 */       0x90c9a731,
 241         /* XFER_UDMA_3 */       0x90cfa731,
 242         /* XFER_UDMA_2 */       0x90caa731,
 243         /* XFER_UDMA_1 */       0x90cba731,
 244         /* XFER_UDMA_0 */       0x90c8a731,
 245
 246         /* XFER_MW_DMA_2 */     0xa0c8a731,
 247         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 248         /* XFER_MW_DMA_0 */     0xa0c8a797,
 249
 250         /* XFER_PIO_4 */        0xc0c8a731,
 251         /* XFER_PIO_3 */        0xc0c8a742,
 252         /* XFER_PIO_2 */        0xc0d0a753,
 253         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 254         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 255 };
 256
 257 static u32 twenty_five_base_hpt36x[] = {
 258         /* XFER_UDMA_6 */       0x90c98521,
 259         /* XFER_UDMA_5 */       0x90c98521,
 260         /* XFER_UDMA_4 */       0x90c98521,
 261         /* XFER_UDMA_3 */       0x90cf8521,
 262         /* XFER_UDMA_2 */       0x90cf8521,
 263         /* XFER_UDMA_1 */       0x90cb8521,
 264         /* XFER_UDMA_0 */       0x90cb8521,
 265
 266         /* XFER_MW_DMA_2 */     0xa0ca8521,
 267         /* XFER_MW_DMA_1 */     0xa0ca8532,
 268         /* XFER_MW_DMA_0 */     0xa0ca8575,
 269
 270         /* XFER_PIO_4 */        0xc0ca8521,
 271         /* XFER_PIO_3 */        0xc0ca8532,
 272         /* XFER_PIO_2 */        0xc0ca8542,
 273         /* XFER_PIO_1 */        0xc0d08572,
 274         /* XFER_PIO_0 */        0xc0d08585
 275 };
 276
 277 static u32 thirty_three_base_hpt37x[] = {
 278         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 279         /* XFER_UDMA_5 */       0x12446231,
 280         /* XFER_UDMA_4 */       0x12446231,
 281         /* XFER_UDMA_3 */       0x126c6231,
 282         /* XFER_UDMA_2 */       0x12486231,
 283         /* XFER_UDMA_1 */       0x124c6233,
 284         /* XFER_UDMA_0 */       0x12506297,
 285
 286         /* XFER_MW_DMA_2 */     0x22406c31,
 287         /* XFER_MW_DMA_1 */     0x22406c33,
 288         /* XFER_MW_DMA_0 */     0x22406c97,
 289
 290         /* XFER_PIO_4 */        0x06414e31,
 291         /* XFER_PIO_3 */        0x06414e42,
 292         /* XFER_PIO_2 */        0x06414e53,
 293         /* XFER_PIO_1 */        0x06814e93,
 294         /* XFER_PIO_0 */        0x06814ea7
 295 };
 296
 297 static u32 fifty_base_hpt37x[] = {
 298         /* XFER_UDMA_6 */       0x12848242,
 299         /* XFER_UDMA_5 */       0x12848242,
 300         /* XFER_UDMA_4 */       0x12ac8242,
 301         /* XFER_UDMA_3 */       0x128c8242,
 302         /* XFER_UDMA_2 */       0x120c8242,
 303         /* XFER_UDMA_1 */       0x12148254,
 304         /* XFER_UDMA_0 */       0x121882ea,
 305
 306         /* XFER_MW_DMA_2 */     0x22808242,
 307         /* XFER_MW_DMA_1 */     0x22808254,
 308         /* XFER_MW_DMA_0 */     0x228082ea,
 309
 310         /* XFER_PIO_4 */        0x0a81f442,
 311         /* XFER_PIO_3 */        0x0a81f443,
 312         /* XFER_PIO_2 */        0x0a81f454,
 313         /* XFER_PIO_1 */        0x0ac1f465,
 314         /* XFER_PIO_0 */        0x0ac1f48a
 315 };
 316
 317 static u32 sixty_six_base_hpt37x[] = {
 318         /* XFER_UDMA_6 */       0x1c869c62,
 319         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 320         /* XFER_UDMA_4 */       0x1c8a9c62,
 321         /* XFER_UDMA_3 */       0x1c8e9c62,
 322         /* XFER_UDMA_2 */       0x1c929c62,
 323         /* XFER_UDMA_1 */       0x1c9a9c62,
 324         /* XFER_UDMA_0 */       0x1c829c62,
 325
 326         /* XFER_MW_DMA_2 */     0x2c829c62,
 327         /* XFER_MW_DMA_1 */     0x2c829c66,
 328         /* XFER_MW_DMA_0 */     0x2c829d2e,
 329
 330         /* XFER_PIO_4 */        0x0c829c62,
 331         /* XFER_PIO_3 */        0x0c829c84,
 332         /* XFER_PIO_2 */        0x0c829ca6,
 333         /* XFER_PIO_1 */        0x0d029d26,
 334         /* XFER_PIO_0 */        0x0d029d5e
 335 };
 336
 337 #define HPT366_DEBUG_DRIVE_INFO         0
 338 #define HPT374_ALLOW_ATA133_6           0
 339 #define HPT371_ALLOW_ATA133_6           0
 340 #define HPT302_ALLOW_ATA133_6           0
 341 #define HPT372_ALLOW_ATA133_6           0
 342 #define HPT370_ALLOW_ATA100_5           0
 343 #define HPT366_ALLOW_ATA66_4            1
 344 #define HPT366_ALLOW_ATA66_3            1
 345 #define HPT366_MAX_DEVS                 8
 346
 347 #define F_LOW_PCI_33    0x23
 348 #define F_LOW_PCI_40    0x29
 349 #define F_LOW_PCI_50    0x2d
 350 #define F_LOW_PCI_66    0x42
 351
 352 /*
 353  *      Hold all the highpoint quirks and revision information in one
 354  *      place.
 355  */
 356
 357 struct hpt_info
 358 {
 359         u8 max_mode;            /* Speeds allowed */
 360         u8 revision;            /* Chipset revision */
 361         u8 flags;               /* Chipset properties */
 362 #define PLL_MODE        1
 363 #define IS_3xxN         2
 364 #define PCI_66MHZ       4
 365                                 /* Speed table */
 366         u32 *speed;
 367 };
 368
 369 /*
 370  *      This wants fixing so that we do everything not by revision
 371  *      (which breaks on the newest chips) but by creating an
 372  *      enumeration of chip variants and using that
 373  */
 374
 375 static __devinit u8 hpt_revision(struct pci_dev *dev)
 376 {
 377         u8 rev = 0;
 378
 379         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
 380
 381         switch(dev->device) {
 382                 /* Remap new 372N onto 372 */
 383                 case PCI_DEVICE_ID_TTI_HPT372N:
 384                         rev = PCI_DEVICE_ID_TTI_HPT372;
 385                         break;
 386                 case PCI_DEVICE_ID_TTI_HPT374:
 387                         rev = PCI_DEVICE_ID_TTI_HPT374;
 388                         break;
 389                 case PCI_DEVICE_ID_TTI_HPT371:
 390                         rev = PCI_DEVICE_ID_TTI_HPT371;
 391                         break;
 392                 case PCI_DEVICE_ID_TTI_HPT302:
 393                         rev = PCI_DEVICE_ID_TTI_HPT302;
 394                         break;
 395                 case PCI_DEVICE_ID_TTI_HPT372:
 396                         rev = PCI_DEVICE_ID_TTI_HPT372;
 397                         break;
 398                 default:
 399                         break;
 400         }
 401         return rev;
 402 }
 403
 404 static int check_in_drive_list(ide_drive_t *drive, const char **list)
 405 {
 406         struct hd_driveid *id = drive->id;
 407
 408         while (*list)
 409                 if (!strcmp(*list++,id->model))
 410                         return 1;
 411         return 0;
 412 }
 413
 414 static u8 hpt3xx_ratemask(ide_drive_t *drive)
 415 {
 416         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 417         u8 mode                 = info->max_mode;
 418
 419         if (!eighty_ninty_three(drive) && mode)
 420                 mode = min(mode, (u8)1);
 421         return mode;
 422 }
 423
 424 /*
 425  *      Note for the future; the SATA hpt37x we must set
 426  *      either PIO or UDMA modes 0,4,5
 427  */
 428
 429 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
 430 {
 431         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 432         u8 mode                 = hpt3xx_ratemask(drive);
 433
 434         if (drive->media != ide_disk)
 435                 return min(speed, (u8)XFER_PIO_4);
 436
 437         switch (mode) {
 438                 case 0x04:
 439                         speed = min(speed, (u8)XFER_UDMA_6);
 440                         break;
 441                 case 0x03:
 442                         speed = min(speed, (u8)XFER_UDMA_5);
 443                         if (info->revision >= 5)
 444                                 break;
 445                         if (!check_in_drive_list(drive, bad_ata100_5))
 446                                 goto check_bad_ata33;
 447                         /* fall thru */
 448                 case 0x02:
 449                         speed = min_t(u8, speed, XFER_UDMA_4);
 450         /*
 451          * CHECK ME, Does this need to be set to 5 ??
 452          */
 453                         if (info->revision >= 3)
 454                                 goto check_bad_ata33;
 455                         if (HPT366_ALLOW_ATA66_4 &&
 456                             !check_in_drive_list(drive, bad_ata66_4))
 457                                 goto check_bad_ata33;
 458
 459                         speed = min_t(u8, speed, XFER_UDMA_3);
 460                         if (HPT366_ALLOW_ATA66_3 &&
 461                             !check_in_drive_list(drive, bad_ata66_3))
 462                                 goto check_bad_ata33;
 463                         /* fall thru */
 464                 case 0x01:
 465                         speed = min_t(u8, speed, XFER_UDMA_2);
 466
 467                 check_bad_ata33:
 468                         if (info->revision >= 4)
 469                                 break;
 470                         if (!check_in_drive_list(drive, bad_ata33))
 471                                 break;
 472                         /* fall thru */
 473                 case 0x00:
 474                 default:
 475                         speed = min_t(u8, speed, XFER_MW_DMA_2);
 476                         break;
 477         }
 478         return speed;
 479 }
 480
 481 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
 482 {
 483         int i;
 484
 485         /*
 486          * Lookup the transfer mode table to get the index into
 487          * the timing table.
 488          *
 489          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 490          */
 491         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 492                 if (xfer_speeds[i] == speed)
 493                         break;
 494         return chipset_table[i];
 495 }
 496
 497 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 498 {
 499         ide_hwif_t *hwif        = drive->hwif;
 500         struct pci_dev *dev     = hwif->pci_dev;
 501         struct hpt_info *info   = ide_get_hwifdata(hwif);
 502         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 503         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 504         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
 505         u8 drive_fast           = 0;
 506         u32 reg1 = 0, reg2      = 0;
 507
 508         /*
 509          * Disable the "fast interrupt" prediction.
 510          */
 511         pci_read_config_byte(dev, regfast, &drive_fast);
 512         if (drive_fast & 0x80)
 513                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 514
 515         reg2 = pci_bus_clock_list(speed, info->speed);
 516
 517         /*
 518          * Disable on-chip PIO FIFO/buffer
 519          *  (to avoid problems handling I/O errors later)
 520          */
 521         pci_read_config_dword(dev, regtime, &reg1);
 522         if (speed >= XFER_MW_DMA_0) {
 523                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 524         } else {
 525                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 526         }
 527         reg2 &= ~0x80000000;
 528
 529         pci_write_config_dword(dev, regtime, reg2);
 530
 531         return ide_config_drive_speed(drive, speed);
 532 }
 533
 534 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 535 {
 536         ide_hwif_t *hwif        = drive->hwif;
 537         struct pci_dev *dev = hwif->pci_dev;
 538         struct hpt_info *info   = ide_get_hwifdata(hwif);
 539         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 540         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 541         u8 drive_pci    = 0x40 + (drive->dn * 4);
 542         u8 new_fast     = 0, drive_fast = 0;
 543         u32 list_conf   = 0, drive_conf = 0;
 544         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 545
 546         /*
 547          * Disable the "fast interrupt" prediction.
 548          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 549          */
 550         pci_read_config_byte(dev, regfast, &drive_fast);
 551         new_fast = drive_fast;
 552         if (new_fast & 0x02)
 553                 new_fast &= ~0x02;
 554
 555 #ifdef HPT_DELAY_INTERRUPT
 556         if (new_fast & 0x01)
 557                 new_fast &= ~0x01;
 558 #else
 559         if ((new_fast & 0x01) == 0)
 560                 new_fast |= 0x01;
 561 #endif
 562         if (new_fast != drive_fast)
 563                 pci_write_config_byte(dev, regfast, new_fast);
 564
 565         list_conf = pci_bus_clock_list(speed, info->speed);
 566
 567         pci_read_config_dword(dev, drive_pci, &drive_conf);
 568         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 569
 570         if (speed < XFER_MW_DMA_0)
 571                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 572         pci_write_config_dword(dev, drive_pci, list_conf);
 573
 574         return ide_config_drive_speed(drive, speed);
 575 }
 576
 577 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 578 {
 579         ide_hwif_t *hwif        = drive->hwif;
 580         struct pci_dev *dev     = hwif->pci_dev;
 581         struct hpt_info *info   = ide_get_hwifdata(hwif);
 582         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 583         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 584         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 585         u32 list_conf   = 0, drive_conf = 0;
 586         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 587
 588         /*
 589          * Disable the "fast interrupt" prediction.
 590          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 591          */
 592         pci_read_config_byte(dev, regfast, &drive_fast);
 593         drive_fast &= ~0x07;
 594         pci_write_config_byte(dev, regfast, drive_fast);
 595
 596         list_conf = pci_bus_clock_list(speed, info->speed);
 597         pci_read_config_dword(dev, drive_pci, &drive_conf);
 598         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 599         if (speed < XFER_MW_DMA_0)
 600                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 601         pci_write_config_dword(dev, drive_pci, list_conf);
 602
 603         return ide_config_drive_speed(drive, speed);
 604 }
 605
 606 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 607 {
 608         ide_hwif_t *hwif        = drive->hwif;
 609         struct hpt_info *info   = ide_get_hwifdata(hwif);
 610
 611         if (info->revision >= 8)
 612                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 613         else if (info->revision >= 5)
 614                 return hpt372_tune_chipset(drive, speed);
 615         else if (info->revision >= 3)
 616                 return hpt370_tune_chipset(drive, speed);
 617         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 618                 return hpt36x_tune_chipset(drive, speed);
 619 }
 620
 621 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 622 {
 623         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 624         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 625 }
 626
 627 /*
 628  * This allows the configuration of ide_pci chipset registers
 629  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 630  * after the drive is reported by the OS.  Initially for designed for
 631  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 632  *
 633  * check_in_drive_lists(drive, bad_ata66_4)
 634  * check_in_drive_lists(drive, bad_ata66_3)
 635  * check_in_drive_lists(drive, bad_ata33)
 636  *
 637  */
 638 static int config_chipset_for_dma (ide_drive_t *drive)
 639 {
 640         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 641         ide_hwif_t *hwif = drive->hwif;
 642         struct hpt_info *info   = ide_get_hwifdata(hwif);
 643
 644         if (!speed)
 645                 return 0;
 646
 647         /* If we don't have any timings we can't do a lot */
 648         if (info->speed == NULL)
 649                 return 0;
 650
 651         (void) hpt3xx_tune_chipset(drive, speed);
 652         return ide_dma_enable(drive);
 653 }
 654
 655 static int hpt3xx_quirkproc(ide_drive_t *drive)
 656 {
 657         struct hd_driveid *id   = drive->id;
 658         const  char **list      = quirk_drives;
 659
 660         while (*list)
 661                 if (strstr(id->model, *list++))
 662                         return 1;
 663         return 0;
 664 }
 665
 666 static void hpt3xx_intrproc (ide_drive_t *drive)
 667 {
 668         ide_hwif_t *hwif = drive->hwif;
 669
 670         if (drive->quirk_list)
 671                 return;
 672         /* drives in the quirk_list may not like intr setups/cleanups */
 673         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 674 }
 675
 676 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 677 {
 678         ide_hwif_t *hwif = drive->hwif;
 679         struct hpt_info *info = ide_get_hwifdata(hwif);
 680         struct pci_dev *dev = hwif->pci_dev;
 681
 682         if (drive->quirk_list) {
 683                 if (info->revision >= 3) {
 684                         u8 reg5a = 0;
 685                         pci_read_config_byte(dev, 0x5a, &reg5a);
 686                         if (((reg5a & 0x10) >> 4) != mask)
 687                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 688                 } else {
 689                         if (mask) {
 690                                 disable_irq(hwif->irq);
 691                         } else {
 692                                 enable_irq(hwif->irq);
 693                         }
 694                 }
 695         } else {
 696                 if (IDE_CONTROL_REG)
 697                         hwif->OUTB(mask ? (drive->ctl | 2) :
 698                                                  (drive->ctl & ~2),
 699                                                  IDE_CONTROL_REG);
 700         }
 701 }
 702
 703 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 704 {
 705         ide_hwif_t *hwif        = drive->hwif;
 706         struct hd_driveid *id   = drive->id;
 707
 708         drive->init_speed = 0;
 709
 710         if ((id->capability & 1) && drive->autodma) {
 711
 712                 if (ide_use_dma(drive)) {
 713                         if (config_chipset_for_dma(drive))
 714                                 return hwif->ide_dma_on(drive);
 715                 }
 716
 717                 goto fast_ata_pio;
 718
 719         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 720 fast_ata_pio:
 721                 hpt3xx_tune_drive(drive, 5);
 722                 return hwif->ide_dma_off_quietly(drive);
 723         }
 724         /* IORDY not supported */
 725         return 0;
 726 }
 727
 728 /*
 729  * This is specific to the HPT366 UDMA bios chipset
 730  * by HighPoint|Triones Technologies, Inc.
 731  */
 732 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 733 {
 734         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 735         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 736
 737         pci_read_config_byte(dev, 0x50, &reg50h);
 738         pci_read_config_byte(dev, 0x52, &reg52h);
 739         pci_read_config_byte(dev, 0x5a, &reg5ah);
 740         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 741                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 742         if (reg5ah & 0x10)
 743                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 744         return __ide_dma_lostirq(drive);
 745 }
 746
 747 static void hpt370_clear_engine (ide_drive_t *drive)
 748 {
 749         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 750         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 751         udelay(10);
 752 }
 753
 754 static void hpt370_ide_dma_start(ide_drive_t *drive)
 755 {
 756 #ifdef HPT_RESET_STATE_ENGINE
 757         hpt370_clear_engine(drive);
 758 #endif
 759         ide_dma_start(drive);
 760 }
 761
 762 static int hpt370_ide_dma_end (ide_drive_t *drive)
 763 {
 764         ide_hwif_t *hwif        = HWIF(drive);
 765         u8 dma_stat             = hwif->INB(hwif->dma_status);
 766
 767         if (dma_stat & 0x01) {
 768                 /* wait a little */
 769                 udelay(20);
 770                 dma_stat = hwif->INB(hwif->dma_status);
 771         }
 772         if ((dma_stat & 0x01) != 0)
 773                 /* fallthrough */
 774                 (void) HWIF(drive)->ide_dma_timeout(drive);
 775
 776         return __ide_dma_end(drive);
 777 }
 778
 779 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 780 {
 781         ide_hwif_t *hwif        = HWIF(drive);
 782         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 783         u8 dma_stat = 0, dma_cmd = 0;
 784
 785         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 786         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 787         hpt370_clear_engine(drive);
 788         /* get dma command mode */
 789         dma_cmd = hwif->INB(hwif->dma_command);
 790         /* stop dma */
 791         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 792         dma_stat = hwif->INB(hwif->dma_status);
 793         /* clear errors */
 794         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 795 }
 796
 797 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 798 {
 799         hpt370_lostirq_timeout(drive);
 800         hpt370_clear_engine(drive);
 801         return __ide_dma_timeout(drive);
 802 }
 803
 804 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 805 {
 806         hpt370_lostirq_timeout(drive);
 807         hpt370_clear_engine(drive);
 808         return __ide_dma_lostirq(drive);
 809 }
 810
 811 /* returns 1 if DMA IRQ issued, 0 otherwise */
 812 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 813 {
 814         ide_hwif_t *hwif        = HWIF(drive);
 815         u16 bfifo               = 0;
 816         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 817         u8 dma_stat;
 818
 819         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 820         if (bfifo & 0x1FF) {
 821 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 822                 return 0;
 823         }
 824
 825         dma_stat = hwif->INB(hwif->dma_status);
 826         /* return 1 if INTR asserted */
 827         if ((dma_stat & 4) == 4)
 828                 return 1;
 829
 830         if (!drive->waiting_for_dma)
 831                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 832                                 drive->name, __FUNCTION__);
 833         return 0;
 834 }
 835
 836 static int hpt374_ide_dma_end (ide_drive_t *drive)
 837 {
 838         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 839         ide_hwif_t *hwif        = HWIF(drive);
 840         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 841         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 842
 843         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 844         pci_read_config_byte(dev, mscreg, &msc_stat);
 845         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 846                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 847         return __ide_dma_end(drive);
 848 }
 849
 850 /**
 851  *      hpt3xxn_set_clock       -       perform clock switching dance
 852  *      @hwif: hwif to switch
 853  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 854  *
 855  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 856  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 857  *      doesn't physically exist anyway...
 858  */
 859
 860 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 861 {
 862         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 863
 864         if ((scr2 & 0x7f) == mode)
 865                 return;
 866
 867         /* MISC. control register 1 has the channel enable bit... */
 868         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 869
 870         /* Tristate the bus */
 871         if (mcr1 & 0x04)
 872                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 873         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 874
 875         /* Switch clock and reset channels */
 876         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 877         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 878
 879         /* Reset state machines */
 880         if (mcr1 & 0x04)
 881                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
 882         hwif->OUTB(0x37, hwif->dma_master + 0x74);
 883
 884         /* Complete reset */
 885         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 886
 887         /* Reconnect channels to bus */
 888         if (mcr1 & 0x04)
 889                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
 890         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 891 }
 892
 893 /**
 894  *      hpt3xxn_rw_disk         -       prepare for I/O
 895  *      @drive: drive for command
 896  *      @rq: block request structure
 897  *
 898  *      This is called when a disk I/O is issued to HPT3xxN.
 899  *      We need it because of the clock switching.
 900  */
 901
 902 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 903 {
 904         ide_hwif_t *hwif        = HWIF(drive);
 905         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
 906
 907         hpt3xxn_set_clock(hwif, wantclock);
 908 }
 909
 910 /*
 911  * Set/get power state for a drive.
 912  *
 913  * When we turn the power back on, we need to re-initialize things.
 914  */
 915 #define TRISTATE_BIT  0x8000
 916
 917 static int hpt3xx_busproc(ide_drive_t *drive, int state)
 918 {
 919         ide_hwif_t *hwif        = drive->hwif;
 920         struct pci_dev *dev     = hwif->pci_dev;
 921         u8  tristate, resetmask, bus_reg = 0;
 922         u16 tri_reg = 0;
 923
 924         hwif->bus_state = state;
 925
 926         if (hwif->channel) {
 927                 /* secondary channel */
 928                 tristate  = 0x56;
 929                 resetmask = 0x80;
 930         } else {
 931                 /* primary channel */
 932                 tristate  = 0x52;
 933                 resetmask = 0x40;
 934         }
 935
 936         /* Grab the status. */
 937         pci_read_config_word(dev, tristate, &tri_reg);
 938         pci_read_config_byte(dev, 0x59, &bus_reg);
 939
 940         /*
 941          * Set the state. We don't set it if we don't need to do so.
 942          * Make sure that the drive knows that it has failed if it's off.
 943          */
 944         switch (state) {
 945         case BUSSTATE_ON:
 946                 if (!(bus_reg & resetmask))
 947                         return 0;
 948                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
 949
 950                 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
 951                 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
 952                 return 0;
 953         case BUSSTATE_OFF:
 954                 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
 955                         return 0;
 956                 tri_reg &= ~TRISTATE_BIT;
 957                 break;
 958         case BUSSTATE_TRISTATE:
 959                 if ((bus_reg & resetmask) &&  (tri_reg & TRISTATE_BIT))
 960                         return 0;
 961                 tri_reg |= TRISTATE_BIT;
 962                 break;
 963         default:
 964                 return -EINVAL;
 965         }
 966
 967         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 968         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 969
 970         pci_write_config_word(dev, tristate, tri_reg);
 971         pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
 972         return 0;
 973 }
 974
 975 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
 976 {
 977         u32 reg1        = 0;
 978         struct hpt_info *info = ide_get_hwifdata(hwif);
 979
 980         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
 981
 982         /* detect bus speed by looking at control reg timing: */
 983         switch((reg1 >> 8) & 7) {
 984                 case 5:
 985                         info->speed = forty_base_hpt36x;
 986                         break;
 987                 case 9:
 988                         info->speed = twenty_five_base_hpt36x;
 989                         break;
 990                 case 7:
 991                 default:
 992                         info->speed = thirty_three_base_hpt36x;
 993                         break;
 994         }
 995 }
 996
 997 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
 998 {
 999         struct hpt_info *info   = ide_get_hwifdata(hwif);
1000         struct pci_dev  *dev    = hwif->pci_dev;
1001         char *name              = hwif->cds->name;
1002         int adjust, i;
1003         u16 freq = 0;
1004         u32 pll, temp = 0;
1005         u8 reg5bh = 0, mcr1 = 0;
1006
1007         /*
1008          * default to pci clock. make sure MA15/16 are set to output
1009          * to prevent drives having problems with 40-pin cables. Needed
1010          * for some drives such as IBM-DTLA which will not enter ready
1011          * state on reset when PDIAG is a input.
1012          *
1013          * ToDo: should we set 0x21 when using PLL mode ?
1014          */
1015         pci_write_config_byte(dev, 0x5b, 0x23);
1016
1017         /*
1018          * We'll have to read f_CNT value in order to determine
1019          * the PCI clock frequency according to the following ratio:
1020          *
1021          * f_CNT = Fpci * 192 / Fdpll
1022          *
1023          * First try reading the register in which the HighPoint BIOS
1024          * saves f_CNT value before  reprogramming the DPLL from its
1025          * default setting (which differs for the various chips).
1026          * NOTE: This register is only accessible via I/O space.
1027          *
1028          * In case the signature check fails, we'll have to resort to
1029          * reading the f_CNT register itself in hopes that nobody has
1030          * touched the DPLL yet...
1031          */
1032         temp = inl(pci_resource_start(dev, 4) + 0x90);
1033         if ((temp & 0xFFFFF000) != 0xABCDE000) {
1034                 printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
1035
1036                 /* Calculate the average value of f_CNT */
1037                 for (temp = i = 0; i < 128; i++) {
1038                         pci_read_config_word(dev, 0x78, &freq);
1039                         temp += freq & 0x1ff;
1040                         mdelay(1);
1041                 }
1042                 freq = temp / 128;
1043         } else
1044                 freq = temp & 0x1ff;
1045
1046         /*
1047          * HPT3xxN chips use different PCI clock information.
1048          * Currently we always set up the PLL for them.
1049          */
1050
1051         if (info->flags & IS_3xxN) {
1052                 if(freq < 0x55)
1053                         pll = F_LOW_PCI_33;
1054                 else if(freq < 0x70)
1055                         pll = F_LOW_PCI_40;
1056                 else if(freq < 0x7F)
1057                         pll = F_LOW_PCI_50;
1058                 else
1059                         pll = F_LOW_PCI_66;
1060
1061         } else {
1062                 if(freq < 0x9C)
1063                         pll = F_LOW_PCI_33;
1064                 else if(freq < 0xb0)
1065                         pll = F_LOW_PCI_40;
1066                 else if(freq <0xc8)
1067                         pll = F_LOW_PCI_50;
1068                 else
1069                         pll = F_LOW_PCI_66;
1070         }
1071         printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
1072
1073         if (!(info->flags & IS_3xxN)) {
1074                 if (pll == F_LOW_PCI_33) {
1075                         info->speed = thirty_three_base_hpt37x;
1076                         printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
1077                 } else if (pll == F_LOW_PCI_40) {
1078                         /* Unsupported */
1079                 } else if (pll == F_LOW_PCI_50) {
1080                         info->speed = fifty_base_hpt37x;
1081                         printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
1082                 } else {
1083                         info->speed = sixty_six_base_hpt37x;
1084                         printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
1085                 }
1086         }
1087
1088         if (pll == F_LOW_PCI_66)
1089                 info->flags |= PCI_66MHZ;
1090
1091         /*
1092          * only try the pll if we don't have a table for the clock
1093          * speed that we're running at. NOTE: the internal PLL will
1094          * result in slow reads when using a 33MHz PCI clock. we also
1095          * don't like to use the PLL because it will cause glitches
1096          * on PRST/SRST when the HPT state engine gets reset.
1097          *
1098          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1099          * 372 device so we can get ATA133 support
1100          */
1101         if (info->speed)
1102                 goto init_hpt37X_done;
1103
1104         info->flags |= PLL_MODE;
1105
1106         /*
1107          * Adjust the PLL based upon the PCI clock, enable it, and
1108          * wait for stabilization...
1109          */
1110         adjust = 0;
1111         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1112         while (adjust++ < 6) {
1113                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1114                                        pll | 0x100);
1115
1116                 /* wait for clock stabilization */
1117                 for (i = 0; i < 0x50000; i++) {
1118                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1119                         if (reg5bh & 0x80) {
1120                                 /* spin looking for the clock to destabilize */
1121                                 for (i = 0; i < 0x1000; ++i) {
1122                                         pci_read_config_byte(dev, 0x5b,
1123                                                              &reg5bh);
1124                                         if ((reg5bh & 0x80) == 0)
1125                                                 goto pll_recal;
1126                                 }
1127                                 pci_read_config_dword(dev, 0x5c, &pll);
1128                                 pci_write_config_dword(dev, 0x5c,
1129                                                        pll & ~0x100);
1130                                 pci_write_config_byte(dev, 0x5b, 0x21);
1131
1132                                 info->speed = fifty_base_hpt37x;
1133                                 printk("%s: using 50MHz internal PLL\n", name);
1134                                 goto init_hpt37X_done;
1135                         }
1136                 }
1137 pll_recal:
1138                 if (adjust & 1)
1139                         pll -= (adjust >> 1);
1140                 else
1141                         pll += (adjust >> 1);
1142         }
1143
1144 init_hpt37X_done:
1145         if (!info->speed)
1146                 printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
1147                        name, pll, freq);
1148         /*
1149          * Reset the state engines.
1150          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1151          */
1152         pci_read_config_byte(dev, 0x50, &mcr1);
1153         if (mcr1 & 0x04)
1154                 pci_write_config_byte(dev, 0x50, 0x37);
1155         pci_write_config_byte(dev, 0x54, 0x37);
1156         udelay(100);
1157 }
1158
1159 static int __devinit init_hpt37x(struct pci_dev *dev)
1160 {
1161         u8 reg5ah;
1162
1163         pci_read_config_byte(dev, 0x5a, &reg5ah);
1164         /* interrupt force enable */
1165         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1166         return 0;
1167 }
1168
1169 static int __devinit init_hpt366(struct pci_dev *dev)
1170 {
1171         u32 reg1        = 0;
1172         u8 drive_fast   = 0;
1173
1174         /*
1175          * Disable the "fast interrupt" prediction.
1176          */
1177         pci_read_config_byte(dev, 0x51, &drive_fast);
1178         if (drive_fast & 0x80)
1179                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1180         pci_read_config_dword(dev, 0x40, &reg1);
1181
1182         return 0;
1183 }
1184
1185 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1186 {
1187         int ret = 0;
1188
1189         /*
1190          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1191          * We don't seem to be using it.
1192          */
1193         if (dev->resource[PCI_ROM_RESOURCE].start)
1194                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1195                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1196
1197         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1198         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1199         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1200         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1201
1202         if (hpt_revision(dev) >= 3)
1203                 ret = init_hpt37x(dev);
1204         else
1205                 ret = init_hpt366(dev);
1206
1207         if (ret)
1208                 return ret;
1209
1210         return dev->irq;
1211 }
1212
1213 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1214 {
1215         struct pci_dev *dev             = hwif->pci_dev;
1216         struct hpt_info *info           = ide_get_hwifdata(hwif);
1217         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1218         int serialize                   = HPT_SERIALIZE_IO;
1219
1220         hwif->tuneproc                  = &hpt3xx_tune_drive;
1221         hwif->speedproc                 = &hpt3xx_tune_chipset;
1222         hwif->quirkproc                 = &hpt3xx_quirkproc;
1223         hwif->intrproc                  = &hpt3xx_intrproc;
1224         hwif->maskproc                  = &hpt3xx_maskproc;
1225
1226         /*
1227          * HPT3xxN chips have some complications:
1228          *
1229          * - on 33 MHz PCI we must clock switch
1230          * - on 66 MHz PCI we must NOT use the PCI clock
1231          */
1232         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1233                 /*
1234                  * Clock is shared between the channels,
1235                  * so we'll have to serialize them... :-(
1236                  */
1237                 serialize = 1;
1238                 hwif->rw_disk = &hpt3xxn_rw_disk;
1239         }
1240
1241         /*
1242          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1243          * address lines to access an external eeprom.  To read valid
1244          * cable detect state the pins must be enabled as inputs.
1245          */
1246         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1247                 /*
1248                  * HPT374 PCI function 1
1249                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1250                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1251                  */
1252                 u16 mcr3, mcr6;
1253                 pci_read_config_word(dev, 0x52, &mcr3);
1254                 pci_read_config_word(dev, 0x56, &mcr6);
1255                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1256                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1257                 /* now read cable id register */
1258                 pci_read_config_byte(dev, 0x5a, &ata66);
1259                 pci_write_config_word(dev, 0x52, mcr3);
1260                 pci_write_config_word(dev, 0x56, mcr6);
1261         } else if (info->revision >= 3) {
1262                 /*
1263                  * HPT370/372 and 374 pcifn 0
1264                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1265                  */
1266                 u8 scr2;
1267                 pci_read_config_byte(dev, 0x5b, &scr2);
1268                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1269                 /* now read cable id register */
1270                 pci_read_config_byte(dev, 0x5a, &ata66);
1271                 pci_write_config_byte(dev, 0x5b, scr2);
1272         } else {
1273                 pci_read_config_byte(dev, 0x5a, &ata66);
1274         }
1275
1276 #ifdef DEBUG
1277         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1278                 ata66, (ata66 & regmask) ? "33" : "66",
1279                 PCI_FUNC(hwif->pci_dev->devfn));
1280 #endif /* DEBUG */
1281
1282         /* Serialize access to this device */
1283         if (serialize && hwif->mate)
1284                 hwif->serialized = hwif->mate->serialized = 1;
1285
1286         /*
1287          * Set up ioctl for power status.
1288          * NOTE:  power affects both drives on each channel.
1289          */
1290         hwif->busproc = &hpt3xx_busproc;
1291
1292         if (!hwif->dma_base) {
1293                 hwif->drives[0].autotune = 1;
1294                 hwif->drives[1].autotune = 1;
1295                 return;
1296         }
1297
1298         hwif->ultra_mask = 0x7f;
1299         hwif->mwdma_mask = 0x07;
1300
1301         if (!(hwif->udma_four))
1302                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1303         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1304
1305         if (info->revision >= 8) {
1306                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1307                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1308         } else if (info->revision >= 5) {
1309                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1310                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1311         } else if (info->revision >= 3) {
1312                 hwif->dma_start = &hpt370_ide_dma_start;
1313                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1314                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1315                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1316         } else if (info->revision >= 2)
1317                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1318         else
1319                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1320
1321         if (!noautodma)
1322                 hwif->autodma = 1;
1323         hwif->drives[0].autodma = hwif->autodma;
1324         hwif->drives[1].autodma = hwif->autodma;
1325 }
1326
1327 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1328 {
1329         struct hpt_info *info   = ide_get_hwifdata(hwif);
1330         u8 masterdma    = 0, slavedma = 0;
1331         u8 dma_new      = 0, dma_old = 0;
1332         u8 primary      = hwif->channel ? 0x4b : 0x43;
1333         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1334         unsigned long flags;
1335
1336         if (!dmabase)
1337                 return;
1338
1339         if(info->speed == NULL) {
1340                 printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n",
1341                        hwif->cds->name);
1342                 return;
1343         }
1344
1345         dma_old = hwif->INB(dmabase+2);
1346
1347         local_irq_save(flags);
1348
1349         dma_new = dma_old;
1350         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1351         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1352
1353         if (masterdma & 0x30)   dma_new |= 0x20;
1354         if (slavedma & 0x30)    dma_new |= 0x40;
1355         if (dma_new != dma_old)
1356                 hwif->OUTB(dma_new, dmabase+2);
1357
1358         local_irq_restore(flags);
1359
1360         ide_setup_dma(hwif, dmabase, 8);
1361 }
1362
1363 /*
1364  *      We "borrow" this hook in order to set the data structures
1365  *      up early enough before dma or init_hwif calls are made.
1366  */
1367
1368 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1369 {
1370         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1371         struct pci_dev  *dev    = hwif->pci_dev;
1372         u16 did                 = dev->device;
1373         u8 mode, rid            = 0;
1374
1375         if(info == NULL) {
1376                 printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name);
1377                 return;
1378         }
1379         ide_set_hwifdata(hwif, info);
1380
1381         /* Avoid doing the same thing twice. */
1382         if (hwif->channel && hwif->mate) {
1383                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1384                 return;
1385         }
1386
1387         pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
1388
1389         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1390             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1391               did == PCI_DEVICE_ID_TTI_HPT302  ||
1392               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1393               did == PCI_DEVICE_ID_TTI_HPT372N)
1394                 info->flags |= IS_3xxN;
1395
1396         rid = info->revision = hpt_revision(dev);
1397         if (rid >= 8)                   /* HPT374 */
1398                 mode = HPT374_ALLOW_ATA133_6 ? 4 : 3;
1399         else if (rid >= 7)              /* HPT371 and HPT371N */
1400                 mode = HPT371_ALLOW_ATA133_6 ? 4 : 3;
1401         else if (rid >= 6)              /* HPT302 and HPT302N */
1402                 mode = HPT302_ALLOW_ATA133_6 ? 4 : 3;
1403         else if (rid >= 5)              /* HPT372, HPT372A, and HPT372N */
1404                 mode = HPT372_ALLOW_ATA133_6 ? 4 : 3;
1405         else if (rid >= 3)              /* HPT370 and HPT370A */
1406                 mode = HPT370_ALLOW_ATA100_5 ? 3 : 2;
1407         else                            /* HPT366 and HPT368 */
1408                 mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1;
1409         info->max_mode = mode;
1410
1411         if (rid >= 3)
1412                 hpt37x_clocking(hwif);
1413         else
1414                 hpt366_clocking(hwif);
1415 }
1416
1417 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1418 {
1419         struct pci_dev *findev = NULL;
1420
1421         if (PCI_FUNC(dev->devfn) & 1)
1422                 return -ENODEV;
1423
1424         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1425                 if ((findev->vendor == dev->vendor) &&
1426                     (findev->device == dev->device) &&
1427                     ((findev->devfn - dev->devfn) == 1) &&
1428                     (PCI_FUNC(findev->devfn) & 1)) {
1429                         if (findev->irq != dev->irq) {
1430                                 /* FIXME: we need a core pci_set_interrupt() */
1431                                 findev->irq = dev->irq;
1432                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1433                                         "fixed.\n", d->name);
1434                         }
1435                         return ide_setup_pci_devices(dev, findev, d);
1436                 }
1437         }
1438         return ide_setup_pci_device(dev, d);
1439 }
1440
1441 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1442 {
1443         return ide_setup_pci_device(dev, d);
1444 }
1445
1446 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1447 {
1448         u8 rev = 0, mcr1 = 0;
1449
1450         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1451
1452         if (rev > 1)
1453                 d->name = "HPT371N";
1454
1455         /*
1456          * HPT371 chips physically have only one channel, the secondary one,
1457          * but the primary channel registers do exist!  Go figure...
1458          * So,  we manually disable the non-existing channel here
1459          * (if the BIOS hasn't done this already).
1460          */
1461         pci_read_config_byte(dev, 0x50, &mcr1);
1462         if (mcr1 & 0x04)
1463                 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1464
1465         return ide_setup_pci_device(dev, d);
1466 }
1467
1468 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1469 {
1470         u8 rev = 0;
1471
1472         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1473
1474         if (rev > 1)
1475                 d->name = "HPT372N";
1476
1477         return ide_setup_pci_device(dev, d);
1478 }
1479
1480 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1481 {
1482         u8 rev = 0;
1483
1484         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1485
1486         if (rev > 1)
1487                 d->name = "HPT302N";
1488
1489         return ide_setup_pci_device(dev, d);
1490 }
1491
1492 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1493 {
1494         struct pci_dev *findev = NULL;
1495         u8 rev = 0, pin1 = 0, pin2 = 0;
1496         static char   *chipset_names[] = { "HPT366", "HPT366",  "HPT368",
1497                                            "HPT370", "HPT370A", "HPT372",
1498                                            "HPT372N" };
1499
1500         if (PCI_FUNC(dev->devfn) & 1)
1501                 return -ENODEV;
1502
1503         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1504
1505         if (rev > 6)
1506                 rev = 6;
1507
1508         d->name = chipset_names[rev];
1509
1510         if (rev > 2)
1511                 goto init_single;
1512
1513         d->channels = 1;
1514
1515         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1516         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1517                 if ((findev->vendor == dev->vendor) &&
1518                     (findev->device == dev->device) &&
1519                     ((findev->devfn - dev->devfn) == 1) &&
1520                     (PCI_FUNC(findev->devfn) & 1)) {
1521                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1522                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1523                                 d->bootable = ON_BOARD;
1524                                 printk("%s: onboard version of chipset, "
1525                                         "pin1=%d pin2=%d\n", d->name,
1526                                         pin1, pin2);
1527                         }
1528                         return ide_setup_pci_devices(dev, findev, d);
1529                 }
1530         }
1531 init_single:
1532         return ide_setup_pci_device(dev, d);
1533 }
1534
1535 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1536         {       /* 0 */
1537                 .name           = "HPT366",
1538                 .init_setup     = init_setup_hpt366,
1539                 .init_chipset   = init_chipset_hpt366,
1540                 .init_iops      = init_iops_hpt366,
1541                 .init_hwif      = init_hwif_hpt366,
1542                 .init_dma       = init_dma_hpt366,
1543                 .channels       = 2,
1544                 .autodma        = AUTODMA,
1545                 .bootable       = OFF_BOARD,
1546                 .extra          = 240
1547         },{     /* 1 */
1548                 .name           = "HPT372A",
1549                 .init_setup     = init_setup_hpt372a,
1550                 .init_chipset   = init_chipset_hpt366,
1551                 .init_iops      = init_iops_hpt366,
1552                 .init_hwif      = init_hwif_hpt366,
1553                 .init_dma       = init_dma_hpt366,
1554                 .channels       = 2,
1555                 .autodma        = AUTODMA,
1556                 .bootable       = OFF_BOARD,
1557                 .extra          = 240
1558         },{     /* 2 */
1559                 .name           = "HPT302",
1560                 .init_setup     = init_setup_hpt302,
1561                 .init_chipset   = init_chipset_hpt366,
1562                 .init_iops      = init_iops_hpt366,
1563                 .init_hwif      = init_hwif_hpt366,
1564                 .init_dma       = init_dma_hpt366,
1565                 .channels       = 2,
1566                 .autodma        = AUTODMA,
1567                 .bootable       = OFF_BOARD,
1568                 .extra          = 240
1569         },{     /* 3 */
1570                 .name           = "HPT371",
1571                 .init_setup     = init_setup_hpt371,
1572                 .init_chipset   = init_chipset_hpt366,
1573                 .init_iops      = init_iops_hpt366,
1574                 .init_hwif      = init_hwif_hpt366,
1575                 .init_dma       = init_dma_hpt366,
1576                 .channels       = 2,
1577                 .autodma        = AUTODMA,
1578                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1579                 .bootable       = OFF_BOARD,
1580                 .extra          = 240
1581         },{     /* 4 */
1582                 .name           = "HPT374",
1583                 .init_setup     = init_setup_hpt374,
1584                 .init_chipset   = init_chipset_hpt366,
1585                 .init_iops      = init_iops_hpt366,
1586                 .init_hwif      = init_hwif_hpt366,
1587                 .init_dma       = init_dma_hpt366,
1588                 .channels       = 2,    /* 4 */
1589                 .autodma        = AUTODMA,
1590                 .bootable       = OFF_BOARD,
1591                 .extra          = 240
1592         },{     /* 5 */
1593                 .name           = "HPT372N",
1594                 .init_setup     = init_setup_hpt372n,
1595                 .init_chipset   = init_chipset_hpt366,
1596                 .init_iops      = init_iops_hpt366,
1597                 .init_hwif      = init_hwif_hpt366,
1598                 .init_dma       = init_dma_hpt366,
1599                 .channels       = 2,    /* 4 */
1600                 .autodma        = AUTODMA,
1601                 .bootable       = OFF_BOARD,
1602                 .extra          = 240
1603         }
1604 };
1605
1606 /**
1607  *      hpt366_init_one -       called when an HPT366 is found
1608  *      @dev: the hpt366 device
1609  *      @id: the matching pci id
1610  *
1611  *      Called when the PCI registration layer (or the IDE initialization)
1612  *      finds a device matching our IDE device tables.
1613  *
1614  *      NOTE: since we'll have to modify some fields of the ide_pci_device_t
1615  *      structure depending on the chip's revision, we'd better pass a local
1616  *      copy down the call chain...
1617  */
1618 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1619 {
1620         ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1621
1622         return d.init_setup(dev, &d);
1623 }
1624
1625 static struct pci_device_id hpt366_pci_tbl[] = {
1626         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1627         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1628         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1629         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1630         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1631         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1632         { 0, },
1633 };
1634 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1635
1636 static struct pci_driver driver = {
1637         .name           = "HPT366_IDE",
1638         .id_table       = hpt366_pci_tbl,
1639         .probe          = hpt366_init_one,
1640 };
1641
1642 static int __init hpt366_ide_init(void)
1643 {
1644         return ide_pci_register_driver(&driver);
1645 }
1646
1647 module_init(hpt366_ide_init);
1648
1649 MODULE_AUTHOR("Andre Hedrick");
1650 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1651 MODULE_LICENSE("GPL");