drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 1.01    Dec 23, 2006
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - disable UltraATA/100 for HPT370 by default as the 33 MHz clock being used
  64  *   does not allow for this speed anyway
  65  * - avoid touching disabled channels (e.g. HPT371/N are single channel chips,
  66  *   their primary channel is kind of virtual, it isn't tied to any pins)
  67  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  68  *   HPT37x chip family; save space by introducing the separate transfer mode
  69  *   table in which the mode lookup is done
  70  * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  71  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
  72  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  73  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  74  * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  75  *   they tamper with its fields
  76  * - pass  to the init_setup handlers a copy of the ide_pci_device_t structure
  77  *   since they may tamper with its fields
  78  * - prefix the driver startup messages with the real chip name
  79  * - claim the extra 240 bytes of I/O space for all chips
  80  * - optimize the rate masking/filtering and the drive list lookup code
  81  * - use pci_get_slot() to get to the function 1 of HPT36x/374
  82  * - cache offset of the channel's misc. control registers (MCRs) being used
  83  *   throughout the driver
  84  * - only touch the relevant MCR when detecting the cable type on HPT374's
  85  *   function 1
  86  * - rename all the register related variables consistently
  87  * - move all the interrupt twiddling code from the speedproc handlers into
  88  *   init_hwif_hpt366(), also grouping all the DMA related code together there
  89  * - merge two HPT37x speedproc handlers, fix the PIO timing register mask and
  90  *   separate the UltraDMA and MWDMA masks there to avoid changing PIO timings
  91  *   when setting an UltraDMA mode
  92  * - fix hpt3xx_tune_drive() to set the PIO mode requested, not always select
  93  *   the best possible one
  94  * - clean up DMA timeout handling for HPT370
  95  * - switch to using the enumeration type to differ between the numerous chip
  96  *   variants, matching PCI device/revision ID with the chip type early, at the
  97  *   init_setup stage
  98  * - extend the hpt_info structure to hold the DPLL and PCI clock frequencies,
  99  *   stop duplicating it for each channel by storing the pointer in the pci_dev
 100  *   structure: first, at the init_setup stage, point it to a static "template"
 101  *   with only the chip type and its specific base DPLL frequency, the highest
 102  *   supported DMA mode, and the chip settings table pointer filled, then, at
 103  *   the init_chipset stage, allocate per-chip instance  and fill it with the
 104  *   rest of the necessary information
 105  * - get rid of the constant thresholds in the HPT37x PCI clock detection code,
 106  *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
 107  *   frequency
 108  * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
 109  *   anything  newer than HPT370/A
 110  * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
 111  *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
 112  *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
 113  *   the register setting lists into the table indexed by the clock selected
 114  *      Sergei Shtylyov, <sshtylyov@ru.mvista.com> or <source@mvista.com>
 115  */
 116
 117 #include <linux/types.h>
 118 #include <linux/module.h>
 119 #include <linux/kernel.h>
 120 #include <linux/delay.h>
 121 #include <linux/timer.h>
 122 #include <linux/mm.h>
 123 #include <linux/ioport.h>
 124 #include <linux/blkdev.h>
 125 #include <linux/hdreg.h>
 126
 127 #include <linux/interrupt.h>
 128 #include <linux/pci.h>
 129 #include <linux/init.h>
 130 #include <linux/ide.h>
 131
 132 #include <asm/uaccess.h>
 133 #include <asm/io.h>
 134 #include <asm/irq.h>
 135
 136 /* various tuning parameters */
 137 #define HPT_RESET_STATE_ENGINE
 138 #undef  HPT_DELAY_INTERRUPT
 139 #define HPT_SERIALIZE_IO        0
 140
 141 static const char *quirk_drives[] = {
 142         "QUANTUM FIREBALLlct08 08",
 143         "QUANTUM FIREBALLP KA6.4",
 144         "QUANTUM FIREBALLP LM20.4",
 145         "QUANTUM FIREBALLP LM20.5",
 146         NULL
 147 };
 148
 149 static const char *bad_ata100_5[] = {
 150         "IBM-DTLA-307075",
 151         "IBM-DTLA-307060",
 152         "IBM-DTLA-307045",
 153         "IBM-DTLA-307030",
 154         "IBM-DTLA-307020",
 155         "IBM-DTLA-307015",
 156         "IBM-DTLA-305040",
 157         "IBM-DTLA-305030",
 158         "IBM-DTLA-305020",
 159         "IC35L010AVER07-0",
 160         "IC35L020AVER07-0",
 161         "IC35L030AVER07-0",
 162         "IC35L040AVER07-0",
 163         "IC35L060AVER07-0",
 164         "WDC AC310200R",
 165         NULL
 166 };
 167
 168 static const char *bad_ata66_4[] = {
 169         "IBM-DTLA-307075",
 170         "IBM-DTLA-307060",
 171         "IBM-DTLA-307045",
 172         "IBM-DTLA-307030",
 173         "IBM-DTLA-307020",
 174         "IBM-DTLA-307015",
 175         "IBM-DTLA-305040",
 176         "IBM-DTLA-305030",
 177         "IBM-DTLA-305020",
 178         "IC35L010AVER07-0",
 179         "IC35L020AVER07-0",
 180         "IC35L030AVER07-0",
 181         "IC35L040AVER07-0",
 182         "IC35L060AVER07-0",
 183         "WDC AC310200R",
 184         NULL
 185 };
 186
 187 static const char *bad_ata66_3[] = {
 188         "WDC AC310200R",
 189         NULL
 190 };
 191
 192 static const char *bad_ata33[] = {
 193         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 194         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 195         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 196         "Maxtor 90510D4",
 197         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 198         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 199         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 200         NULL
 201 };
 202
 203 static u8 xfer_speeds[] = {
 204         XFER_UDMA_6,
 205         XFER_UDMA_5,
 206         XFER_UDMA_4,
 207         XFER_UDMA_3,
 208         XFER_UDMA_2,
 209         XFER_UDMA_1,
 210         XFER_UDMA_0,
 211
 212         XFER_MW_DMA_2,
 213         XFER_MW_DMA_1,
 214         XFER_MW_DMA_0,
 215
 216         XFER_PIO_4,
 217         XFER_PIO_3,
 218         XFER_PIO_2,
 219         XFER_PIO_1,
 220         XFER_PIO_0
 221 };
 222
 223 /* Key for bus clock timings
 224  * 36x   37x
 225  * bits  bits
 226  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 227  *              cycles = value + 1
 228  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 229  *              cycles = value + 1
 230  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 231  *              register access.
 232  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 233  *              register access.
 234  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 235  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 236  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 237  *              MW DMA xfer.
 238  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 239  *              task file register access.
 240  * 28    28     UDMA enable.
 241  * 29    29     DMA  enable.
 242  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 243  *              PIO xfer.
 244  * 31    31     FIFO enable.
 245  */
 246
 247 static u32 forty_base_hpt36x[] = {
 248         /* XFER_UDMA_6 */       0x900fd943,
 249         /* XFER_UDMA_5 */       0x900fd943,
 250         /* XFER_UDMA_4 */       0x900fd943,
 251         /* XFER_UDMA_3 */       0x900ad943,
 252         /* XFER_UDMA_2 */       0x900bd943,
 253         /* XFER_UDMA_1 */       0x9008d943,
 254         /* XFER_UDMA_0 */       0x9008d943,
 255
 256         /* XFER_MW_DMA_2 */     0xa008d943,
 257         /* XFER_MW_DMA_1 */     0xa010d955,
 258         /* XFER_MW_DMA_0 */     0xa010d9fc,
 259
 260         /* XFER_PIO_4 */        0xc008d963,
 261         /* XFER_PIO_3 */        0xc010d974,
 262         /* XFER_PIO_2 */        0xc010d997,
 263         /* XFER_PIO_1 */        0xc010d9c7,
 264         /* XFER_PIO_0 */        0xc018d9d9
 265 };
 266
 267 static u32 thirty_three_base_hpt36x[] = {
 268         /* XFER_UDMA_6 */       0x90c9a731,
 269         /* XFER_UDMA_5 */       0x90c9a731,
 270         /* XFER_UDMA_4 */       0x90c9a731,
 271         /* XFER_UDMA_3 */       0x90cfa731,
 272         /* XFER_UDMA_2 */       0x90caa731,
 273         /* XFER_UDMA_1 */       0x90cba731,
 274         /* XFER_UDMA_0 */       0x90c8a731,
 275
 276         /* XFER_MW_DMA_2 */     0xa0c8a731,
 277         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 278         /* XFER_MW_DMA_0 */     0xa0c8a797,
 279
 280         /* XFER_PIO_4 */        0xc0c8a731,
 281         /* XFER_PIO_3 */        0xc0c8a742,
 282         /* XFER_PIO_2 */        0xc0d0a753,
 283         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 284         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 285 };
 286
 287 static u32 twenty_five_base_hpt36x[] = {
 288         /* XFER_UDMA_6 */       0x90c98521,
 289         /* XFER_UDMA_5 */       0x90c98521,
 290         /* XFER_UDMA_4 */       0x90c98521,
 291         /* XFER_UDMA_3 */       0x90cf8521,
 292         /* XFER_UDMA_2 */       0x90cf8521,
 293         /* XFER_UDMA_1 */       0x90cb8521,
 294         /* XFER_UDMA_0 */       0x90cb8521,
 295
 296         /* XFER_MW_DMA_2 */     0xa0ca8521,
 297         /* XFER_MW_DMA_1 */     0xa0ca8532,
 298         /* XFER_MW_DMA_0 */     0xa0ca8575,
 299
 300         /* XFER_PIO_4 */        0xc0ca8521,
 301         /* XFER_PIO_3 */        0xc0ca8532,
 302         /* XFER_PIO_2 */        0xc0ca8542,
 303         /* XFER_PIO_1 */        0xc0d08572,
 304         /* XFER_PIO_0 */        0xc0d08585
 305 };
 306
 307 static u32 thirty_three_base_hpt37x[] = {
 308         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 309         /* XFER_UDMA_5 */       0x12446231,
 310         /* XFER_UDMA_4 */       0x12446231,
 311         /* XFER_UDMA_3 */       0x126c6231,
 312         /* XFER_UDMA_2 */       0x12486231,
 313         /* XFER_UDMA_1 */       0x124c6233,
 314         /* XFER_UDMA_0 */       0x12506297,
 315
 316         /* XFER_MW_DMA_2 */     0x22406c31,
 317         /* XFER_MW_DMA_1 */     0x22406c33,
 318         /* XFER_MW_DMA_0 */     0x22406c97,
 319
 320         /* XFER_PIO_4 */        0x06414e31,
 321         /* XFER_PIO_3 */        0x06414e42,
 322         /* XFER_PIO_2 */        0x06414e53,
 323         /* XFER_PIO_1 */        0x06814e93,
 324         /* XFER_PIO_0 */        0x06814ea7
 325 };
 326
 327 static u32 fifty_base_hpt37x[] = {
 328         /* XFER_UDMA_6 */       0x12848242,
 329         /* XFER_UDMA_5 */       0x12848242,
 330         /* XFER_UDMA_4 */       0x12ac8242,
 331         /* XFER_UDMA_3 */       0x128c8242,
 332         /* XFER_UDMA_2 */       0x120c8242,
 333         /* XFER_UDMA_1 */       0x12148254,
 334         /* XFER_UDMA_0 */       0x121882ea,
 335
 336         /* XFER_MW_DMA_2 */     0x22808242,
 337         /* XFER_MW_DMA_1 */     0x22808254,
 338         /* XFER_MW_DMA_0 */     0x228082ea,
 339
 340         /* XFER_PIO_4 */        0x0a81f442,
 341         /* XFER_PIO_3 */        0x0a81f443,
 342         /* XFER_PIO_2 */        0x0a81f454,
 343         /* XFER_PIO_1 */        0x0ac1f465,
 344         /* XFER_PIO_0 */        0x0ac1f48a
 345 };
 346
 347 static u32 sixty_six_base_hpt37x[] = {
 348         /* XFER_UDMA_6 */       0x1c869c62,
 349         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 350         /* XFER_UDMA_4 */       0x1c8a9c62,
 351         /* XFER_UDMA_3 */       0x1c8e9c62,
 352         /* XFER_UDMA_2 */       0x1c929c62,
 353         /* XFER_UDMA_1 */       0x1c9a9c62,
 354         /* XFER_UDMA_0 */       0x1c829c62,
 355
 356         /* XFER_MW_DMA_2 */     0x2c829c62,
 357         /* XFER_MW_DMA_1 */     0x2c829c66,
 358         /* XFER_MW_DMA_0 */     0x2c829d2e,
 359
 360         /* XFER_PIO_4 */        0x0c829c62,
 361         /* XFER_PIO_3 */        0x0c829c84,
 362         /* XFER_PIO_2 */        0x0c829ca6,
 363         /* XFER_PIO_1 */        0x0d029d26,
 364         /* XFER_PIO_0 */        0x0d029d5e
 365 };
 366
 367 #define HPT366_DEBUG_DRIVE_INFO         0
 368 #define HPT374_ALLOW_ATA133_6           1
 369 #define HPT371_ALLOW_ATA133_6           1
 370 #define HPT302_ALLOW_ATA133_6           1
 371 #define HPT372_ALLOW_ATA133_6           1
 372 #define HPT370_ALLOW_ATA100_5           0
 373 #define HPT366_ALLOW_ATA66_4            1
 374 #define HPT366_ALLOW_ATA66_3            1
 375 #define HPT366_MAX_DEVS                 8
 376
 377 /* Supported ATA clock frequencies */
 378 enum ata_clock {
 379         ATA_CLOCK_25MHZ,
 380         ATA_CLOCK_33MHZ,
 381         ATA_CLOCK_40MHZ,
 382         ATA_CLOCK_50MHZ,
 383         ATA_CLOCK_66MHZ,
 384         NUM_ATA_CLOCKS
 385 };
 386
 387 /*
 388  *      Hold all the HighPoint chip information in one place.
 389  */
 390
 391 struct hpt_info {
 392         u8 chip_type;           /* Chip type */
 393         u8 max_mode;            /* Speeds allowed */
 394         u8 dpll_clk;            /* DPLL clock in MHz */
 395         u8 pci_clk;             /* PCI  clock in MHz */
 396         u32 **settings;         /* Chipset settings table */
 397 };
 398
 399 /* Supported HighPoint chips */
 400 enum {
 401         HPT36x,
 402         HPT370,
 403         HPT370A,
 404         HPT374,
 405         HPT372,
 406         HPT372A,
 407         HPT302,
 408         HPT371,
 409         HPT372N,
 410         HPT302N,
 411         HPT371N
 412 };
 413
 414 static u32 *hpt36x_settings[NUM_ATA_CLOCKS] = {
 415         twenty_five_base_hpt36x,
 416         thirty_three_base_hpt36x,
 417         forty_base_hpt36x,
 418         NULL,
 419         NULL
 420 };
 421
 422 static u32 *hpt37x_settings[NUM_ATA_CLOCKS] = {
 423         NULL,
 424         thirty_three_base_hpt37x,
 425         NULL,
 426         fifty_base_hpt37x,
 427         sixty_six_base_hpt37x
 428 };
 429
 430 static struct hpt_info hpt36x __devinitdata = {
 431         .chip_type      = HPT36x,
 432         .max_mode       = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1,
 433         .dpll_clk       = 0,    /* no DPLL */
 434         .settings       = hpt36x_settings
 435 };
 436
 437 static struct hpt_info hpt370 __devinitdata = {
 438         .chip_type      = HPT370,
 439         .max_mode       = HPT370_ALLOW_ATA100_5 ? 3 : 2,
 440         .dpll_clk       = 48,
 441         .settings       = hpt37x_settings
 442 };
 443
 444 static struct hpt_info hpt370a __devinitdata = {
 445         .chip_type      = HPT370A,
 446         .max_mode       = HPT370_ALLOW_ATA100_5 ? 3 : 2,
 447         .dpll_clk       = 48,
 448         .settings       = hpt37x_settings
 449 };
 450
 451 static struct hpt_info hpt374 __devinitdata = {
 452         .chip_type      = HPT374,
 453         .max_mode       = HPT374_ALLOW_ATA133_6 ? 4 : 3,
 454         .dpll_clk       = 48,
 455         .settings       = hpt37x_settings
 456 };
 457
 458 static struct hpt_info hpt372 __devinitdata = {
 459         .chip_type      = HPT372,
 460         .max_mode       = HPT372_ALLOW_ATA133_6 ? 4 : 3,
 461         .dpll_clk       = 55,
 462         .settings       = hpt37x_settings
 463 };
 464
 465 static struct hpt_info hpt372a __devinitdata = {
 466         .chip_type      = HPT372A,
 467         .max_mode       = HPT372_ALLOW_ATA133_6 ? 4 : 3,
 468         .dpll_clk       = 66,
 469         .settings       = hpt37x_settings
 470 };
 471
 472 static struct hpt_info hpt302 __devinitdata = {
 473         .chip_type      = HPT302,
 474         .max_mode       = HPT302_ALLOW_ATA133_6 ? 4 : 3,
 475         .dpll_clk       = 66,
 476         .settings       = hpt37x_settings
 477 };
 478
 479 static struct hpt_info hpt371 __devinitdata = {
 480         .chip_type      = HPT371,
 481         .max_mode       = HPT371_ALLOW_ATA133_6 ? 4 : 3,
 482         .dpll_clk       = 66,
 483         .settings       = hpt37x_settings
 484 };
 485
 486 static struct hpt_info hpt372n __devinitdata = {
 487         .chip_type      = HPT372N,
 488         .max_mode       = HPT372_ALLOW_ATA133_6 ? 4 : 3,
 489         .dpll_clk       = 77,
 490         .settings       = hpt37x_settings
 491 };
 492
 493 static struct hpt_info hpt302n __devinitdata = {
 494         .chip_type      = HPT302N,
 495         .max_mode       = HPT302_ALLOW_ATA133_6 ? 4 : 3,
 496         .dpll_clk       = 77,
 497 };
 498
 499 static struct hpt_info hpt371n __devinitdata = {
 500         .chip_type      = HPT371N,
 501         .max_mode       = HPT371_ALLOW_ATA133_6 ? 4 : 3,
 502         .dpll_clk       = 77,
 503         .settings       = hpt37x_settings
 504 };
 505
 506 static int check_in_drive_list(ide_drive_t *drive, const char **list)
 507 {
 508         struct hd_driveid *id = drive->id;
 509
 510         while (*list)
 511                 if (!strcmp(*list++,id->model))
 512                         return 1;
 513         return 0;
 514 }
 515
 516 static u8 hpt3xx_ratemask(ide_drive_t *drive)
 517 {
 518         struct hpt_info *info   = pci_get_drvdata(HWIF(drive)->pci_dev);
 519         u8 mode                 = info->max_mode;
 520
 521         if (!eighty_ninty_three(drive) && mode)
 522                 mode = min(mode, (u8)1);
 523         return mode;
 524 }
 525
 526 /*
 527  *      Note for the future; the SATA hpt37x we must set
 528  *      either PIO or UDMA modes 0,4,5
 529  */
 530
 531 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
 532 {
 533         struct hpt_info *info   = pci_get_drvdata(HWIF(drive)->pci_dev);
 534         u8 chip_type            = info->chip_type;
 535         u8 mode                 = hpt3xx_ratemask(drive);
 536
 537         if (drive->media != ide_disk)
 538                 return min(speed, (u8)XFER_PIO_4);
 539
 540         switch (mode) {
 541                 case 0x04:
 542                         speed = min_t(u8, speed, XFER_UDMA_6);
 543                         break;
 544                 case 0x03:
 545                         speed = min_t(u8, speed, XFER_UDMA_5);
 546                         if (chip_type >= HPT374)
 547                                 break;
 548                         if (!check_in_drive_list(drive, bad_ata100_5))
 549                                 goto check_bad_ata33;
 550                         /* fall thru */
 551                 case 0x02:
 552                         speed = min_t(u8, speed, XFER_UDMA_4);
 553
 554                         /*
 555                          * CHECK ME, Does this need to be changed to HPT374 ??
 556                          */
 557                         if (chip_type >= HPT370)
 558                                 goto check_bad_ata33;
 559                         if (HPT366_ALLOW_ATA66_4 &&
 560                             !check_in_drive_list(drive, bad_ata66_4))
 561                                 goto check_bad_ata33;
 562
 563                         speed = min_t(u8, speed, XFER_UDMA_3);
 564                         if (HPT366_ALLOW_ATA66_3 &&
 565                             !check_in_drive_list(drive, bad_ata66_3))
 566                                 goto check_bad_ata33;
 567                         /* fall thru */
 568                 case 0x01:
 569                         speed = min_t(u8, speed, XFER_UDMA_2);
 570
 571                 check_bad_ata33:
 572                         if (chip_type >= HPT370A)
 573                                 break;
 574                         if (!check_in_drive_list(drive, bad_ata33))
 575                                 break;
 576                         /* fall thru */
 577                 case 0x00:
 578                 default:
 579                         speed = min_t(u8, speed, XFER_MW_DMA_2);
 580                         break;
 581         }
 582         return speed;
 583 }
 584
 585 static u32 get_speed_setting(u8 speed, struct hpt_info *info)
 586 {
 587         int i;
 588
 589         /*
 590          * Lookup the transfer mode table to get the index into
 591          * the timing table.
 592          *
 593          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 594          */
 595         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 596                 if (xfer_speeds[i] == speed)
 597                         break;
 598         /*
 599          * NOTE: info->settings only points to the pointer
 600          * to the list of the actual register values
 601          */
 602         return (*info->settings)[i];
 603 }
 604
 605 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 606 {
 607         ide_hwif_t *hwif        = HWIF(drive);
 608         struct pci_dev  *dev    = hwif->pci_dev;
 609         struct hpt_info *info   = pci_get_drvdata(dev);
 610         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 611         u8  itr_addr            = drive->dn ? 0x44 : 0x40;
 612         u32 itr_mask            = speed < XFER_MW_DMA_0 ? 0x30070000 :
 613                                  (speed < XFER_UDMA_0   ? 0xc0070000 : 0xc03800ff);
 614         u32 new_itr             = get_speed_setting(speed, info);
 615         u32 old_itr             = 0;
 616
 617         /*
 618          * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 619          * to avoid problems handling I/O errors later
 620          */
 621         pci_read_config_dword(dev, itr_addr, &old_itr);
 622         new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 623         new_itr &= ~0xc0000000;
 624
 625         pci_write_config_dword(dev, itr_addr, new_itr);
 626
 627         return ide_config_drive_speed(drive, speed);
 628 }
 629
 630 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 631 {
 632         ide_hwif_t *hwif        = HWIF(drive);
 633         struct pci_dev  *dev    = hwif->pci_dev;
 634         struct hpt_info *info   = pci_get_drvdata(dev);
 635         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 636         u8  itr_addr            = 0x40 + (drive->dn * 4);
 637         u32 itr_mask            = speed < XFER_MW_DMA_0 ? 0x303c0000 :
 638                                  (speed < XFER_UDMA_0   ? 0xc03c0000 : 0xc1c001ff);
 639         u32 new_itr             = get_speed_setting(speed, info);
 640         u32 old_itr             = 0;
 641
 642         pci_read_config_dword(dev, itr_addr, &old_itr);
 643         new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 644
 645         if (speed < XFER_MW_DMA_0)
 646                 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 647         pci_write_config_dword(dev, itr_addr, new_itr);
 648
 649         return ide_config_drive_speed(drive, speed);
 650 }
 651
 652 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
 653 {
 654         ide_hwif_t *hwif        = HWIF(drive);
 655         struct hpt_info *info   = pci_get_drvdata(hwif->pci_dev);
 656
 657         if (info->chip_type >= HPT370)
 658                 return hpt37x_tune_chipset(drive, speed);
 659         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 660                 return hpt36x_tune_chipset(drive, speed);
 661 }
 662
 663 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
 664 {
 665         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 666         (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
 667 }
 668
 669 /*
 670  * This allows the configuration of ide_pci chipset registers
 671  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 672  * after the drive is reported by the OS.  Initially designed for
 673  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 674  *
 675  */
 676 static int config_chipset_for_dma(ide_drive_t *drive)
 677 {
 678         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 679
 680         if (!speed)
 681                 return 0;
 682
 683         (void) hpt3xx_tune_chipset(drive, speed);
 684         return ide_dma_enable(drive);
 685 }
 686
 687 static int hpt3xx_quirkproc(ide_drive_t *drive)
 688 {
 689         struct hd_driveid *id   = drive->id;
 690         const  char **list      = quirk_drives;
 691
 692         while (*list)
 693                 if (strstr(id->model, *list++))
 694                         return 1;
 695         return 0;
 696 }
 697
 698 static void hpt3xx_intrproc(ide_drive_t *drive)
 699 {
 700         ide_hwif_t *hwif = HWIF(drive);
 701
 702         if (drive->quirk_list)
 703                 return;
 704         /* drives in the quirk_list may not like intr setups/cleanups */
 705         hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
 706 }
 707
 708 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
 709 {
 710         ide_hwif_t *hwif        = HWIF(drive);
 711         struct pci_dev  *dev    = hwif->pci_dev;
 712         struct hpt_info *info   = pci_get_drvdata(dev);
 713
 714         if (drive->quirk_list) {
 715                 if (info->chip_type >= HPT370) {
 716                         u8 scr1 = 0;
 717
 718                         pci_read_config_byte(dev, 0x5a, &scr1);
 719                         if (((scr1 & 0x10) >> 4) != mask) {
 720                                 if (mask)
 721                                         scr1 |=  0x10;
 722                                 else
 723                                         scr1 &= ~0x10;
 724                                 pci_write_config_byte(dev, 0x5a, scr1);
 725                         }
 726                 } else {
 727                         if (mask)
 728                                 disable_irq(hwif->irq);
 729                         else
 730                                 enable_irq (hwif->irq);
 731                 }
 732         } else
 733                 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 734                            IDE_CONTROL_REG);
 735 }
 736
 737 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
 738 {
 739         ide_hwif_t *hwif        = HWIF(drive);
 740
 741         drive->init_speed = 0;
 742
 743         if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 744                 return hwif->ide_dma_on(drive);
 745
 746         if (ide_use_fast_pio(drive)) {
 747                 hpt3xx_tune_drive(drive, 255);
 748                 return hwif->ide_dma_off_quietly(drive);
 749         }
 750         /* IORDY not supported */
 751         return 0;
 752 }
 753
 754 /*
 755  * This is specific to the HPT366 UDMA chipset
 756  * by HighPoint|Triones Technologies, Inc.
 757  */
 758 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
 759 {
 760         struct pci_dev *dev = HWIF(drive)->pci_dev;
 761         u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 762
 763         pci_read_config_byte(dev, 0x50, &mcr1);
 764         pci_read_config_byte(dev, 0x52, &mcr3);
 765         pci_read_config_byte(dev, 0x5a, &scr1);
 766         printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 767                 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
 768         if (scr1 & 0x10)
 769                 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 770         return __ide_dma_lostirq(drive);
 771 }
 772
 773 static void hpt370_clear_engine(ide_drive_t *drive)
 774 {
 775         ide_hwif_t *hwif = HWIF(drive);
 776
 777         pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
 778         udelay(10);
 779 }
 780
 781 static void hpt370_irq_timeout(ide_drive_t *drive)
 782 {
 783         ide_hwif_t *hwif        = HWIF(drive);
 784         u16 bfifo               = 0;
 785         u8  dma_cmd;
 786
 787         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 788         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
 789
 790         /* get DMA command mode */
 791         dma_cmd = hwif->INB(hwif->dma_command);
 792         /* stop DMA */
 793         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 794         hpt370_clear_engine(drive);
 795 }
 796
 797 static void hpt370_ide_dma_start(ide_drive_t *drive)
 798 {
 799 #ifdef HPT_RESET_STATE_ENGINE
 800         hpt370_clear_engine(drive);
 801 #endif
 802         ide_dma_start(drive);
 803 }
 804
 805 static int hpt370_ide_dma_end(ide_drive_t *drive)
 806 {
 807         ide_hwif_t *hwif        = HWIF(drive);
 808         u8  dma_stat            = hwif->INB(hwif->dma_status);
 809
 810         if (dma_stat & 0x01) {
 811                 /* wait a little */
 812                 udelay(20);
 813                 dma_stat = hwif->INB(hwif->dma_status);
 814                 if (dma_stat & 0x01)
 815                         hpt370_irq_timeout(drive);
 816         }
 817         return __ide_dma_end(drive);
 818 }
 819
 820 static int hpt370_ide_dma_timeout(ide_drive_t *drive)
 821 {
 822         hpt370_irq_timeout(drive);
 823         return __ide_dma_timeout(drive);
 824 }
 825
 826 /* returns 1 if DMA IRQ issued, 0 otherwise */
 827 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 828 {
 829         ide_hwif_t *hwif        = HWIF(drive);
 830         u16 bfifo               = 0;
 831         u8  dma_stat;
 832
 833         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 834         if (bfifo & 0x1FF) {
 835 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 836                 return 0;
 837         }
 838
 839         dma_stat = inb(hwif->dma_status);
 840         /* return 1 if INTR asserted */
 841         if (dma_stat & 4)
 842                 return 1;
 843
 844         if (!drive->waiting_for_dma)
 845                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 846                                 drive->name, __FUNCTION__);
 847         return 0;
 848 }
 849
 850 static int hpt374_ide_dma_end(ide_drive_t *drive)
 851 {
 852         ide_hwif_t *hwif        = HWIF(drive);
 853         struct pci_dev  *dev    = hwif->pci_dev;
 854         u8 mcr  = 0, mcr_addr   = hwif->select_data;
 855         u8 bwsr = 0, mask       = hwif->channel ? 0x02 : 0x01;
 856
 857         pci_read_config_byte(dev, 0x6a, &bwsr);
 858         pci_read_config_byte(dev, mcr_addr, &mcr);
 859         if (bwsr & mask)
 860                 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 861         return __ide_dma_end(drive);
 862 }
 863
 864 /**
 865  *      hpt3xxn_set_clock       -       perform clock switching dance
 866  *      @hwif: hwif to switch
 867  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 868  *
 869  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 870  */
 871
 872 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 873 {
 874         u8 scr2 = hwif->INB(hwif->dma_master + 0x7b);
 875
 876         if ((scr2 & 0x7f) == mode)
 877                 return;
 878
 879         /* Tristate the bus */
 880         hwif->OUTB(0x80, hwif->dma_master + 0x73);
 881         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 882
 883         /* Switch clock and reset channels */
 884         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 885         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 886
 887         /*
 888          * Reset the state machines.
 889          * NOTE: avoid accidentally enabling the disabled channels.
 890          */
 891         hwif->OUTB(hwif->INB(hwif->dma_master + 0x70) | 0x32,
 892                    hwif->dma_master + 0x70);
 893         hwif->OUTB(hwif->INB(hwif->dma_master + 0x74) | 0x32,
 894                    hwif->dma_master + 0x74);
 895
 896         /* Complete reset */
 897         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 898
 899         /* Reconnect channels to bus */
 900         hwif->OUTB(0x00, hwif->dma_master + 0x73);
 901         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 902 }
 903
 904 /**
 905  *      hpt3xxn_rw_disk         -       prepare for I/O
 906  *      @drive: drive for command
 907  *      @rq: block request structure
 908  *
 909  *      This is called when a disk I/O is issued to HPT3xxN.
 910  *      We need it because of the clock switching.
 911  */
 912
 913 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 914 {
 915         hpt3xxn_set_clock(HWIF(drive), rq_data_dir(rq) ? 0x23 : 0x21);
 916 }
 917
 918 /*
 919  * Set/get power state for a drive.
 920  * NOTE: affects both drives on each channel.
 921  *
 922  * When we turn the power back on, we need to re-initialize things.
 923  */
 924 #define TRISTATE_BIT  0x8000
 925
 926 static int hpt3xx_busproc(ide_drive_t *drive, int state)
 927 {
 928         ide_hwif_t *hwif        = HWIF(drive);
 929         struct pci_dev *dev     = hwif->pci_dev;
 930         u8  mcr_addr            = hwif->select_data + 2;
 931         u8  resetmask           = hwif->channel ? 0x80 : 0x40;
 932         u8  bsr2                = 0;
 933         u16 mcr                 = 0;
 934
 935         hwif->bus_state = state;
 936
 937         /* Grab the status. */
 938         pci_read_config_word(dev, mcr_addr, &mcr);
 939         pci_read_config_byte(dev, 0x59, &bsr2);
 940
 941         /*
 942          * Set the state. We don't set it if we don't need to do so.
 943          * Make sure that the drive knows that it has failed if it's off.
 944          */
 945         switch (state) {
 946         case BUSSTATE_ON:
 947                 if (!(bsr2 & resetmask))
 948                         return 0;
 949                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
 950
 951                 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
 952                 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
 953                 return 0;
 954         case BUSSTATE_OFF:
 955                 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
 956                         return 0;
 957                 mcr &= ~TRISTATE_BIT;
 958                 break;
 959         case BUSSTATE_TRISTATE:
 960                 if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
 961                         return 0;
 962                 mcr |= TRISTATE_BIT;
 963                 break;
 964         default:
 965                 return -EINVAL;
 966         }
 967
 968         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 969         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 970
 971         pci_write_config_word(dev, mcr_addr, mcr);
 972         pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
 973         return 0;
 974 }
 975
 976 /**
 977  *      hpt37x_calibrate_dpll   -       calibrate the DPLL
 978  *      @dev: PCI device
 979  *
 980  *      Perform a calibration cycle on the DPLL.
 981  *      Returns 1 if this succeeds
 982  */
 983 static int __devinit hpt37x_calibrate_dpll(struct pci_dev *dev, u16 f_low, u16 f_high)
 984 {
 985         u32 dpll = (f_high << 16) | f_low | 0x100;
 986         u8  scr2;
 987         int i;
 988
 989         pci_write_config_dword(dev, 0x5c, dpll);
 990
 991         /* Wait for oscillator ready */
 992         for(i = 0; i < 0x5000; ++i) {
 993                 udelay(50);
 994                 pci_read_config_byte(dev, 0x5b, &scr2);
 995                 if (scr2 & 0x80)
 996                         break;
 997         }
 998         /* See if it stays ready (we'll just bail out if it's not yet) */
 999         for(i = 0; i < 0x1000; ++i) {
1000                 pci_read_config_byte(dev, 0x5b, &scr2);
1001                 /* DPLL destabilized? */
1002                 if(!(scr2 & 0x80))
1003                         return 0;
1004         }
1005         /* Turn off tuning, we have the DPLL set */
1006         pci_read_config_dword (dev, 0x5c, &dpll);
1007         pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
1008         return 1;
1009 }
1010
1011 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1012 {
1013         struct hpt_info *info   = kmalloc(sizeof(struct hpt_info), GFP_KERNEL);
1014         unsigned long io_base   = pci_resource_start(dev, 4);
1015         u8 pci_clk,  dpll_clk   = 0;    /* PCI and DPLL clock in MHz */
1016         enum ata_clock  clock;
1017
1018         if (info == NULL) {
1019                 printk(KERN_ERR "%s: out of memory!\n", name);
1020                 return -ENOMEM;
1021         }
1022
1023         /*
1024          * Copy everything from a static "template" structure
1025          * to just allocated per-chip hpt_info structure.
1026          */
1027         *info = *(struct hpt_info *)pci_get_drvdata(dev);
1028
1029         /*
1030          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1031          * We don't seem to be using it.
1032          */
1033         if (dev->resource[PCI_ROM_RESOURCE].start)
1034                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1035                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1036
1037         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1038         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1039         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1040         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1041
1042         /*
1043          * First, try to estimate the PCI clock frequency...
1044          */
1045         if (info->chip_type >= HPT370) {
1046                 u8  scr1  = 0;
1047                 u16 f_cnt = 0;
1048                 u32 temp  = 0;
1049
1050                 /* Interrupt force enable. */
1051                 pci_read_config_byte(dev, 0x5a, &scr1);
1052                 if (scr1 & 0x10)
1053                         pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1054
1055                 /*
1056                  * HighPoint does this for HPT372A.
1057                  * NOTE: This register is only writeable via I/O space.
1058                  */
1059                 if (info->chip_type == HPT372A)
1060                         outb(0x0e, io_base + 0x9c);
1061
1062                 /*
1063                  * Default to PCI clock. Make sure MA15/16 are set to output
1064                  * to prevent drives having problems with 40-pin cables.
1065                  */
1066                 pci_write_config_byte(dev, 0x5b, 0x23);
1067
1068                 /*
1069                  * We'll have to read f_CNT value in order to determine
1070                  * the PCI clock frequency according to the following ratio:
1071                  *
1072                  * f_CNT = Fpci * 192 / Fdpll
1073                  *
1074                  * First try reading the register in which the HighPoint BIOS
1075                  * saves f_CNT value before  reprogramming the DPLL from its
1076                  * default setting (which differs for the various chips).
1077                  * NOTE: This register is only accessible via I/O space.
1078                  *
1079                  * In case the signature check fails, we'll have to resort to
1080                  * reading the f_CNT register itself in hopes that nobody has
1081                  * touched the DPLL yet...
1082                  */
1083                 temp = inl(io_base + 0x90);
1084                 if ((temp & 0xFFFFF000) != 0xABCDE000) {
1085                         int i;
1086
1087                         printk(KERN_WARNING "%s: no clock data saved by BIOS\n",
1088                                name);
1089
1090                         /* Calculate the average value of f_CNT. */
1091                         for (temp = i = 0; i < 128; i++) {
1092                                 pci_read_config_word(dev, 0x78, &f_cnt);
1093                                 temp += f_cnt & 0x1ff;
1094                                 mdelay(1);
1095                         }
1096                         f_cnt = temp / 128;
1097                 } else
1098                         f_cnt = temp & 0x1ff;
1099
1100                 dpll_clk = info->dpll_clk;
1101                 pci_clk  = (f_cnt * dpll_clk) / 192;
1102
1103                 /* Clamp PCI clock to bands. */
1104                 if (pci_clk < 40)
1105                         pci_clk = 33;
1106                 else if(pci_clk < 45)
1107                         pci_clk = 40;
1108                 else if(pci_clk < 55)
1109                         pci_clk = 50;
1110                 else
1111                         pci_clk = 66;
1112
1113                 printk(KERN_INFO "%s: DPLL base: %d MHz, f_CNT: %d, "
1114                        "assuming %d MHz PCI\n", name, dpll_clk, f_cnt, pci_clk);
1115         } else {
1116                 u32 itr1 = 0;
1117
1118                 pci_read_config_dword(dev, 0x40, &itr1);
1119
1120                 /* Detect PCI clock by looking at cmd_high_time. */
1121                 switch((itr1 >> 8) & 0x07) {
1122                         case 0x09:
1123                                 pci_clk = 40;
1124                                 break;
1125                         case 0x05:
1126                                 pci_clk = 25;
1127                                 break;
1128                         case 0x07:
1129                         default:
1130                                 pci_clk = 33;
1131                                 break;
1132                 }
1133         }
1134
1135         /* Let's assume we'll use PCI clock for the ATA clock... */
1136         switch (pci_clk) {
1137                 case 25:
1138                         clock = ATA_CLOCK_25MHZ;
1139                         break;
1140                 case 33:
1141                 default:
1142                         clock = ATA_CLOCK_33MHZ;
1143                         break;
1144                 case 40:
1145                         clock = ATA_CLOCK_40MHZ;
1146                         break;
1147                 case 50:
1148                         clock = ATA_CLOCK_50MHZ;
1149                         break;
1150                 case 66:
1151                         clock = ATA_CLOCK_66MHZ;
1152                         break;
1153         }
1154
1155         /*
1156          * Only try the DPLL if we don't have a table for the PCI clock that
1157          * we are running at for HPT370/A, always use it  for anything newer...
1158          *
1159          * NOTE: Using the internal DPLL results in slow reads on 33 MHz PCI.
1160          * We also  don't like using  the DPLL because this causes glitches
1161          * on PRST-/SRST- when the state engine gets reset...
1162          */
1163         if (info->chip_type >= HPT374 || info->settings[clock] == NULL) {
1164                 u16 f_low, delta = pci_clk < 50 ? 2 : 4;
1165                 int adjust;
1166
1167                  /*
1168                   * Select 66 MHz DPLL clock only if UltraATA/133 mode is
1169                   * supported/enabled, use 50 MHz DPLL clock otherwise...
1170                   */
1171                 if (info->max_mode == 0x04) {
1172                         dpll_clk = 66;
1173                         clock = ATA_CLOCK_66MHZ;
1174                 } else if (dpll_clk) {  /* HPT36x chips don't have DPLL */
1175                         dpll_clk = 50;
1176                         clock = ATA_CLOCK_50MHZ;
1177                 }
1178
1179                 if (info->settings[clock] == NULL) {
1180                         printk(KERN_ERR "%s: unknown bus timing!\n", name);
1181                         kfree(info);
1182                         return -EIO;
1183                 }
1184
1185                 /* Select the DPLL clock. */
1186                 pci_write_config_byte(dev, 0x5b, 0x21);
1187
1188                 /*
1189                  * Adjust the DPLL based upon PCI clock, enable it,
1190                  * and wait for stabilization...
1191                  */
1192                 f_low = (pci_clk * 48) / dpll_clk;
1193
1194                 for (adjust = 0; adjust < 8; adjust++) {
1195                         if(hpt37x_calibrate_dpll(dev, f_low, f_low + delta))
1196                                 break;
1197
1198                         /*
1199                          * See if it'll settle at a fractionally different clock
1200                          */
1201                         if (adjust & 1)
1202                                 f_low -= adjust >> 1;
1203                         else
1204                                 f_low += adjust >> 1;
1205                 }
1206                 if (adjust == 8) {
1207                         printk(KERN_ERR "%s: DPLL did not stabilize!\n", name);
1208                         kfree(info);
1209                         return -EIO;
1210                 }
1211
1212                 printk("%s: using %d MHz DPLL clock\n", name, dpll_clk);
1213         } else {
1214                 /* Mark the fact that we're not using the DPLL. */
1215                 dpll_clk = 0;
1216
1217                 printk("%s: using %d MHz PCI clock\n", name, pci_clk);
1218         }
1219
1220         /*
1221          * Advance the table pointer to a slot which points to the list
1222          * of the register values settings matching the clock being used.
1223          */
1224         info->settings += clock;
1225
1226         /* Store the clock frequencies. */
1227         info->dpll_clk  = dpll_clk;
1228         info->pci_clk   = pci_clk;
1229
1230         /* Point to this chip's own instance of the hpt_info structure. */
1231         pci_set_drvdata(dev, info);
1232
1233         if (info->chip_type >= HPT370) {
1234                 u8  mcr1, mcr4;
1235
1236                 /*
1237                  * Reset the state engines.
1238                  * NOTE: Avoid accidentally enabling the disabled channels.
1239                  */
1240                 pci_read_config_byte (dev, 0x50, &mcr1);
1241                 pci_read_config_byte (dev, 0x54, &mcr4);
1242                 pci_write_config_byte(dev, 0x50, (mcr1 | 0x32));
1243                 pci_write_config_byte(dev, 0x54, (mcr4 | 0x32));
1244                 udelay(100);
1245         }
1246
1247         /*
1248          * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
1249          * the MISC. register to stretch the UltraDMA Tss timing.
1250          * NOTE: This register is only writeable via I/O space.
1251          */
1252         if (info->chip_type == HPT371N && clock == ATA_CLOCK_66MHZ)
1253
1254                 outb(inb(io_base + 0x9c) | 0x04, io_base + 0x9c);
1255
1256         return dev->irq;
1257 }
1258
1259 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1260 {
1261         struct pci_dev  *dev            = hwif->pci_dev;
1262         struct hpt_info *info           = pci_get_drvdata(dev);
1263         int serialize                   = HPT_SERIALIZE_IO;
1264         u8  scr1 = 0, ata66             = (hwif->channel) ? 0x01 : 0x02;
1265         u8  chip_type                   = info->chip_type;
1266         u8  new_mcr, old_mcr            = 0;
1267
1268         /* Cache the channel's MISC. control registers' offset */
1269         hwif->select_data               = hwif->channel ? 0x54 : 0x50;
1270
1271         hwif->tuneproc                  = &hpt3xx_tune_drive;
1272         hwif->speedproc                 = &hpt3xx_tune_chipset;
1273         hwif->quirkproc                 = &hpt3xx_quirkproc;
1274         hwif->intrproc                  = &hpt3xx_intrproc;
1275         hwif->maskproc                  = &hpt3xx_maskproc;
1276         hwif->busproc                   = &hpt3xx_busproc;
1277
1278         /*
1279          * HPT3xxN chips have some complications:
1280          *
1281          * - on 33 MHz PCI we must clock switch
1282          * - on 66 MHz PCI we must NOT use the PCI clock
1283          */
1284         if (chip_type >= HPT372N && info->dpll_clk && info->pci_clk < 66) {
1285                 /*
1286                  * Clock is shared between the channels,
1287                  * so we'll have to serialize them... :-(
1288                  */
1289                 serialize = 1;
1290                 hwif->rw_disk = &hpt3xxn_rw_disk;
1291         }
1292
1293         /* Serialize access to this device if needed */
1294         if (serialize && hwif->mate)
1295                 hwif->serialized = hwif->mate->serialized = 1;
1296
1297         /*
1298          * Disable the "fast interrupt" prediction.  Don't hold off
1299          * on interrupts. (== 0x01 despite what the docs say)
1300          */
1301         pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1302
1303         if (info->chip_type >= HPT374)
1304                 new_mcr = old_mcr & ~0x07;
1305         else if (info->chip_type >= HPT370) {
1306                 new_mcr = old_mcr;
1307                 new_mcr &= ~0x02;
1308
1309 #ifdef HPT_DELAY_INTERRUPT
1310                 new_mcr &= ~0x01;
1311 #else
1312                 new_mcr |=  0x01;
1313 #endif
1314         } else                                  /* HPT366 and HPT368  */
1315                 new_mcr = old_mcr & ~0x80;
1316
1317         if (new_mcr != old_mcr)
1318                 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1319
1320         if (!hwif->dma_base) {
1321                 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1322                 return;
1323         }
1324
1325         hwif->ultra_mask = 0x7f;
1326         hwif->mwdma_mask = 0x07;
1327
1328         /*
1329          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1330          * address lines to access an external EEPROM.  To read valid
1331          * cable detect state the pins must be enabled as inputs.
1332          */
1333         if (chip_type == HPT374 && (PCI_FUNC(dev->devfn) & 1)) {
1334                 /*
1335                  * HPT374 PCI function 1
1336                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1337                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1338                  */
1339                 u8  mcr_addr = hwif->select_data + 2;
1340                 u16 mcr;
1341
1342                 pci_read_config_word (dev, mcr_addr, &mcr);
1343                 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1344                 /* now read cable id register */
1345                 pci_read_config_byte (dev, 0x5a, &scr1);
1346                 pci_write_config_word(dev, mcr_addr, mcr);
1347         } else if (chip_type >= HPT370) {
1348                 /*
1349                  * HPT370/372 and 374 pcifn 0
1350                  * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1351                  */
1352                 u8 scr2 = 0;
1353
1354                 pci_read_config_byte (dev, 0x5b, &scr2);
1355                 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1356                 /* now read cable id register */
1357                 pci_read_config_byte (dev, 0x5a, &scr1);
1358                 pci_write_config_byte(dev, 0x5b,  scr2);
1359         } else
1360                 pci_read_config_byte (dev, 0x5a, &scr1);
1361
1362         if (!hwif->udma_four)
1363                 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1364
1365         hwif->ide_dma_check             = &hpt366_config_drive_xfer_rate;
1366
1367         if (chip_type >= HPT374) {
1368                 hwif->ide_dma_test_irq  = &hpt374_ide_dma_test_irq;
1369                 hwif->ide_dma_end       = &hpt374_ide_dma_end;
1370         } else if (chip_type >= HPT370) {
1371                 hwif->dma_start         = &hpt370_ide_dma_start;
1372                 hwif->ide_dma_end       = &hpt370_ide_dma_end;
1373                 hwif->ide_dma_timeout   = &hpt370_ide_dma_timeout;
1374         } else
1375                 hwif->ide_dma_lostirq   = &hpt366_ide_dma_lostirq;
1376
1377         if (!noautodma)
1378                 hwif->autodma = 1;
1379         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1380 }
1381
1382 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1383 {
1384         struct pci_dev  *dev            = hwif->pci_dev;
1385         u8 masterdma    = 0, slavedma   = 0;
1386         u8 dma_new      = 0, dma_old    = 0;
1387         unsigned long flags;
1388
1389         dma_old = hwif->INB(dmabase + 2);
1390
1391         local_irq_save(flags);
1392
1393         dma_new = dma_old;
1394         pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1395         pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1396
1397         if (masterdma & 0x30)   dma_new |= 0x20;
1398         if ( slavedma & 0x30)   dma_new |= 0x40;
1399         if (dma_new != dma_old)
1400                 hwif->OUTB(dma_new, dmabase + 2);
1401
1402         local_irq_restore(flags);
1403
1404         ide_setup_dma(hwif, dmabase, 8);
1405 }
1406
1407 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1408 {
1409         struct pci_dev *dev2;
1410
1411         if (PCI_FUNC(dev->devfn) & 1)
1412                 return -ENODEV;
1413
1414         pci_set_drvdata(dev, &hpt374);
1415
1416         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1417                 int ret;
1418
1419                 pci_set_drvdata(dev2, &hpt374);
1420
1421                 if (dev2->irq != dev->irq) {
1422                         /* FIXME: we need a core pci_set_interrupt() */
1423                         dev2->irq = dev->irq;
1424                         printk(KERN_WARNING "%s: PCI config space interrupt "
1425                                "fixed.\n", d->name);
1426                 }
1427                 ret = ide_setup_pci_devices(dev, dev2, d);
1428                 if (ret < 0)
1429                         pci_dev_put(dev2);
1430                 return ret;
1431         }
1432         return ide_setup_pci_device(dev, d);
1433 }
1434
1435 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1436 {
1437         pci_set_drvdata(dev, &hpt372n);
1438
1439         return ide_setup_pci_device(dev, d);
1440 }
1441
1442 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1443 {
1444         struct hpt_info *info;
1445         u8 rev = 0, mcr1 = 0;
1446
1447         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1448
1449         if (rev > 1) {
1450                 d->name = "HPT371N";
1451
1452                 info = &hpt371n;
1453         } else
1454                 info = &hpt371;
1455
1456         /*
1457          * HPT371 chips physically have only one channel, the secondary one,
1458          * but the primary channel registers do exist!  Go figure...
1459          * So,  we manually disable the non-existing channel here
1460          * (if the BIOS hasn't done this already).
1461          */
1462         pci_read_config_byte(dev, 0x50, &mcr1);
1463         if (mcr1 & 0x04)
1464                 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1465
1466         pci_set_drvdata(dev, info);
1467
1468         return ide_setup_pci_device(dev, d);
1469 }
1470
1471 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1472 {
1473         struct hpt_info *info;
1474         u8 rev = 0;
1475
1476         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1477
1478         if (rev > 1) {
1479                 d->name = "HPT372N";
1480
1481                 info = &hpt372n;
1482         } else
1483                 info = &hpt372a;
1484         pci_set_drvdata(dev, info);
1485
1486         return ide_setup_pci_device(dev, d);
1487 }
1488
1489 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1490 {
1491         struct hpt_info *info;
1492         u8 rev = 0;
1493
1494         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1495
1496         if (rev > 1) {
1497                 d->name = "HPT302N";
1498
1499                 info = &hpt302n;
1500         } else
1501                 info = &hpt302;
1502         pci_set_drvdata(dev, info);
1503
1504         return ide_setup_pci_device(dev, d);
1505 }
1506
1507 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1508 {
1509         struct pci_dev *dev2;
1510         u8 rev = 0;
1511         static char   *chipset_names[] = { "HPT366", "HPT366",  "HPT368",
1512                                            "HPT370", "HPT370A", "HPT372",
1513                                            "HPT372N" };
1514         static struct hpt_info *info[] = { &hpt36x,  &hpt36x,  &hpt36x,
1515                                            &hpt370,  &hpt370a, &hpt372,
1516                                            &hpt372n  };
1517
1518         if (PCI_FUNC(dev->devfn) & 1)
1519                 return -ENODEV;
1520
1521         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1522
1523         if (rev > 6)
1524                 rev = 6;
1525
1526         d->name = chipset_names[rev];
1527
1528         pci_set_drvdata(dev, info[rev]);
1529
1530         if (rev > 2)
1531                 goto init_single;
1532
1533         d->channels = 1;
1534
1535         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1536                 u8  pin1 = 0, pin2 = 0;
1537                 int ret;
1538
1539                 pci_set_drvdata(dev2, info[rev]);
1540
1541                 pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1542                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1543                 if (pin1 != pin2 && dev->irq == dev2->irq) {
1544                         d->bootable = ON_BOARD;
1545                         printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1546                                d->name, pin1, pin2);
1547                 }
1548                 ret = ide_setup_pci_devices(dev, dev2, d);
1549                 if (ret < 0)
1550                         pci_dev_put(dev2);
1551                 return ret;
1552         }
1553 init_single:
1554         return ide_setup_pci_device(dev, d);
1555 }
1556
1557 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1558         {       /* 0 */
1559                 .name           = "HPT366",
1560                 .init_setup     = init_setup_hpt366,
1561                 .init_chipset   = init_chipset_hpt366,
1562                 .init_hwif      = init_hwif_hpt366,
1563                 .init_dma       = init_dma_hpt366,
1564                 .channels       = 2,
1565                 .autodma        = AUTODMA,
1566                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1567                 .bootable       = OFF_BOARD,
1568                 .extra          = 240
1569         },{     /* 1 */
1570                 .name           = "HPT372A",
1571                 .init_setup     = init_setup_hpt372a,
1572                 .init_chipset   = init_chipset_hpt366,
1573                 .init_hwif      = init_hwif_hpt366,
1574                 .init_dma       = init_dma_hpt366,
1575                 .channels       = 2,
1576                 .autodma        = AUTODMA,
1577                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1578                 .bootable       = OFF_BOARD,
1579                 .extra          = 240
1580         },{     /* 2 */
1581                 .name           = "HPT302",
1582                 .init_setup     = init_setup_hpt302,
1583                 .init_chipset   = init_chipset_hpt366,
1584                 .init_hwif      = init_hwif_hpt366,
1585                 .init_dma       = init_dma_hpt366,
1586                 .channels       = 2,
1587                 .autodma        = AUTODMA,
1588                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1589                 .bootable       = OFF_BOARD,
1590                 .extra          = 240
1591         },{     /* 3 */
1592                 .name           = "HPT371",
1593                 .init_setup     = init_setup_hpt371,
1594                 .init_chipset   = init_chipset_hpt366,
1595                 .init_hwif      = init_hwif_hpt366,
1596                 .init_dma       = init_dma_hpt366,
1597                 .channels       = 2,
1598                 .autodma        = AUTODMA,
1599                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1600                 .bootable       = OFF_BOARD,
1601                 .extra          = 240
1602         },{     /* 4 */
1603                 .name           = "HPT374",
1604                 .init_setup     = init_setup_hpt374,
1605                 .init_chipset   = init_chipset_hpt366,
1606                 .init_hwif      = init_hwif_hpt366,
1607                 .init_dma       = init_dma_hpt366,
1608                 .channels       = 2,    /* 4 */
1609                 .autodma        = AUTODMA,
1610                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1611                 .bootable       = OFF_BOARD,
1612                 .extra          = 240
1613         },{     /* 5 */
1614                 .name           = "HPT372N",
1615                 .init_setup     = init_setup_hpt372n,
1616                 .init_chipset   = init_chipset_hpt366,
1617                 .init_hwif      = init_hwif_hpt366,
1618                 .init_dma       = init_dma_hpt366,
1619                 .channels       = 2,    /* 4 */
1620                 .autodma        = AUTODMA,
1621                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1622                 .bootable       = OFF_BOARD,
1623                 .extra          = 240
1624         }
1625 };
1626
1627 /**
1628  *      hpt366_init_one -       called when an HPT366 is found
1629  *      @dev: the hpt366 device
1630  *      @id: the matching pci id
1631  *
1632  *      Called when the PCI registration layer (or the IDE initialization)
1633  *      finds a device matching our IDE device tables.
1634  *
1635  *      NOTE: since we'll have to modify some fields of the ide_pci_device_t
1636  *      structure depending on the chip's revision, we'd better pass a local
1637  *      copy down the call chain...
1638  */
1639 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1640 {
1641         ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1642
1643         return d.init_setup(dev, &d);
1644 }
1645
1646 static struct pci_device_id hpt366_pci_tbl[] = {
1647         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1648         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1649         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1650         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1651         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1652         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1653         { 0, },
1654 };
1655 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1656
1657 static struct pci_driver driver = {
1658         .name           = "HPT366_IDE",
1659         .id_table       = hpt366_pci_tbl,
1660         .probe          = hpt366_init_one,
1661 };
1662
1663 static int __init hpt366_ide_init(void)
1664 {
1665         return ide_pci_register_driver(&driver);
1666 }
1667
1668 module_init(hpt366_ide_init);
1669
1670 MODULE_AUTHOR("Andre Hedrick");
1671 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1672 MODULE_LICENSE("GPL");