drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.50    May 28, 2006
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
  66  *   as the ATA clock being used does not allow for this speed anyway
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  71  *   HPT37x chip family; save space by introducing the separate transfer mode
  72  *   table in which the mode lookup is done
  73  * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  74  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
  75  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  76  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  77  * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  78  *   they tamper with its fields
  79  * - prefix the driver startup messages with the real chip name
  80  * - claim the extra 240 bytes of I/O space for all chips
  81  * - optimize the rate masking/filtering and the drive list lookup code
  82  * - use pci_get_slot() to get to the function 1 of HPT36x/374
  83  * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting
  84  *   the cable type on HPT374's function 1
  85  * - rename all the register related variables consistently
  86  * - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the
  87  *   PIO timing register mask for HPT37x
  88  *              <source@mvista.com>
  89  *
  90  */
  91
  92
  93 #include <linux/types.h>
  94 #include <linux/module.h>
  95 #include <linux/kernel.h>
  96 #include <linux/delay.h>
  97 #include <linux/timer.h>
  98 #include <linux/mm.h>
  99 #include <linux/ioport.h>
 100 #include <linux/blkdev.h>
 101 #include <linux/hdreg.h>
 102
 103 #include <linux/interrupt.h>
 104 #include <linux/pci.h>
 105 #include <linux/init.h>
 106 #include <linux/ide.h>
 107
 108 #include <asm/uaccess.h>
 109 #include <asm/io.h>
 110 #include <asm/irq.h>
 111
 112 /* various tuning parameters */
 113 #define HPT_RESET_STATE_ENGINE
 114 #undef  HPT_DELAY_INTERRUPT
 115 #define HPT_SERIALIZE_IO        0
 116
 117 static const char *quirk_drives[] = {
 118         "QUANTUM FIREBALLlct08 08",
 119         "QUANTUM FIREBALLP KA6.4",
 120         "QUANTUM FIREBALLP LM20.4",
 121         "QUANTUM FIREBALLP LM20.5",
 122         NULL
 123 };
 124
 125 static const char *bad_ata100_5[] = {
 126         "IBM-DTLA-307075",
 127         "IBM-DTLA-307060",
 128         "IBM-DTLA-307045",
 129         "IBM-DTLA-307030",
 130         "IBM-DTLA-307020",
 131         "IBM-DTLA-307015",
 132         "IBM-DTLA-305040",
 133         "IBM-DTLA-305030",
 134         "IBM-DTLA-305020",
 135         "IC35L010AVER07-0",
 136         "IC35L020AVER07-0",
 137         "IC35L030AVER07-0",
 138         "IC35L040AVER07-0",
 139         "IC35L060AVER07-0",
 140         "WDC AC310200R",
 141         NULL
 142 };
 143
 144 static const char *bad_ata66_4[] = {
 145         "IBM-DTLA-307075",
 146         "IBM-DTLA-307060",
 147         "IBM-DTLA-307045",
 148         "IBM-DTLA-307030",
 149         "IBM-DTLA-307020",
 150         "IBM-DTLA-307015",
 151         "IBM-DTLA-305040",
 152         "IBM-DTLA-305030",
 153         "IBM-DTLA-305020",
 154         "IC35L010AVER07-0",
 155         "IC35L020AVER07-0",
 156         "IC35L030AVER07-0",
 157         "IC35L040AVER07-0",
 158         "IC35L060AVER07-0",
 159         "WDC AC310200R",
 160         NULL
 161 };
 162
 163 static const char *bad_ata66_3[] = {
 164         "WDC AC310200R",
 165         NULL
 166 };
 167
 168 static const char *bad_ata33[] = {
 169         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 170         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 171         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 172         "Maxtor 90510D4",
 173         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 174         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 175         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 176         NULL
 177 };
 178
 179 static u8 xfer_speeds[] = {
 180         XFER_UDMA_6,
 181         XFER_UDMA_5,
 182         XFER_UDMA_4,
 183         XFER_UDMA_3,
 184         XFER_UDMA_2,
 185         XFER_UDMA_1,
 186         XFER_UDMA_0,
 187
 188         XFER_MW_DMA_2,
 189         XFER_MW_DMA_1,
 190         XFER_MW_DMA_0,
 191
 192         XFER_PIO_4,
 193         XFER_PIO_3,
 194         XFER_PIO_2,
 195         XFER_PIO_1,
 196         XFER_PIO_0
 197 };
 198
 199 /* Key for bus clock timings
 200  * 36x   37x
 201  * bits  bits
 202  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 203  *              cycles = value + 1
 204  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 205  *              cycles = value + 1
 206  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 207  *              register access.
 208  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 209  *              register access.
 210  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 211  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 212  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 213  *              MW DMA xfer.
 214  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 215  *              task file register access.
 216  * 28    28     UDMA enable.
 217  * 29    29     DMA  enable.
 218  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 219  *              PIO xfer.
 220  * 31    31     FIFO enable.
 221  */
 222
 223 static u32 forty_base_hpt36x[] = {
 224         /* XFER_UDMA_6 */       0x900fd943,
 225         /* XFER_UDMA_5 */       0x900fd943,
 226         /* XFER_UDMA_4 */       0x900fd943,
 227         /* XFER_UDMA_3 */       0x900ad943,
 228         /* XFER_UDMA_2 */       0x900bd943,
 229         /* XFER_UDMA_1 */       0x9008d943,
 230         /* XFER_UDMA_0 */       0x9008d943,
 231
 232         /* XFER_MW_DMA_2 */     0xa008d943,
 233         /* XFER_MW_DMA_1 */     0xa010d955,
 234         /* XFER_MW_DMA_0 */     0xa010d9fc,
 235
 236         /* XFER_PIO_4 */        0xc008d963,
 237         /* XFER_PIO_3 */        0xc010d974,
 238         /* XFER_PIO_2 */        0xc010d997,
 239         /* XFER_PIO_1 */        0xc010d9c7,
 240         /* XFER_PIO_0 */        0xc018d9d9
 241 };
 242
 243 static u32 thirty_three_base_hpt36x[] = {
 244         /* XFER_UDMA_6 */       0x90c9a731,
 245         /* XFER_UDMA_5 */       0x90c9a731,
 246         /* XFER_UDMA_4 */       0x90c9a731,
 247         /* XFER_UDMA_3 */       0x90cfa731,
 248         /* XFER_UDMA_2 */       0x90caa731,
 249         /* XFER_UDMA_1 */       0x90cba731,
 250         /* XFER_UDMA_0 */       0x90c8a731,
 251
 252         /* XFER_MW_DMA_2 */     0xa0c8a731,
 253         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 254         /* XFER_MW_DMA_0 */     0xa0c8a797,
 255
 256         /* XFER_PIO_4 */        0xc0c8a731,
 257         /* XFER_PIO_3 */        0xc0c8a742,
 258         /* XFER_PIO_2 */        0xc0d0a753,
 259         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 260         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 261 };
 262
 263 static u32 twenty_five_base_hpt36x[] = {
 264         /* XFER_UDMA_6 */       0x90c98521,
 265         /* XFER_UDMA_5 */       0x90c98521,
 266         /* XFER_UDMA_4 */       0x90c98521,
 267         /* XFER_UDMA_3 */       0x90cf8521,
 268         /* XFER_UDMA_2 */       0x90cf8521,
 269         /* XFER_UDMA_1 */       0x90cb8521,
 270         /* XFER_UDMA_0 */       0x90cb8521,
 271
 272         /* XFER_MW_DMA_2 */     0xa0ca8521,
 273         /* XFER_MW_DMA_1 */     0xa0ca8532,
 274         /* XFER_MW_DMA_0 */     0xa0ca8575,
 275
 276         /* XFER_PIO_4 */        0xc0ca8521,
 277         /* XFER_PIO_3 */        0xc0ca8532,
 278         /* XFER_PIO_2 */        0xc0ca8542,
 279         /* XFER_PIO_1 */        0xc0d08572,
 280         /* XFER_PIO_0 */        0xc0d08585
 281 };
 282
 283 static u32 thirty_three_base_hpt37x[] = {
 284         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 285         /* XFER_UDMA_5 */       0x12446231,
 286         /* XFER_UDMA_4 */       0x12446231,
 287         /* XFER_UDMA_3 */       0x126c6231,
 288         /* XFER_UDMA_2 */       0x12486231,
 289         /* XFER_UDMA_1 */       0x124c6233,
 290         /* XFER_UDMA_0 */       0x12506297,
 291
 292         /* XFER_MW_DMA_2 */     0x22406c31,
 293         /* XFER_MW_DMA_1 */     0x22406c33,
 294         /* XFER_MW_DMA_0 */     0x22406c97,
 295
 296         /* XFER_PIO_4 */        0x06414e31,
 297         /* XFER_PIO_3 */        0x06414e42,
 298         /* XFER_PIO_2 */        0x06414e53,
 299         /* XFER_PIO_1 */        0x06814e93,
 300         /* XFER_PIO_0 */        0x06814ea7
 301 };
 302
 303 static u32 fifty_base_hpt37x[] = {
 304         /* XFER_UDMA_6 */       0x12848242,
 305         /* XFER_UDMA_5 */       0x12848242,
 306         /* XFER_UDMA_4 */       0x12ac8242,
 307         /* XFER_UDMA_3 */       0x128c8242,
 308         /* XFER_UDMA_2 */       0x120c8242,
 309         /* XFER_UDMA_1 */       0x12148254,
 310         /* XFER_UDMA_0 */       0x121882ea,
 311
 312         /* XFER_MW_DMA_2 */     0x22808242,
 313         /* XFER_MW_DMA_1 */     0x22808254,
 314         /* XFER_MW_DMA_0 */     0x228082ea,
 315
 316         /* XFER_PIO_4 */        0x0a81f442,
 317         /* XFER_PIO_3 */        0x0a81f443,
 318         /* XFER_PIO_2 */        0x0a81f454,
 319         /* XFER_PIO_1 */        0x0ac1f465,
 320         /* XFER_PIO_0 */        0x0ac1f48a
 321 };
 322
 323 static u32 sixty_six_base_hpt37x[] = {
 324         /* XFER_UDMA_6 */       0x1c869c62,
 325         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 326         /* XFER_UDMA_4 */       0x1c8a9c62,
 327         /* XFER_UDMA_3 */       0x1c8e9c62,
 328         /* XFER_UDMA_2 */       0x1c929c62,
 329         /* XFER_UDMA_1 */       0x1c9a9c62,
 330         /* XFER_UDMA_0 */       0x1c829c62,
 331
 332         /* XFER_MW_DMA_2 */     0x2c829c62,
 333         /* XFER_MW_DMA_1 */     0x2c829c66,
 334         /* XFER_MW_DMA_0 */     0x2c829d2e,
 335
 336         /* XFER_PIO_4 */        0x0c829c62,
 337         /* XFER_PIO_3 */        0x0c829c84,
 338         /* XFER_PIO_2 */        0x0c829ca6,
 339         /* XFER_PIO_1 */        0x0d029d26,
 340         /* XFER_PIO_0 */        0x0d029d5e
 341 };
 342
 343 #define HPT366_DEBUG_DRIVE_INFO         0
 344 #define HPT374_ALLOW_ATA133_6           0
 345 #define HPT371_ALLOW_ATA133_6           0
 346 #define HPT302_ALLOW_ATA133_6           0
 347 #define HPT372_ALLOW_ATA133_6           0
 348 #define HPT370_ALLOW_ATA100_5           0
 349 #define HPT366_ALLOW_ATA66_4            1
 350 #define HPT366_ALLOW_ATA66_3            1
 351 #define HPT366_MAX_DEVS                 8
 352
 353 #define F_LOW_PCI_33    0x23
 354 #define F_LOW_PCI_40    0x29
 355 #define F_LOW_PCI_50    0x2d
 356 #define F_LOW_PCI_66    0x42
 357
 358 /*
 359  *      Hold all the highpoint quirks and revision information in one
 360  *      place.
 361  */
 362
 363 struct hpt_info
 364 {
 365         u8 max_mode;            /* Speeds allowed */
 366         u8 revision;            /* Chipset revision */
 367         u8 flags;               /* Chipset properties */
 368 #define PLL_MODE        1
 369 #define IS_3xxN         2
 370 #define PCI_66MHZ       4
 371                                 /* Speed table */
 372         u32 *speed;
 373 };
 374
 375 /*
 376  *      This wants fixing so that we do everything not by revision
 377  *      (which breaks on the newest chips) but by creating an
 378  *      enumeration of chip variants and using that
 379  */
 380
 381 static __devinit u8 hpt_revision(struct pci_dev *dev)
 382 {
 383         u8 rev = 0;
 384
 385         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
 386
 387         switch(dev->device) {
 388                 /* Remap new 372N onto 372 */
 389                 case PCI_DEVICE_ID_TTI_HPT372N:
 390                         rev = PCI_DEVICE_ID_TTI_HPT372;
 391                         break;
 392                 case PCI_DEVICE_ID_TTI_HPT374:
 393                         rev = PCI_DEVICE_ID_TTI_HPT374;
 394                         break;
 395                 case PCI_DEVICE_ID_TTI_HPT371:
 396                         rev = PCI_DEVICE_ID_TTI_HPT371;
 397                         break;
 398                 case PCI_DEVICE_ID_TTI_HPT302:
 399                         rev = PCI_DEVICE_ID_TTI_HPT302;
 400                         break;
 401                 case PCI_DEVICE_ID_TTI_HPT372:
 402                         rev = PCI_DEVICE_ID_TTI_HPT372;
 403                         break;
 404                 default:
 405                         break;
 406         }
 407         return rev;
 408 }
 409
 410 static int check_in_drive_list(ide_drive_t *drive, const char **list)
 411 {
 412         struct hd_driveid *id = drive->id;
 413
 414         while (*list)
 415                 if (!strcmp(*list++,id->model))
 416                         return 1;
 417         return 0;
 418 }
 419
 420 static u8 hpt3xx_ratemask(ide_drive_t *drive)
 421 {
 422         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 423         u8 mode                 = info->max_mode;
 424
 425         if (!eighty_ninty_three(drive) && mode)
 426                 mode = min(mode, (u8)1);
 427         return mode;
 428 }
 429
 430 /*
 431  *      Note for the future; the SATA hpt37x we must set
 432  *      either PIO or UDMA modes 0,4,5
 433  */
 434
 435 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
 436 {
 437         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 438         u8 mode                 = hpt3xx_ratemask(drive);
 439
 440         if (drive->media != ide_disk)
 441                 return min(speed, (u8)XFER_PIO_4);
 442
 443         switch (mode) {
 444                 case 0x04:
 445                         speed = min(speed, (u8)XFER_UDMA_6);
 446                         break;
 447                 case 0x03:
 448                         speed = min(speed, (u8)XFER_UDMA_5);
 449                         if (info->revision >= 5)
 450                                 break;
 451                         if (!check_in_drive_list(drive, bad_ata100_5))
 452                                 goto check_bad_ata33;
 453                         /* fall thru */
 454                 case 0x02:
 455                         speed = min_t(u8, speed, XFER_UDMA_4);
 456         /*
 457          * CHECK ME, Does this need to be set to 5 ??
 458          */
 459                         if (info->revision >= 3)
 460                                 goto check_bad_ata33;
 461                         if (HPT366_ALLOW_ATA66_4 &&
 462                             !check_in_drive_list(drive, bad_ata66_4))
 463                                 goto check_bad_ata33;
 464
 465                         speed = min_t(u8, speed, XFER_UDMA_3);
 466                         if (HPT366_ALLOW_ATA66_3 &&
 467                             !check_in_drive_list(drive, bad_ata66_3))
 468                                 goto check_bad_ata33;
 469                         /* fall thru */
 470                 case 0x01:
 471                         speed = min_t(u8, speed, XFER_UDMA_2);
 472
 473                 check_bad_ata33:
 474                         if (info->revision >= 4)
 475                                 break;
 476                         if (!check_in_drive_list(drive, bad_ata33))
 477                                 break;
 478                         /* fall thru */
 479                 case 0x00:
 480                 default:
 481                         speed = min_t(u8, speed, XFER_MW_DMA_2);
 482                         break;
 483         }
 484         return speed;
 485 }
 486
 487 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
 488 {
 489         int i;
 490
 491         /*
 492          * Lookup the transfer mode table to get the index into
 493          * the timing table.
 494          *
 495          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 496          */
 497         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 498                 if (xfer_speeds[i] == speed)
 499                         break;
 500         return chipset_table[i];
 501 }
 502
 503 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 504 {
 505         ide_hwif_t *hwif        = HWIF(drive);
 506         struct pci_dev  *dev    = hwif->pci_dev;
 507         struct hpt_info *info   = ide_get_hwifdata (hwif);
 508         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 509         u8  itr_addr            = drive->dn ? 0x44 : 0x40;
 510         u8  mcr_addr            = hwif->select_data + 1;
 511         u8  mcr                 = 0;
 512         u32 new_itr, old_itr    = 0;
 513         u32 itr_mask            = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000;
 514
 515         /*
 516          * Disable the "fast interrupt" prediction.
 517          */
 518         pci_read_config_byte(dev, mcr_addr, &mcr);
 519         if (mcr & 0x80)
 520                 pci_write_config_byte(dev, mcr_addr, mcr & ~0x80);
 521
 522         new_itr = pci_bus_clock_list(speed, info->speed);
 523
 524         /*
 525          * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 526          * to avoid problems handling I/O errors later
 527          */
 528         pci_read_config_dword(dev, itr_addr, &old_itr);
 529         new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 530         new_itr &= ~0xc0000000;
 531
 532         pci_write_config_dword(dev, itr_addr, new_itr);
 533
 534         return ide_config_drive_speed(drive, speed);
 535 }
 536
 537 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 538 {
 539         ide_hwif_t *hwif        = HWIF(drive);
 540         struct pci_dev  *dev    = hwif->pci_dev;
 541         struct hpt_info *info   = ide_get_hwifdata (hwif);
 542         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 543         u8  mcr_addr            = hwif->select_data + 1;
 544         u8  itr_addr            = 0x40 + (drive->dn * 4);
 545         u8  new_mcr             = 0, old_mcr = 0;
 546         u32 new_itr, old_itr    = 0;
 547         u32 itr_mask            = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
 548
 549         /*
 550          * Disable the "fast interrupt" prediction.
 551          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 552          */
 553         pci_read_config_byte(dev, mcr_addr, &old_mcr);
 554         new_mcr = old_mcr;
 555         if (new_mcr & 0x02)
 556                 new_mcr &= ~0x02;
 557
 558 #ifdef HPT_DELAY_INTERRUPT
 559         if (new_mcr & 0x01)
 560                 new_mcr &= ~0x01;
 561 #else
 562         if ((new_mcr & 0x01) == 0)
 563                 new_mcr |= 0x01;
 564 #endif
 565         if (new_mcr != old_mcr)
 566                 pci_write_config_byte(dev, mcr_addr, new_mcr);
 567
 568         new_itr = pci_bus_clock_list(speed, info->speed);
 569
 570         pci_read_config_dword(dev, itr_addr, &old_itr);
 571         new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 572
 573         if (speed < XFER_MW_DMA_0)
 574                 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 575         pci_write_config_dword(dev, itr_addr, new_itr);
 576
 577         return ide_config_drive_speed(drive, speed);
 578 }
 579
 580 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 581 {
 582         ide_hwif_t *hwif        = HWIF(drive);
 583         struct pci_dev  *dev    = hwif->pci_dev;
 584         struct hpt_info *info   = ide_get_hwifdata (hwif);
 585         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 586         u8  mcr_addr            = hwif->select_data + 1;
 587         u8  itr_addr            = 0x40 + (drive->dn * 4);
 588         u8  mcr                 = 0;
 589         u32 new_itr, old_itr    = 0;
 590         u32 itr_mask            = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
 591
 592         /*
 593          * Disable the "fast interrupt" prediction.
 594          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 595          */
 596         pci_read_config_byte (dev, mcr_addr, &mcr);
 597         pci_write_config_byte(dev, mcr_addr, (mcr & ~0x07));
 598
 599         new_itr = pci_bus_clock_list(speed, info->speed);
 600         pci_read_config_dword(dev, itr_addr, &old_itr);
 601         new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 602         if (speed < XFER_MW_DMA_0)
 603                 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 604         pci_write_config_dword(dev, itr_addr, new_itr);
 605
 606         return ide_config_drive_speed(drive, speed);
 607 }
 608
 609 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 610 {
 611         ide_hwif_t *hwif        = drive->hwif;
 612         struct hpt_info *info   = ide_get_hwifdata(hwif);
 613
 614         if (info->revision >= 8)
 615                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 616         else if (info->revision >= 5)
 617                 return hpt372_tune_chipset(drive, speed);
 618         else if (info->revision >= 3)
 619                 return hpt370_tune_chipset(drive, speed);
 620         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 621                 return hpt36x_tune_chipset(drive, speed);
 622 }
 623
 624 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 625 {
 626         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 627         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 628 }
 629
 630 /*
 631  * This allows the configuration of ide_pci chipset registers
 632  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 633  * after the drive is reported by the OS.  Initially for designed for
 634  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 635  *
 636  * check_in_drive_lists(drive, bad_ata66_4)
 637  * check_in_drive_lists(drive, bad_ata66_3)
 638  * check_in_drive_lists(drive, bad_ata33)
 639  *
 640  */
 641 static int config_chipset_for_dma (ide_drive_t *drive)
 642 {
 643         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 644         ide_hwif_t *hwif = drive->hwif;
 645         struct hpt_info *info   = ide_get_hwifdata(hwif);
 646
 647         if (!speed)
 648                 return 0;
 649
 650         /* If we don't have any timings we can't do a lot */
 651         if (info->speed == NULL)
 652                 return 0;
 653
 654         (void) hpt3xx_tune_chipset(drive, speed);
 655         return ide_dma_enable(drive);
 656 }
 657
 658 static int hpt3xx_quirkproc(ide_drive_t *drive)
 659 {
 660         struct hd_driveid *id   = drive->id;
 661         const  char **list      = quirk_drives;
 662
 663         while (*list)
 664                 if (strstr(id->model, *list++))
 665                         return 1;
 666         return 0;
 667 }
 668
 669 static void hpt3xx_intrproc (ide_drive_t *drive)
 670 {
 671         ide_hwif_t *hwif = HWIF(drive);
 672
 673         if (drive->quirk_list)
 674                 return;
 675         /* drives in the quirk_list may not like intr setups/cleanups */
 676         hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
 677 }
 678
 679 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 680 {
 681         ide_hwif_t *hwif        = HWIF(drive);
 682         struct pci_dev  *dev    = hwif->pci_dev;
 683         struct hpt_info *info   = ide_get_hwifdata(hwif);
 684
 685         if (drive->quirk_list) {
 686                 if (info->revision >= 3) {
 687                         u8 scr1 = 0;
 688
 689                         pci_read_config_byte(dev, 0x5a, &scr1);
 690                         if (((scr1 & 0x10) >> 4) != mask) {
 691                                 if (mask)
 692                                         scr1 |=  0x10;
 693                                 else
 694                                         scr1 &= ~0x10;
 695                                 pci_write_config_byte(dev, 0x5a, scr1);
 696                         }
 697                 } else {
 698                         if (mask)
 699                                 disable_irq(hwif->irq);
 700                         else
 701                                 enable_irq (hwif->irq);
 702                 }
 703         } else
 704                 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 705                            IDE_CONTROL_REG);
 706 }
 707
 708 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 709 {
 710         ide_hwif_t *hwif        = drive->hwif;
 711         struct hd_driveid *id   = drive->id;
 712
 713         drive->init_speed = 0;
 714
 715         if ((id->capability & 1) && drive->autodma) {
 716
 717                 if (ide_use_dma(drive)) {
 718                         if (config_chipset_for_dma(drive))
 719                                 return hwif->ide_dma_on(drive);
 720                 }
 721
 722                 goto fast_ata_pio;
 723
 724         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 725 fast_ata_pio:
 726                 hpt3xx_tune_drive(drive, 5);
 727                 return hwif->ide_dma_off_quietly(drive);
 728         }
 729         /* IORDY not supported */
 730         return 0;
 731 }
 732
 733 /*
 734  * This is specific to the HPT366 UDMA chipset
 735  * by HighPoint|Triones Technologies, Inc.
 736  */
 737 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
 738 {
 739         struct pci_dev *dev = HWIF(drive)->pci_dev;
 740         u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 741
 742         pci_read_config_byte(dev, 0x50, &mcr1);
 743         pci_read_config_byte(dev, 0x52, &mcr3);
 744         pci_read_config_byte(dev, 0x5a, &scr1);
 745         printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 746                 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
 747         if (scr1 & 0x10)
 748                 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 749         return __ide_dma_lostirq(drive);
 750 }
 751
 752 static void hpt370_clear_engine (ide_drive_t *drive)
 753 {
 754         ide_hwif_t *hwif = HWIF(drive);
 755
 756         pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
 757         udelay(10);
 758 }
 759
 760 static void hpt370_ide_dma_start(ide_drive_t *drive)
 761 {
 762 #ifdef HPT_RESET_STATE_ENGINE
 763         hpt370_clear_engine(drive);
 764 #endif
 765         ide_dma_start(drive);
 766 }
 767
 768 static int hpt370_ide_dma_end (ide_drive_t *drive)
 769 {
 770         ide_hwif_t *hwif        = HWIF(drive);
 771         u8 dma_stat             = hwif->INB(hwif->dma_status);
 772
 773         if (dma_stat & 0x01) {
 774                 /* wait a little */
 775                 udelay(20);
 776                 dma_stat = hwif->INB(hwif->dma_status);
 777         }
 778         if ((dma_stat & 0x01) != 0)
 779                 /* fallthrough */
 780                 (void) HWIF(drive)->ide_dma_timeout(drive);
 781
 782         return __ide_dma_end(drive);
 783 }
 784
 785 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 786 {
 787         ide_hwif_t *hwif        = HWIF(drive);
 788         u8 bfifo = 0;
 789         u8 dma_stat = 0, dma_cmd = 0;
 790
 791         pci_read_config_byte(HWIF(drive)->pci_dev, hwif->select_data + 2, &bfifo);
 792         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 793         hpt370_clear_engine(drive);
 794         /* get dma command mode */
 795         dma_cmd = hwif->INB(hwif->dma_command);
 796         /* stop dma */
 797         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 798         dma_stat = hwif->INB(hwif->dma_status);
 799         /* clear errors */
 800         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 801 }
 802
 803 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 804 {
 805         hpt370_lostirq_timeout(drive);
 806         hpt370_clear_engine(drive);
 807         return __ide_dma_timeout(drive);
 808 }
 809
 810 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 811 {
 812         hpt370_lostirq_timeout(drive);
 813         hpt370_clear_engine(drive);
 814         return __ide_dma_lostirq(drive);
 815 }
 816
 817 /* returns 1 if DMA IRQ issued, 0 otherwise */
 818 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 819 {
 820         ide_hwif_t *hwif        = HWIF(drive);
 821         u16 bfifo               = 0;
 822         u8  dma_stat;
 823
 824         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 825         if (bfifo & 0x1FF) {
 826 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 827                 return 0;
 828         }
 829
 830         dma_stat = hwif->INB(hwif->dma_status);
 831         /* return 1 if INTR asserted */
 832         if (dma_stat & 4)
 833                 return 1;
 834
 835         if (!drive->waiting_for_dma)
 836                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 837                                 drive->name, __FUNCTION__);
 838         return 0;
 839 }
 840
 841 static int hpt374_ide_dma_end(ide_drive_t *drive)
 842 {
 843         ide_hwif_t *hwif        = HWIF(drive);
 844         struct pci_dev  *dev    = hwif->pci_dev;
 845         u8 mcr  = 0, mcr_addr   = hwif->select_data;
 846         u8 bwsr = 0, mask       = hwif->channel ? 0x02 : 0x01;
 847
 848         pci_read_config_byte(dev, 0x6a, &bwsr);
 849         pci_read_config_byte(dev, mcr_addr, &mcr);
 850         if (bwsr & mask)
 851                 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 852         return __ide_dma_end(drive);
 853 }
 854
 855 /**
 856  *      hpt3xxn_set_clock       -       perform clock switching dance
 857  *      @hwif: hwif to switch
 858  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 859  *
 860  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 861  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 862  *      doesn't physically exist anyway...
 863  */
 864
 865 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 866 {
 867         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 868
 869         if ((scr2 & 0x7f) == mode)
 870                 return;
 871
 872         /* MISC. control register 1 has the channel enable bit... */
 873         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 874
 875         /* Tristate the bus */
 876         if (mcr1 & 0x04)
 877                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 878         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 879
 880         /* Switch clock and reset channels */
 881         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 882         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 883
 884         /* Reset state machines */
 885         if (mcr1 & 0x04)
 886                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
 887         hwif->OUTB(0x37, hwif->dma_master + 0x74);
 888
 889         /* Complete reset */
 890         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 891
 892         /* Reconnect channels to bus */
 893         if (mcr1 & 0x04)
 894                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
 895         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 896 }
 897
 898 /**
 899  *      hpt3xxn_rw_disk         -       prepare for I/O
 900  *      @drive: drive for command
 901  *      @rq: block request structure
 902  *
 903  *      This is called when a disk I/O is issued to HPT3xxN.
 904  *      We need it because of the clock switching.
 905  */
 906
 907 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 908 {
 909         ide_hwif_t *hwif        = HWIF(drive);
 910         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
 911
 912         hpt3xxn_set_clock(hwif, wantclock);
 913 }
 914
 915 /*
 916  * Set/get power state for a drive.
 917  * NOTE: affects both drives on each channel.
 918  *
 919  * When we turn the power back on, we need to re-initialize things.
 920  */
 921 #define TRISTATE_BIT  0x8000
 922
 923 static int hpt3xx_busproc(ide_drive_t *drive, int state)
 924 {
 925         ide_hwif_t *hwif        = HWIF(drive);
 926         struct pci_dev *dev     = hwif->pci_dev;
 927         u8  mcr_addr            = hwif->select_data + 2;
 928         u8  resetmask           = hwif->channel ? 0x80 : 0x40;
 929         u8  bsr2                = 0;
 930         u16 mcr                 = 0;
 931
 932         hwif->bus_state = state;
 933
 934         /* Grab the status. */
 935         pci_read_config_word(dev, mcr_addr, &mcr);
 936         pci_read_config_byte(dev, 0x59, &bsr2);
 937
 938         /*
 939          * Set the state. We don't set it if we don't need to do so.
 940          * Make sure that the drive knows that it has failed if it's off.
 941          */
 942         switch (state) {
 943         case BUSSTATE_ON:
 944                 if (!(bsr2 & resetmask))
 945                         return 0;
 946                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
 947
 948                 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
 949                 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
 950                 return 0;
 951         case BUSSTATE_OFF:
 952                 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
 953                         return 0;
 954                 mcr &= ~TRISTATE_BIT;
 955                 break;
 956         case BUSSTATE_TRISTATE:
 957                 if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
 958                         return 0;
 959                 mcr |= TRISTATE_BIT;
 960                 break;
 961         default:
 962                 return -EINVAL;
 963         }
 964
 965         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 966         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 967
 968         pci_write_config_word(dev, mcr_addr, mcr);
 969         pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
 970         return 0;
 971 }
 972
 973 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
 974 {
 975         u32 itr1        = 0;
 976         struct hpt_info *info = ide_get_hwifdata(hwif);
 977
 978         pci_read_config_dword(hwif->pci_dev, 0x40, &itr1);
 979
 980         /* detect bus speed by looking at control reg timing: */
 981         switch((itr1 >> 8) & 7) {
 982                 case 5:
 983                         info->speed = forty_base_hpt36x;
 984                         break;
 985                 case 9:
 986                         info->speed = twenty_five_base_hpt36x;
 987                         break;
 988                 case 7:
 989                 default:
 990                         info->speed = thirty_three_base_hpt36x;
 991                         break;
 992         }
 993 }
 994
 995 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
 996 {
 997         struct hpt_info *info   = ide_get_hwifdata(hwif);
 998         struct pci_dev  *dev    = hwif->pci_dev;
 999         char *name              = hwif->cds->name;
1000         int adjust, i;
1001         u16 freq = 0;
1002         u32 pll, temp = 0;
1003         u8  scr2 = 0, mcr1 = 0;
1004
1005         /*
1006          * default to pci clock. make sure MA15/16 are set to output
1007          * to prevent drives having problems with 40-pin cables. Needed
1008          * for some drives such as IBM-DTLA which will not enter ready
1009          * state on reset when PDIAG is a input.
1010          *
1011          * ToDo: should we set 0x21 when using PLL mode ?
1012          */
1013         pci_write_config_byte(dev, 0x5b, 0x23);
1014
1015         /*
1016          * We'll have to read f_CNT value in order to determine
1017          * the PCI clock frequency according to the following ratio:
1018          *
1019          * f_CNT = Fpci * 192 / Fdpll
1020          *
1021          * First try reading the register in which the HighPoint BIOS
1022          * saves f_CNT value before  reprogramming the DPLL from its
1023          * default setting (which differs for the various chips).
1024          * NOTE: This register is only accessible via I/O space.
1025          *
1026          * In case the signature check fails, we'll have to resort to
1027          * reading the f_CNT register itself in hopes that nobody has
1028          * touched the DPLL yet...
1029          */
1030         temp = inl(pci_resource_start(dev, 4) + 0x90);
1031         if ((temp & 0xFFFFF000) != 0xABCDE000) {
1032                 printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
1033
1034                 /* Calculate the average value of f_CNT */
1035                 for (temp = i = 0; i < 128; i++) {
1036                         pci_read_config_word(dev, 0x78, &freq);
1037                         temp += freq & 0x1ff;
1038                         mdelay(1);
1039                 }
1040                 freq = temp / 128;
1041         } else
1042                 freq = temp & 0x1ff;
1043
1044         /*
1045          * HPT3xxN chips use different PCI clock information.
1046          * Currently we always set up the PLL for them.
1047          */
1048
1049         if (info->flags & IS_3xxN) {
1050                 if(freq < 0x55)
1051                         pll = F_LOW_PCI_33;
1052                 else if(freq < 0x70)
1053                         pll = F_LOW_PCI_40;
1054                 else if(freq < 0x7F)
1055                         pll = F_LOW_PCI_50;
1056                 else
1057                         pll = F_LOW_PCI_66;
1058
1059         } else {
1060                 if(freq < 0x9C)
1061                         pll = F_LOW_PCI_33;
1062                 else if(freq < 0xb0)
1063                         pll = F_LOW_PCI_40;
1064                 else if(freq <0xc8)
1065                         pll = F_LOW_PCI_50;
1066                 else
1067                         pll = F_LOW_PCI_66;
1068         }
1069         printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
1070
1071         if (!(info->flags & IS_3xxN)) {
1072                 if (pll == F_LOW_PCI_33) {
1073                         info->speed = thirty_three_base_hpt37x;
1074                         printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
1075                 } else if (pll == F_LOW_PCI_40) {
1076                         /* Unsupported */
1077                 } else if (pll == F_LOW_PCI_50) {
1078                         info->speed = fifty_base_hpt37x;
1079                         printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
1080                 } else {
1081                         info->speed = sixty_six_base_hpt37x;
1082                         printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
1083                 }
1084         }
1085
1086         if (pll == F_LOW_PCI_66)
1087                 info->flags |= PCI_66MHZ;
1088
1089         /*
1090          * only try the pll if we don't have a table for the clock
1091          * speed that we're running at. NOTE: the internal PLL will
1092          * result in slow reads when using a 33MHz PCI clock. we also
1093          * don't like to use the PLL because it will cause glitches
1094          * on PRST/SRST when the HPT state engine gets reset.
1095          *
1096          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1097          * 372 device so we can get ATA133 support
1098          */
1099         if (info->speed)
1100                 goto init_hpt37X_done;
1101
1102         info->flags |= PLL_MODE;
1103
1104         /*
1105          * Adjust the PLL based upon the PCI clock, enable it, and
1106          * wait for stabilization...
1107          */
1108         adjust = 0;
1109         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1110         while (adjust++ < 6) {
1111                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1112                                        pll | 0x100);
1113
1114                 /* wait for clock stabilization */
1115                 for (i = 0; i < 0x50000; i++) {
1116                         pci_read_config_byte(dev, 0x5b, &scr2);
1117                         if (scr2 & 0x80) {
1118                                 /* spin looking for the clock to destabilize */
1119                                 for (i = 0; i < 0x1000; ++i) {
1120                                         pci_read_config_byte(dev, 0x5b,
1121                                                              &scr2);
1122                                         if ((scr2 & 0x80) == 0)
1123                                                 goto pll_recal;
1124                                 }
1125                                 pci_read_config_dword(dev, 0x5c, &pll);
1126                                 pci_write_config_dword(dev, 0x5c,
1127                                                        pll & ~0x100);
1128                                 pci_write_config_byte(dev, 0x5b, 0x21);
1129
1130                                 info->speed = fifty_base_hpt37x;
1131                                 printk("%s: using 50MHz internal PLL\n", name);
1132                                 goto init_hpt37X_done;
1133                         }
1134                 }
1135 pll_recal:
1136                 if (adjust & 1)
1137                         pll -= (adjust >> 1);
1138                 else
1139                         pll += (adjust >> 1);
1140         }
1141
1142 init_hpt37X_done:
1143         if (!info->speed)
1144                 printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
1145                        name, pll, freq);
1146         /*
1147          * Reset the state engines.
1148          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1149          */
1150         pci_read_config_byte(dev, 0x50, &mcr1);
1151         if (mcr1 & 0x04)
1152                 pci_write_config_byte(dev, 0x50, 0x37);
1153         pci_write_config_byte(dev, 0x54, 0x37);
1154         udelay(100);
1155 }
1156
1157 static int __devinit init_hpt37x(struct pci_dev *dev)
1158 {
1159         u8 scr1;
1160
1161         pci_read_config_byte (dev, 0x5a, &scr1);
1162         /* interrupt force enable */
1163         pci_write_config_byte(dev, 0x5a, (scr1 & ~0x10));
1164         return 0;
1165 }
1166
1167 static int __devinit init_hpt366(struct pci_dev *dev)
1168 {
1169         u8 mcr  = 0;
1170
1171         /*
1172          * Disable the "fast interrupt" prediction.
1173          */
1174         pci_read_config_byte(dev, 0x51, &mcr);
1175         if (mcr & 0x80)
1176                 pci_write_config_byte(dev, 0x51, mcr & ~0x80);
1177
1178         return 0;
1179 }
1180
1181 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1182 {
1183         int ret = 0;
1184
1185         /*
1186          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1187          * We don't seem to be using it.
1188          */
1189         if (dev->resource[PCI_ROM_RESOURCE].start)
1190                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1191                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1192
1193         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1194         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1195         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1196         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1197
1198         if (hpt_revision(dev) >= 3)
1199                 ret = init_hpt37x(dev);
1200         else
1201                 ret = init_hpt366(dev);
1202
1203         if (ret)
1204                 return ret;
1205
1206         return dev->irq;
1207 }
1208
1209 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1210 {
1211         struct pci_dev  *dev            = hwif->pci_dev;
1212         struct hpt_info *info           = ide_get_hwifdata(hwif);
1213         int serialize                   = HPT_SERIALIZE_IO;
1214         u8  scr1 = 0, ata66             = (hwif->channel) ? 0x01 : 0x02;
1215
1216         /* Cache the channel's MISC. control registers' offset */
1217         hwif->select_data               = hwif->channel ? 0x54 : 0x50;
1218
1219         hwif->tuneproc                  = &hpt3xx_tune_drive;
1220         hwif->speedproc                 = &hpt3xx_tune_chipset;
1221         hwif->quirkproc                 = &hpt3xx_quirkproc;
1222         hwif->intrproc                  = &hpt3xx_intrproc;
1223         hwif->maskproc                  = &hpt3xx_maskproc;
1224         hwif->busproc                   = &hpt3xx_busproc;
1225
1226         /*
1227          * HPT3xxN chips have some complications:
1228          *
1229          * - on 33 MHz PCI we must clock switch
1230          * - on 66 MHz PCI we must NOT use the PCI clock
1231          */
1232         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1233                 /*
1234                  * Clock is shared between the channels,
1235                  * so we'll have to serialize them... :-(
1236                  */
1237                 serialize = 1;
1238                 hwif->rw_disk = &hpt3xxn_rw_disk;
1239         }
1240
1241         /*
1242          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1243          * address lines to access an external EEPROM.  To read valid
1244          * cable detect state the pins must be enabled as inputs.
1245          */
1246         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1247                 /*
1248                  * HPT374 PCI function 1
1249                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1250                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1251                  */
1252                 u8  mcr_addr = hwif->select_data + 2;
1253                 u16 mcr;
1254
1255                 pci_read_config_word (dev, mcr_addr, &mcr);
1256                 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1257                 /* now read cable id register */
1258                 pci_read_config_byte (dev, 0x5a, &scr1);
1259                 pci_write_config_word(dev, mcr_addr, mcr);
1260         } else if (info->revision >= 3) {
1261                 /*
1262                  * HPT370/372 and 374 pcifn 0
1263                  * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1264                  */
1265                 u8 scr2 = 0;
1266
1267                 pci_read_config_byte (dev, 0x5b, &scr2);
1268                 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1269                 /* now read cable id register */
1270                 pci_read_config_byte (dev, 0x5a, &scr1);
1271                 pci_write_config_byte(dev, 0x5b,  scr2);
1272         } else
1273                 pci_read_config_byte (dev, 0x5a, &scr1);
1274
1275         /* Serialize access to this device */
1276         if (serialize && hwif->mate)
1277                 hwif->serialized = hwif->mate->serialized = 1;
1278
1279         /*
1280          * Set up ioctl for power status.
1281          * NOTE:  power affects both drives on each channel.
1282          */
1283         hwif->busproc = &hpt3xx_busproc;
1284
1285         if (!hwif->dma_base) {
1286                 hwif->drives[0].autotune = 1;
1287                 hwif->drives[1].autotune = 1;
1288                 return;
1289         }
1290
1291         hwif->ultra_mask = 0x7f;
1292         hwif->mwdma_mask = 0x07;
1293
1294         if (!(hwif->udma_four))
1295                 hwif->udma_four = ((scr1 & ata66) ? 0 : 1);
1296         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1297
1298         if (info->revision >= 8) {
1299                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1300                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1301         } else if (info->revision >= 5) {
1302                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1303                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1304         } else if (info->revision >= 3) {
1305                 hwif->dma_start = &hpt370_ide_dma_start;
1306                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1307                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1308                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1309         } else if (info->revision >= 2)
1310                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1311         else
1312                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1313
1314         if (!noautodma)
1315                 hwif->autodma = 1;
1316         hwif->drives[0].autodma = hwif->autodma;
1317         hwif->drives[1].autodma = hwif->autodma;
1318 }
1319
1320 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1321 {
1322         struct pci_dev  *dev            = hwif->pci_dev;
1323         struct hpt_info *info           = ide_get_hwifdata(hwif);
1324         u8 masterdma    = 0, slavedma   = 0;
1325         u8 dma_new      = 0, dma_old    = 0;
1326         unsigned long flags;
1327
1328         if (!dmabase)
1329                 return;
1330
1331         if(info->speed == NULL) {
1332                 printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n",
1333                        hwif->cds->name);
1334                 return;
1335         }
1336
1337         dma_old = hwif->INB(dmabase+2);
1338
1339         local_irq_save(flags);
1340
1341         dma_new = dma_old;
1342         pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1343         pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1344
1345         if (masterdma & 0x30)   dma_new |= 0x20;
1346         if ( slavedma & 0x30)   dma_new |= 0x40;
1347         if (dma_new != dma_old)
1348                 hwif->OUTB(dma_new, dmabase + 2);
1349
1350         local_irq_restore(flags);
1351
1352         ide_setup_dma(hwif, dmabase, 8);
1353 }
1354
1355 /*
1356  *      We "borrow" this hook in order to set the data structures
1357  *      up early enough before dma or init_hwif calls are made.
1358  */
1359
1360 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1361 {
1362         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1363         struct pci_dev  *dev    = hwif->pci_dev;
1364         u16 did                 = dev->device;
1365         u8 mode, rid            = 0;
1366
1367         if(info == NULL) {
1368                 printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name);
1369                 return;
1370         }
1371         ide_set_hwifdata(hwif, info);
1372
1373         /* Avoid doing the same thing twice. */
1374         if (hwif->channel && hwif->mate) {
1375                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1376                 return;
1377         }
1378
1379         pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
1380
1381         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1382             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1383               did == PCI_DEVICE_ID_TTI_HPT302  ||
1384               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1385               did == PCI_DEVICE_ID_TTI_HPT372N)
1386                 info->flags |= IS_3xxN;
1387
1388         rid = info->revision = hpt_revision(dev);
1389         if (rid >= 8)                   /* HPT374 */
1390                 mode = HPT374_ALLOW_ATA133_6 ? 4 : 3;
1391         else if (rid >= 7)              /* HPT371 and HPT371N */
1392                 mode = HPT371_ALLOW_ATA133_6 ? 4 : 3;
1393         else if (rid >= 6)              /* HPT302 and HPT302N */
1394                 mode = HPT302_ALLOW_ATA133_6 ? 4 : 3;
1395         else if (rid >= 5)              /* HPT372, HPT372A, and HPT372N */
1396                 mode = HPT372_ALLOW_ATA133_6 ? 4 : 3;
1397         else if (rid >= 3)              /* HPT370 and HPT370A */
1398                 mode = HPT370_ALLOW_ATA100_5 ? 3 : 2;
1399         else                            /* HPT366 and HPT368 */
1400                 mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1;
1401         info->max_mode = mode;
1402
1403         if (rid >= 3)
1404                 hpt37x_clocking(hwif);
1405         else
1406                 hpt366_clocking(hwif);
1407 }
1408
1409 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1410 {
1411         struct pci_dev *dev2;
1412
1413         if (PCI_FUNC(dev->devfn) & 1)
1414                 return -ENODEV;
1415
1416         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1417                 int ret;
1418
1419                 if (dev2->irq != dev->irq) {
1420                         /* FIXME: we need a core pci_set_interrupt() */
1421                         dev2->irq = dev->irq;
1422                         printk(KERN_WARNING "%s: PCI config space interrupt "
1423                                "fixed.\n", d->name);
1424                 }
1425                 ret = ide_setup_pci_devices(dev, dev2, d);
1426                 if (ret < 0)
1427                         pci_dev_put(dev2);
1428                 return ret;
1429         }
1430         return ide_setup_pci_device(dev, d);
1431 }
1432
1433 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1434 {
1435         return ide_setup_pci_device(dev, d);
1436 }
1437
1438 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1439 {
1440         u8 rev = 0, mcr1 = 0;
1441
1442         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1443
1444         if (rev > 1)
1445                 d->name = "HPT371N";
1446
1447         /*
1448          * HPT371 chips physically have only one channel, the secondary one,
1449          * but the primary channel registers do exist!  Go figure...
1450          * So,  we manually disable the non-existing channel here
1451          * (if the BIOS hasn't done this already).
1452          */
1453         pci_read_config_byte(dev, 0x50, &mcr1);
1454         if (mcr1 & 0x04)
1455                 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1456
1457         return ide_setup_pci_device(dev, d);
1458 }
1459
1460 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1461 {
1462         u8 rev = 0;
1463
1464         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1465
1466         if (rev > 1)
1467                 d->name = "HPT372N";
1468
1469         return ide_setup_pci_device(dev, d);
1470 }
1471
1472 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1473 {
1474         u8 rev = 0;
1475
1476         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1477
1478         if (rev > 1)
1479                 d->name = "HPT302N";
1480
1481         return ide_setup_pci_device(dev, d);
1482 }
1483
1484 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1485 {
1486         struct pci_dev *dev2;
1487         u8 rev = 0;
1488         static char   *chipset_names[] = { "HPT366", "HPT366",  "HPT368",
1489                                            "HPT370", "HPT370A", "HPT372",
1490                                            "HPT372N" };
1491
1492         if (PCI_FUNC(dev->devfn) & 1)
1493                 return -ENODEV;
1494
1495         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1496
1497         if (rev > 6)
1498                 rev = 6;
1499
1500         d->name = chipset_names[rev];
1501
1502         if (rev > 2)
1503                 goto init_single;
1504
1505         d->channels = 1;
1506
1507         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1508                 u8  pin1 = 0, pin2 = 0;
1509                 int ret;
1510
1511                 pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1512                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1513                 if (pin1 != pin2 && dev->irq == dev2->irq) {
1514                         d->bootable = ON_BOARD;
1515                         printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1516                                d->name, pin1, pin2);
1517                 }
1518                 ret = ide_setup_pci_devices(dev, dev2, d);
1519                 if (ret < 0)
1520                         pci_dev_put(dev2);
1521                 return ret;
1522         }
1523 init_single:
1524         return ide_setup_pci_device(dev, d);
1525 }
1526
1527 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1528         {       /* 0 */
1529                 .name           = "HPT366",
1530                 .init_setup     = init_setup_hpt366,
1531                 .init_chipset   = init_chipset_hpt366,
1532                 .init_iops      = init_iops_hpt366,
1533                 .init_hwif      = init_hwif_hpt366,
1534                 .init_dma       = init_dma_hpt366,
1535                 .channels       = 2,
1536                 .autodma        = AUTODMA,
1537                 .bootable       = OFF_BOARD,
1538                 .extra          = 240
1539         },{     /* 1 */
1540                 .name           = "HPT372A",
1541                 .init_setup     = init_setup_hpt372a,
1542                 .init_chipset   = init_chipset_hpt366,
1543                 .init_iops      = init_iops_hpt366,
1544                 .init_hwif      = init_hwif_hpt366,
1545                 .init_dma       = init_dma_hpt366,
1546                 .channels       = 2,
1547                 .autodma        = AUTODMA,
1548                 .bootable       = OFF_BOARD,
1549                 .extra          = 240
1550         },{     /* 2 */
1551                 .name           = "HPT302",
1552                 .init_setup     = init_setup_hpt302,
1553                 .init_chipset   = init_chipset_hpt366,
1554                 .init_iops      = init_iops_hpt366,
1555                 .init_hwif      = init_hwif_hpt366,
1556                 .init_dma       = init_dma_hpt366,
1557                 .channels       = 2,
1558                 .autodma        = AUTODMA,
1559                 .bootable       = OFF_BOARD,
1560                 .extra          = 240
1561         },{     /* 3 */
1562                 .name           = "HPT371",
1563                 .init_setup     = init_setup_hpt371,
1564                 .init_chipset   = init_chipset_hpt366,
1565                 .init_iops      = init_iops_hpt366,
1566                 .init_hwif      = init_hwif_hpt366,
1567                 .init_dma       = init_dma_hpt366,
1568                 .channels       = 2,
1569                 .autodma        = AUTODMA,
1570                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1571                 .bootable       = OFF_BOARD,
1572                 .extra          = 240
1573         },{     /* 4 */
1574                 .name           = "HPT374",
1575                 .init_setup     = init_setup_hpt374,
1576                 .init_chipset   = init_chipset_hpt366,
1577                 .init_iops      = init_iops_hpt366,
1578                 .init_hwif      = init_hwif_hpt366,
1579                 .init_dma       = init_dma_hpt366,
1580                 .channels       = 2,    /* 4 */
1581                 .autodma        = AUTODMA,
1582                 .bootable       = OFF_BOARD,
1583                 .extra          = 240
1584         },{     /* 5 */
1585                 .name           = "HPT372N",
1586                 .init_setup     = init_setup_hpt372n,
1587                 .init_chipset   = init_chipset_hpt366,
1588                 .init_iops      = init_iops_hpt366,
1589                 .init_hwif      = init_hwif_hpt366,
1590                 .init_dma       = init_dma_hpt366,
1591                 .channels       = 2,    /* 4 */
1592                 .autodma        = AUTODMA,
1593                 .bootable       = OFF_BOARD,
1594                 .extra          = 240
1595         }
1596 };
1597
1598 /**
1599  *      hpt366_init_one -       called when an HPT366 is found
1600  *      @dev: the hpt366 device
1601  *      @id: the matching pci id
1602  *
1603  *      Called when the PCI registration layer (or the IDE initialization)
1604  *      finds a device matching our IDE device tables.
1605  *
1606  *      NOTE: since we'll have to modify some fields of the ide_pci_device_t
1607  *      structure depending on the chip's revision, we'd better pass a local
1608  *      copy down the call chain...
1609  */
1610 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1611 {
1612         ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1613
1614         return d.init_setup(dev, &d);
1615 }
1616
1617 static struct pci_device_id hpt366_pci_tbl[] = {
1618         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1619         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1620         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1621         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1622         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1623         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1624         { 0, },
1625 };
1626 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1627
1628 static struct pci_driver driver = {
1629         .name           = "HPT366_IDE",
1630         .id_table       = hpt366_pci_tbl,
1631         .probe          = hpt366_init_one,
1632 };
1633
1634 static int __init hpt366_ide_init(void)
1635 {
1636         return ide_pci_register_driver(&driver);
1637 }
1638
1639 module_init(hpt366_ide_init);
1640
1641 MODULE_AUTHOR("Andre Hedrick");
1642 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1643 MODULE_LICENSE("GPL");