drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.52    Jun 07, 2006
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 and UltraATA/100 for HPT370 by default
  66  *   as the ATA clock being used does not allow for this speed anyway
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  71  *   HPT37x chip family; save space by introducing the separate transfer mode
  72  *   table in which the mode lookup is done
  73  * - use f_CNT value saved by  the HighPoint BIOS as reading it directly gives
  74  *   the wrong PCI frequency since DPLL has already been calibrated by BIOS
  75  * - fix the hotswap code:  it caused RESET- to glitch when tristating the bus,
  76  *   and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
  77  * - pass to init_chipset() handlers a copy of the IDE PCI device structure as
  78  *   they tamper with its fields
  79  * - prefix the driver startup messages with the real chip name
  80  * - claim the extra 240 bytes of I/O space for all chips
  81  * - optimize the rate masking/filtering and the drive list lookup code
  82  * - use pci_get_slot() to get to the function 1 of HPT36x/374
  83  * - cache the channel's MCRs' offset; only touch the relevant MCR when detecting
  84  *   the cable type on HPT374's function 1
  85  * - rename all the register related variables consistently
  86  * - move the interrupt twiddling code from the speedproc handlers into the
  87  *   init_hwif handler, also grouping all the DMA related code together there;
  88  *   simplify  the init_chipset handler
  89  * - merge two HPT37x speedproc handlers and fix the PIO timing register mask
  90  *   there; make HPT36x speedproc handler look the same way as the HPT37x one
  91  * - fix  the tuneproc handler to always set the PIO mode requested,  not the
  92  *   best possible one
  93  * - clean up DMA timeout handling for HPT370
  94  *              <source@mvista.com>
  95  */
  96
  97 #include <linux/types.h>
  98 #include <linux/module.h>
  99 #include <linux/kernel.h>
 100 #include <linux/delay.h>
 101 #include <linux/timer.h>
 102 #include <linux/mm.h>
 103 #include <linux/ioport.h>
 104 #include <linux/blkdev.h>
 105 #include <linux/hdreg.h>
 106
 107 #include <linux/interrupt.h>
 108 #include <linux/pci.h>
 109 #include <linux/init.h>
 110 #include <linux/ide.h>
 111
 112 #include <asm/uaccess.h>
 113 #include <asm/io.h>
 114 #include <asm/irq.h>
 115
 116 /* various tuning parameters */
 117 #define HPT_RESET_STATE_ENGINE
 118 #undef  HPT_DELAY_INTERRUPT
 119 #define HPT_SERIALIZE_IO        0
 120
 121 static const char *quirk_drives[] = {
 122         "QUANTUM FIREBALLlct08 08",
 123         "QUANTUM FIREBALLP KA6.4",
 124         "QUANTUM FIREBALLP LM20.4",
 125         "QUANTUM FIREBALLP LM20.5",
 126         NULL
 127 };
 128
 129 static const char *bad_ata100_5[] = {
 130         "IBM-DTLA-307075",
 131         "IBM-DTLA-307060",
 132         "IBM-DTLA-307045",
 133         "IBM-DTLA-307030",
 134         "IBM-DTLA-307020",
 135         "IBM-DTLA-307015",
 136         "IBM-DTLA-305040",
 137         "IBM-DTLA-305030",
 138         "IBM-DTLA-305020",
 139         "IC35L010AVER07-0",
 140         "IC35L020AVER07-0",
 141         "IC35L030AVER07-0",
 142         "IC35L040AVER07-0",
 143         "IC35L060AVER07-0",
 144         "WDC AC310200R",
 145         NULL
 146 };
 147
 148 static const char *bad_ata66_4[] = {
 149         "IBM-DTLA-307075",
 150         "IBM-DTLA-307060",
 151         "IBM-DTLA-307045",
 152         "IBM-DTLA-307030",
 153         "IBM-DTLA-307020",
 154         "IBM-DTLA-307015",
 155         "IBM-DTLA-305040",
 156         "IBM-DTLA-305030",
 157         "IBM-DTLA-305020",
 158         "IC35L010AVER07-0",
 159         "IC35L020AVER07-0",
 160         "IC35L030AVER07-0",
 161         "IC35L040AVER07-0",
 162         "IC35L060AVER07-0",
 163         "WDC AC310200R",
 164         NULL
 165 };
 166
 167 static const char *bad_ata66_3[] = {
 168         "WDC AC310200R",
 169         NULL
 170 };
 171
 172 static const char *bad_ata33[] = {
 173         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 174         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 175         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 176         "Maxtor 90510D4",
 177         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 178         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 179         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 180         NULL
 181 };
 182
 183 static u8 xfer_speeds[] = {
 184         XFER_UDMA_6,
 185         XFER_UDMA_5,
 186         XFER_UDMA_4,
 187         XFER_UDMA_3,
 188         XFER_UDMA_2,
 189         XFER_UDMA_1,
 190         XFER_UDMA_0,
 191
 192         XFER_MW_DMA_2,
 193         XFER_MW_DMA_1,
 194         XFER_MW_DMA_0,
 195
 196         XFER_PIO_4,
 197         XFER_PIO_3,
 198         XFER_PIO_2,
 199         XFER_PIO_1,
 200         XFER_PIO_0
 201 };
 202
 203 /* Key for bus clock timings
 204  * 36x   37x
 205  * bits  bits
 206  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 207  *              cycles = value + 1
 208  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 209  *              cycles = value + 1
 210  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 211  *              register access.
 212  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 213  *              register access.
 214  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 215  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 216  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 217  *              MW DMA xfer.
 218  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 219  *              task file register access.
 220  * 28    28     UDMA enable.
 221  * 29    29     DMA  enable.
 222  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 223  *              PIO xfer.
 224  * 31    31     FIFO enable.
 225  */
 226
 227 static u32 forty_base_hpt36x[] = {
 228         /* XFER_UDMA_6 */       0x900fd943,
 229         /* XFER_UDMA_5 */       0x900fd943,
 230         /* XFER_UDMA_4 */       0x900fd943,
 231         /* XFER_UDMA_3 */       0x900ad943,
 232         /* XFER_UDMA_2 */       0x900bd943,
 233         /* XFER_UDMA_1 */       0x9008d943,
 234         /* XFER_UDMA_0 */       0x9008d943,
 235
 236         /* XFER_MW_DMA_2 */     0xa008d943,
 237         /* XFER_MW_DMA_1 */     0xa010d955,
 238         /* XFER_MW_DMA_0 */     0xa010d9fc,
 239
 240         /* XFER_PIO_4 */        0xc008d963,
 241         /* XFER_PIO_3 */        0xc010d974,
 242         /* XFER_PIO_2 */        0xc010d997,
 243         /* XFER_PIO_1 */        0xc010d9c7,
 244         /* XFER_PIO_0 */        0xc018d9d9
 245 };
 246
 247 static u32 thirty_three_base_hpt36x[] = {
 248         /* XFER_UDMA_6 */       0x90c9a731,
 249         /* XFER_UDMA_5 */       0x90c9a731,
 250         /* XFER_UDMA_4 */       0x90c9a731,
 251         /* XFER_UDMA_3 */       0x90cfa731,
 252         /* XFER_UDMA_2 */       0x90caa731,
 253         /* XFER_UDMA_1 */       0x90cba731,
 254         /* XFER_UDMA_0 */       0x90c8a731,
 255
 256         /* XFER_MW_DMA_2 */     0xa0c8a731,
 257         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 258         /* XFER_MW_DMA_0 */     0xa0c8a797,
 259
 260         /* XFER_PIO_4 */        0xc0c8a731,
 261         /* XFER_PIO_3 */        0xc0c8a742,
 262         /* XFER_PIO_2 */        0xc0d0a753,
 263         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 264         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 265 };
 266
 267 static u32 twenty_five_base_hpt36x[] = {
 268         /* XFER_UDMA_6 */       0x90c98521,
 269         /* XFER_UDMA_5 */       0x90c98521,
 270         /* XFER_UDMA_4 */       0x90c98521,
 271         /* XFER_UDMA_3 */       0x90cf8521,
 272         /* XFER_UDMA_2 */       0x90cf8521,
 273         /* XFER_UDMA_1 */       0x90cb8521,
 274         /* XFER_UDMA_0 */       0x90cb8521,
 275
 276         /* XFER_MW_DMA_2 */     0xa0ca8521,
 277         /* XFER_MW_DMA_1 */     0xa0ca8532,
 278         /* XFER_MW_DMA_0 */     0xa0ca8575,
 279
 280         /* XFER_PIO_4 */        0xc0ca8521,
 281         /* XFER_PIO_3 */        0xc0ca8532,
 282         /* XFER_PIO_2 */        0xc0ca8542,
 283         /* XFER_PIO_1 */        0xc0d08572,
 284         /* XFER_PIO_0 */        0xc0d08585
 285 };
 286
 287 static u32 thirty_three_base_hpt37x[] = {
 288         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 289         /* XFER_UDMA_5 */       0x12446231,
 290         /* XFER_UDMA_4 */       0x12446231,
 291         /* XFER_UDMA_3 */       0x126c6231,
 292         /* XFER_UDMA_2 */       0x12486231,
 293         /* XFER_UDMA_1 */       0x124c6233,
 294         /* XFER_UDMA_0 */       0x12506297,
 295
 296         /* XFER_MW_DMA_2 */     0x22406c31,
 297         /* XFER_MW_DMA_1 */     0x22406c33,
 298         /* XFER_MW_DMA_0 */     0x22406c97,
 299
 300         /* XFER_PIO_4 */        0x06414e31,
 301         /* XFER_PIO_3 */        0x06414e42,
 302         /* XFER_PIO_2 */        0x06414e53,
 303         /* XFER_PIO_1 */        0x06814e93,
 304         /* XFER_PIO_0 */        0x06814ea7
 305 };
 306
 307 static u32 fifty_base_hpt37x[] = {
 308         /* XFER_UDMA_6 */       0x12848242,
 309         /* XFER_UDMA_5 */       0x12848242,
 310         /* XFER_UDMA_4 */       0x12ac8242,
 311         /* XFER_UDMA_3 */       0x128c8242,
 312         /* XFER_UDMA_2 */       0x120c8242,
 313         /* XFER_UDMA_1 */       0x12148254,
 314         /* XFER_UDMA_0 */       0x121882ea,
 315
 316         /* XFER_MW_DMA_2 */     0x22808242,
 317         /* XFER_MW_DMA_1 */     0x22808254,
 318         /* XFER_MW_DMA_0 */     0x228082ea,
 319
 320         /* XFER_PIO_4 */        0x0a81f442,
 321         /* XFER_PIO_3 */        0x0a81f443,
 322         /* XFER_PIO_2 */        0x0a81f454,
 323         /* XFER_PIO_1 */        0x0ac1f465,
 324         /* XFER_PIO_0 */        0x0ac1f48a
 325 };
 326
 327 static u32 sixty_six_base_hpt37x[] = {
 328         /* XFER_UDMA_6 */       0x1c869c62,
 329         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 330         /* XFER_UDMA_4 */       0x1c8a9c62,
 331         /* XFER_UDMA_3 */       0x1c8e9c62,
 332         /* XFER_UDMA_2 */       0x1c929c62,
 333         /* XFER_UDMA_1 */       0x1c9a9c62,
 334         /* XFER_UDMA_0 */       0x1c829c62,
 335
 336         /* XFER_MW_DMA_2 */     0x2c829c62,
 337         /* XFER_MW_DMA_1 */     0x2c829c66,
 338         /* XFER_MW_DMA_0 */     0x2c829d2e,
 339
 340         /* XFER_PIO_4 */        0x0c829c62,
 341         /* XFER_PIO_3 */        0x0c829c84,
 342         /* XFER_PIO_2 */        0x0c829ca6,
 343         /* XFER_PIO_1 */        0x0d029d26,
 344         /* XFER_PIO_0 */        0x0d029d5e
 345 };
 346
 347 #define HPT366_DEBUG_DRIVE_INFO         0
 348 #define HPT374_ALLOW_ATA133_6           0
 349 #define HPT371_ALLOW_ATA133_6           0
 350 #define HPT302_ALLOW_ATA133_6           0
 351 #define HPT372_ALLOW_ATA133_6           0
 352 #define HPT370_ALLOW_ATA100_5           0
 353 #define HPT366_ALLOW_ATA66_4            1
 354 #define HPT366_ALLOW_ATA66_3            1
 355 #define HPT366_MAX_DEVS                 8
 356
 357 #define F_LOW_PCI_33    0x23
 358 #define F_LOW_PCI_40    0x29
 359 #define F_LOW_PCI_50    0x2d
 360 #define F_LOW_PCI_66    0x42
 361
 362 /*
 363  *      Hold all the highpoint quirks and revision information in one
 364  *      place.
 365  */
 366
 367 struct hpt_info
 368 {
 369         u8 max_mode;            /* Speeds allowed */
 370         u8 revision;            /* Chipset revision */
 371         u8 flags;               /* Chipset properties */
 372 #define PLL_MODE        1
 373 #define IS_3xxN         2
 374 #define PCI_66MHZ       4
 375                                 /* Speed table */
 376         u32 *speed;
 377 };
 378
 379 /*
 380  *      This wants fixing so that we do everything not by revision
 381  *      (which breaks on the newest chips) but by creating an
 382  *      enumeration of chip variants and using that
 383  */
 384
 385 static __devinit u8 hpt_revision(struct pci_dev *dev)
 386 {
 387         u8 rev = 0;
 388
 389         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
 390
 391         switch(dev->device) {
 392                 /* Remap new 372N onto 372 */
 393                 case PCI_DEVICE_ID_TTI_HPT372N:
 394                         rev = PCI_DEVICE_ID_TTI_HPT372;
 395                         break;
 396                 case PCI_DEVICE_ID_TTI_HPT374:
 397                         rev = PCI_DEVICE_ID_TTI_HPT374;
 398                         break;
 399                 case PCI_DEVICE_ID_TTI_HPT371:
 400                         rev = PCI_DEVICE_ID_TTI_HPT371;
 401                         break;
 402                 case PCI_DEVICE_ID_TTI_HPT302:
 403                         rev = PCI_DEVICE_ID_TTI_HPT302;
 404                         break;
 405                 case PCI_DEVICE_ID_TTI_HPT372:
 406                         rev = PCI_DEVICE_ID_TTI_HPT372;
 407                         break;
 408                 default:
 409                         break;
 410         }
 411         return rev;
 412 }
 413
 414 static int check_in_drive_list(ide_drive_t *drive, const char **list)
 415 {
 416         struct hd_driveid *id = drive->id;
 417
 418         while (*list)
 419                 if (!strcmp(*list++,id->model))
 420                         return 1;
 421         return 0;
 422 }
 423
 424 static u8 hpt3xx_ratemask(ide_drive_t *drive)
 425 {
 426         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 427         u8 mode                 = info->max_mode;
 428
 429         if (!eighty_ninty_three(drive) && mode)
 430                 mode = min(mode, (u8)1);
 431         return mode;
 432 }
 433
 434 /*
 435  *      Note for the future; the SATA hpt37x we must set
 436  *      either PIO or UDMA modes 0,4,5
 437  */
 438
 439 static u8 hpt3xx_ratefilter(ide_drive_t *drive, u8 speed)
 440 {
 441         struct hpt_info *info   = ide_get_hwifdata(HWIF(drive));
 442         u8 mode                 = hpt3xx_ratemask(drive);
 443
 444         if (drive->media != ide_disk)
 445                 return min(speed, (u8)XFER_PIO_4);
 446
 447         switch (mode) {
 448                 case 0x04:
 449                         speed = min(speed, (u8)XFER_UDMA_6);
 450                         break;
 451                 case 0x03:
 452                         speed = min(speed, (u8)XFER_UDMA_5);
 453                         if (info->revision >= 5)
 454                                 break;
 455                         if (!check_in_drive_list(drive, bad_ata100_5))
 456                                 goto check_bad_ata33;
 457                         /* fall thru */
 458                 case 0x02:
 459                         speed = min_t(u8, speed, XFER_UDMA_4);
 460         /*
 461          * CHECK ME, Does this need to be set to 5 ??
 462          */
 463                         if (info->revision >= 3)
 464                                 goto check_bad_ata33;
 465                         if (HPT366_ALLOW_ATA66_4 &&
 466                             !check_in_drive_list(drive, bad_ata66_4))
 467                                 goto check_bad_ata33;
 468
 469                         speed = min_t(u8, speed, XFER_UDMA_3);
 470                         if (HPT366_ALLOW_ATA66_3 &&
 471                             !check_in_drive_list(drive, bad_ata66_3))
 472                                 goto check_bad_ata33;
 473                         /* fall thru */
 474                 case 0x01:
 475                         speed = min_t(u8, speed, XFER_UDMA_2);
 476
 477                 check_bad_ata33:
 478                         if (info->revision >= 4)
 479                                 break;
 480                         if (!check_in_drive_list(drive, bad_ata33))
 481                                 break;
 482                         /* fall thru */
 483                 case 0x00:
 484                 default:
 485                         speed = min_t(u8, speed, XFER_MW_DMA_2);
 486                         break;
 487         }
 488         return speed;
 489 }
 490
 491 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
 492 {
 493         int i;
 494
 495         /*
 496          * Lookup the transfer mode table to get the index into
 497          * the timing table.
 498          *
 499          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 500          */
 501         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 502                 if (xfer_speeds[i] == speed)
 503                         break;
 504         return chipset_table[i];
 505 }
 506
 507 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 508 {
 509         ide_hwif_t *hwif        = HWIF(drive);
 510         struct pci_dev  *dev    = hwif->pci_dev;
 511         struct hpt_info *info   = ide_get_hwifdata (hwif);
 512         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 513         u8  itr_addr            = drive->dn ? 0x44 : 0x40;
 514         u32 itr_mask            = (speed < XFER_MW_DMA_0) ? 0x30070000 : 0xc0000000;
 515         u32 new_itr             = pci_bus_clock_list(speed, info->speed);
 516         u32 old_itr             = 0;
 517
 518         /*
 519          * Disable on-chip PIO FIFO/buffer (and PIO MST mode as well)
 520          * to avoid problems handling I/O errors later
 521          */
 522         pci_read_config_dword(dev, itr_addr, &old_itr);
 523         new_itr  = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 524         new_itr &= ~0xc0000000;
 525
 526         pci_write_config_dword(dev, itr_addr, new_itr);
 527
 528         return ide_config_drive_speed(drive, speed);
 529 }
 530
 531 static int hpt37x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 532 {
 533         ide_hwif_t *hwif        = HWIF(drive);
 534         struct pci_dev  *dev    = hwif->pci_dev;
 535         struct hpt_info *info   = ide_get_hwifdata (hwif);
 536         u8  speed               = hpt3xx_ratefilter(drive, xferspeed);
 537         u8  itr_addr            = 0x40 + (drive->dn * 4);
 538         u32 itr_mask            = (speed < XFER_MW_DMA_0) ? 0x303c0000 : 0xc0000000;
 539         u32 new_itr             = pci_bus_clock_list(speed, info->speed);
 540         u32 old_itr             = 0;
 541
 542         pci_read_config_dword(dev, itr_addr, &old_itr);
 543         new_itr = (new_itr & ~itr_mask) | (old_itr & itr_mask);
 544
 545         if (speed < XFER_MW_DMA_0)
 546                 new_itr &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 547         pci_write_config_dword(dev, itr_addr, new_itr);
 548
 549         return ide_config_drive_speed(drive, speed);
 550 }
 551
 552 static int hpt3xx_tune_chipset(ide_drive_t *drive, u8 speed)
 553 {
 554         ide_hwif_t *hwif        = HWIF(drive);
 555         struct hpt_info *info   = ide_get_hwifdata(hwif);
 556
 557         if (info->revision >= 3)
 558                 return hpt37x_tune_chipset(drive, speed);
 559         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 560                 return hpt36x_tune_chipset(drive, speed);
 561 }
 562
 563 static void hpt3xx_tune_drive(ide_drive_t *drive, u8 pio)
 564 {
 565         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 566         (void) hpt3xx_tune_chipset (drive, XFER_PIO_0 + pio);
 567 }
 568
 569 /*
 570  * This allows the configuration of ide_pci chipset registers
 571  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 572  * after the drive is reported by the OS.  Initially designed for
 573  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 574  *
 575  */
 576 static int config_chipset_for_dma(ide_drive_t *drive)
 577 {
 578         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 579         ide_hwif_t *hwif        = HWIF(drive);
 580         struct hpt_info *info   = ide_get_hwifdata(hwif);
 581
 582         if (!speed)
 583                 return 0;
 584
 585         /* If we don't have any timings we can't do a lot */
 586         if (info->speed == NULL)
 587                 return 0;
 588
 589         (void) hpt3xx_tune_chipset(drive, speed);
 590         return ide_dma_enable(drive);
 591 }
 592
 593 static int hpt3xx_quirkproc(ide_drive_t *drive)
 594 {
 595         struct hd_driveid *id   = drive->id;
 596         const  char **list      = quirk_drives;
 597
 598         while (*list)
 599                 if (strstr(id->model, *list++))
 600                         return 1;
 601         return 0;
 602 }
 603
 604 static void hpt3xx_intrproc(ide_drive_t *drive)
 605 {
 606         ide_hwif_t *hwif = HWIF(drive);
 607
 608         if (drive->quirk_list)
 609                 return;
 610         /* drives in the quirk_list may not like intr setups/cleanups */
 611         hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
 612 }
 613
 614 static void hpt3xx_maskproc(ide_drive_t *drive, int mask)
 615 {
 616         ide_hwif_t *hwif        = HWIF(drive);
 617         struct pci_dev  *dev    = hwif->pci_dev;
 618         struct hpt_info *info   = ide_get_hwifdata(hwif);
 619
 620         if (drive->quirk_list) {
 621                 if (info->revision >= 3) {
 622                         u8 scr1 = 0;
 623
 624                         pci_read_config_byte(dev, 0x5a, &scr1);
 625                         if (((scr1 & 0x10) >> 4) != mask) {
 626                                 if (mask)
 627                                         scr1 |=  0x10;
 628                                 else
 629                                         scr1 &= ~0x10;
 630                                 pci_write_config_byte(dev, 0x5a, scr1);
 631                         }
 632                 } else {
 633                         if (mask)
 634                                 disable_irq(hwif->irq);
 635                         else
 636                                 enable_irq (hwif->irq);
 637                 }
 638         } else
 639                 hwif->OUTB(mask ? (drive->ctl | 2) : (drive->ctl & ~2),
 640                            IDE_CONTROL_REG);
 641 }
 642
 643 static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
 644 {
 645         ide_hwif_t *hwif        = HWIF(drive);
 646         struct hd_driveid *id   = drive->id;
 647
 648         drive->init_speed = 0;
 649
 650         if ((id->capability & 1) && drive->autodma) {
 651                 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
 652                         return hwif->ide_dma_on(drive);
 653
 654                 goto fast_ata_pio;
 655
 656         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 657 fast_ata_pio:
 658                 hpt3xx_tune_drive(drive, 255);
 659                 return hwif->ide_dma_off_quietly(drive);
 660         }
 661         /* IORDY not supported */
 662         return 0;
 663 }
 664
 665 /*
 666  * This is specific to the HPT366 UDMA chipset
 667  * by HighPoint|Triones Technologies, Inc.
 668  */
 669 static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
 670 {
 671         struct pci_dev *dev = HWIF(drive)->pci_dev;
 672         u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
 673
 674         pci_read_config_byte(dev, 0x50, &mcr1);
 675         pci_read_config_byte(dev, 0x52, &mcr3);
 676         pci_read_config_byte(dev, 0x5a, &scr1);
 677         printk("%s: (%s)  mcr1=0x%02x, mcr3=0x%02x, scr1=0x%02x\n",
 678                 drive->name, __FUNCTION__, mcr1, mcr3, scr1);
 679         if (scr1 & 0x10)
 680                 pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
 681         return __ide_dma_lostirq(drive);
 682 }
 683
 684 static void hpt370_clear_engine(ide_drive_t *drive)
 685 {
 686         ide_hwif_t *hwif = HWIF(drive);
 687
 688         pci_write_config_byte(hwif->pci_dev, hwif->select_data, 0x37);
 689         udelay(10);
 690 }
 691
 692 static void hpt370_irq_timeout(ide_drive_t *drive)
 693 {
 694         ide_hwif_t *hwif        = HWIF(drive);
 695         u16 bfifo               = 0;
 696         u8  dma_cmd;
 697
 698         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 699         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo & 0x1ff);
 700
 701         /* get DMA command mode */
 702         dma_cmd = hwif->INB(hwif->dma_command);
 703         /* stop DMA */
 704         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 705         hpt370_clear_engine(drive);
 706 }
 707
 708 static void hpt370_ide_dma_start(ide_drive_t *drive)
 709 {
 710 #ifdef HPT_RESET_STATE_ENGINE
 711         hpt370_clear_engine(drive);
 712 #endif
 713         ide_dma_start(drive);
 714 }
 715
 716 static int hpt370_ide_dma_end(ide_drive_t *drive)
 717 {
 718         ide_hwif_t *hwif        = HWIF(drive);
 719         u8  dma_stat            = hwif->INB(hwif->dma_status);
 720
 721         if (dma_stat & 0x01) {
 722                 /* wait a little */
 723                 udelay(20);
 724                 dma_stat = hwif->INB(hwif->dma_status);
 725                 if (dma_stat & 0x01)
 726                         hpt370_irq_timeout(drive);
 727         }
 728         return __ide_dma_end(drive);
 729 }
 730
 731 static int hpt370_ide_dma_timeout(ide_drive_t *drive)
 732 {
 733         hpt370_irq_timeout(drive);
 734         return __ide_dma_timeout(drive);
 735 }
 736
 737 /* returns 1 if DMA IRQ issued, 0 otherwise */
 738 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 739 {
 740         ide_hwif_t *hwif        = HWIF(drive);
 741         u16 bfifo               = 0;
 742         u8  dma_stat;
 743
 744         pci_read_config_word(hwif->pci_dev, hwif->select_data + 2, &bfifo);
 745         if (bfifo & 0x1FF) {
 746 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 747                 return 0;
 748         }
 749
 750         dma_stat = hwif->INB(hwif->dma_status);
 751         /* return 1 if INTR asserted */
 752         if (dma_stat & 4)
 753                 return 1;
 754
 755         if (!drive->waiting_for_dma)
 756                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 757                                 drive->name, __FUNCTION__);
 758         return 0;
 759 }
 760
 761 static int hpt374_ide_dma_end(ide_drive_t *drive)
 762 {
 763         ide_hwif_t *hwif        = HWIF(drive);
 764         struct pci_dev  *dev    = hwif->pci_dev;
 765         u8 mcr  = 0, mcr_addr   = hwif->select_data;
 766         u8 bwsr = 0, mask       = hwif->channel ? 0x02 : 0x01;
 767
 768         pci_read_config_byte(dev, 0x6a, &bwsr);
 769         pci_read_config_byte(dev, mcr_addr, &mcr);
 770         if (bwsr & mask)
 771                 pci_write_config_byte(dev, mcr_addr, mcr | 0x30);
 772         return __ide_dma_end(drive);
 773 }
 774
 775 /**
 776  *      hpt3xxn_set_clock       -       perform clock switching dance
 777  *      @hwif: hwif to switch
 778  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 779  *
 780  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 781  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 782  *      doesn't physically exist anyway...
 783  */
 784
 785 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 786 {
 787         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 788
 789         if ((scr2 & 0x7f) == mode)
 790                 return;
 791
 792         /* MISC. control register 1 has the channel enable bit... */
 793         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 794
 795         /* Tristate the bus */
 796         if (mcr1 & 0x04)
 797                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 798         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 799
 800         /* Switch clock and reset channels */
 801         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 802         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 803
 804         /* Reset state machines */
 805         if (mcr1 & 0x04)
 806                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
 807         hwif->OUTB(0x37, hwif->dma_master + 0x74);
 808
 809         /* Complete reset */
 810         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 811
 812         /* Reconnect channels to bus */
 813         if (mcr1 & 0x04)
 814                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
 815         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 816 }
 817
 818 /**
 819  *      hpt3xxn_rw_disk         -       prepare for I/O
 820  *      @drive: drive for command
 821  *      @rq: block request structure
 822  *
 823  *      This is called when a disk I/O is issued to HPT3xxN.
 824  *      We need it because of the clock switching.
 825  */
 826
 827 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 828 {
 829         ide_hwif_t *hwif        = HWIF(drive);
 830         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
 831
 832         hpt3xxn_set_clock(hwif, wantclock);
 833 }
 834
 835 /*
 836  * Set/get power state for a drive.
 837  * NOTE: affects both drives on each channel.
 838  *
 839  * When we turn the power back on, we need to re-initialize things.
 840  */
 841 #define TRISTATE_BIT  0x8000
 842
 843 static int hpt3xx_busproc(ide_drive_t *drive, int state)
 844 {
 845         ide_hwif_t *hwif        = HWIF(drive);
 846         struct pci_dev *dev     = hwif->pci_dev;
 847         u8  mcr_addr            = hwif->select_data + 2;
 848         u8  resetmask           = hwif->channel ? 0x80 : 0x40;
 849         u8  bsr2                = 0;
 850         u16 mcr                 = 0;
 851
 852         hwif->bus_state = state;
 853
 854         /* Grab the status. */
 855         pci_read_config_word(dev, mcr_addr, &mcr);
 856         pci_read_config_byte(dev, 0x59, &bsr2);
 857
 858         /*
 859          * Set the state. We don't set it if we don't need to do so.
 860          * Make sure that the drive knows that it has failed if it's off.
 861          */
 862         switch (state) {
 863         case BUSSTATE_ON:
 864                 if (!(bsr2 & resetmask))
 865                         return 0;
 866                 hwif->drives[0].failures = hwif->drives[1].failures = 0;
 867
 868                 pci_write_config_byte(dev, 0x59, bsr2 & ~resetmask);
 869                 pci_write_config_word(dev, mcr_addr, mcr & ~TRISTATE_BIT);
 870                 return 0;
 871         case BUSSTATE_OFF:
 872                 if ((bsr2 & resetmask) && !(mcr & TRISTATE_BIT))
 873                         return 0;
 874                 mcr &= ~TRISTATE_BIT;
 875                 break;
 876         case BUSSTATE_TRISTATE:
 877                 if ((bsr2 & resetmask) &&  (mcr & TRISTATE_BIT))
 878                         return 0;
 879                 mcr |= TRISTATE_BIT;
 880                 break;
 881         default:
 882                 return -EINVAL;
 883         }
 884
 885         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 886         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 887
 888         pci_write_config_word(dev, mcr_addr, mcr);
 889         pci_write_config_byte(dev, 0x59, bsr2 | resetmask);
 890         return 0;
 891 }
 892
 893 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
 894 {
 895         u32 itr1        = 0;
 896         struct hpt_info *info = ide_get_hwifdata(hwif);
 897
 898         pci_read_config_dword(hwif->pci_dev, 0x40, &itr1);
 899
 900         /* detect bus speed by looking at control reg timing: */
 901         switch((itr1 >> 8) & 7) {
 902                 case 5:
 903                         info->speed = forty_base_hpt36x;
 904                         break;
 905                 case 9:
 906                         info->speed = twenty_five_base_hpt36x;
 907                         break;
 908                 case 7:
 909                 default:
 910                         info->speed = thirty_three_base_hpt36x;
 911                         break;
 912         }
 913 }
 914
 915 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
 916 {
 917         struct hpt_info *info   = ide_get_hwifdata(hwif);
 918         struct pci_dev  *dev    = hwif->pci_dev;
 919         char *name              = hwif->cds->name;
 920         int adjust, i;
 921         u16 freq = 0;
 922         u32 pll, temp = 0;
 923         u8  scr2 = 0, mcr1 = 0;
 924
 925         /*
 926          * default to pci clock. make sure MA15/16 are set to output
 927          * to prevent drives having problems with 40-pin cables. Needed
 928          * for some drives such as IBM-DTLA which will not enter ready
 929          * state on reset when PDIAG is a input.
 930          *
 931          * ToDo: should we set 0x21 when using PLL mode ?
 932          */
 933         pci_write_config_byte(dev, 0x5b, 0x23);
 934
 935         /*
 936          * We'll have to read f_CNT value in order to determine
 937          * the PCI clock frequency according to the following ratio:
 938          *
 939          * f_CNT = Fpci * 192 / Fdpll
 940          *
 941          * First try reading the register in which the HighPoint BIOS
 942          * saves f_CNT value before  reprogramming the DPLL from its
 943          * default setting (which differs for the various chips).
 944          * NOTE: This register is only accessible via I/O space.
 945          *
 946          * In case the signature check fails, we'll have to resort to
 947          * reading the f_CNT register itself in hopes that nobody has
 948          * touched the DPLL yet...
 949          */
 950         temp = inl(pci_resource_start(dev, 4) + 0x90);
 951         if ((temp & 0xFFFFF000) != 0xABCDE000) {
 952                 printk(KERN_WARNING "%s: no clock data saved by BIOS\n", name);
 953
 954                 /* Calculate the average value of f_CNT */
 955                 for (temp = i = 0; i < 128; i++) {
 956                         pci_read_config_word(dev, 0x78, &freq);
 957                         temp += freq & 0x1ff;
 958                         mdelay(1);
 959                 }
 960                 freq = temp / 128;
 961         } else
 962                 freq = temp & 0x1ff;
 963
 964         /*
 965          * HPT3xxN chips use different PCI clock information.
 966          * Currently we always set up the PLL for them.
 967          */
 968
 969         if (info->flags & IS_3xxN) {
 970                 if(freq < 0x55)
 971                         pll = F_LOW_PCI_33;
 972                 else if(freq < 0x70)
 973                         pll = F_LOW_PCI_40;
 974                 else if(freq < 0x7F)
 975                         pll = F_LOW_PCI_50;
 976                 else
 977                         pll = F_LOW_PCI_66;
 978
 979         } else {
 980                 if(freq < 0x9C)
 981                         pll = F_LOW_PCI_33;
 982                 else if(freq < 0xb0)
 983                         pll = F_LOW_PCI_40;
 984                 else if(freq <0xc8)
 985                         pll = F_LOW_PCI_50;
 986                 else
 987                         pll = F_LOW_PCI_66;
 988         }
 989         printk(KERN_INFO "%s: FREQ: %d, PLL: %d\n", name, freq, pll);
 990
 991         if (!(info->flags & IS_3xxN)) {
 992                 if (pll == F_LOW_PCI_33) {
 993                         info->speed = thirty_three_base_hpt37x;
 994                         printk(KERN_DEBUG "%s: using 33MHz PCI clock\n", name);
 995                 } else if (pll == F_LOW_PCI_40) {
 996                         /* Unsupported */
 997                 } else if (pll == F_LOW_PCI_50) {
 998                         info->speed = fifty_base_hpt37x;
 999                         printk(KERN_DEBUG "%s: using 50MHz PCI clock\n", name);
1000                 } else {
1001                         info->speed = sixty_six_base_hpt37x;
1002                         printk(KERN_DEBUG "%s: using 66MHz PCI clock\n", name);
1003                 }
1004         }
1005
1006         if (pll == F_LOW_PCI_66)
1007                 info->flags |= PCI_66MHZ;
1008
1009         /*
1010          * only try the pll if we don't have a table for the clock
1011          * speed that we're running at. NOTE: the internal PLL will
1012          * result in slow reads when using a 33MHz PCI clock. we also
1013          * don't like to use the PLL because it will cause glitches
1014          * on PRST/SRST when the HPT state engine gets reset.
1015          *
1016          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1017          * 372 device so we can get ATA133 support
1018          */
1019         if (info->speed)
1020                 goto init_hpt37X_done;
1021
1022         info->flags |= PLL_MODE;
1023
1024         /*
1025          * Adjust the PLL based upon the PCI clock, enable it, and
1026          * wait for stabilization...
1027          */
1028         adjust = 0;
1029         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1030         while (adjust++ < 6) {
1031                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1032                                        pll | 0x100);
1033
1034                 /* wait for clock stabilization */
1035                 for (i = 0; i < 0x50000; i++) {
1036                         pci_read_config_byte(dev, 0x5b, &scr2);
1037                         if (scr2 & 0x80) {
1038                                 /* spin looking for the clock to destabilize */
1039                                 for (i = 0; i < 0x1000; ++i) {
1040                                         pci_read_config_byte(dev, 0x5b,
1041                                                              &scr2);
1042                                         if ((scr2 & 0x80) == 0)
1043                                                 goto pll_recal;
1044                                 }
1045                                 pci_read_config_dword(dev, 0x5c, &pll);
1046                                 pci_write_config_dword(dev, 0x5c,
1047                                                        pll & ~0x100);
1048                                 pci_write_config_byte(dev, 0x5b, 0x21);
1049
1050                                 info->speed = fifty_base_hpt37x;
1051                                 printk("%s: using 50MHz internal PLL\n", name);
1052                                 goto init_hpt37X_done;
1053                         }
1054                 }
1055 pll_recal:
1056                 if (adjust & 1)
1057                         pll -= (adjust >> 1);
1058                 else
1059                         pll += (adjust >> 1);
1060         }
1061
1062 init_hpt37X_done:
1063         if (!info->speed)
1064                 printk(KERN_ERR "%s: unknown bus timing [%d %d].\n",
1065                        name, pll, freq);
1066         /*
1067          * Reset the state engines.
1068          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1069          */
1070         pci_read_config_byte(dev, 0x50, &mcr1);
1071         if (mcr1 & 0x04)
1072                 pci_write_config_byte(dev, 0x50, 0x37);
1073         pci_write_config_byte(dev, 0x54, 0x37);
1074         udelay(100);
1075 }
1076
1077 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1078 {
1079         /*
1080          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1081          * We don't seem to be using it.
1082          */
1083         if (dev->resource[PCI_ROM_RESOURCE].start)
1084                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1085                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1086
1087         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1088         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1089         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1090         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1091
1092         if (hpt_revision(dev) >= 3) {
1093                 u8 scr1 = 0;
1094
1095                 /* Interrupt force enable. */
1096                 pci_read_config_byte(dev, 0x5a, &scr1);
1097                 if (scr1 & 0x10)
1098                         pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
1099         }
1100
1101         return dev->irq;
1102 }
1103
1104 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1105 {
1106         struct pci_dev  *dev            = hwif->pci_dev;
1107         struct hpt_info *info           = ide_get_hwifdata(hwif);
1108         int serialize                   = HPT_SERIALIZE_IO;
1109         u8  scr1 = 0, ata66             = (hwif->channel) ? 0x01 : 0x02;
1110         u8  new_mcr, old_mcr            = 0;
1111
1112         /* Cache the channel's MISC. control registers' offset */
1113         hwif->select_data               = hwif->channel ? 0x54 : 0x50;
1114
1115         hwif->tuneproc                  = &hpt3xx_tune_drive;
1116         hwif->speedproc                 = &hpt3xx_tune_chipset;
1117         hwif->quirkproc                 = &hpt3xx_quirkproc;
1118         hwif->intrproc                  = &hpt3xx_intrproc;
1119         hwif->maskproc                  = &hpt3xx_maskproc;
1120         hwif->busproc                   = &hpt3xx_busproc;
1121
1122         /*
1123          * HPT3xxN chips have some complications:
1124          *
1125          * - on 33 MHz PCI we must clock switch
1126          * - on 66 MHz PCI we must NOT use the PCI clock
1127          */
1128         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1129                 /*
1130                  * Clock is shared between the channels,
1131                  * so we'll have to serialize them... :-(
1132                  */
1133                 serialize = 1;
1134                 hwif->rw_disk = &hpt3xxn_rw_disk;
1135         }
1136
1137         /* Serialize access to this device if needed */
1138         if (serialize && hwif->mate)
1139                 hwif->serialized = hwif->mate->serialized = 1;
1140
1141         /*
1142          * Disable the "fast interrupt" prediction.  Don't hold off
1143          * on interrupts. (== 0x01 despite what the docs say)
1144          */
1145         pci_read_config_byte(dev, hwif->select_data + 1, &old_mcr);
1146
1147         if (info->revision >= 5)                /* HPT372 and newer   */
1148                 new_mcr = old_mcr & ~0x07;
1149         else if (info->revision >= 3) {         /* HPT370 and HPT370A */
1150                 new_mcr = old_mcr;
1151                 new_mcr &= ~0x02;
1152
1153 #ifdef HPT_DELAY_INTERRUPT
1154                 new_mcr &= ~0x01;
1155 #else
1156                 new_mcr |=  0x01;
1157 #endif
1158         } else                                  /* HPT366 and HPT368  */
1159                 new_mcr = old_mcr & ~0x80;
1160
1161         if (new_mcr != old_mcr)
1162                 pci_write_config_byte(dev, hwif->select_data + 1, new_mcr);
1163
1164         if (!hwif->dma_base) {
1165                 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
1166                 return;
1167         }
1168
1169         hwif->ultra_mask = 0x7f;
1170         hwif->mwdma_mask = 0x07;
1171
1172         /*
1173          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1174          * address lines to access an external EEPROM.  To read valid
1175          * cable detect state the pins must be enabled as inputs.
1176          */
1177         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1178                 /*
1179                  * HPT374 PCI function 1
1180                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1181                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1182                  */
1183                 u8  mcr_addr = hwif->select_data + 2;
1184                 u16 mcr;
1185
1186                 pci_read_config_word (dev, mcr_addr, &mcr);
1187                 pci_write_config_word(dev, mcr_addr, (mcr | 0x8000));
1188                 /* now read cable id register */
1189                 pci_read_config_byte (dev, 0x5a, &scr1);
1190                 pci_write_config_word(dev, mcr_addr, mcr);
1191         } else if (info->revision >= 3) {
1192                 /*
1193                  * HPT370/372 and 374 pcifn 0
1194                  * - clear bit 0 of reg 0x5b to enable P/SCBLID as inputs
1195                  */
1196                 u8 scr2 = 0;
1197
1198                 pci_read_config_byte (dev, 0x5b, &scr2);
1199                 pci_write_config_byte(dev, 0x5b, (scr2 & ~1));
1200                 /* now read cable id register */
1201                 pci_read_config_byte (dev, 0x5a, &scr1);
1202                 pci_write_config_byte(dev, 0x5b,  scr2);
1203         } else
1204                 pci_read_config_byte (dev, 0x5a, &scr1);
1205
1206         if (!hwif->udma_four)
1207                 hwif->udma_four = (scr1 & ata66) ? 0 : 1;
1208
1209         hwif->ide_dma_check             = &hpt366_config_drive_xfer_rate;
1210
1211         if (info->revision >= 5) {
1212                 hwif->ide_dma_test_irq  = &hpt374_ide_dma_test_irq;
1213                 hwif->ide_dma_end       = &hpt374_ide_dma_end;
1214         } else if (info->revision >= 3) {
1215                 hwif->dma_start         = &hpt370_ide_dma_start;
1216                 hwif->ide_dma_end       = &hpt370_ide_dma_end;
1217                 hwif->ide_dma_timeout   = &hpt370_ide_dma_timeout;
1218         } else
1219                 hwif->ide_dma_lostirq   = &hpt366_ide_dma_lostirq;
1220
1221         if (!noautodma)
1222                 hwif->autodma = 1;
1223         hwif->drives[0].autodma = hwif->drives[1].autodma = hwif->autodma;
1224 }
1225
1226 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1227 {
1228         struct pci_dev  *dev            = hwif->pci_dev;
1229         struct hpt_info *info           = ide_get_hwifdata(hwif);
1230         u8 masterdma    = 0, slavedma   = 0;
1231         u8 dma_new      = 0, dma_old    = 0;
1232         unsigned long flags;
1233
1234         if (!dmabase)
1235                 return;
1236
1237         if(info->speed == NULL) {
1238                 printk(KERN_WARNING "%s: no known IDE timings, disabling DMA.\n",
1239                        hwif->cds->name);
1240                 return;
1241         }
1242
1243         dma_old = hwif->INB(dmabase + 2);
1244
1245         local_irq_save(flags);
1246
1247         dma_new = dma_old;
1248         pci_read_config_byte(dev, hwif->channel ? 0x4b : 0x43, &masterdma);
1249         pci_read_config_byte(dev, hwif->channel ? 0x4f : 0x47,  &slavedma);
1250
1251         if (masterdma & 0x30)   dma_new |= 0x20;
1252         if ( slavedma & 0x30)   dma_new |= 0x40;
1253         if (dma_new != dma_old)
1254                 hwif->OUTB(dma_new, dmabase + 2);
1255
1256         local_irq_restore(flags);
1257
1258         ide_setup_dma(hwif, dmabase, 8);
1259 }
1260
1261 /*
1262  *      We "borrow" this hook in order to set the data structures
1263  *      up early enough before dma or init_hwif calls are made.
1264  */
1265
1266 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1267 {
1268         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1269         struct pci_dev  *dev    = hwif->pci_dev;
1270         u16 did                 = dev->device;
1271         u8 mode, rid            = 0;
1272
1273         if(info == NULL) {
1274                 printk(KERN_WARNING "%s: out of memory.\n", hwif->cds->name);
1275                 return;
1276         }
1277         ide_set_hwifdata(hwif, info);
1278
1279         /* Avoid doing the same thing twice. */
1280         if (hwif->channel && hwif->mate) {
1281                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1282                 return;
1283         }
1284
1285         pci_read_config_byte(dev, PCI_REVISION_ID, &rid);
1286
1287         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1288             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1289               did == PCI_DEVICE_ID_TTI_HPT302  ||
1290               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1291               did == PCI_DEVICE_ID_TTI_HPT372N)
1292                 info->flags |= IS_3xxN;
1293
1294         rid = info->revision = hpt_revision(dev);
1295         if (rid >= 8)                   /* HPT374 */
1296                 mode = HPT374_ALLOW_ATA133_6 ? 4 : 3;
1297         else if (rid >= 7)              /* HPT371 and HPT371N */
1298                 mode = HPT371_ALLOW_ATA133_6 ? 4 : 3;
1299         else if (rid >= 6)              /* HPT302 and HPT302N */
1300                 mode = HPT302_ALLOW_ATA133_6 ? 4 : 3;
1301         else if (rid >= 5)              /* HPT372, HPT372A, and HPT372N */
1302                 mode = HPT372_ALLOW_ATA133_6 ? 4 : 3;
1303         else if (rid >= 3)              /* HPT370 and HPT370A */
1304                 mode = HPT370_ALLOW_ATA100_5 ? 3 : 2;
1305         else                            /* HPT366 and HPT368 */
1306                 mode = (HPT366_ALLOW_ATA66_4 || HPT366_ALLOW_ATA66_3) ? 2 : 1;
1307         info->max_mode = mode;
1308
1309         if (rid >= 3)
1310                 hpt37x_clocking(hwif);
1311         else
1312                 hpt366_clocking(hwif);
1313 }
1314
1315 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1316 {
1317         struct pci_dev *dev2;
1318
1319         if (PCI_FUNC(dev->devfn) & 1)
1320                 return -ENODEV;
1321
1322         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1323                 int ret;
1324
1325                 if (dev2->irq != dev->irq) {
1326                         /* FIXME: we need a core pci_set_interrupt() */
1327                         dev2->irq = dev->irq;
1328                         printk(KERN_WARNING "%s: PCI config space interrupt "
1329                                "fixed.\n", d->name);
1330                 }
1331                 ret = ide_setup_pci_devices(dev, dev2, d);
1332                 if (ret < 0)
1333                         pci_dev_put(dev2);
1334                 return ret;
1335         }
1336         return ide_setup_pci_device(dev, d);
1337 }
1338
1339 static int __devinit init_setup_hpt372n(struct pci_dev *dev, ide_pci_device_t *d)
1340 {
1341         return ide_setup_pci_device(dev, d);
1342 }
1343
1344 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1345 {
1346         u8 rev = 0, mcr1 = 0;
1347
1348         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1349
1350         if (rev > 1)
1351                 d->name = "HPT371N";
1352
1353         /*
1354          * HPT371 chips physically have only one channel, the secondary one,
1355          * but the primary channel registers do exist!  Go figure...
1356          * So,  we manually disable the non-existing channel here
1357          * (if the BIOS hasn't done this already).
1358          */
1359         pci_read_config_byte(dev, 0x50, &mcr1);
1360         if (mcr1 & 0x04)
1361                 pci_write_config_byte(dev, 0x50, mcr1 & ~0x04);
1362
1363         return ide_setup_pci_device(dev, d);
1364 }
1365
1366 static int __devinit init_setup_hpt372a(struct pci_dev *dev, ide_pci_device_t *d)
1367 {
1368         u8 rev = 0;
1369
1370         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1371
1372         if (rev > 1)
1373                 d->name = "HPT372N";
1374
1375         return ide_setup_pci_device(dev, d);
1376 }
1377
1378 static int __devinit init_setup_hpt302(struct pci_dev *dev, ide_pci_device_t *d)
1379 {
1380         u8 rev = 0;
1381
1382         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1383
1384         if (rev > 1)
1385                 d->name = "HPT302N";
1386
1387         return ide_setup_pci_device(dev, d);
1388 }
1389
1390 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1391 {
1392         struct pci_dev *dev2;
1393         u8 rev = 0;
1394         static char   *chipset_names[] = { "HPT366", "HPT366",  "HPT368",
1395                                            "HPT370", "HPT370A", "HPT372",
1396                                            "HPT372N" };
1397
1398         if (PCI_FUNC(dev->devfn) & 1)
1399                 return -ENODEV;
1400
1401         pci_read_config_byte(dev, PCI_REVISION_ID, &rev);
1402
1403         if (rev > 6)
1404                 rev = 6;
1405
1406         d->name = chipset_names[rev];
1407
1408         if (rev > 2)
1409                 goto init_single;
1410
1411         d->channels = 1;
1412
1413         if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
1414                 u8  pin1 = 0, pin2 = 0;
1415                 int ret;
1416
1417                 pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
1418                 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
1419                 if (pin1 != pin2 && dev->irq == dev2->irq) {
1420                         d->bootable = ON_BOARD;
1421                         printk("%s: onboard version of chipset, pin1=%d pin2=%d\n",
1422                                d->name, pin1, pin2);
1423                 }
1424                 ret = ide_setup_pci_devices(dev, dev2, d);
1425                 if (ret < 0)
1426                         pci_dev_put(dev2);
1427                 return ret;
1428         }
1429 init_single:
1430         return ide_setup_pci_device(dev, d);
1431 }
1432
1433 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1434         {       /* 0 */
1435                 .name           = "HPT366",
1436                 .init_setup     = init_setup_hpt366,
1437                 .init_chipset   = init_chipset_hpt366,
1438                 .init_iops      = init_iops_hpt366,
1439                 .init_hwif      = init_hwif_hpt366,
1440                 .init_dma       = init_dma_hpt366,
1441                 .channels       = 2,
1442                 .autodma        = AUTODMA,
1443                 .bootable       = OFF_BOARD,
1444                 .extra          = 240
1445         },{     /* 1 */
1446                 .name           = "HPT372A",
1447                 .init_setup     = init_setup_hpt372a,
1448                 .init_chipset   = init_chipset_hpt366,
1449                 .init_iops      = init_iops_hpt366,
1450                 .init_hwif      = init_hwif_hpt366,
1451                 .init_dma       = init_dma_hpt366,
1452                 .channels       = 2,
1453                 .autodma        = AUTODMA,
1454                 .bootable       = OFF_BOARD,
1455                 .extra          = 240
1456         },{     /* 2 */
1457                 .name           = "HPT302",
1458                 .init_setup     = init_setup_hpt302,
1459                 .init_chipset   = init_chipset_hpt366,
1460                 .init_iops      = init_iops_hpt366,
1461                 .init_hwif      = init_hwif_hpt366,
1462                 .init_dma       = init_dma_hpt366,
1463                 .channels       = 2,
1464                 .autodma        = AUTODMA,
1465                 .bootable       = OFF_BOARD,
1466                 .extra          = 240
1467         },{     /* 3 */
1468                 .name           = "HPT371",
1469                 .init_setup     = init_setup_hpt371,
1470                 .init_chipset   = init_chipset_hpt366,
1471                 .init_iops      = init_iops_hpt366,
1472                 .init_hwif      = init_hwif_hpt366,
1473                 .init_dma       = init_dma_hpt366,
1474                 .channels       = 2,
1475                 .autodma        = AUTODMA,
1476                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1477                 .bootable       = OFF_BOARD,
1478                 .extra          = 240
1479         },{     /* 4 */
1480                 .name           = "HPT374",
1481                 .init_setup     = init_setup_hpt374,
1482                 .init_chipset   = init_chipset_hpt366,
1483                 .init_iops      = init_iops_hpt366,
1484                 .init_hwif      = init_hwif_hpt366,
1485                 .init_dma       = init_dma_hpt366,
1486                 .channels       = 2,    /* 4 */
1487                 .autodma        = AUTODMA,
1488                 .bootable       = OFF_BOARD,
1489                 .extra          = 240
1490         },{     /* 5 */
1491                 .name           = "HPT372N",
1492                 .init_setup     = init_setup_hpt372n,
1493                 .init_chipset   = init_chipset_hpt366,
1494                 .init_iops      = init_iops_hpt366,
1495                 .init_hwif      = init_hwif_hpt366,
1496                 .init_dma       = init_dma_hpt366,
1497                 .channels       = 2,    /* 4 */
1498                 .autodma        = AUTODMA,
1499                 .bootable       = OFF_BOARD,
1500                 .extra          = 240
1501         }
1502 };
1503
1504 /**
1505  *      hpt366_init_one -       called when an HPT366 is found
1506  *      @dev: the hpt366 device
1507  *      @id: the matching pci id
1508  *
1509  *      Called when the PCI registration layer (or the IDE initialization)
1510  *      finds a device matching our IDE device tables.
1511  *
1512  *      NOTE: since we'll have to modify some fields of the ide_pci_device_t
1513  *      structure depending on the chip's revision, we'd better pass a local
1514  *      copy down the call chain...
1515  */
1516 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1517 {
1518         ide_pci_device_t d = hpt366_chipsets[id->driver_data];
1519
1520         return d.init_setup(dev, &d);
1521 }
1522
1523 static struct pci_device_id hpt366_pci_tbl[] = {
1524         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1525         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1526         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1527         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1528         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1529         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1530         { 0, },
1531 };
1532 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1533
1534 static struct pci_driver driver = {
1535         .name           = "HPT366_IDE",
1536         .id_table       = hpt366_pci_tbl,
1537         .probe          = hpt366_init_one,
1538 };
1539
1540 static int __init hpt366_ide_init(void)
1541 {
1542         return ide_pci_register_driver(&driver);
1543 }
1544
1545 module_init(hpt366_ide_init);
1546
1547 MODULE_AUTHOR("Andre Hedrick");
1548 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1549 MODULE_LICENSE("GPL");