drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
  66  *   allow for this speed anyway)
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  * - fix/remove bad/unused timing tables and use one set of tables for the whole
  71  *   HPT37x chip family; save space by introducing the separate transfer mode
  72  *   table in which the mode lookup is done
  73  *              <source@mvista.com>
  74  *
  75  */
  76
  77
  78 #include <linux/types.h>
  79 #include <linux/module.h>
  80 #include <linux/kernel.h>
  81 #include <linux/delay.h>
  82 #include <linux/timer.h>
  83 #include <linux/mm.h>
  84 #include <linux/ioport.h>
  85 #include <linux/blkdev.h>
  86 #include <linux/hdreg.h>
  87
  88 #include <linux/interrupt.h>
  89 #include <linux/pci.h>
  90 #include <linux/init.h>
  91 #include <linux/ide.h>
  92
  93 #include <asm/uaccess.h>
  94 #include <asm/io.h>
  95 #include <asm/irq.h>
  96
  97 /* various tuning parameters */
  98 #define HPT_RESET_STATE_ENGINE
  99 #undef  HPT_DELAY_INTERRUPT
 100 #define HPT_SERIALIZE_IO        0
 101
 102 static const char *quirk_drives[] = {
 103         "QUANTUM FIREBALLlct08 08",
 104         "QUANTUM FIREBALLP KA6.4",
 105         "QUANTUM FIREBALLP LM20.4",
 106         "QUANTUM FIREBALLP LM20.5",
 107         NULL
 108 };
 109
 110 static const char *bad_ata100_5[] = {
 111         "IBM-DTLA-307075",
 112         "IBM-DTLA-307060",
 113         "IBM-DTLA-307045",
 114         "IBM-DTLA-307030",
 115         "IBM-DTLA-307020",
 116         "IBM-DTLA-307015",
 117         "IBM-DTLA-305040",
 118         "IBM-DTLA-305030",
 119         "IBM-DTLA-305020",
 120         "IC35L010AVER07-0",
 121         "IC35L020AVER07-0",
 122         "IC35L030AVER07-0",
 123         "IC35L040AVER07-0",
 124         "IC35L060AVER07-0",
 125         "WDC AC310200R",
 126         NULL
 127 };
 128
 129 static const char *bad_ata66_4[] = {
 130         "IBM-DTLA-307075",
 131         "IBM-DTLA-307060",
 132         "IBM-DTLA-307045",
 133         "IBM-DTLA-307030",
 134         "IBM-DTLA-307020",
 135         "IBM-DTLA-307015",
 136         "IBM-DTLA-305040",
 137         "IBM-DTLA-305030",
 138         "IBM-DTLA-305020",
 139         "IC35L010AVER07-0",
 140         "IC35L020AVER07-0",
 141         "IC35L030AVER07-0",
 142         "IC35L040AVER07-0",
 143         "IC35L060AVER07-0",
 144         "WDC AC310200R",
 145         NULL
 146 };
 147
 148 static const char *bad_ata66_3[] = {
 149         "WDC AC310200R",
 150         NULL
 151 };
 152
 153 static const char *bad_ata33[] = {
 154         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 155         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 156         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 157         "Maxtor 90510D4",
 158         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 159         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 160         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 161         NULL
 162 };
 163
 164 static u8 xfer_speeds[] = {
 165         XFER_UDMA_6,
 166         XFER_UDMA_5,
 167         XFER_UDMA_4,
 168         XFER_UDMA_3,
 169         XFER_UDMA_2,
 170         XFER_UDMA_1,
 171         XFER_UDMA_0,
 172
 173         XFER_MW_DMA_2,
 174         XFER_MW_DMA_1,
 175         XFER_MW_DMA_0,
 176
 177         XFER_PIO_4,
 178         XFER_PIO_3,
 179         XFER_PIO_2,
 180         XFER_PIO_1,
 181         XFER_PIO_0
 182 };
 183
 184 /* Key for bus clock timings
 185  * 36x   37x
 186  * bits  bits
 187  * 0:3   0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 188  *              cycles = value + 1
 189  * 4:7   4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 190  *              cycles = value + 1
 191  * 8:11  9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 192  *              register access.
 193  * 12:15 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 194  *              register access.
 195  * 16:18 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 196  * -     21     CLK frequency: 0=ATA clock, 1=dual ATA clock.
 197  * 19:21 22:24  pre_high_time. Time to initialize the 1st cycle for PIO and
 198  *              MW DMA xfer.
 199  * 22:24 25:27  cmd_pre_high_time. Time to initialize the 1st PIO cycle for
 200  *              task file register access.
 201  * 28    28     UDMA enable.
 202  * 29    29     DMA  enable.
 203  * 30    30     PIO MST enable. If set, the chip is in bus master mode during
 204  *              PIO xfer.
 205  * 31    31     FIFO enable.
 206  */
 207
 208 static u32 forty_base_hpt36x[] = {
 209         /* XFER_UDMA_6 */       0x900fd943,
 210         /* XFER_UDMA_5 */       0x900fd943,
 211         /* XFER_UDMA_4 */       0x900fd943,
 212         /* XFER_UDMA_3 */       0x900ad943,
 213         /* XFER_UDMA_2 */       0x900bd943,
 214         /* XFER_UDMA_1 */       0x9008d943,
 215         /* XFER_UDMA_0 */       0x9008d943,
 216
 217         /* XFER_MW_DMA_2 */     0xa008d943,
 218         /* XFER_MW_DMA_1 */     0xa010d955,
 219         /* XFER_MW_DMA_0 */     0xa010d9fc,
 220
 221         /* XFER_PIO_4 */        0xc008d963,
 222         /* XFER_PIO_3 */        0xc010d974,
 223         /* XFER_PIO_2 */        0xc010d997,
 224         /* XFER_PIO_1 */        0xc010d9c7,
 225         /* XFER_PIO_0 */        0xc018d9d9
 226 };
 227
 228 static u32 thirty_three_base_hpt36x[] = {
 229         /* XFER_UDMA_6 */       0x90c9a731,
 230         /* XFER_UDMA_5 */       0x90c9a731,
 231         /* XFER_UDMA_4 */       0x90c9a731,
 232         /* XFER_UDMA_3 */       0x90cfa731,
 233         /* XFER_UDMA_2 */       0x90caa731,
 234         /* XFER_UDMA_1 */       0x90cba731,
 235         /* XFER_UDMA_0 */       0x90c8a731,
 236
 237         /* XFER_MW_DMA_2 */     0xa0c8a731,
 238         /* XFER_MW_DMA_1 */     0xa0c8a732,     /* 0xa0c8a733 */
 239         /* XFER_MW_DMA_0 */     0xa0c8a797,
 240
 241         /* XFER_PIO_4 */        0xc0c8a731,
 242         /* XFER_PIO_3 */        0xc0c8a742,
 243         /* XFER_PIO_2 */        0xc0d0a753,
 244         /* XFER_PIO_1 */        0xc0d0a7a3,     /* 0xc0d0a793 */
 245         /* XFER_PIO_0 */        0xc0d0a7aa      /* 0xc0d0a7a7 */
 246 };
 247
 248 static u32 twenty_five_base_hpt36x[] = {
 249         /* XFER_UDMA_6 */       0x90c98521,
 250         /* XFER_UDMA_5 */       0x90c98521,
 251         /* XFER_UDMA_4 */       0x90c98521,
 252         /* XFER_UDMA_3 */       0x90cf8521,
 253         /* XFER_UDMA_2 */       0x90cf8521,
 254         /* XFER_UDMA_1 */       0x90cb8521,
 255         /* XFER_UDMA_0 */       0x90cb8521,
 256
 257         /* XFER_MW_DMA_2 */     0xa0ca8521,
 258         /* XFER_MW_DMA_1 */     0xa0ca8532,
 259         /* XFER_MW_DMA_0 */     0xa0ca8575,
 260
 261         /* XFER_PIO_4 */        0xc0ca8521,
 262         /* XFER_PIO_3 */        0xc0ca8532,
 263         /* XFER_PIO_2 */        0xc0ca8542,
 264         /* XFER_PIO_1 */        0xc0d08572,
 265         /* XFER_PIO_0 */        0xc0d08585
 266 };
 267
 268 static u32 thirty_three_base_hpt37x[] = {
 269         /* XFER_UDMA_6 */       0x12446231,     /* 0x12646231 ?? */
 270         /* XFER_UDMA_5 */       0x12446231,
 271         /* XFER_UDMA_4 */       0x12446231,
 272         /* XFER_UDMA_3 */       0x126c6231,
 273         /* XFER_UDMA_2 */       0x12486231,
 274         /* XFER_UDMA_1 */       0x124c6233,
 275         /* XFER_UDMA_0 */       0x12506297,
 276
 277         /* XFER_MW_DMA_2 */     0x22406c31,
 278         /* XFER_MW_DMA_1 */     0x22406c33,
 279         /* XFER_MW_DMA_0 */     0x22406c97,
 280
 281         /* XFER_PIO_4 */        0x06414e31,
 282         /* XFER_PIO_3 */        0x06414e42,
 283         /* XFER_PIO_2 */        0x06414e53,
 284         /* XFER_PIO_1 */        0x06814e93,
 285         /* XFER_PIO_0 */        0x06814ea7
 286 };
 287
 288 static u32 fifty_base_hpt37x[] = {
 289         /* XFER_UDMA_6 */       0x12848242,
 290         /* XFER_UDMA_5 */       0x12848242,
 291         /* XFER_UDMA_4 */       0x12ac8242,
 292         /* XFER_UDMA_3 */       0x128c8242,
 293         /* XFER_UDMA_2 */       0x120c8242,
 294         /* XFER_UDMA_1 */       0x12148254,
 295         /* XFER_UDMA_0 */       0x121882ea,
 296
 297         /* XFER_MW_DMA_2 */     0x22808242,
 298         /* XFER_MW_DMA_1 */     0x22808254,
 299         /* XFER_MW_DMA_0 */     0x228082ea,
 300
 301         /* XFER_PIO_4 */        0x0a81f442,
 302         /* XFER_PIO_3 */        0x0a81f443,
 303         /* XFER_PIO_2 */        0x0a81f454,
 304         /* XFER_PIO_1 */        0x0ac1f465,
 305         /* XFER_PIO_0 */        0x0ac1f48a
 306 };
 307
 308 static u32 sixty_six_base_hpt37x[] = {
 309         /* XFER_UDMA_6 */       0x1c869c62,
 310         /* XFER_UDMA_5 */       0x1cae9c62,     /* 0x1c8a9c62 */
 311         /* XFER_UDMA_4 */       0x1c8a9c62,
 312         /* XFER_UDMA_3 */       0x1c8e9c62,
 313         /* XFER_UDMA_2 */       0x1c929c62,
 314         /* XFER_UDMA_1 */       0x1c9a9c62,
 315         /* XFER_UDMA_0 */       0x1c829c62,
 316
 317         /* XFER_MW_DMA_2 */     0x2c829c62,
 318         /* XFER_MW_DMA_1 */     0x2c829c66,
 319         /* XFER_MW_DMA_0 */     0x2c829d2e,
 320
 321         /* XFER_PIO_4 */        0x0c829c62,
 322         /* XFER_PIO_3 */        0x0c829c84,
 323         /* XFER_PIO_2 */        0x0c829ca6,
 324         /* XFER_PIO_1 */        0x0d029d26,
 325         /* XFER_PIO_0 */        0x0d029d5e
 326 };
 327
 328 #define HPT366_DEBUG_DRIVE_INFO         0
 329 #define HPT374_ALLOW_ATA133_6           0
 330 #define HPT371_ALLOW_ATA133_6           0
 331 #define HPT302_ALLOW_ATA133_6           0
 332 #define HPT372_ALLOW_ATA133_6           0
 333 #define HPT370_ALLOW_ATA100_5           1
 334 #define HPT366_ALLOW_ATA66_4            1
 335 #define HPT366_ALLOW_ATA66_3            1
 336 #define HPT366_MAX_DEVS                 8
 337
 338 #define F_LOW_PCI_33    0x23
 339 #define F_LOW_PCI_40    0x29
 340 #define F_LOW_PCI_50    0x2d
 341 #define F_LOW_PCI_66    0x42
 342
 343 /*
 344  *      Hold all the highpoint quirks and revision information in one
 345  *      place.
 346  */
 347
 348 struct hpt_info
 349 {
 350         u8 max_mode;            /* Speeds allowed */
 351         int revision;           /* Chipset revision */
 352         int flags;              /* Chipset properties */
 353 #define PLL_MODE        1
 354 #define IS_3xxN         2
 355 #define PCI_66MHZ       4
 356                                 /* Speed table */
 357         u32 *speed;
 358 };
 359
 360 /*
 361  *      This wants fixing so that we do everything not by classrev
 362  *      (which breaks on the newest chips) but by creating an
 363  *      enumeration of chip variants and using that
 364  */
 365
 366 static __devinit u32 hpt_revision (struct pci_dev *dev)
 367 {
 368         u32 class_rev;
 369         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 370         class_rev &= 0xff;
 371
 372         switch(dev->device) {
 373                 /* Remap new 372N onto 372 */
 374                 case PCI_DEVICE_ID_TTI_HPT372N:
 375                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 376                 case PCI_DEVICE_ID_TTI_HPT374:
 377                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 378                 case PCI_DEVICE_ID_TTI_HPT371:
 379                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 380                 case PCI_DEVICE_ID_TTI_HPT302:
 381                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 382                 case PCI_DEVICE_ID_TTI_HPT372:
 383                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 384                 default:
 385                         break;
 386         }
 387         return class_rev;
 388 }
 389
 390 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 391
 392 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 393 {
 394         ide_hwif_t *hwif        = drive->hwif;
 395         struct hpt_info *info   = ide_get_hwifdata(hwif);
 396         u8 mode                 = 0;
 397
 398         /* FIXME: TODO - move this to set info->mode once at boot */
 399
 400         if (info->revision >= 8) {              /* HPT374 */
 401                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 402         } else if (info->revision >= 7) {       /* HPT371 */
 403                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 404         } else if (info->revision >= 6) {       /* HPT302 */
 405                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 406         } else if (info->revision >= 5) {       /* HPT372 */
 407                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 408         } else if (info->revision >= 4) {       /* HPT370A */
 409                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 410         } else if (info->revision >= 3) {       /* HPT370 */
 411                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 412                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 413         } else {                                /* HPT366 and HPT368 */
 414                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 415         }
 416         if (!eighty_ninty_three(drive) && mode)
 417                 mode = min(mode, (u8)1);
 418         return mode;
 419 }
 420
 421 /*
 422  *      Note for the future; the SATA hpt37x we must set
 423  *      either PIO or UDMA modes 0,4,5
 424  */
 425
 426 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 427 {
 428         ide_hwif_t *hwif        = drive->hwif;
 429         struct hpt_info *info   = ide_get_hwifdata(hwif);
 430         u8 mode                 = hpt3xx_ratemask(drive);
 431
 432         if (drive->media != ide_disk)
 433                 return min(speed, (u8)XFER_PIO_4);
 434
 435         switch(mode) {
 436                 case 0x04:
 437                         speed = min(speed, (u8)XFER_UDMA_6);
 438                         break;
 439                 case 0x03:
 440                         speed = min(speed, (u8)XFER_UDMA_5);
 441                         if (info->revision >= 5)
 442                                 break;
 443                         if (check_in_drive_lists(drive, bad_ata100_5))
 444                                 speed = min(speed, (u8)XFER_UDMA_4);
 445                         break;
 446                 case 0x02:
 447                         speed = min(speed, (u8)XFER_UDMA_4);
 448         /*
 449          * CHECK ME, Does this need to be set to 5 ??
 450          */
 451                         if (info->revision >= 3)
 452                                 break;
 453                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 454                             (!(HPT366_ALLOW_ATA66_4)))
 455                                 speed = min(speed, (u8)XFER_UDMA_3);
 456                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 457                             (!(HPT366_ALLOW_ATA66_3)))
 458                                 speed = min(speed, (u8)XFER_UDMA_2);
 459                         break;
 460                 case 0x01:
 461                         speed = min(speed, (u8)XFER_UDMA_2);
 462         /*
 463          * CHECK ME, Does this need to be set to 5 ??
 464          */
 465                         if (info->revision >= 3)
 466                                 break;
 467                         if (check_in_drive_lists(drive, bad_ata33))
 468                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 469                         break;
 470                 case 0x00:
 471                 default:
 472                         speed = min(speed, (u8)XFER_MW_DMA_2);
 473                         break;
 474         }
 475         return speed;
 476 }
 477
 478 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 479 {
 480         struct hd_driveid *id = drive->id;
 481
 482         if (quirk_drives == list) {
 483                 while (*list)
 484                         if (strstr(id->model, *list++))
 485                                 return 1;
 486         } else {
 487                 while (*list)
 488                         if (!strcmp(*list++,id->model))
 489                                 return 1;
 490         }
 491         return 0;
 492 }
 493
 494 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
 495 {
 496         int i;
 497
 498         /*
 499          * Lookup the transfer mode table to get the index into
 500          * the timing table.
 501          *
 502          * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
 503          */
 504         for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
 505                 if (xfer_speeds[i] == speed)
 506                         break;
 507         return chipset_table[i];
 508 }
 509
 510 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 511 {
 512         ide_hwif_t *hwif        = drive->hwif;
 513         struct pci_dev *dev     = hwif->pci_dev;
 514         struct hpt_info *info   = ide_get_hwifdata(hwif);
 515         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 516         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 517         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
 518         u8 drive_fast           = 0;
 519         u32 reg1 = 0, reg2      = 0;
 520
 521         /*
 522          * Disable the "fast interrupt" prediction.
 523          */
 524         pci_read_config_byte(dev, regfast, &drive_fast);
 525         if (drive_fast & 0x80)
 526                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 527
 528         reg2 = pci_bus_clock_list(speed, info->speed);
 529
 530         /*
 531          * Disable on-chip PIO FIFO/buffer
 532          *  (to avoid problems handling I/O errors later)
 533          */
 534         pci_read_config_dword(dev, regtime, &reg1);
 535         if (speed >= XFER_MW_DMA_0) {
 536                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 537         } else {
 538                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 539         }
 540         reg2 &= ~0x80000000;
 541
 542         pci_write_config_dword(dev, regtime, reg2);
 543
 544         return ide_config_drive_speed(drive, speed);
 545 }
 546
 547 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 548 {
 549         ide_hwif_t *hwif        = drive->hwif;
 550         struct pci_dev *dev = hwif->pci_dev;
 551         struct hpt_info *info   = ide_get_hwifdata(hwif);
 552         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 553         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 554         u8 drive_pci    = 0x40 + (drive->dn * 4);
 555         u8 new_fast     = 0, drive_fast = 0;
 556         u32 list_conf   = 0, drive_conf = 0;
 557         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 558
 559         /*
 560          * Disable the "fast interrupt" prediction.
 561          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 562          */
 563         pci_read_config_byte(dev, regfast, &drive_fast);
 564         new_fast = drive_fast;
 565         if (new_fast & 0x02)
 566                 new_fast &= ~0x02;
 567
 568 #ifdef HPT_DELAY_INTERRUPT
 569         if (new_fast & 0x01)
 570                 new_fast &= ~0x01;
 571 #else
 572         if ((new_fast & 0x01) == 0)
 573                 new_fast |= 0x01;
 574 #endif
 575         if (new_fast != drive_fast)
 576                 pci_write_config_byte(dev, regfast, new_fast);
 577
 578         list_conf = pci_bus_clock_list(speed, info->speed);
 579
 580         pci_read_config_dword(dev, drive_pci, &drive_conf);
 581         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 582
 583         if (speed < XFER_MW_DMA_0)
 584                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 585         pci_write_config_dword(dev, drive_pci, list_conf);
 586
 587         return ide_config_drive_speed(drive, speed);
 588 }
 589
 590 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 591 {
 592         ide_hwif_t *hwif        = drive->hwif;
 593         struct pci_dev *dev     = hwif->pci_dev;
 594         struct hpt_info *info   = ide_get_hwifdata(hwif);
 595         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 596         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 597         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 598         u32 list_conf   = 0, drive_conf = 0;
 599         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 600
 601         /*
 602          * Disable the "fast interrupt" prediction.
 603          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 604          */
 605         pci_read_config_byte(dev, regfast, &drive_fast);
 606         drive_fast &= ~0x07;
 607         pci_write_config_byte(dev, regfast, drive_fast);
 608
 609         list_conf = pci_bus_clock_list(speed, info->speed);
 610         pci_read_config_dword(dev, drive_pci, &drive_conf);
 611         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 612         if (speed < XFER_MW_DMA_0)
 613                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 614         pci_write_config_dword(dev, drive_pci, list_conf);
 615
 616         return ide_config_drive_speed(drive, speed);
 617 }
 618
 619 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 620 {
 621         ide_hwif_t *hwif        = drive->hwif;
 622         struct hpt_info *info   = ide_get_hwifdata(hwif);
 623
 624         if (info->revision >= 8)
 625                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 626         else if (info->revision >= 5)
 627                 return hpt372_tune_chipset(drive, speed);
 628         else if (info->revision >= 3)
 629                 return hpt370_tune_chipset(drive, speed);
 630         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 631                 return hpt36x_tune_chipset(drive, speed);
 632 }
 633
 634 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 635 {
 636         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 637         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 638 }
 639
 640 /*
 641  * This allows the configuration of ide_pci chipset registers
 642  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 643  * after the drive is reported by the OS.  Initially for designed for
 644  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 645  *
 646  * check_in_drive_lists(drive, bad_ata66_4)
 647  * check_in_drive_lists(drive, bad_ata66_3)
 648  * check_in_drive_lists(drive, bad_ata33)
 649  *
 650  */
 651 static int config_chipset_for_dma (ide_drive_t *drive)
 652 {
 653         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 654         ide_hwif_t *hwif = drive->hwif;
 655         struct hpt_info *info   = ide_get_hwifdata(hwif);
 656
 657         if (!speed)
 658                 return 0;
 659
 660         /* If we don't have any timings we can't do a lot */
 661         if (info->speed == NULL)
 662                 return 0;
 663
 664         (void) hpt3xx_tune_chipset(drive, speed);
 665         return ide_dma_enable(drive);
 666 }
 667
 668 static int hpt3xx_quirkproc (ide_drive_t *drive)
 669 {
 670         return ((int) check_in_drive_lists(drive, quirk_drives));
 671 }
 672
 673 static void hpt3xx_intrproc (ide_drive_t *drive)
 674 {
 675         ide_hwif_t *hwif = drive->hwif;
 676
 677         if (drive->quirk_list)
 678                 return;
 679         /* drives in the quirk_list may not like intr setups/cleanups */
 680         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 681 }
 682
 683 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 684 {
 685         ide_hwif_t *hwif = drive->hwif;
 686         struct hpt_info *info = ide_get_hwifdata(hwif);
 687         struct pci_dev *dev = hwif->pci_dev;
 688
 689         if (drive->quirk_list) {
 690                 if (info->revision >= 3) {
 691                         u8 reg5a = 0;
 692                         pci_read_config_byte(dev, 0x5a, &reg5a);
 693                         if (((reg5a & 0x10) >> 4) != mask)
 694                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 695                 } else {
 696                         if (mask) {
 697                                 disable_irq(hwif->irq);
 698                         } else {
 699                                 enable_irq(hwif->irq);
 700                         }
 701                 }
 702         } else {
 703                 if (IDE_CONTROL_REG)
 704                         hwif->OUTB(mask ? (drive->ctl | 2) :
 705                                                  (drive->ctl & ~2),
 706                                                  IDE_CONTROL_REG);
 707         }
 708 }
 709
 710 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 711 {
 712         ide_hwif_t *hwif        = drive->hwif;
 713         struct hd_driveid *id   = drive->id;
 714
 715         drive->init_speed = 0;
 716
 717         if ((id->capability & 1) && drive->autodma) {
 718
 719                 if (ide_use_dma(drive)) {
 720                         if (config_chipset_for_dma(drive))
 721                                 return hwif->ide_dma_on(drive);
 722                 }
 723
 724                 goto fast_ata_pio;
 725
 726         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 727 fast_ata_pio:
 728                 hpt3xx_tune_drive(drive, 5);
 729                 return hwif->ide_dma_off_quietly(drive);
 730         }
 731         /* IORDY not supported */
 732         return 0;
 733 }
 734
 735 /*
 736  * This is specific to the HPT366 UDMA bios chipset
 737  * by HighPoint|Triones Technologies, Inc.
 738  */
 739 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 740 {
 741         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 742         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 743
 744         pci_read_config_byte(dev, 0x50, &reg50h);
 745         pci_read_config_byte(dev, 0x52, &reg52h);
 746         pci_read_config_byte(dev, 0x5a, &reg5ah);
 747         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 748                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 749         if (reg5ah & 0x10)
 750                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 751         return __ide_dma_lostirq(drive);
 752 }
 753
 754 static void hpt370_clear_engine (ide_drive_t *drive)
 755 {
 756         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 757         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 758         udelay(10);
 759 }
 760
 761 static void hpt370_ide_dma_start(ide_drive_t *drive)
 762 {
 763 #ifdef HPT_RESET_STATE_ENGINE
 764         hpt370_clear_engine(drive);
 765 #endif
 766         ide_dma_start(drive);
 767 }
 768
 769 static int hpt370_ide_dma_end (ide_drive_t *drive)
 770 {
 771         ide_hwif_t *hwif        = HWIF(drive);
 772         u8 dma_stat             = hwif->INB(hwif->dma_status);
 773
 774         if (dma_stat & 0x01) {
 775                 /* wait a little */
 776                 udelay(20);
 777                 dma_stat = hwif->INB(hwif->dma_status);
 778         }
 779         if ((dma_stat & 0x01) != 0)
 780                 /* fallthrough */
 781                 (void) HWIF(drive)->ide_dma_timeout(drive);
 782
 783         return __ide_dma_end(drive);
 784 }
 785
 786 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 787 {
 788         ide_hwif_t *hwif        = HWIF(drive);
 789         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 790         u8 dma_stat = 0, dma_cmd = 0;
 791
 792         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 793         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 794         hpt370_clear_engine(drive);
 795         /* get dma command mode */
 796         dma_cmd = hwif->INB(hwif->dma_command);
 797         /* stop dma */
 798         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 799         dma_stat = hwif->INB(hwif->dma_status);
 800         /* clear errors */
 801         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 802 }
 803
 804 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 805 {
 806         hpt370_lostirq_timeout(drive);
 807         hpt370_clear_engine(drive);
 808         return __ide_dma_timeout(drive);
 809 }
 810
 811 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 812 {
 813         hpt370_lostirq_timeout(drive);
 814         hpt370_clear_engine(drive);
 815         return __ide_dma_lostirq(drive);
 816 }
 817
 818 /* returns 1 if DMA IRQ issued, 0 otherwise */
 819 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 820 {
 821         ide_hwif_t *hwif        = HWIF(drive);
 822         u16 bfifo               = 0;
 823         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 824         u8 dma_stat;
 825
 826         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 827         if (bfifo & 0x1FF) {
 828 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 829                 return 0;
 830         }
 831
 832         dma_stat = hwif->INB(hwif->dma_status);
 833         /* return 1 if INTR asserted */
 834         if ((dma_stat & 4) == 4)
 835                 return 1;
 836
 837         if (!drive->waiting_for_dma)
 838                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 839                                 drive->name, __FUNCTION__);
 840         return 0;
 841 }
 842
 843 static int hpt374_ide_dma_end (ide_drive_t *drive)
 844 {
 845         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 846         ide_hwif_t *hwif        = HWIF(drive);
 847         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 848         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 849
 850         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 851         pci_read_config_byte(dev, mscreg, &msc_stat);
 852         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 853                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 854         return __ide_dma_end(drive);
 855 }
 856
 857 /**
 858  *      hpt3xxn_set_clock       -       perform clock switching dance
 859  *      @hwif: hwif to switch
 860  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 861  *
 862  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 863  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 864  *      doesn't physically exist anyway...
 865  */
 866
 867 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 868 {
 869         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 870
 871         if ((scr2 & 0x7f) == mode)
 872                 return;
 873
 874         /* MISC. control register 1 has the channel enable bit... */
 875         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 876
 877         /* Tristate the bus */
 878         if (mcr1 & 0x04)
 879                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 880         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 881
 882         /* Switch clock and reset channels */
 883         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 884         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 885
 886         /* Reset state machines */
 887         if (mcr1 & 0x04)
 888                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
 889         hwif->OUTB(0x37, hwif->dma_master + 0x74);
 890
 891         /* Complete reset */
 892         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 893
 894         /* Reconnect channels to bus */
 895         if (mcr1 & 0x04)
 896                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
 897         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 898 }
 899
 900 /**
 901  *      hpt3xxn_rw_disk         -       prepare for I/O
 902  *      @drive: drive for command
 903  *      @rq: block request structure
 904  *
 905  *      This is called when a disk I/O is issued to HPT3xxN.
 906  *      We need it because of the clock switching.
 907  */
 908
 909 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 910 {
 911         ide_hwif_t *hwif        = HWIF(drive);
 912         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
 913
 914         hpt3xxn_set_clock(hwif, wantclock);
 915 }
 916
 917 /*
 918  * Since SUN Cobalt is attempting to do this operation, I should disclose
 919  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 920  * HOTSWAP ATA Infrastructure.
 921  */
 922
 923 static void hpt3xx_reset (ide_drive_t *drive)
 924 {
 925 }
 926
 927 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 928 {
 929         ide_hwif_t *hwif        = HWIF(drive);
 930         struct pci_dev *dev     = hwif->pci_dev;
 931         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 932         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 933
 934         pci_read_config_byte(dev, 0x59, &reg59h);
 935         pci_read_config_byte(dev, state_reg, &regXXh);
 936
 937         if (state) {
 938                 (void) ide_do_reset(drive);
 939                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 940                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 941         } else {
 942                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 943                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 944                 (void) ide_do_reset(drive);
 945         }
 946         return 0;
 947 }
 948
 949 /*
 950  * set/get power state for a drive.
 951  * turning the power off does the following things:
 952  *   1) soft-reset the drive
 953  *   2) tri-states the ide bus
 954  *
 955  * when we turn things back on, we need to re-initialize things.
 956  */
 957 #define TRISTATE_BIT  0x8000
 958 static int hpt370_busproc(ide_drive_t * drive, int state)
 959 {
 960         ide_hwif_t *hwif        = drive->hwif;
 961         struct pci_dev *dev     = hwif->pci_dev;
 962         u8 tristate = 0, resetmask = 0, bus_reg = 0;
 963         u16 tri_reg;
 964
 965         hwif->bus_state = state;
 966
 967         if (hwif->channel) {
 968                 /* secondary channel */
 969                 tristate = 0x56;
 970                 resetmask = 0x80;
 971         } else {
 972                 /* primary channel */
 973                 tristate = 0x52;
 974                 resetmask = 0x40;
 975         }
 976
 977         /* grab status */
 978         pci_read_config_word(dev, tristate, &tri_reg);
 979         pci_read_config_byte(dev, 0x59, &bus_reg);
 980
 981         /* set the state. we don't set it if we don't need to do so.
 982          * make sure that the drive knows that it has failed if it's off */
 983         switch (state) {
 984         case BUSSTATE_ON:
 985                 hwif->drives[0].failures = 0;
 986                 hwif->drives[1].failures = 0;
 987                 if ((bus_reg & resetmask) == 0)
 988                         return 0;
 989                 tri_reg &= ~TRISTATE_BIT;
 990                 bus_reg &= ~resetmask;
 991                 break;
 992         case BUSSTATE_OFF:
 993                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 994                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 995                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
 996                         return 0;
 997                 tri_reg &= ~TRISTATE_BIT;
 998                 bus_reg |= resetmask;
 999                 break;
1000         case BUSSTATE_TRISTATE:
1001                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1002                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1003                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1004                         return 0;
1005                 tri_reg |= TRISTATE_BIT;
1006                 bus_reg |= resetmask;
1007                 break;
1008         }
1009         pci_write_config_byte(dev, 0x59, bus_reg);
1010         pci_write_config_word(dev, tristate, tri_reg);
1011
1012         return 0;
1013 }
1014
1015 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1016 {
1017         u32 reg1        = 0;
1018         struct hpt_info *info = ide_get_hwifdata(hwif);
1019
1020         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
1021
1022         /* detect bus speed by looking at control reg timing: */
1023         switch((reg1 >> 8) & 7) {
1024                 case 5:
1025                         info->speed = forty_base_hpt36x;
1026                         break;
1027                 case 9:
1028                         info->speed = twenty_five_base_hpt36x;
1029                         break;
1030                 case 7:
1031                 default:
1032                         info->speed = thirty_three_base_hpt36x;
1033                         break;
1034         }
1035 }
1036
1037 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1038 {
1039         struct hpt_info *info = ide_get_hwifdata(hwif);
1040         struct pci_dev *dev = hwif->pci_dev;
1041         int adjust, i;
1042         u16 freq;
1043         u32 pll;
1044         u8 reg5bh = 0, mcr1 = 0;
1045
1046         /*
1047          * default to pci clock. make sure MA15/16 are set to output
1048          * to prevent drives having problems with 40-pin cables. Needed
1049          * for some drives such as IBM-DTLA which will not enter ready
1050          * state on reset when PDIAG is a input.
1051          *
1052          * ToDo: should we set 0x21 when using PLL mode ?
1053          */
1054         pci_write_config_byte(dev, 0x5b, 0x23);
1055
1056         /*
1057          * set up the PLL. we need to adjust it so that it's stable.
1058          * freq = Tpll * 192 / Tpci
1059          *
1060          * Todo. For non x86 should probably check the dword is
1061          * set to 0xABCDExxx indicating the BIOS saved f_CNT
1062          */
1063         pci_read_config_word(dev, 0x78, &freq);
1064         freq &= 0x1FF;
1065
1066         /*
1067          * HPT3xxN chips use different PCI clock information.
1068          * Currently we always set up the PLL for them.
1069          */
1070
1071         if (info->flags & IS_3xxN) {
1072                 if(freq < 0x55)
1073                         pll = F_LOW_PCI_33;
1074                 else if(freq < 0x70)
1075                         pll = F_LOW_PCI_40;
1076                 else if(freq < 0x7F)
1077                         pll = F_LOW_PCI_50;
1078                 else
1079                         pll = F_LOW_PCI_66;
1080
1081                 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1082         }
1083         else
1084         {
1085                 if(freq < 0x9C)
1086                         pll = F_LOW_PCI_33;
1087                 else if(freq < 0xb0)
1088                         pll = F_LOW_PCI_40;
1089                 else if(freq <0xc8)
1090                         pll = F_LOW_PCI_50;
1091                 else
1092                         pll = F_LOW_PCI_66;
1093
1094                 if (pll == F_LOW_PCI_33) {
1095                         info->speed = thirty_three_base_hpt37x;
1096                         printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1097                 } else if (pll == F_LOW_PCI_40) {
1098                         /* Unsupported */
1099                 } else if (pll == F_LOW_PCI_50) {
1100                         info->speed = fifty_base_hpt37x;
1101                         printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1102                 } else {
1103                         info->speed = sixty_six_base_hpt37x;
1104                         printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1105                 }
1106         }
1107
1108         if (pll == F_LOW_PCI_66)
1109                 info->flags |= PCI_66MHZ;
1110
1111         /*
1112          * only try the pll if we don't have a table for the clock
1113          * speed that we're running at. NOTE: the internal PLL will
1114          * result in slow reads when using a 33MHz PCI clock. we also
1115          * don't like to use the PLL because it will cause glitches
1116          * on PRST/SRST when the HPT state engine gets reset.
1117          *
1118          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1119          * 372 device so we can get ATA133 support
1120          */
1121         if (info->speed)
1122                 goto init_hpt37X_done;
1123
1124         info->flags |= PLL_MODE;
1125
1126         /*
1127          * FIXME: make this work correctly, esp with 372N as per
1128          * reference driver code.
1129          *
1130          * adjust PLL based upon PCI clock, enable it, and wait for
1131          * stabilization.
1132          */
1133         adjust = 0;
1134         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1135         while (adjust++ < 6) {
1136                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1137                                        pll | 0x100);
1138
1139                 /* wait for clock stabilization */
1140                 for (i = 0; i < 0x50000; i++) {
1141                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1142                         if (reg5bh & 0x80) {
1143                                 /* spin looking for the clock to destabilize */
1144                                 for (i = 0; i < 0x1000; ++i) {
1145                                         pci_read_config_byte(dev, 0x5b,
1146                                                              &reg5bh);
1147                                         if ((reg5bh & 0x80) == 0)
1148                                                 goto pll_recal;
1149                                 }
1150                                 pci_read_config_dword(dev, 0x5c, &pll);
1151                                 pci_write_config_dword(dev, 0x5c,
1152                                                        pll & ~0x100);
1153                                 pci_write_config_byte(dev, 0x5b, 0x21);
1154
1155                                 info->speed = fifty_base_hpt37x;
1156                                 printk("HPT37X: using 50MHz internal PLL\n");
1157                                 goto init_hpt37X_done;
1158                         }
1159                 }
1160 pll_recal:
1161                 if (adjust & 1)
1162                         pll -= (adjust >> 1);
1163                 else
1164                         pll += (adjust >> 1);
1165         }
1166
1167 init_hpt37X_done:
1168         if (!info->speed)
1169                 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1170                        (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1171         /*
1172          * Reset the state engines.
1173          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1174          */
1175         pci_read_config_byte(dev, 0x50, &mcr1);
1176         if (mcr1 & 0x04)
1177                 pci_write_config_byte(dev, 0x50, 0x37);
1178         pci_write_config_byte(dev, 0x54, 0x37);
1179         udelay(100);
1180 }
1181
1182 static int __devinit init_hpt37x(struct pci_dev *dev)
1183 {
1184         u8 reg5ah;
1185
1186         pci_read_config_byte(dev, 0x5a, &reg5ah);
1187         /* interrupt force enable */
1188         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1189         return 0;
1190 }
1191
1192 static int __devinit init_hpt366(struct pci_dev *dev)
1193 {
1194         u32 reg1        = 0;
1195         u8 drive_fast   = 0;
1196
1197         /*
1198          * Disable the "fast interrupt" prediction.
1199          */
1200         pci_read_config_byte(dev, 0x51, &drive_fast);
1201         if (drive_fast & 0x80)
1202                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1203         pci_read_config_dword(dev, 0x40, &reg1);
1204
1205         return 0;
1206 }
1207
1208 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1209 {
1210         int ret = 0;
1211
1212         /*
1213          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1214          * We don't seem to be using it.
1215          */
1216         if (dev->resource[PCI_ROM_RESOURCE].start)
1217                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1218                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1219
1220         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1221         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1222         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1223         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1224
1225         if (hpt_revision(dev) >= 3)
1226                 ret = init_hpt37x(dev);
1227         else
1228                 ret = init_hpt366(dev);
1229
1230         if (ret)
1231                 return ret;
1232
1233         return dev->irq;
1234 }
1235
1236 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1237 {
1238         struct pci_dev *dev             = hwif->pci_dev;
1239         struct hpt_info *info           = ide_get_hwifdata(hwif);
1240         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1241         int serialize                   = HPT_SERIALIZE_IO;
1242
1243         hwif->tuneproc                  = &hpt3xx_tune_drive;
1244         hwif->speedproc                 = &hpt3xx_tune_chipset;
1245         hwif->quirkproc                 = &hpt3xx_quirkproc;
1246         hwif->intrproc                  = &hpt3xx_intrproc;
1247         hwif->maskproc                  = &hpt3xx_maskproc;
1248
1249         /*
1250          * HPT3xxN chips have some complications:
1251          *
1252          * - on 33 MHz PCI we must clock switch
1253          * - on 66 MHz PCI we must NOT use the PCI clock
1254          */
1255         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1256                 /*
1257                  * Clock is shared between the channels,
1258                  * so we'll have to serialize them... :-(
1259                  */
1260                 serialize = 1;
1261                 hwif->rw_disk = &hpt3xxn_rw_disk;
1262         }
1263
1264         /*
1265          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1266          * address lines to access an external eeprom.  To read valid
1267          * cable detect state the pins must be enabled as inputs.
1268          */
1269         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1270                 /*
1271                  * HPT374 PCI function 1
1272                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1273                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1274                  */
1275                 u16 mcr3, mcr6;
1276                 pci_read_config_word(dev, 0x52, &mcr3);
1277                 pci_read_config_word(dev, 0x56, &mcr6);
1278                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1279                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1280                 /* now read cable id register */
1281                 pci_read_config_byte(dev, 0x5a, &ata66);
1282                 pci_write_config_word(dev, 0x52, mcr3);
1283                 pci_write_config_word(dev, 0x56, mcr6);
1284         } else if (info->revision >= 3) {
1285                 /*
1286                  * HPT370/372 and 374 pcifn 0
1287                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1288                  */
1289                 u8 scr2;
1290                 pci_read_config_byte(dev, 0x5b, &scr2);
1291                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1292                 /* now read cable id register */
1293                 pci_read_config_byte(dev, 0x5a, &ata66);
1294                 pci_write_config_byte(dev, 0x5b, scr2);
1295         } else {
1296                 pci_read_config_byte(dev, 0x5a, &ata66);
1297         }
1298
1299 #ifdef DEBUG
1300         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1301                 ata66, (ata66 & regmask) ? "33" : "66",
1302                 PCI_FUNC(hwif->pci_dev->devfn));
1303 #endif /* DEBUG */
1304
1305         /* Serialize access to this device */
1306         if (serialize && hwif->mate)
1307                 hwif->serialized = hwif->mate->serialized = 1;
1308
1309         if (info->revision >= 3) {
1310                 u8 reg5ah = 0;
1311                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1312                 /*
1313                  * set up ioctl for power status.
1314                  * note: power affects both
1315                  * drives on each channel
1316                  */
1317                 hwif->resetproc = &hpt3xx_reset;
1318                 hwif->busproc   = &hpt370_busproc;
1319         } else if (info->revision >= 2) {
1320                 hwif->resetproc = &hpt3xx_reset;
1321                 hwif->busproc   = &hpt3xx_tristate;
1322         } else {
1323                 hwif->resetproc = &hpt3xx_reset;
1324                 hwif->busproc   = &hpt3xx_tristate;
1325         }
1326
1327         if (!hwif->dma_base) {
1328                 hwif->drives[0].autotune = 1;
1329                 hwif->drives[1].autotune = 1;
1330                 return;
1331         }
1332
1333         hwif->ultra_mask = 0x7f;
1334         hwif->mwdma_mask = 0x07;
1335
1336         if (!(hwif->udma_four))
1337                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1338         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1339
1340         if (info->revision >= 8) {
1341                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1342                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1343         } else if (info->revision >= 5) {
1344                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1345                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1346         } else if (info->revision >= 3) {
1347                 hwif->dma_start = &hpt370_ide_dma_start;
1348                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1349                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1350                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1351         } else if (info->revision >= 2)
1352                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1353         else
1354                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1355
1356         if (!noautodma)
1357                 hwif->autodma = 1;
1358         hwif->drives[0].autodma = hwif->autodma;
1359         hwif->drives[1].autodma = hwif->autodma;
1360 }
1361
1362 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1363 {
1364         struct hpt_info *info   = ide_get_hwifdata(hwif);
1365         u8 masterdma    = 0, slavedma = 0;
1366         u8 dma_new      = 0, dma_old = 0;
1367         u8 primary      = hwif->channel ? 0x4b : 0x43;
1368         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1369         unsigned long flags;
1370
1371         if (!dmabase)
1372                 return;
1373
1374         if(info->speed == NULL) {
1375                 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1376                 return;
1377         }
1378
1379         dma_old = hwif->INB(dmabase+2);
1380
1381         local_irq_save(flags);
1382
1383         dma_new = dma_old;
1384         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1385         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1386
1387         if (masterdma & 0x30)   dma_new |= 0x20;
1388         if (slavedma & 0x30)    dma_new |= 0x40;
1389         if (dma_new != dma_old)
1390                 hwif->OUTB(dma_new, dmabase+2);
1391
1392         local_irq_restore(flags);
1393
1394         ide_setup_dma(hwif, dmabase, 8);
1395 }
1396
1397 /*
1398  *      We "borrow" this hook in order to set the data structures
1399  *      up early enough before dma or init_hwif calls are made.
1400  */
1401
1402 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1403 {
1404         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1405         struct pci_dev  *dev    = hwif->pci_dev;
1406         u16 did                 = dev->device;
1407         u8  rid                 = 0;
1408
1409         if(info == NULL) {
1410                 printk(KERN_WARNING "hpt366: out of memory.\n");
1411                 return;
1412         }
1413         ide_set_hwifdata(hwif, info);
1414
1415         /* Avoid doing the same thing twice. */
1416         if (hwif->channel && hwif->mate) {
1417                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1418                 return;
1419         }
1420
1421         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1422
1423         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1424             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1425               did == PCI_DEVICE_ID_TTI_HPT302  ||
1426               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1427               did == PCI_DEVICE_ID_TTI_HPT372N)
1428                 info->flags |= IS_3xxN;
1429
1430         info->revision = hpt_revision(dev);
1431
1432         if (info->revision >= 3)
1433                 hpt37x_clocking(hwif);
1434         else
1435                 hpt366_clocking(hwif);
1436 }
1437
1438 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1439 {
1440         struct pci_dev *findev = NULL;
1441
1442         if (PCI_FUNC(dev->devfn) & 1)
1443                 return -ENODEV;
1444
1445         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1446                 if ((findev->vendor == dev->vendor) &&
1447                     (findev->device == dev->device) &&
1448                     ((findev->devfn - dev->devfn) == 1) &&
1449                     (PCI_FUNC(findev->devfn) & 1)) {
1450                         if (findev->irq != dev->irq) {
1451                                 /* FIXME: we need a core pci_set_interrupt() */
1452                                 findev->irq = dev->irq;
1453                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1454                                         "fixed.\n", d->name);
1455                         }
1456                         return ide_setup_pci_devices(dev, findev, d);
1457                 }
1458         }
1459         return ide_setup_pci_device(dev, d);
1460 }
1461
1462 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1463 {
1464         return ide_setup_pci_device(dev, d);
1465 }
1466
1467 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1468 {
1469         u8 mcr1 = 0;
1470
1471         /*
1472          * HPT371 chips physically have only one channel, the secondary one,
1473          * but the primary channel registers do exist!  Go figure...
1474          * So,  we manually disable the non-existing channel here
1475          * (if the BIOS hasn't done this already).
1476          */
1477         pci_read_config_byte(dev, 0x50, &mcr1);
1478         if (mcr1 & 0x04)
1479                 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1480
1481         return ide_setup_pci_device(dev, d);
1482 }
1483
1484 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1485 {
1486         struct pci_dev *findev = NULL;
1487         u8 pin1 = 0, pin2 = 0;
1488         unsigned int class_rev;
1489         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1490                                  "HPT370", "HPT370A", "HPT372",
1491                                  "HPT372N" };
1492
1493         if (PCI_FUNC(dev->devfn) & 1)
1494                 return -ENODEV;
1495
1496         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1497         class_rev &= 0xff;
1498
1499         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1500                 class_rev = 6;
1501
1502         if(class_rev <= 6)
1503                 d->name = chipset_names[class_rev];
1504
1505         switch(class_rev) {
1506                 case 6:
1507                 case 5:
1508                 case 4:
1509                 case 3:
1510                         goto init_single;
1511                 default:
1512                         break;
1513         }
1514
1515         d->channels = 1;
1516
1517         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1518         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1519                 if ((findev->vendor == dev->vendor) &&
1520                     (findev->device == dev->device) &&
1521                     ((findev->devfn - dev->devfn) == 1) &&
1522                     (PCI_FUNC(findev->devfn) & 1)) {
1523                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1524                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1525                                 d->bootable = ON_BOARD;
1526                                 printk("%s: onboard version of chipset, "
1527                                         "pin1=%d pin2=%d\n", d->name,
1528                                         pin1, pin2);
1529                         }
1530                         return ide_setup_pci_devices(dev, findev, d);
1531                 }
1532         }
1533 init_single:
1534         return ide_setup_pci_device(dev, d);
1535 }
1536
1537 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1538         {       /* 0 */
1539                 .name           = "HPT366",
1540                 .init_setup     = init_setup_hpt366,
1541                 .init_chipset   = init_chipset_hpt366,
1542                 .init_iops      = init_iops_hpt366,
1543                 .init_hwif      = init_hwif_hpt366,
1544                 .init_dma       = init_dma_hpt366,
1545                 .channels       = 2,
1546                 .autodma        = AUTODMA,
1547                 .bootable       = OFF_BOARD,
1548                 .extra          = 240
1549         },{     /* 1 */
1550                 .name           = "HPT372A",
1551                 .init_setup     = init_setup_hpt37x,
1552                 .init_chipset   = init_chipset_hpt366,
1553                 .init_iops      = init_iops_hpt366,
1554                 .init_hwif      = init_hwif_hpt366,
1555                 .init_dma       = init_dma_hpt366,
1556                 .channels       = 2,
1557                 .autodma        = AUTODMA,
1558                 .bootable       = OFF_BOARD,
1559         },{     /* 2 */
1560                 .name           = "HPT302",
1561                 .init_setup     = init_setup_hpt37x,
1562                 .init_chipset   = init_chipset_hpt366,
1563                 .init_iops      = init_iops_hpt366,
1564                 .init_hwif      = init_hwif_hpt366,
1565                 .init_dma       = init_dma_hpt366,
1566                 .channels       = 2,
1567                 .autodma        = AUTODMA,
1568                 .bootable       = OFF_BOARD,
1569         },{     /* 3 */
1570                 .name           = "HPT371",
1571                 .init_setup     = init_setup_hpt371,
1572                 .init_chipset   = init_chipset_hpt366,
1573                 .init_iops      = init_iops_hpt366,
1574                 .init_hwif      = init_hwif_hpt366,
1575                 .init_dma       = init_dma_hpt366,
1576                 .channels       = 2,
1577                 .autodma        = AUTODMA,
1578                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1579                 .bootable       = OFF_BOARD,
1580         },{     /* 4 */
1581                 .name           = "HPT374",
1582                 .init_setup     = init_setup_hpt374,
1583                 .init_chipset   = init_chipset_hpt366,
1584                 .init_iops      = init_iops_hpt366,
1585                 .init_hwif      = init_hwif_hpt366,
1586                 .init_dma       = init_dma_hpt366,
1587                 .channels       = 2,    /* 4 */
1588                 .autodma        = AUTODMA,
1589                 .bootable       = OFF_BOARD,
1590         },{     /* 5 */
1591                 .name           = "HPT372N",
1592                 .init_setup     = init_setup_hpt37x,
1593                 .init_chipset   = init_chipset_hpt366,
1594                 .init_iops      = init_iops_hpt366,
1595                 .init_hwif      = init_hwif_hpt366,
1596                 .init_dma       = init_dma_hpt366,
1597                 .channels       = 2,    /* 4 */
1598                 .autodma        = AUTODMA,
1599                 .bootable       = OFF_BOARD,
1600         }
1601 };
1602
1603 /**
1604  *      hpt366_init_one -       called when an HPT366 is found
1605  *      @dev: the hpt366 device
1606  *      @id: the matching pci id
1607  *
1608  *      Called when the PCI registration layer (or the IDE initialization)
1609  *      finds a device matching our IDE device tables.
1610  */
1611
1612 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1613 {
1614         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1615
1616         return d->init_setup(dev, d);
1617 }
1618
1619 static struct pci_device_id hpt366_pci_tbl[] = {
1620         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1621         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1622         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1623         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1624         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1625         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1626         { 0, },
1627 };
1628 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1629
1630 static struct pci_driver driver = {
1631         .name           = "HPT366_IDE",
1632         .id_table       = hpt366_pci_tbl,
1633         .probe          = hpt366_init_one,
1634 };
1635
1636 static int hpt366_ide_init(void)
1637 {
1638         return ide_pci_register_driver(&driver);
1639 }
1640
1641 module_init(hpt366_ide_init);
1642
1643 MODULE_AUTHOR("Andre Hedrick");
1644 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1645 MODULE_LICENSE("GPL");