drivers/ide/pci/hpt366.c

   1 /*
   2  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
   3  *
   4  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
   5  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
   6  * Portions Copyright (C) 2003          Red Hat Inc
   7  * Portions Copyright (C) 2005-2006     MontaVista Software, Inc.
   8  *
   9  * Thanks to HighPoint Technologies for their assistance, and hardware.
  10  * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
  11  * donation of an ABit BP6 mainboard, processor, and memory acellerated
  12  * development and support.
  13  *
  14  *
  15  * HighPoint has its own drivers (open source except for the RAID part)
  16  * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
  17  * This may be useful to anyone wanting to work on this driver, however  do not
  18  * trust  them too much since the code tends to become less and less meaningful
  19  * as the time passes... :-/
  20  *
  21  * Note that final HPT370 support was done by force extraction of GPL.
  22  *
  23  * - add function for getting/setting power status of drive
  24  * - the HPT370's state machine can get confused. reset it before each dma
  25  *   xfer to prevent that from happening.
  26  * - reset state engine whenever we get an error.
  27  * - check for busmaster state at end of dma.
  28  * - use new highpoint timings.
  29  * - detect bus speed using highpoint register.
  30  * - use pll if we don't have a clock table. added a 66MHz table that's
  31  *   just 2x the 33MHz table.
  32  * - removed turnaround. NOTE: we never want to switch between pll and
  33  *   pci clocks as the chip can glitch in those cases. the highpoint
  34  *   approved workaround slows everything down too much to be useful. in
  35  *   addition, we would have to serialize access to each chip.
  36  *      Adrian Sun <a.sun@sun.com>
  37  *
  38  * add drive timings for 66MHz PCI bus,
  39  * fix ATA Cable signal detection, fix incorrect /proc info
  40  * add /proc display for per-drive PIO/DMA/UDMA mode and
  41  * per-channel ATA-33/66 Cable detect.
  42  *      Duncan Laurie <void@sun.com>
  43  *
  44  * fixup /proc output for multiple controllers
  45  *      Tim Hockin <thockin@sun.com>
  46  *
  47  * On hpt366:
  48  * Reset the hpt366 on error, reset on dma
  49  * Fix disabling Fast Interrupt hpt366.
  50  *      Mike Waychison <crlf@sun.com>
  51  *
  52  * Added support for 372N clocking and clock switching. The 372N needs
  53  * different clocks on read/write. This requires overloading rw_disk and
  54  * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
  55  * keeping me sane.
  56  *              Alan Cox <alan@redhat.com>
  57  *
  58  * - fix the clock turnaround code: it was writing to the wrong ports when
  59  *   called for the secondary channel, caching the current clock mode per-
  60  *   channel caused the cached register value to get out of sync with the
  61  *   actual one, the channels weren't serialized, the turnaround shouldn't
  62  *   be done on 66 MHz PCI bus
  63  * - avoid calibrating PLL twice as the second time results in a wrong PCI
  64  *   frequency and thus in the wrong timings for the secondary channel
  65  * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
  66  *   allow for this speed anyway)
  67  * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
  68  * - HPT371/N are single channel chips, so avoid touching the primary channel
  69  *   which exists only virtually (there's no pins for it)
  70  * - fix/remove bad/unused timing tables: HPT370/A  66 MHz tables weren't really
  71  *   needed and had many modes over- and  underclocked,  HPT372 33 MHz table was
  72  *   for 66 MHz and 50 MHz table missed UltraDMA mode 6, HPT374 33 MHz table was
  73  *   really for 50 MHz; switch to using HPT372 tables for HPT374...
  74  *              <source@mvista.com>
  75  *
  76  */
  77
  78
  79 #include <linux/types.h>
  80 #include <linux/module.h>
  81 #include <linux/kernel.h>
  82 #include <linux/delay.h>
  83 #include <linux/timer.h>
  84 #include <linux/mm.h>
  85 #include <linux/ioport.h>
  86 #include <linux/blkdev.h>
  87 #include <linux/hdreg.h>
  88
  89 #include <linux/interrupt.h>
  90 #include <linux/pci.h>
  91 #include <linux/init.h>
  92 #include <linux/ide.h>
  93
  94 #include <asm/uaccess.h>
  95 #include <asm/io.h>
  96 #include <asm/irq.h>
  97
  98 /* various tuning parameters */
  99 #define HPT_RESET_STATE_ENGINE
 100 #undef  HPT_DELAY_INTERRUPT
 101 #define HPT_SERIALIZE_IO        0
 102
 103 static const char *quirk_drives[] = {
 104         "QUANTUM FIREBALLlct08 08",
 105         "QUANTUM FIREBALLP KA6.4",
 106         "QUANTUM FIREBALLP LM20.4",
 107         "QUANTUM FIREBALLP LM20.5",
 108         NULL
 109 };
 110
 111 static const char *bad_ata100_5[] = {
 112         "IBM-DTLA-307075",
 113         "IBM-DTLA-307060",
 114         "IBM-DTLA-307045",
 115         "IBM-DTLA-307030",
 116         "IBM-DTLA-307020",
 117         "IBM-DTLA-307015",
 118         "IBM-DTLA-305040",
 119         "IBM-DTLA-305030",
 120         "IBM-DTLA-305020",
 121         "IC35L010AVER07-0",
 122         "IC35L020AVER07-0",
 123         "IC35L030AVER07-0",
 124         "IC35L040AVER07-0",
 125         "IC35L060AVER07-0",
 126         "WDC AC310200R",
 127         NULL
 128 };
 129
 130 static const char *bad_ata66_4[] = {
 131         "IBM-DTLA-307075",
 132         "IBM-DTLA-307060",
 133         "IBM-DTLA-307045",
 134         "IBM-DTLA-307030",
 135         "IBM-DTLA-307020",
 136         "IBM-DTLA-307015",
 137         "IBM-DTLA-305040",
 138         "IBM-DTLA-305030",
 139         "IBM-DTLA-305020",
 140         "IC35L010AVER07-0",
 141         "IC35L020AVER07-0",
 142         "IC35L030AVER07-0",
 143         "IC35L040AVER07-0",
 144         "IC35L060AVER07-0",
 145         "WDC AC310200R",
 146         NULL
 147 };
 148
 149 static const char *bad_ata66_3[] = {
 150         "WDC AC310200R",
 151         NULL
 152 };
 153
 154 static const char *bad_ata33[] = {
 155         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
 156         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
 157         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
 158         "Maxtor 90510D4",
 159         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
 160         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
 161         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
 162         NULL
 163 };
 164
 165 struct chipset_bus_clock_list_entry {
 166         u8              xfer_speed;
 167         unsigned int    chipset_settings;
 168 };
 169
 170 /* key for bus clock timings
 171  * bit
 172  * 0:3    data_high_time. inactive time of DIOW_/DIOR_ for PIO and MW
 173  *        DMA. cycles = value + 1
 174  * 4:8    data_low_time. active time of DIOW_/DIOR_ for PIO and MW
 175  *        DMA. cycles = value + 1
 176  * 9:12   cmd_high_time. inactive time of DIOW_/DIOR_ during task file
 177  *        register access.
 178  * 13:17  cmd_low_time. active time of DIOW_/DIOR_ during task file
 179  *        register access.
 180  * 18:21  udma_cycle_time. clock freq and clock cycles for UDMA xfer.
 181  *        during task file register access.
 182  * 22:24  pre_high_time. time to initialize 1st cycle for PIO and MW DMA
 183  *        xfer.
 184  * 25:27  cmd_pre_high_time. time to initialize 1st PIO cycle for task
 185  *        register access.
 186  * 28     UDMA enable
 187  * 29     DMA enable
 188  * 30     PIO_MST enable. if set, the chip is in bus master mode during
 189  *        PIO.
 190  * 31     FIFO enable.
 191  */
 192 static struct chipset_bus_clock_list_entry forty_base_hpt366[] = {
 193         {       XFER_UDMA_4,    0x900fd943      },
 194         {       XFER_UDMA_3,    0x900ad943      },
 195         {       XFER_UDMA_2,    0x900bd943      },
 196         {       XFER_UDMA_1,    0x9008d943      },
 197         {       XFER_UDMA_0,    0x9008d943      },
 198
 199         {       XFER_MW_DMA_2,  0xa008d943      },
 200         {       XFER_MW_DMA_1,  0xa010d955      },
 201         {       XFER_MW_DMA_0,  0xa010d9fc      },
 202
 203         {       XFER_PIO_4,     0xc008d963      },
 204         {       XFER_PIO_3,     0xc010d974      },
 205         {       XFER_PIO_2,     0xc010d997      },
 206         {       XFER_PIO_1,     0xc010d9c7      },
 207         {       XFER_PIO_0,     0xc018d9d9      },
 208         {       0,              0x0120d9d9      }
 209 };
 210
 211 static struct chipset_bus_clock_list_entry thirty_three_base_hpt366[] = {
 212         {       XFER_UDMA_4,    0x90c9a731      },
 213         {       XFER_UDMA_3,    0x90cfa731      },
 214         {       XFER_UDMA_2,    0x90caa731      },
 215         {       XFER_UDMA_1,    0x90cba731      },
 216         {       XFER_UDMA_0,    0x90c8a731      },
 217
 218         {       XFER_MW_DMA_2,  0xa0c8a731      },
 219         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
 220         {       XFER_MW_DMA_0,  0xa0c8a797      },
 221
 222         {       XFER_PIO_4,     0xc0c8a731      },
 223         {       XFER_PIO_3,     0xc0c8a742      },
 224         {       XFER_PIO_2,     0xc0d0a753      },
 225         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
 226         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
 227         {       0,              0x0120a7a7      }
 228 };
 229
 230 static struct chipset_bus_clock_list_entry twenty_five_base_hpt366[] = {
 231         {       XFER_UDMA_4,    0x90c98521      },
 232         {       XFER_UDMA_3,    0x90cf8521      },
 233         {       XFER_UDMA_2,    0x90cf8521      },
 234         {       XFER_UDMA_1,    0x90cb8521      },
 235         {       XFER_UDMA_0,    0x90cb8521      },
 236
 237         {       XFER_MW_DMA_2,  0xa0ca8521      },
 238         {       XFER_MW_DMA_1,  0xa0ca8532      },
 239         {       XFER_MW_DMA_0,  0xa0ca8575      },
 240
 241         {       XFER_PIO_4,     0xc0ca8521      },
 242         {       XFER_PIO_3,     0xc0ca8532      },
 243         {       XFER_PIO_2,     0xc0ca8542      },
 244         {       XFER_PIO_1,     0xc0d08572      },
 245         {       XFER_PIO_0,     0xc0d08585      },
 246         {       0,              0x01208585      }
 247 };
 248
 249 /* from highpoint documentation. these are old values */
 250 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370[] = {
 251 /*      {       XFER_UDMA_5,    0x1A85F442,     0x16454e31      }, */
 252         {       XFER_UDMA_5,    0x16454e31      },
 253         {       XFER_UDMA_4,    0x16454e31      },
 254         {       XFER_UDMA_3,    0x166d4e31      },
 255         {       XFER_UDMA_2,    0x16494e31      },
 256         {       XFER_UDMA_1,    0x164d4e31      },
 257         {       XFER_UDMA_0,    0x16514e31      },
 258
 259         {       XFER_MW_DMA_2,  0x26514e21      },
 260         {       XFER_MW_DMA_1,  0x26514e33      },
 261         {       XFER_MW_DMA_0,  0x26514e97      },
 262
 263         {       XFER_PIO_4,     0x06514e21      },
 264         {       XFER_PIO_3,     0x06514e22      },
 265         {       XFER_PIO_2,     0x06514e33      },
 266         {       XFER_PIO_1,     0x06914e43      },
 267         {       XFER_PIO_0,     0x06914e57      },
 268         {       0,              0x06514e57      }
 269 };
 270
 271 /* these are the current (4 sep 2001) timings from highpoint */
 272 static struct chipset_bus_clock_list_entry thirty_three_base_hpt370a[] = {
 273         {       XFER_UDMA_5,    0x12446231      },
 274         {       XFER_UDMA_4,    0x12446231      },
 275         {       XFER_UDMA_3,    0x126c6231      },
 276         {       XFER_UDMA_2,    0x12486231      },
 277         {       XFER_UDMA_1,    0x124c6233      },
 278         {       XFER_UDMA_0,    0x12506297      },
 279
 280         {       XFER_MW_DMA_2,  0x22406c31      },
 281         {       XFER_MW_DMA_1,  0x22406c33      },
 282         {       XFER_MW_DMA_0,  0x22406c97      },
 283
 284         {       XFER_PIO_4,     0x06414e31      },
 285         {       XFER_PIO_3,     0x06414e42      },
 286         {       XFER_PIO_2,     0x06414e53      },
 287         {       XFER_PIO_1,     0x06814e93      },
 288         {       XFER_PIO_0,     0x06814ea7      },
 289         {       0,              0x06814ea7      }
 290 };
 291
 292 static struct chipset_bus_clock_list_entry fifty_base_hpt370a[] = {
 293         {       XFER_UDMA_5,    0x12848242      },
 294         {       XFER_UDMA_4,    0x12ac8242      },
 295         {       XFER_UDMA_3,    0x128c8242      },
 296         {       XFER_UDMA_2,    0x120c8242      },
 297         {       XFER_UDMA_1,    0x12148254      },
 298         {       XFER_UDMA_0,    0x121882ea      },
 299
 300         {       XFER_MW_DMA_2,  0x22808242      },
 301         {       XFER_MW_DMA_1,  0x22808254      },
 302         {       XFER_MW_DMA_0,  0x228082ea      },
 303
 304         {       XFER_PIO_4,     0x0a81f442      },
 305         {       XFER_PIO_3,     0x0a81f443      },
 306         {       XFER_PIO_2,     0x0a81f454      },
 307         {       XFER_PIO_1,     0x0ac1f465      },
 308         {       XFER_PIO_0,     0x0ac1f48a      },
 309         {       0,              0x0ac1f48a      }
 310 };
 311
 312 static struct chipset_bus_clock_list_entry thirty_three_base_hpt372[] = {
 313         {       XFER_UDMA_6,    0x12446231      },      /* 0x12646231 ?? */
 314         {       XFER_UDMA_5,    0x12446231      },
 315         {       XFER_UDMA_4,    0x12446231      },
 316         {       XFER_UDMA_3,    0x126c6231      },
 317         {       XFER_UDMA_2,    0x12486231      },
 318         {       XFER_UDMA_1,    0x124c6233      },
 319         {       XFER_UDMA_0,    0x12506297      },
 320
 321         {       XFER_MW_DMA_2,  0x22406c31      },
 322         {       XFER_MW_DMA_1,  0x22406c33      },
 323         {       XFER_MW_DMA_0,  0x22406c97      },
 324
 325         {       XFER_PIO_4,     0x06414e31      },
 326         {       XFER_PIO_3,     0x06414e42      },
 327         {       XFER_PIO_2,     0x06414e53      },
 328         {       XFER_PIO_1,     0x06814e93      },
 329         {       XFER_PIO_0,     0x06814ea7      },
 330         {       0,              0x06814ea7      }
 331 };
 332
 333 static struct chipset_bus_clock_list_entry fifty_base_hpt372[] = {
 334         {       XFER_UDMA_6,    0x12848242      },
 335         {       XFER_UDMA_5,    0x12848242      },
 336         {       XFER_UDMA_4,    0x12ac8242      },
 337         {       XFER_UDMA_3,    0x128c8242      },
 338         {       XFER_UDMA_2,    0x120c8242      },
 339         {       XFER_UDMA_1,    0x12148254      },
 340         {       XFER_UDMA_0,    0x121882ea      },
 341
 342         {       XFER_MW_DMA_2,  0x22808242      },
 343         {       XFER_MW_DMA_1,  0x22808254      },
 344         {       XFER_MW_DMA_0,  0x228082ea      },
 345
 346         {       XFER_PIO_4,     0x0a81f442      },
 347         {       XFER_PIO_3,     0x0a81f443      },
 348         {       XFER_PIO_2,     0x0a81f454      },
 349         {       XFER_PIO_1,     0x0ac1f465      },
 350         {       XFER_PIO_0,     0x0ac1f48a      },
 351         {       0,              0x0a81f443      }
 352 };
 353
 354 static struct chipset_bus_clock_list_entry sixty_six_base_hpt372[] = {
 355         {       XFER_UDMA_6,    0x1c869c62      },
 356         {       XFER_UDMA_5,    0x1cae9c62      },      /* 0x1c8a9c62 */
 357         {       XFER_UDMA_4,    0x1c8a9c62      },
 358         {       XFER_UDMA_3,    0x1c8e9c62      },
 359         {       XFER_UDMA_2,    0x1c929c62      },
 360         {       XFER_UDMA_1,    0x1c9a9c62      },
 361         {       XFER_UDMA_0,    0x1c829c62      },
 362
 363         {       XFER_MW_DMA_2,  0x2c829c62      },
 364         {       XFER_MW_DMA_1,  0x2c829c66      },
 365         {       XFER_MW_DMA_0,  0x2c829d2e      },
 366
 367         {       XFER_PIO_4,     0x0c829c62      },
 368         {       XFER_PIO_3,     0x0c829c84      },
 369         {       XFER_PIO_2,     0x0c829ca6      },
 370         {       XFER_PIO_1,     0x0d029d26      },
 371         {       XFER_PIO_0,     0x0d029d5e      },
 372         {       0,              0x0d029d26      }
 373 };
 374
 375 #define HPT366_DEBUG_DRIVE_INFO         0
 376 #define HPT374_ALLOW_ATA133_6           0
 377 #define HPT371_ALLOW_ATA133_6           0
 378 #define HPT302_ALLOW_ATA133_6           0
 379 #define HPT372_ALLOW_ATA133_6           0
 380 #define HPT370_ALLOW_ATA100_5           1
 381 #define HPT366_ALLOW_ATA66_4            1
 382 #define HPT366_ALLOW_ATA66_3            1
 383 #define HPT366_MAX_DEVS                 8
 384
 385 #define F_LOW_PCI_33    0x23
 386 #define F_LOW_PCI_40    0x29
 387 #define F_LOW_PCI_50    0x2d
 388 #define F_LOW_PCI_66    0x42
 389
 390 /*
 391  *      Hold all the highpoint quirks and revision information in one
 392  *      place.
 393  */
 394
 395 struct hpt_info
 396 {
 397         u8 max_mode;            /* Speeds allowed */
 398         int revision;           /* Chipset revision */
 399         int flags;              /* Chipset properties */
 400 #define PLL_MODE        1
 401 #define IS_3xxN         2
 402 #define PCI_66MHZ       4
 403                                 /* Speed table */
 404         struct chipset_bus_clock_list_entry *speed;
 405 };
 406
 407 /*
 408  *      This wants fixing so that we do everything not by classrev
 409  *      (which breaks on the newest chips) but by creating an
 410  *      enumeration of chip variants and using that
 411  */
 412
 413 static __devinit u32 hpt_revision (struct pci_dev *dev)
 414 {
 415         u32 class_rev;
 416         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 417         class_rev &= 0xff;
 418
 419         switch(dev->device) {
 420                 /* Remap new 372N onto 372 */
 421                 case PCI_DEVICE_ID_TTI_HPT372N:
 422                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 423                 case PCI_DEVICE_ID_TTI_HPT374:
 424                         class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
 425                 case PCI_DEVICE_ID_TTI_HPT371:
 426                         class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
 427                 case PCI_DEVICE_ID_TTI_HPT302:
 428                         class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
 429                 case PCI_DEVICE_ID_TTI_HPT372:
 430                         class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
 431                 default:
 432                         break;
 433         }
 434         return class_rev;
 435 }
 436
 437 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
 438
 439 static u8 hpt3xx_ratemask (ide_drive_t *drive)
 440 {
 441         ide_hwif_t *hwif        = drive->hwif;
 442         struct hpt_info *info   = ide_get_hwifdata(hwif);
 443         u8 mode                 = 0;
 444
 445         /* FIXME: TODO - move this to set info->mode once at boot */
 446
 447         if (info->revision >= 8) {              /* HPT374 */
 448                 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
 449         } else if (info->revision >= 7) {       /* HPT371 */
 450                 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
 451         } else if (info->revision >= 6) {       /* HPT302 */
 452                 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
 453         } else if (info->revision >= 5) {       /* HPT372 */
 454                 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
 455         } else if (info->revision >= 4) {       /* HPT370A */
 456                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 457         } else if (info->revision >= 3) {       /* HPT370 */
 458                 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
 459                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
 460         } else {                                /* HPT366 and HPT368 */
 461                 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
 462         }
 463         if (!eighty_ninty_three(drive) && mode)
 464                 mode = min(mode, (u8)1);
 465         return mode;
 466 }
 467
 468 /*
 469  *      Note for the future; the SATA hpt37x we must set
 470  *      either PIO or UDMA modes 0,4,5
 471  */
 472
 473 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
 474 {
 475         ide_hwif_t *hwif        = drive->hwif;
 476         struct hpt_info *info   = ide_get_hwifdata(hwif);
 477         u8 mode                 = hpt3xx_ratemask(drive);
 478
 479         if (drive->media != ide_disk)
 480                 return min(speed, (u8)XFER_PIO_4);
 481
 482         switch(mode) {
 483                 case 0x04:
 484                         speed = min(speed, (u8)XFER_UDMA_6);
 485                         break;
 486                 case 0x03:
 487                         speed = min(speed, (u8)XFER_UDMA_5);
 488                         if (info->revision >= 5)
 489                                 break;
 490                         if (check_in_drive_lists(drive, bad_ata100_5))
 491                                 speed = min(speed, (u8)XFER_UDMA_4);
 492                         break;
 493                 case 0x02:
 494                         speed = min(speed, (u8)XFER_UDMA_4);
 495         /*
 496          * CHECK ME, Does this need to be set to 5 ??
 497          */
 498                         if (info->revision >= 3)
 499                                 break;
 500                         if ((check_in_drive_lists(drive, bad_ata66_4)) ||
 501                             (!(HPT366_ALLOW_ATA66_4)))
 502                                 speed = min(speed, (u8)XFER_UDMA_3);
 503                         if ((check_in_drive_lists(drive, bad_ata66_3)) ||
 504                             (!(HPT366_ALLOW_ATA66_3)))
 505                                 speed = min(speed, (u8)XFER_UDMA_2);
 506                         break;
 507                 case 0x01:
 508                         speed = min(speed, (u8)XFER_UDMA_2);
 509         /*
 510          * CHECK ME, Does this need to be set to 5 ??
 511          */
 512                         if (info->revision >= 3)
 513                                 break;
 514                         if (check_in_drive_lists(drive, bad_ata33))
 515                                 speed = min(speed, (u8)XFER_MW_DMA_2);
 516                         break;
 517                 case 0x00:
 518                 default:
 519                         speed = min(speed, (u8)XFER_MW_DMA_2);
 520                         break;
 521         }
 522         return speed;
 523 }
 524
 525 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
 526 {
 527         struct hd_driveid *id = drive->id;
 528
 529         if (quirk_drives == list) {
 530                 while (*list)
 531                         if (strstr(id->model, *list++))
 532                                 return 1;
 533         } else {
 534                 while (*list)
 535                         if (!strcmp(*list++,id->model))
 536                                 return 1;
 537         }
 538         return 0;
 539 }
 540
 541 static unsigned int pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
 542 {
 543         for ( ; chipset_table->xfer_speed ; chipset_table++)
 544                 if (chipset_table->xfer_speed == speed)
 545                         return chipset_table->chipset_settings;
 546         return chipset_table->chipset_settings;
 547 }
 548
 549 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 550 {
 551         ide_hwif_t *hwif        = drive->hwif;
 552         struct pci_dev *dev     = hwif->pci_dev;
 553         struct hpt_info *info   = ide_get_hwifdata(hwif);
 554         u8 speed                = hpt3xx_ratefilter(drive, xferspeed);
 555         u8 regtime              = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
 556         u8 regfast              = (hwif->channel) ? 0x55 : 0x51;
 557         u8 drive_fast           = 0;
 558         u32 reg1 = 0, reg2      = 0;
 559
 560         /*
 561          * Disable the "fast interrupt" prediction.
 562          */
 563         pci_read_config_byte(dev, regfast, &drive_fast);
 564         if (drive_fast & 0x80)
 565                 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
 566
 567         reg2 = pci_bus_clock_list(speed, info->speed);
 568
 569         /*
 570          * Disable on-chip PIO FIFO/buffer
 571          *  (to avoid problems handling I/O errors later)
 572          */
 573         pci_read_config_dword(dev, regtime, &reg1);
 574         if (speed >= XFER_MW_DMA_0) {
 575                 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
 576         } else {
 577                 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
 578         }
 579         reg2 &= ~0x80000000;
 580
 581         pci_write_config_dword(dev, regtime, reg2);
 582
 583         return ide_config_drive_speed(drive, speed);
 584 }
 585
 586 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 587 {
 588         ide_hwif_t *hwif        = drive->hwif;
 589         struct pci_dev *dev = hwif->pci_dev;
 590         struct hpt_info *info   = ide_get_hwifdata(hwif);
 591         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 592         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 593         u8 drive_pci    = 0x40 + (drive->dn * 4);
 594         u8 new_fast     = 0, drive_fast = 0;
 595         u32 list_conf   = 0, drive_conf = 0;
 596         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 597
 598         /*
 599          * Disable the "fast interrupt" prediction.
 600          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 601          */
 602         pci_read_config_byte(dev, regfast, &drive_fast);
 603         new_fast = drive_fast;
 604         if (new_fast & 0x02)
 605                 new_fast &= ~0x02;
 606
 607 #ifdef HPT_DELAY_INTERRUPT
 608         if (new_fast & 0x01)
 609                 new_fast &= ~0x01;
 610 #else
 611         if ((new_fast & 0x01) == 0)
 612                 new_fast |= 0x01;
 613 #endif
 614         if (new_fast != drive_fast)
 615                 pci_write_config_byte(dev, regfast, new_fast);
 616
 617         list_conf = pci_bus_clock_list(speed, info->speed);
 618
 619         pci_read_config_dword(dev, drive_pci, &drive_conf);
 620         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 621
 622         if (speed < XFER_MW_DMA_0)
 623                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 624         pci_write_config_dword(dev, drive_pci, list_conf);
 625
 626         return ide_config_drive_speed(drive, speed);
 627 }
 628
 629 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
 630 {
 631         ide_hwif_t *hwif        = drive->hwif;
 632         struct pci_dev *dev     = hwif->pci_dev;
 633         struct hpt_info *info   = ide_get_hwifdata(hwif);
 634         u8 speed        = hpt3xx_ratefilter(drive, xferspeed);
 635         u8 regfast      = (drive->hwif->channel) ? 0x55 : 0x51;
 636         u8 drive_fast   = 0, drive_pci = 0x40 + (drive->dn * 4);
 637         u32 list_conf   = 0, drive_conf = 0;
 638         u32 conf_mask   = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
 639
 640         /*
 641          * Disable the "fast interrupt" prediction.
 642          * don't holdoff on interrupts. (== 0x01 despite what the docs say)
 643          */
 644         pci_read_config_byte(dev, regfast, &drive_fast);
 645         drive_fast &= ~0x07;
 646         pci_write_config_byte(dev, regfast, drive_fast);
 647
 648         list_conf = pci_bus_clock_list(speed, info->speed);
 649         pci_read_config_dword(dev, drive_pci, &drive_conf);
 650         list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
 651         if (speed < XFER_MW_DMA_0)
 652                 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
 653         pci_write_config_dword(dev, drive_pci, list_conf);
 654
 655         return ide_config_drive_speed(drive, speed);
 656 }
 657
 658 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
 659 {
 660         ide_hwif_t *hwif        = drive->hwif;
 661         struct hpt_info *info   = ide_get_hwifdata(hwif);
 662
 663         if (info->revision >= 8)
 664                 return hpt372_tune_chipset(drive, speed); /* not a typo */
 665         else if (info->revision >= 5)
 666                 return hpt372_tune_chipset(drive, speed);
 667         else if (info->revision >= 3)
 668                 return hpt370_tune_chipset(drive, speed);
 669         else    /* hpt368: hpt_minimum_revision(dev, 2) */
 670                 return hpt36x_tune_chipset(drive, speed);
 671 }
 672
 673 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
 674 {
 675         pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
 676         (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
 677 }
 678
 679 /*
 680  * This allows the configuration of ide_pci chipset registers
 681  * for cards that learn about the drive's UDMA, DMA, PIO capabilities
 682  * after the drive is reported by the OS.  Initially for designed for
 683  * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
 684  *
 685  * check_in_drive_lists(drive, bad_ata66_4)
 686  * check_in_drive_lists(drive, bad_ata66_3)
 687  * check_in_drive_lists(drive, bad_ata33)
 688  *
 689  */
 690 static int config_chipset_for_dma (ide_drive_t *drive)
 691 {
 692         u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
 693         ide_hwif_t *hwif = drive->hwif;
 694         struct hpt_info *info   = ide_get_hwifdata(hwif);
 695
 696         if (!speed)
 697                 return 0;
 698
 699         /* If we don't have any timings we can't do a lot */
 700         if (info->speed == NULL)
 701                 return 0;
 702
 703         (void) hpt3xx_tune_chipset(drive, speed);
 704         return ide_dma_enable(drive);
 705 }
 706
 707 static int hpt3xx_quirkproc (ide_drive_t *drive)
 708 {
 709         return ((int) check_in_drive_lists(drive, quirk_drives));
 710 }
 711
 712 static void hpt3xx_intrproc (ide_drive_t *drive)
 713 {
 714         ide_hwif_t *hwif = drive->hwif;
 715
 716         if (drive->quirk_list)
 717                 return;
 718         /* drives in the quirk_list may not like intr setups/cleanups */
 719         hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
 720 }
 721
 722 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
 723 {
 724         ide_hwif_t *hwif = drive->hwif;
 725         struct hpt_info *info = ide_get_hwifdata(hwif);
 726         struct pci_dev *dev = hwif->pci_dev;
 727
 728         if (drive->quirk_list) {
 729                 if (info->revision >= 3) {
 730                         u8 reg5a = 0;
 731                         pci_read_config_byte(dev, 0x5a, &reg5a);
 732                         if (((reg5a & 0x10) >> 4) != mask)
 733                                 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
 734                 } else {
 735                         if (mask) {
 736                                 disable_irq(hwif->irq);
 737                         } else {
 738                                 enable_irq(hwif->irq);
 739                         }
 740                 }
 741         } else {
 742                 if (IDE_CONTROL_REG)
 743                         hwif->OUTB(mask ? (drive->ctl | 2) :
 744                                                  (drive->ctl & ~2),
 745                                                  IDE_CONTROL_REG);
 746         }
 747 }
 748
 749 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
 750 {
 751         ide_hwif_t *hwif        = drive->hwif;
 752         struct hd_driveid *id   = drive->id;
 753
 754         drive->init_speed = 0;
 755
 756         if ((id->capability & 1) && drive->autodma) {
 757
 758                 if (ide_use_dma(drive)) {
 759                         if (config_chipset_for_dma(drive))
 760                                 return hwif->ide_dma_on(drive);
 761                 }
 762
 763                 goto fast_ata_pio;
 764
 765         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 766 fast_ata_pio:
 767                 hpt3xx_tune_drive(drive, 5);
 768                 return hwif->ide_dma_off_quietly(drive);
 769         }
 770         /* IORDY not supported */
 771         return 0;
 772 }
 773
 774 /*
 775  * This is specific to the HPT366 UDMA bios chipset
 776  * by HighPoint|Triones Technologies, Inc.
 777  */
 778 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
 779 {
 780         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 781         u8 reg50h = 0, reg52h = 0, reg5ah = 0;
 782
 783         pci_read_config_byte(dev, 0x50, &reg50h);
 784         pci_read_config_byte(dev, 0x52, &reg52h);
 785         pci_read_config_byte(dev, 0x5a, &reg5ah);
 786         printk("%s: (%s)  reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
 787                 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
 788         if (reg5ah & 0x10)
 789                 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
 790         return __ide_dma_lostirq(drive);
 791 }
 792
 793 static void hpt370_clear_engine (ide_drive_t *drive)
 794 {
 795         u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
 796         pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
 797         udelay(10);
 798 }
 799
 800 static void hpt370_ide_dma_start(ide_drive_t *drive)
 801 {
 802 #ifdef HPT_RESET_STATE_ENGINE
 803         hpt370_clear_engine(drive);
 804 #endif
 805         ide_dma_start(drive);
 806 }
 807
 808 static int hpt370_ide_dma_end (ide_drive_t *drive)
 809 {
 810         ide_hwif_t *hwif        = HWIF(drive);
 811         u8 dma_stat             = hwif->INB(hwif->dma_status);
 812
 813         if (dma_stat & 0x01) {
 814                 /* wait a little */
 815                 udelay(20);
 816                 dma_stat = hwif->INB(hwif->dma_status);
 817         }
 818         if ((dma_stat & 0x01) != 0)
 819                 /* fallthrough */
 820                 (void) HWIF(drive)->ide_dma_timeout(drive);
 821
 822         return __ide_dma_end(drive);
 823 }
 824
 825 static void hpt370_lostirq_timeout (ide_drive_t *drive)
 826 {
 827         ide_hwif_t *hwif        = HWIF(drive);
 828         u8 bfifo = 0, reginfo   = hwif->channel ? 0x56 : 0x52;
 829         u8 dma_stat = 0, dma_cmd = 0;
 830
 831         pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
 832         printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
 833         hpt370_clear_engine(drive);
 834         /* get dma command mode */
 835         dma_cmd = hwif->INB(hwif->dma_command);
 836         /* stop dma */
 837         hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
 838         dma_stat = hwif->INB(hwif->dma_status);
 839         /* clear errors */
 840         hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
 841 }
 842
 843 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
 844 {
 845         hpt370_lostirq_timeout(drive);
 846         hpt370_clear_engine(drive);
 847         return __ide_dma_timeout(drive);
 848 }
 849
 850 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
 851 {
 852         hpt370_lostirq_timeout(drive);
 853         hpt370_clear_engine(drive);
 854         return __ide_dma_lostirq(drive);
 855 }
 856
 857 /* returns 1 if DMA IRQ issued, 0 otherwise */
 858 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
 859 {
 860         ide_hwif_t *hwif        = HWIF(drive);
 861         u16 bfifo               = 0;
 862         u8 reginfo              = hwif->channel ? 0x56 : 0x52;
 863         u8 dma_stat;
 864
 865         pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
 866         if (bfifo & 0x1FF) {
 867 //              printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
 868                 return 0;
 869         }
 870
 871         dma_stat = hwif->INB(hwif->dma_status);
 872         /* return 1 if INTR asserted */
 873         if ((dma_stat & 4) == 4)
 874                 return 1;
 875
 876         if (!drive->waiting_for_dma)
 877                 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
 878                                 drive->name, __FUNCTION__);
 879         return 0;
 880 }
 881
 882 static int hpt374_ide_dma_end (ide_drive_t *drive)
 883 {
 884         struct pci_dev *dev     = HWIF(drive)->pci_dev;
 885         ide_hwif_t *hwif        = HWIF(drive);
 886         u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
 887         u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
 888
 889         pci_read_config_byte(dev, 0x6a, &bwsr_stat);
 890         pci_read_config_byte(dev, mscreg, &msc_stat);
 891         if ((bwsr_stat & bwsr_mask) == bwsr_mask)
 892                 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
 893         return __ide_dma_end(drive);
 894 }
 895
 896 /**
 897  *      hpt3xxn_set_clock       -       perform clock switching dance
 898  *      @hwif: hwif to switch
 899  *      @mode: clocking mode (0x21 for write, 0x23 otherwise)
 900  *
 901  *      Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
 902  *      NOTE: avoid touching the disabled primary channel on HPT371N -- it
 903  *      doesn't physically exist anyway...
 904  */
 905
 906 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
 907 {
 908         u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
 909
 910         if ((scr2 & 0x7f) == mode)
 911                 return;
 912
 913         /* MISC. control register 1 has the channel enable bit... */
 914         mcr1 = hwif->INB(hwif->dma_master + 0x70);
 915
 916         /* Tristate the bus */
 917         if (mcr1 & 0x04)
 918                 hwif->OUTB(0x80, hwif->dma_master + 0x73);
 919         hwif->OUTB(0x80, hwif->dma_master + 0x77);
 920
 921         /* Switch clock and reset channels */
 922         hwif->OUTB(mode, hwif->dma_master + 0x7b);
 923         hwif->OUTB(0xc0, hwif->dma_master + 0x79);
 924
 925         /* Reset state machines */
 926         if (mcr1 & 0x04)
 927                 hwif->OUTB(0x37, hwif->dma_master + 0x70);
 928         hwif->OUTB(0x37, hwif->dma_master + 0x74);
 929
 930         /* Complete reset */
 931         hwif->OUTB(0x00, hwif->dma_master + 0x79);
 932
 933         /* Reconnect channels to bus */
 934         if (mcr1 & 0x04)
 935                 hwif->OUTB(0x00, hwif->dma_master + 0x73);
 936         hwif->OUTB(0x00, hwif->dma_master + 0x77);
 937 }
 938
 939 /**
 940  *      hpt3xxn_rw_disk         -       prepare for I/O
 941  *      @drive: drive for command
 942  *      @rq: block request structure
 943  *
 944  *      This is called when a disk I/O is issued to HPT3xxN.
 945  *      We need it because of the clock switching.
 946  */
 947
 948 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
 949 {
 950         ide_hwif_t *hwif        = HWIF(drive);
 951         u8 wantclock            = rq_data_dir(rq) ? 0x23 : 0x21;
 952
 953         hpt3xxn_set_clock(hwif, wantclock);
 954 }
 955
 956 /*
 957  * Since SUN Cobalt is attempting to do this operation, I should disclose
 958  * this has been a long time ago Thu Jul 27 16:40:57 2000 was the patch date
 959  * HOTSWAP ATA Infrastructure.
 960  */
 961
 962 static void hpt3xx_reset (ide_drive_t *drive)
 963 {
 964 }
 965
 966 static int hpt3xx_tristate (ide_drive_t * drive, int state)
 967 {
 968         ide_hwif_t *hwif        = HWIF(drive);
 969         struct pci_dev *dev     = hwif->pci_dev;
 970         u8 reg59h = 0, reset    = (hwif->channel) ? 0x80 : 0x40;
 971         u8 regXXh = 0, state_reg= (hwif->channel) ? 0x57 : 0x53;
 972
 973         pci_read_config_byte(dev, 0x59, &reg59h);
 974         pci_read_config_byte(dev, state_reg, &regXXh);
 975
 976         if (state) {
 977                 (void) ide_do_reset(drive);
 978                 pci_write_config_byte(dev, state_reg, regXXh|0x80);
 979                 pci_write_config_byte(dev, 0x59, reg59h|reset);
 980         } else {
 981                 pci_write_config_byte(dev, 0x59, reg59h & ~(reset));
 982                 pci_write_config_byte(dev, state_reg, regXXh & ~(0x80));
 983                 (void) ide_do_reset(drive);
 984         }
 985         return 0;
 986 }
 987
 988 /*
 989  * set/get power state for a drive.
 990  * turning the power off does the following things:
 991  *   1) soft-reset the drive
 992  *   2) tri-states the ide bus
 993  *
 994  * when we turn things back on, we need to re-initialize things.
 995  */
 996 #define TRISTATE_BIT  0x8000
 997 static int hpt370_busproc(ide_drive_t * drive, int state)
 998 {
 999         ide_hwif_t *hwif        = drive->hwif;
1000         struct pci_dev *dev     = hwif->pci_dev;
1001         u8 tristate = 0, resetmask = 0, bus_reg = 0;
1002         u16 tri_reg;
1003
1004         hwif->bus_state = state;
1005
1006         if (hwif->channel) {
1007                 /* secondary channel */
1008                 tristate = 0x56;
1009                 resetmask = 0x80;
1010         } else {
1011                 /* primary channel */
1012                 tristate = 0x52;
1013                 resetmask = 0x40;
1014         }
1015
1016         /* grab status */
1017         pci_read_config_word(dev, tristate, &tri_reg);
1018         pci_read_config_byte(dev, 0x59, &bus_reg);
1019
1020         /* set the state. we don't set it if we don't need to do so.
1021          * make sure that the drive knows that it has failed if it's off */
1022         switch (state) {
1023         case BUSSTATE_ON:
1024                 hwif->drives[0].failures = 0;
1025                 hwif->drives[1].failures = 0;
1026                 if ((bus_reg & resetmask) == 0)
1027                         return 0;
1028                 tri_reg &= ~TRISTATE_BIT;
1029                 bus_reg &= ~resetmask;
1030                 break;
1031         case BUSSTATE_OFF:
1032                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1033                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1034                 if ((tri_reg & TRISTATE_BIT) == 0 && (bus_reg & resetmask))
1035                         return 0;
1036                 tri_reg &= ~TRISTATE_BIT;
1037                 bus_reg |= resetmask;
1038                 break;
1039         case BUSSTATE_TRISTATE:
1040                 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
1041                 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
1042                 if ((tri_reg & TRISTATE_BIT) && (bus_reg & resetmask))
1043                         return 0;
1044                 tri_reg |= TRISTATE_BIT;
1045                 bus_reg |= resetmask;
1046                 break;
1047         }
1048         pci_write_config_byte(dev, 0x59, bus_reg);
1049         pci_write_config_word(dev, tristate, tri_reg);
1050
1051         return 0;
1052 }
1053
1054 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
1055 {
1056         u32 reg1        = 0;
1057         struct hpt_info *info = ide_get_hwifdata(hwif);
1058
1059         pci_read_config_dword(hwif->pci_dev, 0x40, &reg1);
1060
1061         /* detect bus speed by looking at control reg timing: */
1062         switch((reg1 >> 8) & 7) {
1063                 case 5:
1064                         info->speed = forty_base_hpt366;
1065                         break;
1066                 case 9:
1067                         info->speed = twenty_five_base_hpt366;
1068                         break;
1069                 case 7:
1070                 default:
1071                         info->speed = thirty_three_base_hpt366;
1072                         break;
1073         }
1074 }
1075
1076 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1077 {
1078         struct hpt_info *info = ide_get_hwifdata(hwif);
1079         struct pci_dev *dev = hwif->pci_dev;
1080         int adjust, i;
1081         u16 freq;
1082         u32 pll;
1083         u8 reg5bh = 0, mcr1 = 0;
1084
1085         /*
1086          * default to pci clock. make sure MA15/16 are set to output
1087          * to prevent drives having problems with 40-pin cables. Needed
1088          * for some drives such as IBM-DTLA which will not enter ready
1089          * state on reset when PDIAG is a input.
1090          *
1091          * ToDo: should we set 0x21 when using PLL mode ?
1092          */
1093         pci_write_config_byte(dev, 0x5b, 0x23);
1094
1095         /*
1096          * set up the PLL. we need to adjust it so that it's stable.
1097          * freq = Tpll * 192 / Tpci
1098          *
1099          * Todo. For non x86 should probably check the dword is
1100          * set to 0xABCDExxx indicating the BIOS saved f_CNT
1101          */
1102         pci_read_config_word(dev, 0x78, &freq);
1103         freq &= 0x1FF;
1104
1105         /*
1106          * HPT3xxN chips use different PCI clock information.
1107          * Currently we always set up the PLL for them.
1108          */
1109
1110         if (info->flags & IS_3xxN) {
1111                 if(freq < 0x55)
1112                         pll = F_LOW_PCI_33;
1113                 else if(freq < 0x70)
1114                         pll = F_LOW_PCI_40;
1115                 else if(freq < 0x7F)
1116                         pll = F_LOW_PCI_50;
1117                 else
1118                         pll = F_LOW_PCI_66;
1119
1120                 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1121         }
1122         else
1123         {
1124                 if(freq < 0x9C)
1125                         pll = F_LOW_PCI_33;
1126                 else if(freq < 0xb0)
1127                         pll = F_LOW_PCI_40;
1128                 else if(freq <0xc8)
1129                         pll = F_LOW_PCI_50;
1130                 else
1131                         pll = F_LOW_PCI_66;
1132
1133                 if (pll == F_LOW_PCI_33) {
1134                         if (info->revision >= 5)
1135                                 info->speed = thirty_three_base_hpt372;
1136                         else if (info->revision >= 4)
1137                                 info->speed = thirty_three_base_hpt370a;
1138                         else
1139                                 info->speed = thirty_three_base_hpt370;
1140                         printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1141                 } else if (pll == F_LOW_PCI_40) {
1142                         /* Unsupported */
1143                 } else if (pll == F_LOW_PCI_50) {
1144                         if (info->revision >= 5)
1145                                 info->speed = fifty_base_hpt372;
1146                         else
1147                                 info->speed = fifty_base_hpt370a;
1148                         printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1149                 } else {
1150                         if (info->revision >= 5) {
1151                                 info->speed = sixty_six_base_hpt372;
1152                                 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1153                         } else
1154                                 printk(KERN_ERR "HPT37x: 66MHz timings not supported.\n");
1155                 }
1156         }
1157
1158         if (pll == F_LOW_PCI_66)
1159                 info->flags |= PCI_66MHZ;
1160
1161         /*
1162          * only try the pll if we don't have a table for the clock
1163          * speed that we're running at. NOTE: the internal PLL will
1164          * result in slow reads when using a 33MHz PCI clock. we also
1165          * don't like to use the PLL because it will cause glitches
1166          * on PRST/SRST when the HPT state engine gets reset.
1167          *
1168          * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1169          * 372 device so we can get ATA133 support
1170          */
1171         if (info->speed)
1172                 goto init_hpt37X_done;
1173
1174         info->flags |= PLL_MODE;
1175
1176         /*
1177          * FIXME: make this work correctly, esp with 372N as per
1178          * reference driver code.
1179          *
1180          * adjust PLL based upon PCI clock, enable it, and wait for
1181          * stabilization.
1182          */
1183         adjust = 0;
1184         freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1185         while (adjust++ < 6) {
1186                 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1187                                        pll | 0x100);
1188
1189                 /* wait for clock stabilization */
1190                 for (i = 0; i < 0x50000; i++) {
1191                         pci_read_config_byte(dev, 0x5b, &reg5bh);
1192                         if (reg5bh & 0x80) {
1193                                 /* spin looking for the clock to destabilize */
1194                                 for (i = 0; i < 0x1000; ++i) {
1195                                         pci_read_config_byte(dev, 0x5b,
1196                                                              &reg5bh);
1197                                         if ((reg5bh & 0x80) == 0)
1198                                                 goto pll_recal;
1199                                 }
1200                                 pci_read_config_dword(dev, 0x5c, &pll);
1201                                 pci_write_config_dword(dev, 0x5c,
1202                                                        pll & ~0x100);
1203                                 pci_write_config_byte(dev, 0x5b, 0x21);
1204                                 if (info->revision >= 8)
1205                                         info->speed = fifty_base_hpt370a;
1206                                 else if (info->revision >= 5)
1207                                         info->speed = fifty_base_hpt372;
1208                                 else if (info->revision >= 4)
1209                                         info->speed = fifty_base_hpt370a;
1210                                 else
1211                                         info->speed = fifty_base_hpt370a;
1212                                 printk("HPT37X: using 50MHz internal PLL\n");
1213                                 goto init_hpt37X_done;
1214                         }
1215                 }
1216 pll_recal:
1217                 if (adjust & 1)
1218                         pll -= (adjust >> 1);
1219                 else
1220                         pll += (adjust >> 1);
1221         }
1222
1223 init_hpt37X_done:
1224         if (!info->speed)
1225                 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1226                        (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1227         /*
1228          * Reset the state engines.
1229          * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1230          */
1231         pci_read_config_byte(dev, 0x50, &mcr1);
1232         if (mcr1 & 0x04)
1233                 pci_write_config_byte(dev, 0x50, 0x37);
1234         pci_write_config_byte(dev, 0x54, 0x37);
1235         udelay(100);
1236 }
1237
1238 static int __devinit init_hpt37x(struct pci_dev *dev)
1239 {
1240         u8 reg5ah;
1241
1242         pci_read_config_byte(dev, 0x5a, &reg5ah);
1243         /* interrupt force enable */
1244         pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1245         return 0;
1246 }
1247
1248 static int __devinit init_hpt366(struct pci_dev *dev)
1249 {
1250         u32 reg1        = 0;
1251         u8 drive_fast   = 0;
1252
1253         /*
1254          * Disable the "fast interrupt" prediction.
1255          */
1256         pci_read_config_byte(dev, 0x51, &drive_fast);
1257         if (drive_fast & 0x80)
1258                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1259         pci_read_config_dword(dev, 0x40, &reg1);
1260
1261         return 0;
1262 }
1263
1264 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1265 {
1266         int ret = 0;
1267
1268         /*
1269          * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1270          * We don't seem to be using it.
1271          */
1272         if (dev->resource[PCI_ROM_RESOURCE].start)
1273                 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1274                         dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1275
1276         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1277         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1278         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1279         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1280
1281         if (hpt_revision(dev) >= 3)
1282                 ret = init_hpt37x(dev);
1283         else
1284                 ret = init_hpt366(dev);
1285
1286         if (ret)
1287                 return ret;
1288
1289         return dev->irq;
1290 }
1291
1292 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1293 {
1294         struct pci_dev *dev             = hwif->pci_dev;
1295         struct hpt_info *info           = ide_get_hwifdata(hwif);
1296         u8 ata66 = 0, regmask           = (hwif->channel) ? 0x01 : 0x02;
1297         int serialize                   = HPT_SERIALIZE_IO;
1298
1299         hwif->tuneproc                  = &hpt3xx_tune_drive;
1300         hwif->speedproc                 = &hpt3xx_tune_chipset;
1301         hwif->quirkproc                 = &hpt3xx_quirkproc;
1302         hwif->intrproc                  = &hpt3xx_intrproc;
1303         hwif->maskproc                  = &hpt3xx_maskproc;
1304
1305         /*
1306          * HPT3xxN chips have some complications:
1307          *
1308          * - on 33 MHz PCI we must clock switch
1309          * - on 66 MHz PCI we must NOT use the PCI clock
1310          */
1311         if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1312                 /*
1313                  * Clock is shared between the channels,
1314                  * so we'll have to serialize them... :-(
1315                  */
1316                 serialize = 1;
1317                 hwif->rw_disk = &hpt3xxn_rw_disk;
1318         }
1319
1320         /*
1321          * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1322          * address lines to access an external eeprom.  To read valid
1323          * cable detect state the pins must be enabled as inputs.
1324          */
1325         if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1326                 /*
1327                  * HPT374 PCI function 1
1328                  * - set bit 15 of reg 0x52 to enable TCBLID as input
1329                  * - set bit 15 of reg 0x56 to enable FCBLID as input
1330                  */
1331                 u16 mcr3, mcr6;
1332                 pci_read_config_word(dev, 0x52, &mcr3);
1333                 pci_read_config_word(dev, 0x56, &mcr6);
1334                 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1335                 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1336                 /* now read cable id register */
1337                 pci_read_config_byte(dev, 0x5a, &ata66);
1338                 pci_write_config_word(dev, 0x52, mcr3);
1339                 pci_write_config_word(dev, 0x56, mcr6);
1340         } else if (info->revision >= 3) {
1341                 /*
1342                  * HPT370/372 and 374 pcifn 0
1343                  * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1344                  */
1345                 u8 scr2;
1346                 pci_read_config_byte(dev, 0x5b, &scr2);
1347                 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1348                 /* now read cable id register */
1349                 pci_read_config_byte(dev, 0x5a, &ata66);
1350                 pci_write_config_byte(dev, 0x5b, scr2);
1351         } else {
1352                 pci_read_config_byte(dev, 0x5a, &ata66);
1353         }
1354
1355 #ifdef DEBUG
1356         printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1357                 ata66, (ata66 & regmask) ? "33" : "66",
1358                 PCI_FUNC(hwif->pci_dev->devfn));
1359 #endif /* DEBUG */
1360
1361         /* Serialize access to this device */
1362         if (serialize && hwif->mate)
1363                 hwif->serialized = hwif->mate->serialized = 1;
1364
1365         if (info->revision >= 3) {
1366                 u8 reg5ah = 0;
1367                         pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
1368                 /*
1369                  * set up ioctl for power status.
1370                  * note: power affects both
1371                  * drives on each channel
1372                  */
1373                 hwif->resetproc = &hpt3xx_reset;
1374                 hwif->busproc   = &hpt370_busproc;
1375         } else if (info->revision >= 2) {
1376                 hwif->resetproc = &hpt3xx_reset;
1377                 hwif->busproc   = &hpt3xx_tristate;
1378         } else {
1379                 hwif->resetproc = &hpt3xx_reset;
1380                 hwif->busproc   = &hpt3xx_tristate;
1381         }
1382
1383         if (!hwif->dma_base) {
1384                 hwif->drives[0].autotune = 1;
1385                 hwif->drives[1].autotune = 1;
1386                 return;
1387         }
1388
1389         hwif->ultra_mask = 0x7f;
1390         hwif->mwdma_mask = 0x07;
1391
1392         if (!(hwif->udma_four))
1393                 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1394         hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1395
1396         if (info->revision >= 8) {
1397                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1398                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1399         } else if (info->revision >= 5) {
1400                 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1401                 hwif->ide_dma_end = &hpt374_ide_dma_end;
1402         } else if (info->revision >= 3) {
1403                 hwif->dma_start = &hpt370_ide_dma_start;
1404                 hwif->ide_dma_end = &hpt370_ide_dma_end;
1405                 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1406                 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1407         } else if (info->revision >= 2)
1408                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1409         else
1410                 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1411
1412         if (!noautodma)
1413                 hwif->autodma = 1;
1414         hwif->drives[0].autodma = hwif->autodma;
1415         hwif->drives[1].autodma = hwif->autodma;
1416 }
1417
1418 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1419 {
1420         struct hpt_info *info   = ide_get_hwifdata(hwif);
1421         u8 masterdma    = 0, slavedma = 0;
1422         u8 dma_new      = 0, dma_old = 0;
1423         u8 primary      = hwif->channel ? 0x4b : 0x43;
1424         u8 secondary    = hwif->channel ? 0x4f : 0x47;
1425         unsigned long flags;
1426
1427         if (!dmabase)
1428                 return;
1429
1430         if(info->speed == NULL) {
1431                 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1432                 return;
1433         }
1434
1435         dma_old = hwif->INB(dmabase+2);
1436
1437         local_irq_save(flags);
1438
1439         dma_new = dma_old;
1440         pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1441         pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1442
1443         if (masterdma & 0x30)   dma_new |= 0x20;
1444         if (slavedma & 0x30)    dma_new |= 0x40;
1445         if (dma_new != dma_old)
1446                 hwif->OUTB(dma_new, dmabase+2);
1447
1448         local_irq_restore(flags);
1449
1450         ide_setup_dma(hwif, dmabase, 8);
1451 }
1452
1453 /*
1454  *      We "borrow" this hook in order to set the data structures
1455  *      up early enough before dma or init_hwif calls are made.
1456  */
1457
1458 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1459 {
1460         struct hpt_info *info   = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1461         struct pci_dev  *dev    = hwif->pci_dev;
1462         u16 did                 = dev->device;
1463         u8  rid                 = 0;
1464
1465         if(info == NULL) {
1466                 printk(KERN_WARNING "hpt366: out of memory.\n");
1467                 return;
1468         }
1469         ide_set_hwifdata(hwif, info);
1470
1471         /* Avoid doing the same thing twice. */
1472         if (hwif->channel && hwif->mate) {
1473                 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1474                 return;
1475         }
1476
1477         pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1478
1479         if (( did == PCI_DEVICE_ID_TTI_HPT366  && rid == 6) ||
1480             ((did == PCI_DEVICE_ID_TTI_HPT372  ||
1481               did == PCI_DEVICE_ID_TTI_HPT302  ||
1482               did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1483               did == PCI_DEVICE_ID_TTI_HPT372N)
1484                 info->flags |= IS_3xxN;
1485
1486         info->revision = hpt_revision(dev);
1487
1488         if (info->revision >= 3)
1489                 hpt37x_clocking(hwif);
1490         else
1491                 hpt366_clocking(hwif);
1492 }
1493
1494 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1495 {
1496         struct pci_dev *findev = NULL;
1497
1498         if (PCI_FUNC(dev->devfn) & 1)
1499                 return -ENODEV;
1500
1501         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1502                 if ((findev->vendor == dev->vendor) &&
1503                     (findev->device == dev->device) &&
1504                     ((findev->devfn - dev->devfn) == 1) &&
1505                     (PCI_FUNC(findev->devfn) & 1)) {
1506                         if (findev->irq != dev->irq) {
1507                                 /* FIXME: we need a core pci_set_interrupt() */
1508                                 findev->irq = dev->irq;
1509                                 printk(KERN_WARNING "%s: pci-config space interrupt "
1510                                         "fixed.\n", d->name);
1511                         }
1512                         return ide_setup_pci_devices(dev, findev, d);
1513                 }
1514         }
1515         return ide_setup_pci_device(dev, d);
1516 }
1517
1518 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1519 {
1520         return ide_setup_pci_device(dev, d);
1521 }
1522
1523 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1524 {
1525         u8 mcr1 = 0;
1526
1527         /*
1528          * HPT371 chips physically have only one channel, the secondary one,
1529          * but the primary channel registers do exist!  Go figure...
1530          * So,  we manually disable the non-existing channel here
1531          * (if the BIOS hasn't done this already).
1532          */
1533         pci_read_config_byte(dev, 0x50, &mcr1);
1534         if (mcr1 & 0x04)
1535                 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1536
1537         return ide_setup_pci_device(dev, d);
1538 }
1539
1540 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1541 {
1542         struct pci_dev *findev = NULL;
1543         u8 pin1 = 0, pin2 = 0;
1544         unsigned int class_rev;
1545         char *chipset_names[] = {"HPT366", "HPT366",  "HPT368",
1546                                  "HPT370", "HPT370A", "HPT372",
1547                                  "HPT372N" };
1548
1549         if (PCI_FUNC(dev->devfn) & 1)
1550                 return -ENODEV;
1551
1552         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1553         class_rev &= 0xff;
1554
1555         if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1556                 class_rev = 6;
1557
1558         if(class_rev <= 6)
1559                 d->name = chipset_names[class_rev];
1560
1561         switch(class_rev) {
1562                 case 6:
1563                 case 5:
1564                 case 4:
1565                 case 3:
1566                         goto init_single;
1567                 default:
1568                         break;
1569         }
1570
1571         d->channels = 1;
1572
1573         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1574         while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1575                 if ((findev->vendor == dev->vendor) &&
1576                     (findev->device == dev->device) &&
1577                     ((findev->devfn - dev->devfn) == 1) &&
1578                     (PCI_FUNC(findev->devfn) & 1)) {
1579                         pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1580                         if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1581                                 d->bootable = ON_BOARD;
1582                                 printk("%s: onboard version of chipset, "
1583                                         "pin1=%d pin2=%d\n", d->name,
1584                                         pin1, pin2);
1585                         }
1586                         return ide_setup_pci_devices(dev, findev, d);
1587                 }
1588         }
1589 init_single:
1590         return ide_setup_pci_device(dev, d);
1591 }
1592
1593 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1594         {       /* 0 */
1595                 .name           = "HPT366",
1596                 .init_setup     = init_setup_hpt366,
1597                 .init_chipset   = init_chipset_hpt366,
1598                 .init_iops      = init_iops_hpt366,
1599                 .init_hwif      = init_hwif_hpt366,
1600                 .init_dma       = init_dma_hpt366,
1601                 .channels       = 2,
1602                 .autodma        = AUTODMA,
1603                 .bootable       = OFF_BOARD,
1604                 .extra          = 240
1605         },{     /* 1 */
1606                 .name           = "HPT372A",
1607                 .init_setup     = init_setup_hpt37x,
1608                 .init_chipset   = init_chipset_hpt366,
1609                 .init_iops      = init_iops_hpt366,
1610                 .init_hwif      = init_hwif_hpt366,
1611                 .init_dma       = init_dma_hpt366,
1612                 .channels       = 2,
1613                 .autodma        = AUTODMA,
1614                 .bootable       = OFF_BOARD,
1615         },{     /* 2 */
1616                 .name           = "HPT302",
1617                 .init_setup     = init_setup_hpt37x,
1618                 .init_chipset   = init_chipset_hpt366,
1619                 .init_iops      = init_iops_hpt366,
1620                 .init_hwif      = init_hwif_hpt366,
1621                 .init_dma       = init_dma_hpt366,
1622                 .channels       = 2,
1623                 .autodma        = AUTODMA,
1624                 .bootable       = OFF_BOARD,
1625         },{     /* 3 */
1626                 .name           = "HPT371",
1627                 .init_setup     = init_setup_hpt371,
1628                 .init_chipset   = init_chipset_hpt366,
1629                 .init_iops      = init_iops_hpt366,
1630                 .init_hwif      = init_hwif_hpt366,
1631                 .init_dma       = init_dma_hpt366,
1632                 .channels       = 2,
1633                 .autodma        = AUTODMA,
1634                 .enablebits     = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1635                 .bootable       = OFF_BOARD,
1636         },{     /* 4 */
1637                 .name           = "HPT374",
1638                 .init_setup     = init_setup_hpt374,
1639                 .init_chipset   = init_chipset_hpt366,
1640                 .init_iops      = init_iops_hpt366,
1641                 .init_hwif      = init_hwif_hpt366,
1642                 .init_dma       = init_dma_hpt366,
1643                 .channels       = 2,    /* 4 */
1644                 .autodma        = AUTODMA,
1645                 .bootable       = OFF_BOARD,
1646         },{     /* 5 */
1647                 .name           = "HPT372N",
1648                 .init_setup     = init_setup_hpt37x,
1649                 .init_chipset   = init_chipset_hpt366,
1650                 .init_iops      = init_iops_hpt366,
1651                 .init_hwif      = init_hwif_hpt366,
1652                 .init_dma       = init_dma_hpt366,
1653                 .channels       = 2,    /* 4 */
1654                 .autodma        = AUTODMA,
1655                 .bootable       = OFF_BOARD,
1656         }
1657 };
1658
1659 /**
1660  *      hpt366_init_one -       called when an HPT366 is found
1661  *      @dev: the hpt366 device
1662  *      @id: the matching pci id
1663  *
1664  *      Called when the PCI registration layer (or the IDE initialization)
1665  *      finds a device matching our IDE device tables.
1666  */
1667
1668 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1669 {
1670         ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1671
1672         return d->init_setup(dev, d);
1673 }
1674
1675 static struct pci_device_id hpt366_pci_tbl[] = {
1676         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1677         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1678         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1679         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1680         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1681         { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1682         { 0, },
1683 };
1684 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1685
1686 static struct pci_driver driver = {
1687         .name           = "HPT366_IDE",
1688         .id_table       = hpt366_pci_tbl,
1689         .probe          = hpt366_init_one,
1690 };
1691
1692 static int hpt366_ide_init(void)
1693 {
1694         return ide_pci_register_driver(&driver);
1695 }
1696
1697 module_init(hpt366_ide_init);
1698
1699 MODULE_AUTHOR("Andre Hedrick");
1700 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1701 MODULE_LICENSE("GPL");