2 * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003
4 * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org>
5 * Portions Copyright (C) 2001 Sun Microsystems, Inc.
6 * Portions Copyright (C) 2003 Red Hat Inc
7 * Portions Copyright (C) 2005-2006 MontaVista Software, Inc.
9 * Thanks to HighPoint Technologies for their assistance, and hardware.
10 * Special Thanks to Jon Burchmore in SanDiego for the deep pockets, his
11 * donation of an ABit BP6 mainboard, processor, and memory acellerated
12 * development and support.
15 * HighPoint has its own drivers (open source except for the RAID part)
16 * available from http://www.highpoint-tech.com/BIOS%20+%20Driver/.
17 * This may be useful to anyone wanting to work on this driver, however do not
18 * trust them too much since the code tends to become less and less meaningful
19 * as the time passes... :-/
21 * Note that final HPT370 support was done by force extraction of GPL.
23 * - add function for getting/setting power status of drive
24 * - the HPT370's state machine can get confused. reset it before each dma
25 * xfer to prevent that from happening.
26 * - reset state engine whenever we get an error.
27 * - check for busmaster state at end of dma.
28 * - use new highpoint timings.
29 * - detect bus speed using highpoint register.
30 * - use pll if we don't have a clock table. added a 66MHz table that's
31 * just 2x the 33MHz table.
32 * - removed turnaround. NOTE: we never want to switch between pll and
33 * pci clocks as the chip can glitch in those cases. the highpoint
34 * approved workaround slows everything down too much to be useful. in
35 * addition, we would have to serialize access to each chip.
36 * Adrian Sun <a.sun@sun.com>
38 * add drive timings for 66MHz PCI bus,
39 * fix ATA Cable signal detection, fix incorrect /proc info
40 * add /proc display for per-drive PIO/DMA/UDMA mode and
41 * per-channel ATA-33/66 Cable detect.
42 * Duncan Laurie <void@sun.com>
44 * fixup /proc output for multiple controllers
45 * Tim Hockin <thockin@sun.com>
48 * Reset the hpt366 on error, reset on dma
49 * Fix disabling Fast Interrupt hpt366.
50 * Mike Waychison <crlf@sun.com>
52 * Added support for 372N clocking and clock switching. The 372N needs
53 * different clocks on read/write. This requires overloading rw_disk and
54 * other deeply crazy things. Thanks to <http://www.hoerstreich.de> for
56 * Alan Cox <alan@redhat.com>
58 * - fix the clock turnaround code: it was writing to the wrong ports when
59 * called for the secondary channel, caching the current clock mode per-
60 * channel caused the cached register value to get out of sync with the
61 * actual one, the channels weren't serialized, the turnaround shouldn't
62 * be done on 66 MHz PCI bus
63 * - avoid calibrating PLL twice as the second time results in a wrong PCI
64 * frequency and thus in the wrong timings for the secondary channel
65 * - disable UltraATA/133 for HPT372 by default (50 MHz DPLL clock do not
66 * allow for this speed anyway)
67 * - add support for HPT302N and HPT371N clocking (the same as for HPT372N)
68 * - HPT371/N are single channel chips, so avoid touching the primary channel
69 * which exists only virtually (there's no pins for it)
70 * - fix/remove bad/unused timing tables and use one set of tables for the whole
71 * HPT37x chip family; save space by introducing the separate transfer mode
72 * table in which the mode lookup is done
73 * - fix the hotswap code: it caused RESET- to glitch when tristating the bus,
74 * and for HPT36x the obsolete HDIO_TRISTATE_HWIF handler was called instead
80 #include <linux/types.h>
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/delay.h>
84 #include <linux/timer.h>
86 #include <linux/ioport.h>
87 #include <linux/blkdev.h>
88 #include <linux/hdreg.h>
90 #include <linux/interrupt.h>
91 #include <linux/pci.h>
92 #include <linux/init.h>
93 #include <linux/ide.h>
95 #include <asm/uaccess.h>
99 /* various tuning parameters */
100 #define HPT_RESET_STATE_ENGINE
101 #undef HPT_DELAY_INTERRUPT
102 #define HPT_SERIALIZE_IO 0
104 static const char *quirk_drives[] = {
105 "QUANTUM FIREBALLlct08 08",
106 "QUANTUM FIREBALLP KA6.4",
107 "QUANTUM FIREBALLP LM20.4",
108 "QUANTUM FIREBALLP LM20.5",
112 static const char *bad_ata100_5[] = {
131 static const char *bad_ata66_4[] = {
150 static const char *bad_ata66_3[] = {
155 static const char *bad_ata33[] = {
156 "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3", "Maxtor 90845U3", "Maxtor 90650U2",
157 "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5", "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
158 "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6", "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
160 "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
161 "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7", "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
162 "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5", "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
166 static u8 xfer_speeds[] = {
186 /* Key for bus clock timings
189 * 0:3 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
191 * 4:7 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
193 * 8:11 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
195 * 12:15 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file
197 * 16:18 18:20 udma_cycle_time. Clock cycles for UDMA xfer.
198 * - 21 CLK frequency: 0=ATA clock, 1=dual ATA clock.
199 * 19:21 22:24 pre_high_time. Time to initialize the 1st cycle for PIO and
201 * 22:24 25:27 cmd_pre_high_time. Time to initialize the 1st PIO cycle for
202 * task file register access.
205 * 30 30 PIO MST enable. If set, the chip is in bus master mode during
210 static u32 forty_base_hpt36x[] = {
211 /* XFER_UDMA_6 */ 0x900fd943,
212 /* XFER_UDMA_5 */ 0x900fd943,
213 /* XFER_UDMA_4 */ 0x900fd943,
214 /* XFER_UDMA_3 */ 0x900ad943,
215 /* XFER_UDMA_2 */ 0x900bd943,
216 /* XFER_UDMA_1 */ 0x9008d943,
217 /* XFER_UDMA_0 */ 0x9008d943,
219 /* XFER_MW_DMA_2 */ 0xa008d943,
220 /* XFER_MW_DMA_1 */ 0xa010d955,
221 /* XFER_MW_DMA_0 */ 0xa010d9fc,
223 /* XFER_PIO_4 */ 0xc008d963,
224 /* XFER_PIO_3 */ 0xc010d974,
225 /* XFER_PIO_2 */ 0xc010d997,
226 /* XFER_PIO_1 */ 0xc010d9c7,
227 /* XFER_PIO_0 */ 0xc018d9d9
230 static u32 thirty_three_base_hpt36x[] = {
231 /* XFER_UDMA_6 */ 0x90c9a731,
232 /* XFER_UDMA_5 */ 0x90c9a731,
233 /* XFER_UDMA_4 */ 0x90c9a731,
234 /* XFER_UDMA_3 */ 0x90cfa731,
235 /* XFER_UDMA_2 */ 0x90caa731,
236 /* XFER_UDMA_1 */ 0x90cba731,
237 /* XFER_UDMA_0 */ 0x90c8a731,
239 /* XFER_MW_DMA_2 */ 0xa0c8a731,
240 /* XFER_MW_DMA_1 */ 0xa0c8a732, /* 0xa0c8a733 */
241 /* XFER_MW_DMA_0 */ 0xa0c8a797,
243 /* XFER_PIO_4 */ 0xc0c8a731,
244 /* XFER_PIO_3 */ 0xc0c8a742,
245 /* XFER_PIO_2 */ 0xc0d0a753,
246 /* XFER_PIO_1 */ 0xc0d0a7a3, /* 0xc0d0a793 */
247 /* XFER_PIO_0 */ 0xc0d0a7aa /* 0xc0d0a7a7 */
250 static u32 twenty_five_base_hpt36x[] = {
251 /* XFER_UDMA_6 */ 0x90c98521,
252 /* XFER_UDMA_5 */ 0x90c98521,
253 /* XFER_UDMA_4 */ 0x90c98521,
254 /* XFER_UDMA_3 */ 0x90cf8521,
255 /* XFER_UDMA_2 */ 0x90cf8521,
256 /* XFER_UDMA_1 */ 0x90cb8521,
257 /* XFER_UDMA_0 */ 0x90cb8521,
259 /* XFER_MW_DMA_2 */ 0xa0ca8521,
260 /* XFER_MW_DMA_1 */ 0xa0ca8532,
261 /* XFER_MW_DMA_0 */ 0xa0ca8575,
263 /* XFER_PIO_4 */ 0xc0ca8521,
264 /* XFER_PIO_3 */ 0xc0ca8532,
265 /* XFER_PIO_2 */ 0xc0ca8542,
266 /* XFER_PIO_1 */ 0xc0d08572,
267 /* XFER_PIO_0 */ 0xc0d08585
270 static u32 thirty_three_base_hpt37x[] = {
271 /* XFER_UDMA_6 */ 0x12446231, /* 0x12646231 ?? */
272 /* XFER_UDMA_5 */ 0x12446231,
273 /* XFER_UDMA_4 */ 0x12446231,
274 /* XFER_UDMA_3 */ 0x126c6231,
275 /* XFER_UDMA_2 */ 0x12486231,
276 /* XFER_UDMA_1 */ 0x124c6233,
277 /* XFER_UDMA_0 */ 0x12506297,
279 /* XFER_MW_DMA_2 */ 0x22406c31,
280 /* XFER_MW_DMA_1 */ 0x22406c33,
281 /* XFER_MW_DMA_0 */ 0x22406c97,
283 /* XFER_PIO_4 */ 0x06414e31,
284 /* XFER_PIO_3 */ 0x06414e42,
285 /* XFER_PIO_2 */ 0x06414e53,
286 /* XFER_PIO_1 */ 0x06814e93,
287 /* XFER_PIO_0 */ 0x06814ea7
290 static u32 fifty_base_hpt37x[] = {
291 /* XFER_UDMA_6 */ 0x12848242,
292 /* XFER_UDMA_5 */ 0x12848242,
293 /* XFER_UDMA_4 */ 0x12ac8242,
294 /* XFER_UDMA_3 */ 0x128c8242,
295 /* XFER_UDMA_2 */ 0x120c8242,
296 /* XFER_UDMA_1 */ 0x12148254,
297 /* XFER_UDMA_0 */ 0x121882ea,
299 /* XFER_MW_DMA_2 */ 0x22808242,
300 /* XFER_MW_DMA_1 */ 0x22808254,
301 /* XFER_MW_DMA_0 */ 0x228082ea,
303 /* XFER_PIO_4 */ 0x0a81f442,
304 /* XFER_PIO_3 */ 0x0a81f443,
305 /* XFER_PIO_2 */ 0x0a81f454,
306 /* XFER_PIO_1 */ 0x0ac1f465,
307 /* XFER_PIO_0 */ 0x0ac1f48a
310 static u32 sixty_six_base_hpt37x[] = {
311 /* XFER_UDMA_6 */ 0x1c869c62,
312 /* XFER_UDMA_5 */ 0x1cae9c62, /* 0x1c8a9c62 */
313 /* XFER_UDMA_4 */ 0x1c8a9c62,
314 /* XFER_UDMA_3 */ 0x1c8e9c62,
315 /* XFER_UDMA_2 */ 0x1c929c62,
316 /* XFER_UDMA_1 */ 0x1c9a9c62,
317 /* XFER_UDMA_0 */ 0x1c829c62,
319 /* XFER_MW_DMA_2 */ 0x2c829c62,
320 /* XFER_MW_DMA_1 */ 0x2c829c66,
321 /* XFER_MW_DMA_0 */ 0x2c829d2e,
323 /* XFER_PIO_4 */ 0x0c829c62,
324 /* XFER_PIO_3 */ 0x0c829c84,
325 /* XFER_PIO_2 */ 0x0c829ca6,
326 /* XFER_PIO_1 */ 0x0d029d26,
327 /* XFER_PIO_0 */ 0x0d029d5e
330 #define HPT366_DEBUG_DRIVE_INFO 0
331 #define HPT374_ALLOW_ATA133_6 0
332 #define HPT371_ALLOW_ATA133_6 0
333 #define HPT302_ALLOW_ATA133_6 0
334 #define HPT372_ALLOW_ATA133_6 0
335 #define HPT370_ALLOW_ATA100_5 1
336 #define HPT366_ALLOW_ATA66_4 1
337 #define HPT366_ALLOW_ATA66_3 1
338 #define HPT366_MAX_DEVS 8
340 #define F_LOW_PCI_33 0x23
341 #define F_LOW_PCI_40 0x29
342 #define F_LOW_PCI_50 0x2d
343 #define F_LOW_PCI_66 0x42
346 * Hold all the highpoint quirks and revision information in one
352 u8 max_mode; /* Speeds allowed */
353 int revision; /* Chipset revision */
354 int flags; /* Chipset properties */
363 * This wants fixing so that we do everything not by classrev
364 * (which breaks on the newest chips) but by creating an
365 * enumeration of chip variants and using that
368 static __devinit u32 hpt_revision (struct pci_dev *dev)
371 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
374 switch(dev->device) {
375 /* Remap new 372N onto 372 */
376 case PCI_DEVICE_ID_TTI_HPT372N:
377 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
378 case PCI_DEVICE_ID_TTI_HPT374:
379 class_rev = PCI_DEVICE_ID_TTI_HPT374; break;
380 case PCI_DEVICE_ID_TTI_HPT371:
381 class_rev = PCI_DEVICE_ID_TTI_HPT371; break;
382 case PCI_DEVICE_ID_TTI_HPT302:
383 class_rev = PCI_DEVICE_ID_TTI_HPT302; break;
384 case PCI_DEVICE_ID_TTI_HPT372:
385 class_rev = PCI_DEVICE_ID_TTI_HPT372; break;
392 static int check_in_drive_lists(ide_drive_t *drive, const char **list);
394 static u8 hpt3xx_ratemask (ide_drive_t *drive)
396 ide_hwif_t *hwif = drive->hwif;
397 struct hpt_info *info = ide_get_hwifdata(hwif);
400 /* FIXME: TODO - move this to set info->mode once at boot */
402 if (info->revision >= 8) { /* HPT374 */
403 mode = (HPT374_ALLOW_ATA133_6) ? 4 : 3;
404 } else if (info->revision >= 7) { /* HPT371 */
405 mode = (HPT371_ALLOW_ATA133_6) ? 4 : 3;
406 } else if (info->revision >= 6) { /* HPT302 */
407 mode = (HPT302_ALLOW_ATA133_6) ? 4 : 3;
408 } else if (info->revision >= 5) { /* HPT372 */
409 mode = (HPT372_ALLOW_ATA133_6) ? 4 : 3;
410 } else if (info->revision >= 4) { /* HPT370A */
411 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
412 } else if (info->revision >= 3) { /* HPT370 */
413 mode = (HPT370_ALLOW_ATA100_5) ? 3 : 2;
414 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : mode;
415 } else { /* HPT366 and HPT368 */
416 mode = (check_in_drive_lists(drive, bad_ata33)) ? 0 : 2;
418 if (!eighty_ninty_three(drive) && mode)
419 mode = min(mode, (u8)1);
424 * Note for the future; the SATA hpt37x we must set
425 * either PIO or UDMA modes 0,4,5
428 static u8 hpt3xx_ratefilter (ide_drive_t *drive, u8 speed)
430 ide_hwif_t *hwif = drive->hwif;
431 struct hpt_info *info = ide_get_hwifdata(hwif);
432 u8 mode = hpt3xx_ratemask(drive);
434 if (drive->media != ide_disk)
435 return min(speed, (u8)XFER_PIO_4);
439 speed = min(speed, (u8)XFER_UDMA_6);
442 speed = min(speed, (u8)XFER_UDMA_5);
443 if (info->revision >= 5)
445 if (check_in_drive_lists(drive, bad_ata100_5))
446 speed = min(speed, (u8)XFER_UDMA_4);
449 speed = min(speed, (u8)XFER_UDMA_4);
451 * CHECK ME, Does this need to be set to 5 ??
453 if (info->revision >= 3)
455 if ((check_in_drive_lists(drive, bad_ata66_4)) ||
456 (!(HPT366_ALLOW_ATA66_4)))
457 speed = min(speed, (u8)XFER_UDMA_3);
458 if ((check_in_drive_lists(drive, bad_ata66_3)) ||
459 (!(HPT366_ALLOW_ATA66_3)))
460 speed = min(speed, (u8)XFER_UDMA_2);
463 speed = min(speed, (u8)XFER_UDMA_2);
465 * CHECK ME, Does this need to be set to 5 ??
467 if (info->revision >= 3)
469 if (check_in_drive_lists(drive, bad_ata33))
470 speed = min(speed, (u8)XFER_MW_DMA_2);
474 speed = min(speed, (u8)XFER_MW_DMA_2);
480 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
482 struct hd_driveid *id = drive->id;
484 if (quirk_drives == list) {
486 if (strstr(id->model, *list++))
490 if (!strcmp(*list++,id->model))
496 static u32 pci_bus_clock_list(u8 speed, u32 *chipset_table)
501 * Lookup the transfer mode table to get the index into
504 * NOTE: For XFER_PIO_SLOW, PIO mode 0 timings will be used.
506 for (i = 0; i < ARRAY_SIZE(xfer_speeds) - 1; i++)
507 if (xfer_speeds[i] == speed)
509 return chipset_table[i];
512 static int hpt36x_tune_chipset(ide_drive_t *drive, u8 xferspeed)
514 ide_hwif_t *hwif = drive->hwif;
515 struct pci_dev *dev = hwif->pci_dev;
516 struct hpt_info *info = ide_get_hwifdata(hwif);
517 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
518 u8 regtime = (drive->select.b.unit & 0x01) ? 0x44 : 0x40;
519 u8 regfast = (hwif->channel) ? 0x55 : 0x51;
521 u32 reg1 = 0, reg2 = 0;
524 * Disable the "fast interrupt" prediction.
526 pci_read_config_byte(dev, regfast, &drive_fast);
527 if (drive_fast & 0x80)
528 pci_write_config_byte(dev, regfast, drive_fast & ~0x80);
530 reg2 = pci_bus_clock_list(speed, info->speed);
533 * Disable on-chip PIO FIFO/buffer
534 * (to avoid problems handling I/O errors later)
536 pci_read_config_dword(dev, regtime, ®1);
537 if (speed >= XFER_MW_DMA_0) {
538 reg2 = (reg2 & ~0xc0000000) | (reg1 & 0xc0000000);
540 reg2 = (reg2 & ~0x30070000) | (reg1 & 0x30070000);
544 pci_write_config_dword(dev, regtime, reg2);
546 return ide_config_drive_speed(drive, speed);
549 static int hpt370_tune_chipset(ide_drive_t *drive, u8 xferspeed)
551 ide_hwif_t *hwif = drive->hwif;
552 struct pci_dev *dev = hwif->pci_dev;
553 struct hpt_info *info = ide_get_hwifdata(hwif);
554 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
555 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
556 u8 drive_pci = 0x40 + (drive->dn * 4);
557 u8 new_fast = 0, drive_fast = 0;
558 u32 list_conf = 0, drive_conf = 0;
559 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
562 * Disable the "fast interrupt" prediction.
563 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
565 pci_read_config_byte(dev, regfast, &drive_fast);
566 new_fast = drive_fast;
570 #ifdef HPT_DELAY_INTERRUPT
574 if ((new_fast & 0x01) == 0)
577 if (new_fast != drive_fast)
578 pci_write_config_byte(dev, regfast, new_fast);
580 list_conf = pci_bus_clock_list(speed, info->speed);
582 pci_read_config_dword(dev, drive_pci, &drive_conf);
583 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
585 if (speed < XFER_MW_DMA_0)
586 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
587 pci_write_config_dword(dev, drive_pci, list_conf);
589 return ide_config_drive_speed(drive, speed);
592 static int hpt372_tune_chipset(ide_drive_t *drive, u8 xferspeed)
594 ide_hwif_t *hwif = drive->hwif;
595 struct pci_dev *dev = hwif->pci_dev;
596 struct hpt_info *info = ide_get_hwifdata(hwif);
597 u8 speed = hpt3xx_ratefilter(drive, xferspeed);
598 u8 regfast = (drive->hwif->channel) ? 0x55 : 0x51;
599 u8 drive_fast = 0, drive_pci = 0x40 + (drive->dn * 4);
600 u32 list_conf = 0, drive_conf = 0;
601 u32 conf_mask = (speed >= XFER_MW_DMA_0) ? 0xc0000000 : 0x30070000;
604 * Disable the "fast interrupt" prediction.
605 * don't holdoff on interrupts. (== 0x01 despite what the docs say)
607 pci_read_config_byte(dev, regfast, &drive_fast);
609 pci_write_config_byte(dev, regfast, drive_fast);
611 list_conf = pci_bus_clock_list(speed, info->speed);
612 pci_read_config_dword(dev, drive_pci, &drive_conf);
613 list_conf = (list_conf & ~conf_mask) | (drive_conf & conf_mask);
614 if (speed < XFER_MW_DMA_0)
615 list_conf &= ~0x80000000; /* Disable on-chip PIO FIFO/buffer */
616 pci_write_config_dword(dev, drive_pci, list_conf);
618 return ide_config_drive_speed(drive, speed);
621 static int hpt3xx_tune_chipset (ide_drive_t *drive, u8 speed)
623 ide_hwif_t *hwif = drive->hwif;
624 struct hpt_info *info = ide_get_hwifdata(hwif);
626 if (info->revision >= 8)
627 return hpt372_tune_chipset(drive, speed); /* not a typo */
628 else if (info->revision >= 5)
629 return hpt372_tune_chipset(drive, speed);
630 else if (info->revision >= 3)
631 return hpt370_tune_chipset(drive, speed);
632 else /* hpt368: hpt_minimum_revision(dev, 2) */
633 return hpt36x_tune_chipset(drive, speed);
636 static void hpt3xx_tune_drive (ide_drive_t *drive, u8 pio)
638 pio = ide_get_best_pio_mode(drive, 255, pio, NULL);
639 (void) hpt3xx_tune_chipset(drive, (XFER_PIO_0 + pio));
643 * This allows the configuration of ide_pci chipset registers
644 * for cards that learn about the drive's UDMA, DMA, PIO capabilities
645 * after the drive is reported by the OS. Initially for designed for
646 * HPT366 UDMA chipset by HighPoint|Triones Technologies, Inc.
648 * check_in_drive_lists(drive, bad_ata66_4)
649 * check_in_drive_lists(drive, bad_ata66_3)
650 * check_in_drive_lists(drive, bad_ata33)
653 static int config_chipset_for_dma (ide_drive_t *drive)
655 u8 speed = ide_dma_speed(drive, hpt3xx_ratemask(drive));
656 ide_hwif_t *hwif = drive->hwif;
657 struct hpt_info *info = ide_get_hwifdata(hwif);
662 /* If we don't have any timings we can't do a lot */
663 if (info->speed == NULL)
666 (void) hpt3xx_tune_chipset(drive, speed);
667 return ide_dma_enable(drive);
670 static int hpt3xx_quirkproc (ide_drive_t *drive)
672 return ((int) check_in_drive_lists(drive, quirk_drives));
675 static void hpt3xx_intrproc (ide_drive_t *drive)
677 ide_hwif_t *hwif = drive->hwif;
679 if (drive->quirk_list)
681 /* drives in the quirk_list may not like intr setups/cleanups */
682 hwif->OUTB(drive->ctl|2, IDE_CONTROL_REG);
685 static void hpt3xx_maskproc (ide_drive_t *drive, int mask)
687 ide_hwif_t *hwif = drive->hwif;
688 struct hpt_info *info = ide_get_hwifdata(hwif);
689 struct pci_dev *dev = hwif->pci_dev;
691 if (drive->quirk_list) {
692 if (info->revision >= 3) {
694 pci_read_config_byte(dev, 0x5a, ®5a);
695 if (((reg5a & 0x10) >> 4) != mask)
696 pci_write_config_byte(dev, 0x5a, mask ? (reg5a | 0x10) : (reg5a & ~0x10));
699 disable_irq(hwif->irq);
701 enable_irq(hwif->irq);
706 hwif->OUTB(mask ? (drive->ctl | 2) :
712 static int hpt366_config_drive_xfer_rate (ide_drive_t *drive)
714 ide_hwif_t *hwif = drive->hwif;
715 struct hd_driveid *id = drive->id;
717 drive->init_speed = 0;
719 if ((id->capability & 1) && drive->autodma) {
721 if (ide_use_dma(drive)) {
722 if (config_chipset_for_dma(drive))
723 return hwif->ide_dma_on(drive);
728 } else if ((id->capability & 8) || (id->field_valid & 2)) {
730 hpt3xx_tune_drive(drive, 5);
731 return hwif->ide_dma_off_quietly(drive);
733 /* IORDY not supported */
738 * This is specific to the HPT366 UDMA bios chipset
739 * by HighPoint|Triones Technologies, Inc.
741 static int hpt366_ide_dma_lostirq (ide_drive_t *drive)
743 struct pci_dev *dev = HWIF(drive)->pci_dev;
744 u8 reg50h = 0, reg52h = 0, reg5ah = 0;
746 pci_read_config_byte(dev, 0x50, ®50h);
747 pci_read_config_byte(dev, 0x52, ®52h);
748 pci_read_config_byte(dev, 0x5a, ®5ah);
749 printk("%s: (%s) reg50h=0x%02x, reg52h=0x%02x, reg5ah=0x%02x\n",
750 drive->name, __FUNCTION__, reg50h, reg52h, reg5ah);
752 pci_write_config_byte(dev, 0x5a, reg5ah & ~0x10);
753 return __ide_dma_lostirq(drive);
756 static void hpt370_clear_engine (ide_drive_t *drive)
758 u8 regstate = HWIF(drive)->channel ? 0x54 : 0x50;
759 pci_write_config_byte(HWIF(drive)->pci_dev, regstate, 0x37);
763 static void hpt370_ide_dma_start(ide_drive_t *drive)
765 #ifdef HPT_RESET_STATE_ENGINE
766 hpt370_clear_engine(drive);
768 ide_dma_start(drive);
771 static int hpt370_ide_dma_end (ide_drive_t *drive)
773 ide_hwif_t *hwif = HWIF(drive);
774 u8 dma_stat = hwif->INB(hwif->dma_status);
776 if (dma_stat & 0x01) {
779 dma_stat = hwif->INB(hwif->dma_status);
781 if ((dma_stat & 0x01) != 0)
783 (void) HWIF(drive)->ide_dma_timeout(drive);
785 return __ide_dma_end(drive);
788 static void hpt370_lostirq_timeout (ide_drive_t *drive)
790 ide_hwif_t *hwif = HWIF(drive);
791 u8 bfifo = 0, reginfo = hwif->channel ? 0x56 : 0x52;
792 u8 dma_stat = 0, dma_cmd = 0;
794 pci_read_config_byte(HWIF(drive)->pci_dev, reginfo, &bfifo);
795 printk(KERN_DEBUG "%s: %d bytes in FIFO\n", drive->name, bfifo);
796 hpt370_clear_engine(drive);
797 /* get dma command mode */
798 dma_cmd = hwif->INB(hwif->dma_command);
800 hwif->OUTB(dma_cmd & ~0x1, hwif->dma_command);
801 dma_stat = hwif->INB(hwif->dma_status);
803 hwif->OUTB(dma_stat | 0x6, hwif->dma_status);
806 static int hpt370_ide_dma_timeout (ide_drive_t *drive)
808 hpt370_lostirq_timeout(drive);
809 hpt370_clear_engine(drive);
810 return __ide_dma_timeout(drive);
813 static int hpt370_ide_dma_lostirq (ide_drive_t *drive)
815 hpt370_lostirq_timeout(drive);
816 hpt370_clear_engine(drive);
817 return __ide_dma_lostirq(drive);
820 /* returns 1 if DMA IRQ issued, 0 otherwise */
821 static int hpt374_ide_dma_test_irq(ide_drive_t *drive)
823 ide_hwif_t *hwif = HWIF(drive);
825 u8 reginfo = hwif->channel ? 0x56 : 0x52;
828 pci_read_config_word(hwif->pci_dev, reginfo, &bfifo);
830 // printk("%s: %d bytes in FIFO\n", drive->name, bfifo);
834 dma_stat = hwif->INB(hwif->dma_status);
835 /* return 1 if INTR asserted */
836 if ((dma_stat & 4) == 4)
839 if (!drive->waiting_for_dma)
840 printk(KERN_WARNING "%s: (%s) called while not waiting\n",
841 drive->name, __FUNCTION__);
845 static int hpt374_ide_dma_end (ide_drive_t *drive)
847 struct pci_dev *dev = HWIF(drive)->pci_dev;
848 ide_hwif_t *hwif = HWIF(drive);
849 u8 msc_stat = 0, mscreg = hwif->channel ? 0x54 : 0x50;
850 u8 bwsr_stat = 0, bwsr_mask = hwif->channel ? 0x02 : 0x01;
852 pci_read_config_byte(dev, 0x6a, &bwsr_stat);
853 pci_read_config_byte(dev, mscreg, &msc_stat);
854 if ((bwsr_stat & bwsr_mask) == bwsr_mask)
855 pci_write_config_byte(dev, mscreg, msc_stat|0x30);
856 return __ide_dma_end(drive);
860 * hpt3xxn_set_clock - perform clock switching dance
861 * @hwif: hwif to switch
862 * @mode: clocking mode (0x21 for write, 0x23 otherwise)
864 * Switch the DPLL clock on the HPT3xxN devices. This is a right mess.
865 * NOTE: avoid touching the disabled primary channel on HPT371N -- it
866 * doesn't physically exist anyway...
869 static void hpt3xxn_set_clock(ide_hwif_t *hwif, u8 mode)
871 u8 mcr1, scr2 = hwif->INB(hwif->dma_master + 0x7b);
873 if ((scr2 & 0x7f) == mode)
876 /* MISC. control register 1 has the channel enable bit... */
877 mcr1 = hwif->INB(hwif->dma_master + 0x70);
879 /* Tristate the bus */
881 hwif->OUTB(0x80, hwif->dma_master + 0x73);
882 hwif->OUTB(0x80, hwif->dma_master + 0x77);
884 /* Switch clock and reset channels */
885 hwif->OUTB(mode, hwif->dma_master + 0x7b);
886 hwif->OUTB(0xc0, hwif->dma_master + 0x79);
888 /* Reset state machines */
890 hwif->OUTB(0x37, hwif->dma_master + 0x70);
891 hwif->OUTB(0x37, hwif->dma_master + 0x74);
894 hwif->OUTB(0x00, hwif->dma_master + 0x79);
896 /* Reconnect channels to bus */
898 hwif->OUTB(0x00, hwif->dma_master + 0x73);
899 hwif->OUTB(0x00, hwif->dma_master + 0x77);
903 * hpt3xxn_rw_disk - prepare for I/O
904 * @drive: drive for command
905 * @rq: block request structure
907 * This is called when a disk I/O is issued to HPT3xxN.
908 * We need it because of the clock switching.
911 static void hpt3xxn_rw_disk(ide_drive_t *drive, struct request *rq)
913 ide_hwif_t *hwif = HWIF(drive);
914 u8 wantclock = rq_data_dir(rq) ? 0x23 : 0x21;
916 hpt3xxn_set_clock(hwif, wantclock);
920 * Set/get power state for a drive.
922 * When we turn the power back on, we need to re-initialize things.
924 #define TRISTATE_BIT 0x8000
926 static int hpt3xx_busproc(ide_drive_t *drive, int state)
928 ide_hwif_t *hwif = drive->hwif;
929 struct pci_dev *dev = hwif->pci_dev;
930 u8 tristate, resetmask, bus_reg = 0;
933 hwif->bus_state = state;
936 /* secondary channel */
940 /* primary channel */
945 /* Grab the status. */
946 pci_read_config_word(dev, tristate, &tri_reg);
947 pci_read_config_byte(dev, 0x59, &bus_reg);
950 * Set the state. We don't set it if we don't need to do so.
951 * Make sure that the drive knows that it has failed if it's off.
955 if (!(bus_reg & resetmask))
957 hwif->drives[0].failures = hwif->drives[1].failures = 0;
959 pci_write_config_byte(dev, 0x59, bus_reg & ~resetmask);
960 pci_write_config_word(dev, tristate, tri_reg & ~TRISTATE_BIT);
963 if ((bus_reg & resetmask) && !(tri_reg & TRISTATE_BIT))
965 tri_reg &= ~TRISTATE_BIT;
967 case BUSSTATE_TRISTATE:
968 if ((bus_reg & resetmask) && (tri_reg & TRISTATE_BIT))
970 tri_reg |= TRISTATE_BIT;
976 hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
977 hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
979 pci_write_config_word(dev, tristate, tri_reg);
980 pci_write_config_byte(dev, 0x59, bus_reg | resetmask);
984 static void __devinit hpt366_clocking(ide_hwif_t *hwif)
987 struct hpt_info *info = ide_get_hwifdata(hwif);
989 pci_read_config_dword(hwif->pci_dev, 0x40, ®1);
991 /* detect bus speed by looking at control reg timing: */
992 switch((reg1 >> 8) & 7) {
994 info->speed = forty_base_hpt36x;
997 info->speed = twenty_five_base_hpt36x;
1001 info->speed = thirty_three_base_hpt36x;
1006 static void __devinit hpt37x_clocking(ide_hwif_t *hwif)
1008 struct hpt_info *info = ide_get_hwifdata(hwif);
1009 struct pci_dev *dev = hwif->pci_dev;
1013 u8 reg5bh = 0, mcr1 = 0;
1016 * default to pci clock. make sure MA15/16 are set to output
1017 * to prevent drives having problems with 40-pin cables. Needed
1018 * for some drives such as IBM-DTLA which will not enter ready
1019 * state on reset when PDIAG is a input.
1021 * ToDo: should we set 0x21 when using PLL mode ?
1023 pci_write_config_byte(dev, 0x5b, 0x23);
1026 * set up the PLL. we need to adjust it so that it's stable.
1027 * freq = Tpll * 192 / Tpci
1029 * Todo. For non x86 should probably check the dword is
1030 * set to 0xABCDExxx indicating the BIOS saved f_CNT
1032 pci_read_config_word(dev, 0x78, &freq);
1036 * HPT3xxN chips use different PCI clock information.
1037 * Currently we always set up the PLL for them.
1040 if (info->flags & IS_3xxN) {
1043 else if(freq < 0x70)
1045 else if(freq < 0x7F)
1050 printk(KERN_INFO "HPT3xxN detected, FREQ: %d, PLL: %d\n", freq, pll);
1056 else if(freq < 0xb0)
1063 if (pll == F_LOW_PCI_33) {
1064 info->speed = thirty_three_base_hpt37x;
1065 printk(KERN_DEBUG "HPT37X: using 33MHz PCI clock\n");
1066 } else if (pll == F_LOW_PCI_40) {
1068 } else if (pll == F_LOW_PCI_50) {
1069 info->speed = fifty_base_hpt37x;
1070 printk(KERN_DEBUG "HPT37X: using 50MHz PCI clock\n");
1072 info->speed = sixty_six_base_hpt37x;
1073 printk(KERN_DEBUG "HPT37X: using 66MHz PCI clock\n");
1077 if (pll == F_LOW_PCI_66)
1078 info->flags |= PCI_66MHZ;
1081 * only try the pll if we don't have a table for the clock
1082 * speed that we're running at. NOTE: the internal PLL will
1083 * result in slow reads when using a 33MHz PCI clock. we also
1084 * don't like to use the PLL because it will cause glitches
1085 * on PRST/SRST when the HPT state engine gets reset.
1087 * ToDo: Use 66MHz PLL when ATA133 devices are present on a
1088 * 372 device so we can get ATA133 support
1091 goto init_hpt37X_done;
1093 info->flags |= PLL_MODE;
1096 * FIXME: make this work correctly, esp with 372N as per
1097 * reference driver code.
1099 * adjust PLL based upon PCI clock, enable it, and wait for
1103 freq = (pll < F_LOW_PCI_50) ? 2 : 4;
1104 while (adjust++ < 6) {
1105 pci_write_config_dword(dev, 0x5c, (freq + pll) << 16 |
1108 /* wait for clock stabilization */
1109 for (i = 0; i < 0x50000; i++) {
1110 pci_read_config_byte(dev, 0x5b, ®5bh);
1111 if (reg5bh & 0x80) {
1112 /* spin looking for the clock to destabilize */
1113 for (i = 0; i < 0x1000; ++i) {
1114 pci_read_config_byte(dev, 0x5b,
1116 if ((reg5bh & 0x80) == 0)
1119 pci_read_config_dword(dev, 0x5c, &pll);
1120 pci_write_config_dword(dev, 0x5c,
1122 pci_write_config_byte(dev, 0x5b, 0x21);
1124 info->speed = fifty_base_hpt37x;
1125 printk("HPT37X: using 50MHz internal PLL\n");
1126 goto init_hpt37X_done;
1131 pll -= (adjust >> 1);
1133 pll += (adjust >> 1);
1138 printk(KERN_ERR "HPT37x%s: unknown bus timing [%d %d].\n",
1139 (info->flags & IS_3xxN) ? "N" : "", pll, freq);
1141 * Reset the state engines.
1142 * NOTE: avoid accidentally enabling the primary channel on HPT371N.
1144 pci_read_config_byte(dev, 0x50, &mcr1);
1146 pci_write_config_byte(dev, 0x50, 0x37);
1147 pci_write_config_byte(dev, 0x54, 0x37);
1151 static int __devinit init_hpt37x(struct pci_dev *dev)
1155 pci_read_config_byte(dev, 0x5a, ®5ah);
1156 /* interrupt force enable */
1157 pci_write_config_byte(dev, 0x5a, (reg5ah & ~0x10));
1161 static int __devinit init_hpt366(struct pci_dev *dev)
1167 * Disable the "fast interrupt" prediction.
1169 pci_read_config_byte(dev, 0x51, &drive_fast);
1170 if (drive_fast & 0x80)
1171 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
1172 pci_read_config_dword(dev, 0x40, ®1);
1177 static unsigned int __devinit init_chipset_hpt366(struct pci_dev *dev, const char *name)
1182 * FIXME: Not portable. Also, why do we enable the ROM in the first place?
1183 * We don't seem to be using it.
1185 if (dev->resource[PCI_ROM_RESOURCE].start)
1186 pci_write_config_dword(dev, PCI_ROM_ADDRESS,
1187 dev->resource[PCI_ROM_RESOURCE].start | PCI_ROM_ADDRESS_ENABLE);
1189 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
1190 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
1191 pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
1192 pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
1194 if (hpt_revision(dev) >= 3)
1195 ret = init_hpt37x(dev);
1197 ret = init_hpt366(dev);
1205 static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
1207 struct pci_dev *dev = hwif->pci_dev;
1208 struct hpt_info *info = ide_get_hwifdata(hwif);
1209 u8 ata66 = 0, regmask = (hwif->channel) ? 0x01 : 0x02;
1210 int serialize = HPT_SERIALIZE_IO;
1212 hwif->tuneproc = &hpt3xx_tune_drive;
1213 hwif->speedproc = &hpt3xx_tune_chipset;
1214 hwif->quirkproc = &hpt3xx_quirkproc;
1215 hwif->intrproc = &hpt3xx_intrproc;
1216 hwif->maskproc = &hpt3xx_maskproc;
1219 * HPT3xxN chips have some complications:
1221 * - on 33 MHz PCI we must clock switch
1222 * - on 66 MHz PCI we must NOT use the PCI clock
1224 if ((info->flags & (IS_3xxN | PCI_66MHZ)) == IS_3xxN) {
1226 * Clock is shared between the channels,
1227 * so we'll have to serialize them... :-(
1230 hwif->rw_disk = &hpt3xxn_rw_disk;
1234 * The HPT37x uses the CBLID pins as outputs for MA15/MA16
1235 * address lines to access an external eeprom. To read valid
1236 * cable detect state the pins must be enabled as inputs.
1238 if (info->revision >= 8 && (PCI_FUNC(dev->devfn) & 1)) {
1240 * HPT374 PCI function 1
1241 * - set bit 15 of reg 0x52 to enable TCBLID as input
1242 * - set bit 15 of reg 0x56 to enable FCBLID as input
1245 pci_read_config_word(dev, 0x52, &mcr3);
1246 pci_read_config_word(dev, 0x56, &mcr6);
1247 pci_write_config_word(dev, 0x52, mcr3 | 0x8000);
1248 pci_write_config_word(dev, 0x56, mcr6 | 0x8000);
1249 /* now read cable id register */
1250 pci_read_config_byte(dev, 0x5a, &ata66);
1251 pci_write_config_word(dev, 0x52, mcr3);
1252 pci_write_config_word(dev, 0x56, mcr6);
1253 } else if (info->revision >= 3) {
1255 * HPT370/372 and 374 pcifn 0
1256 * - clear bit 0 of 0x5b to enable P/SCBLID as inputs
1259 pci_read_config_byte(dev, 0x5b, &scr2);
1260 pci_write_config_byte(dev, 0x5b, scr2 & ~1);
1261 /* now read cable id register */
1262 pci_read_config_byte(dev, 0x5a, &ata66);
1263 pci_write_config_byte(dev, 0x5b, scr2);
1265 pci_read_config_byte(dev, 0x5a, &ata66);
1269 printk("HPT366: reg5ah=0x%02x ATA-%s Cable Port%d\n",
1270 ata66, (ata66 & regmask) ? "33" : "66",
1271 PCI_FUNC(hwif->pci_dev->devfn));
1274 /* Serialize access to this device */
1275 if (serialize && hwif->mate)
1276 hwif->serialized = hwif->mate->serialized = 1;
1279 * Set up ioctl for power status.
1280 * NOTE: power affects both drives on each channel.
1282 hwif->busproc = &hpt3xx_busproc;
1284 if (!hwif->dma_base) {
1285 hwif->drives[0].autotune = 1;
1286 hwif->drives[1].autotune = 1;
1290 hwif->ultra_mask = 0x7f;
1291 hwif->mwdma_mask = 0x07;
1293 if (!(hwif->udma_four))
1294 hwif->udma_four = ((ata66 & regmask) ? 0 : 1);
1295 hwif->ide_dma_check = &hpt366_config_drive_xfer_rate;
1297 if (info->revision >= 8) {
1298 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1299 hwif->ide_dma_end = &hpt374_ide_dma_end;
1300 } else if (info->revision >= 5) {
1301 hwif->ide_dma_test_irq = &hpt374_ide_dma_test_irq;
1302 hwif->ide_dma_end = &hpt374_ide_dma_end;
1303 } else if (info->revision >= 3) {
1304 hwif->dma_start = &hpt370_ide_dma_start;
1305 hwif->ide_dma_end = &hpt370_ide_dma_end;
1306 hwif->ide_dma_timeout = &hpt370_ide_dma_timeout;
1307 hwif->ide_dma_lostirq = &hpt370_ide_dma_lostirq;
1308 } else if (info->revision >= 2)
1309 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1311 hwif->ide_dma_lostirq = &hpt366_ide_dma_lostirq;
1315 hwif->drives[0].autodma = hwif->autodma;
1316 hwif->drives[1].autodma = hwif->autodma;
1319 static void __devinit init_dma_hpt366(ide_hwif_t *hwif, unsigned long dmabase)
1321 struct hpt_info *info = ide_get_hwifdata(hwif);
1322 u8 masterdma = 0, slavedma = 0;
1323 u8 dma_new = 0, dma_old = 0;
1324 u8 primary = hwif->channel ? 0x4b : 0x43;
1325 u8 secondary = hwif->channel ? 0x4f : 0x47;
1326 unsigned long flags;
1331 if(info->speed == NULL) {
1332 printk(KERN_WARNING "hpt366: no known IDE timings, disabling DMA.\n");
1336 dma_old = hwif->INB(dmabase+2);
1338 local_irq_save(flags);
1341 pci_read_config_byte(hwif->pci_dev, primary, &masterdma);
1342 pci_read_config_byte(hwif->pci_dev, secondary, &slavedma);
1344 if (masterdma & 0x30) dma_new |= 0x20;
1345 if (slavedma & 0x30) dma_new |= 0x40;
1346 if (dma_new != dma_old)
1347 hwif->OUTB(dma_new, dmabase+2);
1349 local_irq_restore(flags);
1351 ide_setup_dma(hwif, dmabase, 8);
1355 * We "borrow" this hook in order to set the data structures
1356 * up early enough before dma or init_hwif calls are made.
1359 static void __devinit init_iops_hpt366(ide_hwif_t *hwif)
1361 struct hpt_info *info = kzalloc(sizeof(struct hpt_info), GFP_KERNEL);
1362 struct pci_dev *dev = hwif->pci_dev;
1363 u16 did = dev->device;
1367 printk(KERN_WARNING "hpt366: out of memory.\n");
1370 ide_set_hwifdata(hwif, info);
1372 /* Avoid doing the same thing twice. */
1373 if (hwif->channel && hwif->mate) {
1374 memcpy(info, ide_get_hwifdata(hwif->mate), sizeof(struct hpt_info));
1378 pci_read_config_byte(dev, PCI_CLASS_REVISION, &rid);
1380 if (( did == PCI_DEVICE_ID_TTI_HPT366 && rid == 6) ||
1381 ((did == PCI_DEVICE_ID_TTI_HPT372 ||
1382 did == PCI_DEVICE_ID_TTI_HPT302 ||
1383 did == PCI_DEVICE_ID_TTI_HPT371) && rid > 1) ||
1384 did == PCI_DEVICE_ID_TTI_HPT372N)
1385 info->flags |= IS_3xxN;
1387 info->revision = hpt_revision(dev);
1389 if (info->revision >= 3)
1390 hpt37x_clocking(hwif);
1392 hpt366_clocking(hwif);
1395 static int __devinit init_setup_hpt374(struct pci_dev *dev, ide_pci_device_t *d)
1397 struct pci_dev *findev = NULL;
1399 if (PCI_FUNC(dev->devfn) & 1)
1402 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1403 if ((findev->vendor == dev->vendor) &&
1404 (findev->device == dev->device) &&
1405 ((findev->devfn - dev->devfn) == 1) &&
1406 (PCI_FUNC(findev->devfn) & 1)) {
1407 if (findev->irq != dev->irq) {
1408 /* FIXME: we need a core pci_set_interrupt() */
1409 findev->irq = dev->irq;
1410 printk(KERN_WARNING "%s: pci-config space interrupt "
1411 "fixed.\n", d->name);
1413 return ide_setup_pci_devices(dev, findev, d);
1416 return ide_setup_pci_device(dev, d);
1419 static int __devinit init_setup_hpt37x(struct pci_dev *dev, ide_pci_device_t *d)
1421 return ide_setup_pci_device(dev, d);
1424 static int __devinit init_setup_hpt371(struct pci_dev *dev, ide_pci_device_t *d)
1429 * HPT371 chips physically have only one channel, the secondary one,
1430 * but the primary channel registers do exist! Go figure...
1431 * So, we manually disable the non-existing channel here
1432 * (if the BIOS hasn't done this already).
1434 pci_read_config_byte(dev, 0x50, &mcr1);
1436 pci_write_config_byte(dev, 0x50, (mcr1 & ~0x04));
1438 return ide_setup_pci_device(dev, d);
1441 static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
1443 struct pci_dev *findev = NULL;
1444 u8 pin1 = 0, pin2 = 0;
1445 unsigned int class_rev;
1446 char *chipset_names[] = {"HPT366", "HPT366", "HPT368",
1447 "HPT370", "HPT370A", "HPT372",
1450 if (PCI_FUNC(dev->devfn) & 1)
1453 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1456 if(dev->device == PCI_DEVICE_ID_TTI_HPT372N)
1460 d->name = chipset_names[class_rev];
1474 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin1);
1475 while ((findev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, findev)) != NULL) {
1476 if ((findev->vendor == dev->vendor) &&
1477 (findev->device == dev->device) &&
1478 ((findev->devfn - dev->devfn) == 1) &&
1479 (PCI_FUNC(findev->devfn) & 1)) {
1480 pci_read_config_byte(findev, PCI_INTERRUPT_PIN, &pin2);
1481 if ((pin1 != pin2) && (dev->irq == findev->irq)) {
1482 d->bootable = ON_BOARD;
1483 printk("%s: onboard version of chipset, "
1484 "pin1=%d pin2=%d\n", d->name,
1487 return ide_setup_pci_devices(dev, findev, d);
1491 return ide_setup_pci_device(dev, d);
1494 static ide_pci_device_t hpt366_chipsets[] __devinitdata = {
1497 .init_setup = init_setup_hpt366,
1498 .init_chipset = init_chipset_hpt366,
1499 .init_iops = init_iops_hpt366,
1500 .init_hwif = init_hwif_hpt366,
1501 .init_dma = init_dma_hpt366,
1504 .bootable = OFF_BOARD,
1508 .init_setup = init_setup_hpt37x,
1509 .init_chipset = init_chipset_hpt366,
1510 .init_iops = init_iops_hpt366,
1511 .init_hwif = init_hwif_hpt366,
1512 .init_dma = init_dma_hpt366,
1515 .bootable = OFF_BOARD,
1518 .init_setup = init_setup_hpt37x,
1519 .init_chipset = init_chipset_hpt366,
1520 .init_iops = init_iops_hpt366,
1521 .init_hwif = init_hwif_hpt366,
1522 .init_dma = init_dma_hpt366,
1525 .bootable = OFF_BOARD,
1528 .init_setup = init_setup_hpt371,
1529 .init_chipset = init_chipset_hpt366,
1530 .init_iops = init_iops_hpt366,
1531 .init_hwif = init_hwif_hpt366,
1532 .init_dma = init_dma_hpt366,
1535 .enablebits = {{0x50,0x04,0x04}, {0x54,0x04,0x04}},
1536 .bootable = OFF_BOARD,
1539 .init_setup = init_setup_hpt374,
1540 .init_chipset = init_chipset_hpt366,
1541 .init_iops = init_iops_hpt366,
1542 .init_hwif = init_hwif_hpt366,
1543 .init_dma = init_dma_hpt366,
1544 .channels = 2, /* 4 */
1546 .bootable = OFF_BOARD,
1549 .init_setup = init_setup_hpt37x,
1550 .init_chipset = init_chipset_hpt366,
1551 .init_iops = init_iops_hpt366,
1552 .init_hwif = init_hwif_hpt366,
1553 .init_dma = init_dma_hpt366,
1554 .channels = 2, /* 4 */
1556 .bootable = OFF_BOARD,
1561 * hpt366_init_one - called when an HPT366 is found
1562 * @dev: the hpt366 device
1563 * @id: the matching pci id
1565 * Called when the PCI registration layer (or the IDE initialization)
1566 * finds a device matching our IDE device tables.
1569 static int __devinit hpt366_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1571 ide_pci_device_t *d = &hpt366_chipsets[id->driver_data];
1573 return d->init_setup(dev, d);
1576 static struct pci_device_id hpt366_pci_tbl[] = {
1577 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1579 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT302, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1580 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT371, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
1581 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT374, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
1582 { PCI_VENDOR_ID_TTI, PCI_DEVICE_ID_TTI_HPT372N, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5},
1585 MODULE_DEVICE_TABLE(pci, hpt366_pci_tbl);
1587 static struct pci_driver driver = {
1588 .name = "HPT366_IDE",
1589 .id_table = hpt366_pci_tbl,
1590 .probe = hpt366_init_one,
1593 static int hpt366_ide_init(void)
1595 return ide_pci_register_driver(&driver);
1598 module_init(hpt366_ide_init);
1600 MODULE_AUTHOR("Andre Hedrick");
1601 MODULE_DESCRIPTION("PCI driver module for Highpoint HPT366 IDE");
1602 MODULE_LICENSE("GPL");