2 * linux/drivers/ide/pci/cmd64x.c Version 1.43 Mar 10, 2007
4 * cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
5 * Due to massive hardware bugs, UltraDMA is only supported
6 * on the 646U2 and not on the 646U.
8 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * Copyright (C) 1998 David S. Miller (davem@redhat.com)
11 * Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
12 * Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
15 #include <linux/module.h>
16 #include <linux/types.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/hdreg.h>
20 #include <linux/ide.h>
21 #include <linux/init.h>
25 #define DISPLAY_CMD64X_TIMINGS
30 #define cmdprintk(x...) printk(x)
32 #define cmdprintk(x...)
36 * CMD64x specific registers definition.
39 #define CFR_INTR_CH0 0x02
41 #define CNTRL_DIS_RA0 0x40
42 #define CNTRL_DIS_RA1 0x80
43 #define CNTRL_ENA_2ND 0x08
51 #define ARTTIM23_DIS_RA2 0x04
52 #define ARTTIM23_DIS_RA3 0x08
53 #define ARTTIM23_INTR_CH1 0x10
63 #define MRDMODE_INTR_CH0 0x04
64 #define MRDMODE_INTR_CH1 0x08
65 #define MRDMODE_BLK_CH0 0x10
66 #define MRDMODE_BLK_CH1 0x20
68 #define UDIDETCR0 0x73
73 #define UDIDETCR1 0x7B
76 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
77 #include <linux/stat.h>
78 #include <linux/proc_fs.h>
80 static u8 cmd64x_proc = 0;
82 #define CMD_MAX_DEVS 5
84 static struct pci_dev *cmd_devs[CMD_MAX_DEVS];
85 static int n_cmd_devs;
87 static char * print_cmd64x_get_info (char *buf, struct pci_dev *dev, int index)
91 u8 reg53 = 0, reg54 = 0, reg55 = 0, reg56 = 0; /* primary */
92 u8 reg57 = 0, reg58 = 0, reg5b; /* secondary */
93 u8 reg72 = 0, reg73 = 0; /* primary */
94 u8 reg7a = 0, reg7b = 0; /* secondary */
95 u8 reg50 = 0, reg71 = 0; /* extra */
97 p += sprintf(p, "\nController: %d\n", index);
98 p += sprintf(p, "CMD%x Chipset.\n", dev->device);
99 (void) pci_read_config_byte(dev, CFR, ®50);
100 (void) pci_read_config_byte(dev, ARTTIM0, ®53);
101 (void) pci_read_config_byte(dev, DRWTIM0, ®54);
102 (void) pci_read_config_byte(dev, ARTTIM1, ®55);
103 (void) pci_read_config_byte(dev, DRWTIM1, ®56);
104 (void) pci_read_config_byte(dev, ARTTIM2, ®57);
105 (void) pci_read_config_byte(dev, DRWTIM2, ®58);
106 (void) pci_read_config_byte(dev, DRWTIM3, ®5b);
107 (void) pci_read_config_byte(dev, MRDMODE, ®71);
108 (void) pci_read_config_byte(dev, BMIDESR0, ®72);
109 (void) pci_read_config_byte(dev, UDIDETCR0, ®73);
110 (void) pci_read_config_byte(dev, BMIDESR1, ®7a);
111 (void) pci_read_config_byte(dev, UDIDETCR1, ®7b);
113 p += sprintf(p, "--------------- Primary Channel "
114 "---------------- Secondary Channel "
116 p += sprintf(p, " %sabled "
118 (reg72&0x80)?"dis":" en",
119 (reg7a&0x80)?"dis":" en");
120 p += sprintf(p, "--------------- drive0 "
121 "--------- drive1 -------- drive0 "
122 "---------- drive1 ------\n");
123 p += sprintf(p, "DMA enabled: %s %s"
125 (reg72&0x20)?"yes":"no ", (reg72&0x40)?"yes":"no ",
126 (reg7a&0x20)?"yes":"no ", (reg7a&0x40)?"yes":"no ");
128 p += sprintf(p, "DMA Mode: %s(%s) %s(%s)",
129 (reg72&0x20)?((reg73&0x01)?"UDMA":" DMA"):" PIO",
131 ((reg73&0x30)==0x30)?(((reg73&0x35)==0x35)?"3":"0"):
132 ((reg73&0x20)==0x20)?(((reg73&0x25)==0x25)?"3":"1"):
133 ((reg73&0x10)==0x10)?(((reg73&0x15)==0x15)?"4":"2"):
134 ((reg73&0x00)==0x00)?(((reg73&0x05)==0x05)?"5":"2"):
136 (reg72&0x40)?((reg73&0x02)?"UDMA":" DMA"):" PIO",
138 ((reg73&0xC0)==0xC0)?(((reg73&0xC5)==0xC5)?"3":"0"):
139 ((reg73&0x80)==0x80)?(((reg73&0x85)==0x85)?"3":"1"):
140 ((reg73&0x40)==0x40)?(((reg73&0x4A)==0x4A)?"4":"2"):
141 ((reg73&0x00)==0x00)?(((reg73&0x0A)==0x0A)?"5":"2"):
143 p += sprintf(p, " %s(%s) %s(%s)\n",
144 (reg7a&0x20)?((reg7b&0x01)?"UDMA":" DMA"):" PIO",
146 ((reg7b&0x30)==0x30)?(((reg7b&0x35)==0x35)?"3":"0"):
147 ((reg7b&0x20)==0x20)?(((reg7b&0x25)==0x25)?"3":"1"):
148 ((reg7b&0x10)==0x10)?(((reg7b&0x15)==0x15)?"4":"2"):
149 ((reg7b&0x00)==0x00)?(((reg7b&0x05)==0x05)?"5":"2"):
151 (reg7a&0x40)?((reg7b&0x02)?"UDMA":" DMA"):" PIO",
153 ((reg7b&0xC0)==0xC0)?(((reg7b&0xC5)==0xC5)?"3":"0"):
154 ((reg7b&0x80)==0x80)?(((reg7b&0x85)==0x85)?"3":"1"):
155 ((reg7b&0x40)==0x40)?(((reg7b&0x4A)==0x4A)?"4":"2"):
156 ((reg7b&0x00)==0x00)?(((reg7b&0x0A)==0x0A)?"5":"2"):
158 p += sprintf(p, "PIO Mode: %s %s"
161 p += sprintf(p, " %s %s\n",
162 (reg50 & CFR_INTR_CH0) ? "interrupting" : "polling ",
163 (reg57 & ARTTIM23_INTR_CH1) ? "interrupting" : "polling");
164 p += sprintf(p, " %s %s\n",
165 (reg71 & MRDMODE_INTR_CH0) ? "pending" : "clear ",
166 (reg71 & MRDMODE_INTR_CH1) ? "pending" : "clear");
167 p += sprintf(p, " %s %s\n",
168 (reg71 & MRDMODE_BLK_CH0) ? "blocked" : "enabled",
169 (reg71 & MRDMODE_BLK_CH1) ? "blocked" : "enabled");
174 static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
179 p += sprintf(p, "\n");
180 for (i = 0; i < n_cmd_devs; i++) {
181 struct pci_dev *dev = cmd_devs[i];
182 p = print_cmd64x_get_info(p, dev, i);
184 return p-buffer; /* => must be less than 4k! */
187 #endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
189 static u8 quantize_timing(int timing, int quant)
191 return (timing + quant - 1) / quant;
195 * This routine calculates active/recovery counts and then writes them into
196 * the chipset registers.
198 static void program_cycle_times (ide_drive_t *drive, int cycle_time, int active_time)
200 struct pci_dev *dev = HWIF(drive)->pci_dev;
201 int clock_time = 1000 / system_bus_clock();
202 u8 cycle_count, active_count, recovery_count, drwtim;
203 static const u8 recovery_values[] =
204 {15, 15, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 0};
205 static const u8 drwtim_regs[4] = {DRWTIM0, DRWTIM1, DRWTIM2, DRWTIM3};
207 cmdprintk("program_cycle_times parameters: total=%d, active=%d\n",
208 cycle_time, active_time);
210 cycle_count = quantize_timing( cycle_time, clock_time);
211 active_count = quantize_timing(active_time, clock_time);
212 recovery_count = cycle_count - active_count;
215 * In case we've got too long recovery phase, try to lengthen
218 if (recovery_count > 16) {
219 active_count += recovery_count - 16;
222 if (active_count > 16) /* shouldn't actually happen... */
225 cmdprintk("Final counts: total=%d, active=%d, recovery=%d\n",
226 cycle_count, active_count, recovery_count);
229 * Convert values to internal chipset representation
231 recovery_count = recovery_values[recovery_count];
232 active_count &= 0x0f;
234 /* Program the active/recovery counts into the DRWTIM register */
235 drwtim = (active_count << 4) | recovery_count;
236 (void) pci_write_config_byte(dev, drwtim_regs[drive->dn], drwtim);
237 cmdprintk("Write 0x%02x to reg 0x%x\n", drwtim, drwtim_regs[drive->dn]);
241 * This routine selects drive's best PIO mode and writes into the chipset
242 * registers setup/active/recovery timings.
244 static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
246 ide_hwif_t *hwif = HWIF(drive);
247 struct pci_dev *dev = hwif->pci_dev;
249 u8 pio_mode, setup_count, arttim = 0;
250 static const u8 setup_values[] = {0x40, 0x40, 0x40, 0x80, 0, 0xc0};
251 static const u8 arttim_regs[4] = {ARTTIM0, ARTTIM1, ARTTIM23, ARTTIM23};
252 pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
254 cmdprintk("%s: PIO mode wanted %d, selected %d (%d ns)%s\n",
255 drive->name, mode_wanted, pio_mode, pio.cycle_time,
256 pio.overridden ? " (overriding vendor mode)" : "");
258 program_cycle_times(drive, pio.cycle_time,
259 ide_pio_timings[pio_mode].active_time);
261 setup_count = quantize_timing(ide_pio_timings[pio_mode].setup_time,
262 1000 / system_bus_clock());
265 * The primary channel has individual address setup timing registers
266 * for each drive and the hardware selects the slowest timing itself.
267 * The secondary channel has one common register and we have to select
268 * the slowest address setup timing ourselves.
271 ide_drive_t *drives = hwif->drives;
273 drive->drive_data = setup_count;
274 setup_count = max(drives[0].drive_data, drives[1].drive_data);
277 if (setup_count > 5) /* shouldn't actually happen... */
279 cmdprintk("Final address setup count: %d\n", setup_count);
282 * Program the address setup clocks into the ARTTIM registers.
283 * Avoid clearing the secondary channel's interrupt bit.
285 (void) pci_read_config_byte (dev, arttim_regs[drive->dn], &arttim);
287 arttim &= ~ARTTIM23_INTR_CH1;
289 arttim |= setup_values[setup_count];
290 (void) pci_write_config_byte(dev, arttim_regs[drive->dn], arttim);
291 cmdprintk("Write 0x%02x to reg 0x%x\n", arttim, arttim_regs[drive->dn]);
297 * Attempts to set drive's PIO mode.
298 * Special cases are 8: prefetch off, 9: prefetch on (both never worked),
299 * and 255: auto-select best mode (used at boot time).
301 static void cmd64x_tune_drive (ide_drive_t *drive, u8 pio)
304 * Filter out the prefetch control values
305 * to prevent PIO5 from being programmed
307 if (pio == 8 || pio == 9)
310 pio = cmd64x_tune_pio(drive, pio);
311 (void) ide_config_drive_speed(drive, XFER_PIO_0 + pio);
314 static u8 cmd64x_ratemask (ide_drive_t *drive)
316 struct pci_dev *dev = HWIF(drive)->pci_dev;
319 switch(dev->device) {
320 case PCI_DEVICE_ID_CMD_649:
323 case PCI_DEVICE_ID_CMD_648:
326 case PCI_DEVICE_ID_CMD_643:
329 case PCI_DEVICE_ID_CMD_646:
331 unsigned int class_rev = 0;
332 pci_read_config_dword(dev,
333 PCI_CLASS_REVISION, &class_rev);
336 * UltraDMA only supported on PCI646U and PCI646U2, which
337 * correspond to revisions 0x03, 0x05 and 0x07 respectively.
338 * Actually, although the CMD tech support people won't
339 * tell me the details, the 0x03 revision cannot support
340 * UDMA correctly without hardware modifications, and even
341 * then it only works with Quantum disks due to some
342 * hold time assumptions in the 646U part which are fixed
345 * So we only do UltraDMA on revision 0x05 and 0x07 chipsets.
358 if (!eighty_ninty_three(drive))
359 mode = min(mode, (u8)1);
363 static int cmd64x_tune_chipset (ide_drive_t *drive, u8 speed)
365 ide_hwif_t *hwif = HWIF(drive);
366 struct pci_dev *dev = hwif->pci_dev;
367 u8 unit = drive->dn & 0x01;
368 u8 regU = 0, pciU = hwif->channel ? UDIDETCR1 : UDIDETCR0;
370 speed = ide_rate_filter(cmd64x_ratemask(drive), speed);
372 if (speed >= XFER_SW_DMA_0) {
373 (void) pci_read_config_byte(dev, pciU, ®U);
374 regU &= ~(unit ? 0xCA : 0x35);
379 regU |= unit ? 0x0A : 0x05;
382 regU |= unit ? 0x4A : 0x15;
385 regU |= unit ? 0x8A : 0x25;
388 regU |= unit ? 0x42 : 0x11;
391 regU |= unit ? 0x82 : 0x21;
394 regU |= unit ? 0xC2 : 0x31;
397 program_cycle_times(drive, 120, 70);
400 program_cycle_times(drive, 150, 80);
403 program_cycle_times(drive, 480, 215);
411 (void) cmd64x_tune_pio(drive, speed - XFER_PIO_0);
417 if (speed >= XFER_SW_DMA_0)
418 (void) pci_write_config_byte(dev, pciU, regU);
420 return ide_config_drive_speed(drive, speed);
423 static int config_chipset_for_dma (ide_drive_t *drive)
425 u8 speed = ide_dma_speed(drive, cmd64x_ratemask(drive));
430 if (cmd64x_tune_chipset(drive, speed))
433 return ide_dma_enable(drive);
436 static int cmd64x_config_drive_for_dma (ide_drive_t *drive)
438 if (ide_use_dma(drive) && config_chipset_for_dma(drive))
441 if (ide_use_fast_pio(drive))
442 cmd64x_tune_drive(drive, 255);
447 static int cmd64x_alt_dma_status (struct pci_dev *dev)
449 switch(dev->device) {
450 case PCI_DEVICE_ID_CMD_648:
451 case PCI_DEVICE_ID_CMD_649:
459 static int cmd64x_ide_dma_end (ide_drive_t *drive)
461 u8 dma_stat = 0, dma_cmd = 0;
462 ide_hwif_t *hwif = HWIF(drive);
463 struct pci_dev *dev = hwif->pci_dev;
465 drive->waiting_for_dma = 0;
466 /* read DMA command state */
467 dma_cmd = inb(hwif->dma_command);
469 outb(dma_cmd & ~1, hwif->dma_command);
471 dma_stat = inb(hwif->dma_status);
472 /* clear the INTR & ERROR bits */
473 outb(dma_stat | 6, hwif->dma_status);
474 if (cmd64x_alt_dma_status(dev)) {
476 u8 dma_mask = (hwif->channel) ? ARTTIM23_INTR_CH1 :
478 u8 dma_reg = (hwif->channel) ? ARTTIM2 : CFR;
479 (void) pci_read_config_byte(dev, dma_reg, &dma_intr);
480 /* clear the INTR bit */
481 (void) pci_write_config_byte(dev, dma_reg, dma_intr|dma_mask);
483 /* purge DMA mappings */
484 ide_destroy_dmatable(drive);
485 /* verify good DMA status */
486 return (dma_stat & 7) != 4;
489 static int cmd64x_ide_dma_test_irq (ide_drive_t *drive)
491 ide_hwif_t *hwif = HWIF(drive);
492 struct pci_dev *dev = hwif->pci_dev;
493 u8 dma_alt_stat = 0, mask = (hwif->channel) ? MRDMODE_INTR_CH1 :
495 u8 dma_stat = inb(hwif->dma_status);
497 (void) pci_read_config_byte(dev, MRDMODE, &dma_alt_stat);
499 printk("%s: dma_stat: 0x%02x dma_alt_stat: "
500 "0x%02x mask: 0x%02x\n", drive->name,
501 dma_stat, dma_alt_stat, mask);
503 if (!(dma_alt_stat & mask))
506 /* return 1 if INTR asserted */
507 if ((dma_stat & 4) == 4)
514 * ASUS P55T2P4D with CMD646 chipset revision 0x01 requires the old
515 * event order for DMA transfers.
518 static int cmd646_1_ide_dma_end (ide_drive_t *drive)
520 ide_hwif_t *hwif = HWIF(drive);
521 u8 dma_stat = 0, dma_cmd = 0;
523 drive->waiting_for_dma = 0;
525 dma_stat = inb(hwif->dma_status);
526 /* read DMA command state */
527 dma_cmd = inb(hwif->dma_command);
529 outb(dma_cmd & ~1, hwif->dma_command);
530 /* clear the INTR & ERROR bits */
531 outb(dma_stat | 6, hwif->dma_status);
532 /* and free any DMA resources */
533 ide_destroy_dmatable(drive);
534 /* verify good DMA status */
535 return (dma_stat & 7) != 4;
538 static unsigned int __devinit init_chipset_cmd64x(struct pci_dev *dev, const char *name)
543 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
546 switch(dev->device) {
547 case PCI_DEVICE_ID_CMD_643:
549 case PCI_DEVICE_ID_CMD_646:
550 printk(KERN_INFO "%s: chipset revision 0x%02X, ", name, class_rev);
554 printk("UltraDMA Capable");
557 printk("MultiWord DMA Force Limited");
561 printk("MultiWord DMA Limited, IRQ workaround enabled");
566 case PCI_DEVICE_ID_CMD_648:
567 case PCI_DEVICE_ID_CMD_649:
573 /* Set a good latency timer and cache line size value. */
574 (void) pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
575 /* FIXME: pci_set_master() to ensure a good latency timer value */
577 /* Setup interrupts. */
578 (void) pci_read_config_byte(dev, MRDMODE, &mrdmode);
580 (void) pci_write_config_byte(dev, MRDMODE, mrdmode);
582 /* Use MEMORY READ LINE for reads.
583 * NOTE: Although not mentioned in the PCI0646U specs,
584 * these bits are write only and won't be read
585 * back as set or not. The PCI0646U2 specs clarify
588 (void) pci_write_config_byte(dev, MRDMODE, mrdmode | 0x02);
590 /* Set reasonable active/recovery/address-setup values. */
591 (void) pci_write_config_byte(dev, ARTTIM0, 0x40);
592 (void) pci_write_config_byte(dev, DRWTIM0, 0x3f);
593 (void) pci_write_config_byte(dev, ARTTIM1, 0x40);
594 (void) pci_write_config_byte(dev, DRWTIM1, 0x3f);
596 (void) pci_write_config_byte(dev, ARTTIM23, 0x1c);
598 (void) pci_write_config_byte(dev, ARTTIM23, 0x5c);
600 (void) pci_write_config_byte(dev, DRWTIM23, 0x3f);
601 (void) pci_write_config_byte(dev, DRWTIM3, 0x3f);
603 (void) pci_write_config_byte(dev, UDIDETCR0, 0xf0);
604 #endif /* CONFIG_PPC */
606 #if defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS)
608 cmd_devs[n_cmd_devs++] = dev;
612 ide_pci_create_host_proc("cmd64x", cmd64x_get_info);
614 #endif /* DISPLAY_CMD64X_TIMINGS && CONFIG_PROC_FS */
619 static unsigned int __devinit ata66_cmd64x(ide_hwif_t *hwif)
621 u8 ata66 = 0, mask = (hwif->channel) ? 0x02 : 0x01;
623 switch(hwif->pci_dev->device) {
624 case PCI_DEVICE_ID_CMD_643:
625 case PCI_DEVICE_ID_CMD_646:
630 pci_read_config_byte(hwif->pci_dev, BMIDECSR, &ata66);
631 return (ata66 & mask) ? 1 : 0;
634 static void __devinit init_hwif_cmd64x(ide_hwif_t *hwif)
636 struct pci_dev *dev = hwif->pci_dev;
637 unsigned int class_rev;
640 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
643 hwif->tuneproc = &cmd64x_tune_drive;
644 hwif->speedproc = &cmd64x_tune_chipset;
646 hwif->drives[0].autotune = hwif->drives[1].autotune = 1;
653 hwif->ultra_mask = 0x3f;
654 hwif->mwdma_mask = 0x07;
656 if (dev->device == PCI_DEVICE_ID_CMD_643)
657 hwif->ultra_mask = 0x80;
658 if (dev->device == PCI_DEVICE_ID_CMD_646)
659 hwif->ultra_mask = (class_rev > 0x04) ? 0x07 : 0x80;
660 if (dev->device == PCI_DEVICE_ID_CMD_648)
661 hwif->ultra_mask = 0x1f;
663 hwif->ide_dma_check = &cmd64x_config_drive_for_dma;
664 if (!(hwif->udma_four))
665 hwif->udma_four = ata66_cmd64x(hwif);
667 if (dev->device == PCI_DEVICE_ID_CMD_646) {
668 hwif->chipset = ide_cmd646;
669 if (class_rev == 0x01) {
670 hwif->ide_dma_end = &cmd646_1_ide_dma_end;
672 hwif->ide_dma_end = &cmd64x_ide_dma_end;
673 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
676 hwif->ide_dma_end = &cmd64x_ide_dma_end;
677 hwif->ide_dma_test_irq = &cmd64x_ide_dma_test_irq;
683 hwif->drives[0].autodma = hwif->autodma;
684 hwif->drives[1].autodma = hwif->autodma;
687 static ide_pci_device_t cmd64x_chipsets[] __devinitdata = {
690 .init_chipset = init_chipset_cmd64x,
691 .init_hwif = init_hwif_cmd64x,
694 .bootable = ON_BOARD,
697 .init_chipset = init_chipset_cmd64x,
698 .init_hwif = init_hwif_cmd64x,
701 .enablebits = {{0x00,0x00,0x00}, {0x51,0x80,0x80}},
702 .bootable = ON_BOARD,
705 .init_chipset = init_chipset_cmd64x,
706 .init_hwif = init_hwif_cmd64x,
709 .bootable = ON_BOARD,
712 .init_chipset = init_chipset_cmd64x,
713 .init_hwif = init_hwif_cmd64x,
716 .bootable = ON_BOARD,
720 static int __devinit cmd64x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
722 return ide_setup_pci_device(dev, &cmd64x_chipsets[id->driver_data]);
725 static struct pci_device_id cmd64x_pci_tbl[] = {
726 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
727 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
728 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
729 { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_CMD_649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
732 MODULE_DEVICE_TABLE(pci, cmd64x_pci_tbl);
734 static struct pci_driver driver = {
735 .name = "CMD64x_IDE",
736 .id_table = cmd64x_pci_tbl,
737 .probe = cmd64x_init_one,
740 static int __init cmd64x_ide_init(void)
742 return ide_pci_register_driver(&driver);
745 module_init(cmd64x_ide_init);
747 MODULE_AUTHOR("Eddie Dost, David Miller, Andre Hedrick");
748 MODULE_DESCRIPTION("PCI driver module for CMD64x IDE");
749 MODULE_LICENSE("GPL");