2 * linux/drivers/ide/mips/au1xxx-ide.c version 01.30.00 Aug. 02 2005
4 * BRIEF MODULE DESCRIPTION
5 * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
7 * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
9 * This program is free software; you can redistribute it and/or modify it under
10 * the terms of the GNU General Public License as published by the Free Software
11 * Foundation; either version 2 of the License, or (at your option) any later
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
15 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
16 * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
17 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
18 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
19 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
20 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
21 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
22 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
23 * POSSIBILITY OF SUCH DAMAGE.
25 * You should have received a copy of the GNU General Public License along with
26 * this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
29 * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
30 * Interface and Linux Device Driver" Application Note.
32 #include <linux/types.h>
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/delay.h>
36 #include <linux/platform_device.h>
38 #include <linux/init.h>
39 #include <linux/ide.h>
40 #include <linux/sysdev.h>
42 #include <linux/dma-mapping.h>
44 #include "ide-timing.h"
47 #include <asm/mach-au1x00/au1xxx.h>
48 #include <asm/mach-au1x00/au1xxx_dbdma.h>
50 #include <asm/mach-au1x00/au1xxx_ide.h>
52 #define DRV_NAME "au1200-ide"
53 #define DRV_VERSION "1.0"
54 #define DRV_AUTHOR "Enrico Walther <enrico.walther@amd.com> / Pete Popov <ppopov@embeddedalley.com>"
56 /* enable the burstmode in the dbdma */
57 #define IDE_AU1XXX_BURSTMODE 1
59 static _auide_hwif auide_hwif;
60 static int dbdma_init_done;
62 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
64 void auide_insw(unsigned long port, void *addr, u32 count)
66 _auide_hwif *ahwif = &auide_hwif;
70 if(!put_dest_flags(ahwif->rx_chan, (void*)addr, count << 1,
72 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
75 ctp = *((chan_tab_t **)ahwif->rx_chan);
77 while (dp->dscr_cmd0 & DSCR_CMD0_V)
79 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
82 void auide_outsw(unsigned long port, void *addr, u32 count)
84 _auide_hwif *ahwif = &auide_hwif;
88 if(!put_source_flags(ahwif->tx_chan, (void*)addr,
89 count << 1, DDMA_FLAGS_NOIE)) {
90 printk(KERN_ERR "%s failed %d\n", __FUNCTION__, __LINE__);
93 ctp = *((chan_tab_t **)ahwif->tx_chan);
95 while (dp->dscr_cmd0 & DSCR_CMD0_V)
97 ctp->cur_ptr = au1xxx_ddma_get_nextptr_virt(dp);
102 static void au1xxx_set_pio_mode(ide_drive_t *drive, const u8 pio)
104 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
109 mem_sttime = SBC_IDE_TIMING(PIO0);
111 /* set configuration for RCS2# */
112 mem_stcfg |= TS_MASK;
113 mem_stcfg &= ~TCSOE_MASK;
114 mem_stcfg &= ~TOECS_MASK;
115 mem_stcfg |= SBC_IDE_PIO0_TCSOE | SBC_IDE_PIO0_TOECS;
119 mem_sttime = SBC_IDE_TIMING(PIO1);
121 /* set configuration for RCS2# */
122 mem_stcfg |= TS_MASK;
123 mem_stcfg &= ~TCSOE_MASK;
124 mem_stcfg &= ~TOECS_MASK;
125 mem_stcfg |= SBC_IDE_PIO1_TCSOE | SBC_IDE_PIO1_TOECS;
129 mem_sttime = SBC_IDE_TIMING(PIO2);
131 /* set configuration for RCS2# */
132 mem_stcfg &= ~TS_MASK;
133 mem_stcfg &= ~TCSOE_MASK;
134 mem_stcfg &= ~TOECS_MASK;
135 mem_stcfg |= SBC_IDE_PIO2_TCSOE | SBC_IDE_PIO2_TOECS;
139 mem_sttime = SBC_IDE_TIMING(PIO3);
141 /* set configuration for RCS2# */
142 mem_stcfg &= ~TS_MASK;
143 mem_stcfg &= ~TCSOE_MASK;
144 mem_stcfg &= ~TOECS_MASK;
145 mem_stcfg |= SBC_IDE_PIO3_TCSOE | SBC_IDE_PIO3_TOECS;
150 mem_sttime = SBC_IDE_TIMING(PIO4);
152 /* set configuration for RCS2# */
153 mem_stcfg &= ~TS_MASK;
154 mem_stcfg &= ~TCSOE_MASK;
155 mem_stcfg &= ~TOECS_MASK;
156 mem_stcfg |= SBC_IDE_PIO4_TCSOE | SBC_IDE_PIO4_TOECS;
160 au_writel(mem_sttime,MEM_STTIME2);
161 au_writel(mem_stcfg,MEM_STCFG2);
164 static void auide_set_dma_mode(ide_drive_t *drive, const u8 speed)
166 int mem_sttime = 0, mem_stcfg = au_readl(MEM_STCFG2);
169 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
171 mem_sttime = SBC_IDE_TIMING(MDMA2);
173 /* set configuration for RCS2# */
174 mem_stcfg &= ~TS_MASK;
175 mem_stcfg &= ~TCSOE_MASK;
176 mem_stcfg &= ~TOECS_MASK;
177 mem_stcfg |= SBC_IDE_MDMA2_TCSOE | SBC_IDE_MDMA2_TOECS;
181 mem_sttime = SBC_IDE_TIMING(MDMA1);
183 /* set configuration for RCS2# */
184 mem_stcfg &= ~TS_MASK;
185 mem_stcfg &= ~TCSOE_MASK;
186 mem_stcfg &= ~TOECS_MASK;
187 mem_stcfg |= SBC_IDE_MDMA1_TCSOE | SBC_IDE_MDMA1_TOECS;
191 mem_sttime = SBC_IDE_TIMING(MDMA0);
193 /* set configuration for RCS2# */
194 mem_stcfg |= TS_MASK;
195 mem_stcfg &= ~TCSOE_MASK;
196 mem_stcfg &= ~TOECS_MASK;
197 mem_stcfg |= SBC_IDE_MDMA0_TCSOE | SBC_IDE_MDMA0_TOECS;
203 au_writel(mem_sttime,MEM_STTIME2);
204 au_writel(mem_stcfg,MEM_STCFG2);
208 * Multi-Word DMA + DbDMA functions
211 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
212 static int auide_build_dmatable(ide_drive_t *drive)
214 int i, iswrite, count = 0;
215 ide_hwif_t *hwif = HWIF(drive);
217 struct request *rq = HWGROUP(drive)->rq;
219 _auide_hwif *ahwif = (_auide_hwif*)hwif->hwif_data;
220 struct scatterlist *sg;
222 iswrite = (rq_data_dir(rq) == WRITE);
223 /* Save for interrupt context */
224 ahwif->drive = drive;
226 hwif->sg_nents = i = ide_build_sglist(drive, rq);
231 /* fill the descriptors */
233 while (i && sg_dma_len(sg)) {
237 cur_addr = sg_dma_address(sg);
238 cur_len = sg_dma_len(sg);
241 u32 flags = DDMA_FLAGS_NOIE;
242 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
244 if (++count >= PRD_ENTRIES) {
245 printk(KERN_WARNING "%s: DMA table too small\n",
247 goto use_pio_instead;
250 /* Lets enable intr for the last descriptor only */
252 flags = DDMA_FLAGS_IE;
254 flags = DDMA_FLAGS_NOIE;
257 if(!put_source_flags(ahwif->tx_chan,
260 printk(KERN_ERR "%s failed %d\n",
261 __FUNCTION__, __LINE__);
265 if(!put_dest_flags(ahwif->rx_chan,
268 printk(KERN_ERR "%s failed %d\n",
269 __FUNCTION__, __LINE__);
284 ide_destroy_dmatable(drive);
286 return 0; /* revert to PIO for this request */
289 static int auide_dma_end(ide_drive_t *drive)
291 ide_hwif_t *hwif = HWIF(drive);
293 if (hwif->sg_nents) {
294 ide_destroy_dmatable(drive);
301 static void auide_dma_start(ide_drive_t *drive )
306 static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command)
308 /* issue cmd to drive */
309 ide_execute_command(drive, command, &ide_dma_intr,
313 static int auide_dma_setup(ide_drive_t *drive)
315 struct request *rq = HWGROUP(drive)->rq;
317 if (!auide_build_dmatable(drive)) {
318 ide_map_sg(drive, rq);
322 drive->waiting_for_dma = 1;
326 static u8 auide_mdma_filter(ide_drive_t *drive)
329 * FIXME: ->white_list and ->black_list are based on completely bogus
330 * ->ide_dma_check implementation which didn't set neither the host
331 * controller timings nor the device for the desired transfer mode.
333 * They should be either removed or 0x00 MWDMA mask should be
334 * returned for devices on the ->black_list.
337 if (dbdma_init_done == 0) {
338 auide_hwif.white_list = ide_in_drive_list(drive->id,
340 auide_hwif.black_list = ide_in_drive_list(drive->id,
342 auide_hwif.drive = drive;
343 auide_ddma_init(&auide_hwif);
347 /* Is the drive in our DMA black list? */
348 if (auide_hwif.black_list)
349 printk(KERN_WARNING "%s: Disabling DMA for %s (blacklisted)\n",
350 drive->name, drive->id->model);
352 return drive->hwif->mwdma_mask;
355 static int auide_dma_test_irq(ide_drive_t *drive)
357 if (drive->waiting_for_dma == 0)
358 printk(KERN_WARNING "%s: ide_dma_test_irq \
359 called while not waiting\n", drive->name);
361 /* If dbdma didn't execute the STOP command yet, the
362 * active bit is still set
364 drive->waiting_for_dma++;
365 if (drive->waiting_for_dma >= DMA_WAIT_TIMEOUT) {
366 printk(KERN_WARNING "%s: timeout waiting for ddma to \
367 complete\n", drive->name);
374 static void auide_dma_host_set(ide_drive_t *drive, int on)
378 static void auide_dma_lost_irq(ide_drive_t *drive)
380 printk(KERN_ERR "%s: IRQ lost\n", drive->name);
383 static void auide_ddma_tx_callback(int irq, void *param)
385 _auide_hwif *ahwif = (_auide_hwif*)param;
386 ahwif->drive->waiting_for_dma = 0;
389 static void auide_ddma_rx_callback(int irq, void *param)
391 _auide_hwif *ahwif = (_auide_hwif*)param;
392 ahwif->drive->waiting_for_dma = 0;
395 #endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
397 static void auide_init_dbdma_dev(dbdev_tab_t *dev, u32 dev_id, u32 tsize, u32 devwidth, u32 flags)
399 dev->dev_id = dev_id;
400 dev->dev_physaddr = (u32)AU1XXX_ATA_PHYS_ADDR;
401 dev->dev_intlevel = 0;
402 dev->dev_intpolarity = 0;
403 dev->dev_tsize = tsize;
404 dev->dev_devwidth = devwidth;
405 dev->dev_flags = flags;
408 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
410 static void auide_dma_timeout(ide_drive_t *drive)
412 ide_hwif_t *hwif = HWIF(drive);
414 printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
416 if (hwif->ide_dma_test_irq(drive))
419 hwif->ide_dma_end(drive);
423 static int auide_ddma_init(_auide_hwif *auide) {
425 dbdev_tab_t source_dev_tab, target_dev_tab;
426 u32 dev_id, tsize, devwidth, flags;
427 ide_hwif_t *hwif = auide->hwif;
429 dev_id = AU1XXX_ATA_DDMA_REQ;
431 if (auide->white_list || auide->black_list) {
439 printk(KERN_ERR "au1xxx-ide: %s is not on ide driver whitelist.\n",auide_hwif.drive->id->model);
440 printk(KERN_ERR " please read 'Documentation/mips/AU1xxx_IDE.README'");
443 #ifdef IDE_AU1XXX_BURSTMODE
444 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
446 flags = DEV_FLAGS_SYNC;
449 /* setup dev_tab for tx channel */
450 auide_init_dbdma_dev( &source_dev_tab,
452 tsize, devwidth, DEV_FLAGS_OUT | flags);
453 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
455 auide_init_dbdma_dev( &source_dev_tab,
457 tsize, devwidth, DEV_FLAGS_IN | flags);
458 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
460 /* We also need to add a target device for the DMA */
461 auide_init_dbdma_dev( &target_dev_tab,
462 (u32)DSCR_CMD0_ALWAYS,
463 tsize, devwidth, DEV_FLAGS_ANYUSE);
464 auide->target_dev_id = au1xxx_ddma_add_device(&target_dev_tab);
466 /* Get a channel for TX */
467 auide->tx_chan = au1xxx_dbdma_chan_alloc(auide->target_dev_id,
469 auide_ddma_tx_callback,
472 /* Get a channel for RX */
473 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
474 auide->target_dev_id,
475 auide_ddma_rx_callback,
478 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
480 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
483 hwif->dmatable_cpu = dma_alloc_coherent(hwif->dev,
484 PRD_ENTRIES * PRD_BYTES, /* 1 Page */
485 &hwif->dmatable_dma, GFP_KERNEL);
487 au1xxx_dbdma_start( auide->tx_chan );
488 au1xxx_dbdma_start( auide->rx_chan );
494 static int auide_ddma_init( _auide_hwif *auide )
496 dbdev_tab_t source_dev_tab;
499 #ifdef IDE_AU1XXX_BURSTMODE
500 flags = DEV_FLAGS_SYNC | DEV_FLAGS_BURSTABLE;
502 flags = DEV_FLAGS_SYNC;
505 /* setup dev_tab for tx channel */
506 auide_init_dbdma_dev( &source_dev_tab,
507 (u32)DSCR_CMD0_ALWAYS,
508 8, 32, DEV_FLAGS_OUT | flags);
509 auide->tx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
511 auide_init_dbdma_dev( &source_dev_tab,
512 (u32)DSCR_CMD0_ALWAYS,
513 8, 32, DEV_FLAGS_IN | flags);
514 auide->rx_dev_id = au1xxx_ddma_add_device( &source_dev_tab );
516 /* Get a channel for TX */
517 auide->tx_chan = au1xxx_dbdma_chan_alloc(DSCR_CMD0_ALWAYS,
522 /* Get a channel for RX */
523 auide->rx_chan = au1xxx_dbdma_chan_alloc(auide->rx_dev_id,
528 auide->tx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->tx_chan,
530 auide->rx_desc_head = (void*)au1xxx_dbdma_ring_alloc(auide->rx_chan,
533 au1xxx_dbdma_start( auide->tx_chan );
534 au1xxx_dbdma_start( auide->rx_chan );
540 static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif)
543 unsigned long *ata_regs = hw->io_ports;
546 for (i = 0; i < IDE_CONTROL_OFFSET; i++) {
547 *ata_regs++ = ahwif->regbase + (i << AU1XXX_ATA_REG_OFFSET);
550 /* set the Alternative Status register */
551 *ata_regs = ahwif->regbase + (14 << AU1XXX_ATA_REG_OFFSET);
554 static int au_ide_probe(struct device *dev)
556 struct platform_device *pdev = to_platform_device(dev);
557 _auide_hwif *ahwif = &auide_hwif;
559 struct resource *res;
561 u8 idx[4] = { 0xff, 0xff, 0xff, 0xff };
564 #if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
565 char *mode = "MWDMA2";
566 #elif defined(CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA)
567 char *mode = "PIO+DDMA(offload)";
570 memset(&auide_hwif, 0, sizeof(_auide_hwif));
571 ahwif->irq = platform_get_irq(pdev, 0);
573 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
576 pr_debug("%s %d: no base address\n", DRV_NAME, pdev->id);
580 if (ahwif->irq < 0) {
581 pr_debug("%s %d: no IRQ\n", DRV_NAME, pdev->id);
586 if (!request_mem_region (res->start, res->end-res->start, pdev->name)) {
587 pr_debug("%s: request_mem_region failed\n", DRV_NAME);
592 ahwif->regbase = (u32)ioremap(res->start, res->end-res->start);
593 if (ahwif->regbase == 0) {
598 /* FIXME: This might possibly break PCMCIA IDE devices */
600 hwif = &ide_hwifs[pdev->id];
602 memset(&hw, 0, sizeof(hw));
603 auide_setup_ports(&hw, ahwif);
606 hw.chipset = ide_au1xxx;
608 ide_init_port_hw(hwif, &hw);
612 hwif->ultra_mask = 0x0; /* Disable Ultra DMA */
613 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
614 hwif->mwdma_mask = 0x07; /* Multimode-2 DMA */
615 hwif->swdma_mask = 0x00;
617 hwif->mwdma_mask = 0x0;
618 hwif->swdma_mask = 0x0;
621 hwif->pio_mask = ATA_PIO4;
622 hwif->host_flags = IDE_HFLAG_POST_SET_MODE;
624 hwif->drives[0].unmask = 1;
625 hwif->drives[1].unmask = 1;
627 /* hold should be on in all cases */
632 /* If the user has selected DDMA assisted copies,
633 then set up a few local I/O function entry points
636 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
637 hwif->INSW = auide_insw;
638 hwif->OUTSW = auide_outsw;
641 hwif->set_pio_mode = &au1xxx_set_pio_mode;
642 hwif->set_dma_mode = &auide_set_dma_mode;
644 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
645 hwif->dma_timeout = &auide_dma_timeout;
647 hwif->mdma_filter = &auide_mdma_filter;
649 hwif->dma_host_set = &auide_dma_host_set;
650 hwif->dma_exec_cmd = &auide_dma_exec_cmd;
651 hwif->dma_start = &auide_dma_start;
652 hwif->ide_dma_end = &auide_dma_end;
653 hwif->dma_setup = &auide_dma_setup;
654 hwif->ide_dma_test_irq = &auide_dma_test_irq;
655 hwif->dma_lost_irq = &auide_dma_lost_irq;
658 hwif->select_data = 0; /* no chipset-specific code */
659 hwif->config_data = 0; /* no chipset-specific code */
661 hwif->drives[0].autotune = 1; /* 1=autotune, 2=noautotune, 0=default */
662 hwif->drives[1].autotune = 1;
664 hwif->drives[0].no_io_32bit = 1;
665 hwif->drives[1].no_io_32bit = 1;
667 auide_hwif.hwif = hwif;
668 hwif->hwif_data = &auide_hwif;
670 #ifdef CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
671 auide_ddma_init(&auide_hwif);
675 idx[0] = hwif->index;
679 dev_set_drvdata(dev, hwif);
681 printk(KERN_INFO "Au1xxx IDE(builtin) configured for %s\n", mode );
687 static int au_ide_remove(struct device *dev)
689 struct platform_device *pdev = to_platform_device(dev);
690 struct resource *res;
691 ide_hwif_t *hwif = dev_get_drvdata(dev);
692 _auide_hwif *ahwif = &auide_hwif;
694 ide_unregister(hwif->index);
696 iounmap((void *)ahwif->regbase);
698 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
699 release_mem_region(res->start, res->end - res->start);
704 static struct device_driver au1200_ide_driver = {
705 .name = "au1200-ide",
706 .bus = &platform_bus_type,
707 .probe = au_ide_probe,
708 .remove = au_ide_remove,
711 static int __init au_ide_init(void)
713 return driver_register(&au1200_ide_driver);
716 static void __exit au_ide_exit(void)
718 driver_unregister(&au1200_ide_driver);
721 MODULE_LICENSE("GPL");
722 MODULE_DESCRIPTION("AU1200 IDE driver");
724 module_init(au_ide_init);
725 module_exit(au_ide_exit);