drivers/ide/arm/icside.c

   1 /*
   2  * linux/drivers/ide/arm/icside.c
   3  *
   4  * Copyright (c) 1996-2004 Russell King.
   5  *
   6  * Please note that this platform does not support 32-bit IDE IO.
   7  */
   8
   9 #include <linux/string.h>
  10 #include <linux/module.h>
  11 #include <linux/ioport.h>
  12 #include <linux/slab.h>
  13 #include <linux/blkdev.h>
  14 #include <linux/errno.h>
  15 #include <linux/hdreg.h>
  16 #include <linux/ide.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/device.h>
  19 #include <linux/init.h>
  20 #include <linux/scatterlist.h>
  21
  22 #include <asm/dma.h>
  23 #include <asm/ecard.h>
  24 #include <asm/io.h>
  25
  26 #define ICS_IDENT_OFFSET                0x2280
  27
  28 #define ICS_ARCIN_V5_INTRSTAT           0x0000
  29 #define ICS_ARCIN_V5_INTROFFSET         0x0004
  30 #define ICS_ARCIN_V5_IDEOFFSET          0x2800
  31 #define ICS_ARCIN_V5_IDEALTOFFSET       0x2b80
  32 #define ICS_ARCIN_V5_IDESTEPPING        6
  33
  34 #define ICS_ARCIN_V6_IDEOFFSET_1        0x2000
  35 #define ICS_ARCIN_V6_INTROFFSET_1       0x2200
  36 #define ICS_ARCIN_V6_INTRSTAT_1         0x2290
  37 #define ICS_ARCIN_V6_IDEALTOFFSET_1     0x2380
  38 #define ICS_ARCIN_V6_IDEOFFSET_2        0x3000
  39 #define ICS_ARCIN_V6_INTROFFSET_2       0x3200
  40 #define ICS_ARCIN_V6_INTRSTAT_2         0x3290
  41 #define ICS_ARCIN_V6_IDEALTOFFSET_2     0x3380
  42 #define ICS_ARCIN_V6_IDESTEPPING        6
  43
  44 struct cardinfo {
  45         unsigned int dataoffset;
  46         unsigned int ctrloffset;
  47         unsigned int stepping;
  48 };
  49
  50 static struct cardinfo icside_cardinfo_v5 = {
  51         .dataoffset     = ICS_ARCIN_V5_IDEOFFSET,
  52         .ctrloffset     = ICS_ARCIN_V5_IDEALTOFFSET,
  53         .stepping       = ICS_ARCIN_V5_IDESTEPPING,
  54 };
  55
  56 static struct cardinfo icside_cardinfo_v6_1 = {
  57         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_1,
  58         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_1,
  59         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  60 };
  61
  62 static struct cardinfo icside_cardinfo_v6_2 = {
  63         .dataoffset     = ICS_ARCIN_V6_IDEOFFSET_2,
  64         .ctrloffset     = ICS_ARCIN_V6_IDEALTOFFSET_2,
  65         .stepping       = ICS_ARCIN_V6_IDESTEPPING,
  66 };
  67
  68 struct icside_state {
  69         unsigned int channel;
  70         unsigned int enabled;
  71         void __iomem *irq_port;
  72         void __iomem *ioc_base;
  73         unsigned int type;
  74         /* parent device... until the IDE core gets one of its own */
  75         struct device *dev;
  76         ide_hwif_t *hwif[2];
  77 };
  78
  79 #define ICS_TYPE_A3IN   0
  80 #define ICS_TYPE_A3USER 1
  81 #define ICS_TYPE_V6     3
  82 #define ICS_TYPE_V5     15
  83 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
  84
  85 /* ---------------- Version 5 PCB Support Functions --------------------- */
  86 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  87  * Purpose  : enable interrupts from card
  88  */
  89 static void icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
  90 {
  91         struct icside_state *state = ec->irq_data;
  92
  93         writeb(0, state->irq_port + ICS_ARCIN_V5_INTROFFSET);
  94 }
  95
  96 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
  97  * Purpose  : disable interrupts from card
  98  */
  99 static void icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
 100 {
 101         struct icside_state *state = ec->irq_data;
 102
 103         readb(state->irq_port + ICS_ARCIN_V5_INTROFFSET);
 104 }
 105
 106 static const expansioncard_ops_t icside_ops_arcin_v5 = {
 107         .irqenable      = icside_irqenable_arcin_v5,
 108         .irqdisable     = icside_irqdisable_arcin_v5,
 109 };
 110
 111
 112 /* ---------------- Version 6 PCB Support Functions --------------------- */
 113 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 114  * Purpose  : enable interrupts from card
 115  */
 116 static void icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
 117 {
 118         struct icside_state *state = ec->irq_data;
 119         void __iomem *base = state->irq_port;
 120
 121         state->enabled = 1;
 122
 123         switch (state->channel) {
 124         case 0:
 125                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_1);
 126                 readb(base + ICS_ARCIN_V6_INTROFFSET_2);
 127                 break;
 128         case 1:
 129                 writeb(0, base + ICS_ARCIN_V6_INTROFFSET_2);
 130                 readb(base + ICS_ARCIN_V6_INTROFFSET_1);
 131                 break;
 132         }
 133 }
 134
 135 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 136  * Purpose  : disable interrupts from card
 137  */
 138 static void icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
 139 {
 140         struct icside_state *state = ec->irq_data;
 141
 142         state->enabled = 0;
 143
 144         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 145         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 146 }
 147
 148 /* Prototype: icside_irqprobe(struct expansion_card *ec)
 149  * Purpose  : detect an active interrupt from card
 150  */
 151 static int icside_irqpending_arcin_v6(struct expansion_card *ec)
 152 {
 153         struct icside_state *state = ec->irq_data;
 154
 155         return readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_1) & 1 ||
 156                readb(state->irq_port + ICS_ARCIN_V6_INTRSTAT_2) & 1;
 157 }
 158
 159 static const expansioncard_ops_t icside_ops_arcin_v6 = {
 160         .irqenable      = icside_irqenable_arcin_v6,
 161         .irqdisable     = icside_irqdisable_arcin_v6,
 162         .irqpending     = icside_irqpending_arcin_v6,
 163 };
 164
 165 /*
 166  * Handle routing of interrupts.  This is called before
 167  * we write the command to the drive.
 168  */
 169 static void icside_maskproc(ide_drive_t *drive, int mask)
 170 {
 171         ide_hwif_t *hwif = HWIF(drive);
 172         struct icside_state *state = hwif->hwif_data;
 173         unsigned long flags;
 174
 175         local_irq_save(flags);
 176
 177         state->channel = hwif->channel;
 178
 179         if (state->enabled && !mask) {
 180                 switch (hwif->channel) {
 181                 case 0:
 182                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 183                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 184                         break;
 185                 case 1:
 186                         writeb(0, state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 187                         readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 188                         break;
 189                 }
 190         } else {
 191                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_2);
 192                 readb(state->irq_port + ICS_ARCIN_V6_INTROFFSET_1);
 193         }
 194
 195         local_irq_restore(flags);
 196 }
 197
 198 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
 199 /*
 200  * SG-DMA support.
 201  *
 202  * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
 203  * There is only one DMA controller per card, which means that only
 204  * one drive can be accessed at one time.  NOTE! We do not enforce that
 205  * here, but we rely on the main IDE driver spotting that both
 206  * interfaces use the same IRQ, which should guarantee this.
 207  */
 208
 209 static void icside_build_sglist(ide_drive_t *drive, struct request *rq)
 210 {
 211         ide_hwif_t *hwif = drive->hwif;
 212         struct icside_state *state = hwif->hwif_data;
 213         struct scatterlist *sg = hwif->sg_table;
 214
 215         ide_map_sg(drive, rq);
 216
 217         if (rq_data_dir(rq) == READ)
 218                 hwif->sg_dma_direction = DMA_FROM_DEVICE;
 219         else
 220                 hwif->sg_dma_direction = DMA_TO_DEVICE;
 221
 222         hwif->sg_nents = dma_map_sg(state->dev, sg, hwif->sg_nents,
 223                                     hwif->sg_dma_direction);
 224 }
 225
 226 /*
 227  * Configure the IOMD to give the appropriate timings for the transfer
 228  * mode being requested.  We take the advice of the ATA standards, and
 229  * calculate the cycle time based on the transfer mode, and the EIDE
 230  * MW DMA specs that the drive provides in the IDENTIFY command.
 231  *
 232  * We have the following IOMD DMA modes to choose from:
 233  *
 234  *      Type    Active          Recovery        Cycle
 235  *      A       250 (250)       312 (550)       562 (800)
 236  *      B       187             250             437
 237  *      C       125 (125)       125 (375)       250 (500)
 238  *      D       62              125             187
 239  *
 240  * (figures in brackets are actual measured timings)
 241  *
 242  * However, we also need to take care of the read/write active and
 243  * recovery timings:
 244  *
 245  *                      Read    Write
 246  *      Mode    Active  -- Recovery --  Cycle   IOMD type
 247  *      MW0     215     50      215     480     A
 248  *      MW1     80      50      50      150     C
 249  *      MW2     70      25      25      120     C
 250  */
 251 static int icside_set_speed(ide_drive_t *drive, u8 xfer_mode)
 252 {
 253         int on = 0, cycle_time = 0, use_dma_info = 0;
 254
 255         /*
 256          * Limit the transfer speed to MW_DMA_2.
 257          */
 258         if (xfer_mode > XFER_MW_DMA_2)
 259                 xfer_mode = XFER_MW_DMA_2;
 260
 261         switch (xfer_mode) {
 262         case XFER_MW_DMA_2:
 263                 cycle_time = 250;
 264                 use_dma_info = 1;
 265                 break;
 266
 267         case XFER_MW_DMA_1:
 268                 cycle_time = 250;
 269                 use_dma_info = 1;
 270                 break;
 271
 272         case XFER_MW_DMA_0:
 273                 cycle_time = 480;
 274                 break;
 275
 276         case XFER_SW_DMA_2:
 277         case XFER_SW_DMA_1:
 278         case XFER_SW_DMA_0:
 279                 cycle_time = 480;
 280                 break;
 281         }
 282
 283         /*
 284          * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
 285          * take care to note the values in the ID...
 286          */
 287         if (use_dma_info && drive->id->eide_dma_time > cycle_time)
 288                 cycle_time = drive->id->eide_dma_time;
 289
 290         drive->drive_data = cycle_time;
 291
 292         if (cycle_time && ide_config_drive_speed(drive, xfer_mode) == 0)
 293                 on = 1;
 294         else
 295                 drive->drive_data = 480;
 296
 297         printk("%s: %s selected (peak %dMB/s)\n", drive->name,
 298                 ide_xfer_verbose(xfer_mode), 2000 / drive->drive_data);
 299
 300         drive->current_speed = xfer_mode;
 301
 302         return on;
 303 }
 304
 305 static void icside_dma_host_off(ide_drive_t *drive)
 306 {
 307 }
 308
 309 static void icside_dma_off_quietly(ide_drive_t *drive)
 310 {
 311         drive->using_dma = 0;
 312 }
 313
 314 static void icside_dma_host_on(ide_drive_t *drive)
 315 {
 316 }
 317
 318 static int icside_dma_on(ide_drive_t *drive)
 319 {
 320         drive->using_dma = 1;
 321
 322         return 0;
 323 }
 324
 325 static int icside_dma_check(ide_drive_t *drive)
 326 {
 327         struct hd_driveid *id = drive->id;
 328         ide_hwif_t *hwif = HWIF(drive);
 329         int xfer_mode = XFER_PIO_2;
 330         int on;
 331
 332         if (!(id->capability & 1) || !hwif->autodma)
 333                 goto out;
 334
 335         /*
 336          * Consult the list of known "bad" drives
 337          */
 338         if (__ide_dma_bad_drive(drive))
 339                 goto out;
 340
 341         /*
 342          * Enable DMA on any drive that has multiword DMA
 343          */
 344         if (id->field_valid & 2) {
 345                 xfer_mode = ide_max_dma_mode(drive);
 346                 goto out;
 347         }
 348
 349         /*
 350          * Consult the list of known "good" drives
 351          */
 352         if (__ide_dma_good_drive(drive)) {
 353                 if (id->eide_dma_time > 150)
 354                         goto out;
 355                 xfer_mode = XFER_MW_DMA_1;
 356         }
 357
 358 out:
 359         on = icside_set_speed(drive, xfer_mode);
 360
 361         return on ? 0 : -1;
 362 }
 363
 364 static int icside_dma_end(ide_drive_t *drive)
 365 {
 366         ide_hwif_t *hwif = HWIF(drive);
 367         struct icside_state *state = hwif->hwif_data;
 368
 369         drive->waiting_for_dma = 0;
 370
 371         disable_dma(hwif->hw.dma);
 372
 373         /* Teardown mappings after DMA has completed. */
 374         dma_unmap_sg(state->dev, hwif->sg_table, hwif->sg_nents,
 375                      hwif->sg_dma_direction);
 376
 377         return get_dma_residue(hwif->hw.dma) != 0;
 378 }
 379
 380 static void icside_dma_start(ide_drive_t *drive)
 381 {
 382         ide_hwif_t *hwif = HWIF(drive);
 383
 384         /* We can not enable DMA on both channels simultaneously. */
 385         BUG_ON(dma_channel_active(hwif->hw.dma));
 386         enable_dma(hwif->hw.dma);
 387 }
 388
 389 static int icside_dma_setup(ide_drive_t *drive)
 390 {
 391         ide_hwif_t *hwif = HWIF(drive);
 392         struct request *rq = hwif->hwgroup->rq;
 393         unsigned int dma_mode;
 394
 395         if (rq_data_dir(rq))
 396                 dma_mode = DMA_MODE_WRITE;
 397         else
 398                 dma_mode = DMA_MODE_READ;
 399
 400         /*
 401          * We can not enable DMA on both channels.
 402          */
 403         BUG_ON(dma_channel_active(hwif->hw.dma));
 404
 405         icside_build_sglist(drive, rq);
 406
 407         /*
 408          * Ensure that we have the right interrupt routed.
 409          */
 410         icside_maskproc(drive, 0);
 411
 412         /*
 413          * Route the DMA signals to the correct interface.
 414          */
 415         writeb(hwif->select_data, hwif->config_data);
 416
 417         /*
 418          * Select the correct timing for this drive.
 419          */
 420         set_dma_speed(hwif->hw.dma, drive->drive_data);
 421
 422         /*
 423          * Tell the DMA engine about the SG table and
 424          * data direction.
 425          */
 426         set_dma_sg(hwif->hw.dma, hwif->sg_table, hwif->sg_nents);
 427         set_dma_mode(hwif->hw.dma, dma_mode);
 428
 429         drive->waiting_for_dma = 1;
 430
 431         return 0;
 432 }
 433
 434 static void icside_dma_exec_cmd(ide_drive_t *drive, u8 cmd)
 435 {
 436         /* issue cmd to drive */
 437         ide_execute_command(drive, cmd, ide_dma_intr, 2 * WAIT_CMD, NULL);
 438 }
 439
 440 static int icside_dma_test_irq(ide_drive_t *drive)
 441 {
 442         ide_hwif_t *hwif = HWIF(drive);
 443         struct icside_state *state = hwif->hwif_data;
 444
 445         return readb(state->irq_port +
 446                      (hwif->channel ?
 447                         ICS_ARCIN_V6_INTRSTAT_2 :
 448                         ICS_ARCIN_V6_INTRSTAT_1)) & 1;
 449 }
 450
 451 static void icside_dma_timeout(ide_drive_t *drive)
 452 {
 453         printk(KERN_ERR "%s: DMA timeout occurred: ", drive->name);
 454
 455         if (icside_dma_test_irq(drive))
 456                 return;
 457
 458         ide_dump_status(drive, "DMA timeout", HWIF(drive)->INB(IDE_STATUS_REG));
 459
 460         icside_dma_end(drive);
 461 }
 462
 463 static void icside_dma_lost_irq(ide_drive_t *drive)
 464 {
 465         printk(KERN_ERR "%s: IRQ lost\n", drive->name);
 466 }
 467
 468 static void icside_dma_init(ide_hwif_t *hwif)
 469 {
 470         printk("    %s: SG-DMA", hwif->name);
 471
 472         hwif->atapi_dma         = 1;
 473         hwif->mwdma_mask        = 7; /* MW0..2 */
 474         hwif->swdma_mask        = 7; /* SW0..2 */
 475
 476         hwif->dmatable_cpu      = NULL;
 477         hwif->dmatable_dma      = 0;
 478         hwif->speedproc         = icside_set_speed;
 479         hwif->autodma           = 1;
 480
 481         hwif->ide_dma_check     = icside_dma_check;
 482         hwif->dma_host_off      = icside_dma_host_off;
 483         hwif->dma_off_quietly   = icside_dma_off_quietly;
 484         hwif->dma_host_on       = icside_dma_host_on;
 485         hwif->ide_dma_on        = icside_dma_on;
 486         hwif->dma_setup         = icside_dma_setup;
 487         hwif->dma_exec_cmd      = icside_dma_exec_cmd;
 488         hwif->dma_start         = icside_dma_start;
 489         hwif->ide_dma_end       = icside_dma_end;
 490         hwif->ide_dma_test_irq  = icside_dma_test_irq;
 491         hwif->dma_timeout       = icside_dma_timeout;
 492         hwif->dma_lost_irq      = icside_dma_lost_irq;
 493
 494         hwif->drives[0].autodma = hwif->autodma;
 495         hwif->drives[1].autodma = hwif->autodma;
 496
 497         printk(" capable%s\n", hwif->autodma ? ", auto-enable" : "");
 498 }
 499 #else
 500 #define icside_dma_init(hwif)   (0)
 501 #endif
 502
 503 static ide_hwif_t *icside_find_hwif(unsigned long dataport)
 504 {
 505         ide_hwif_t *hwif;
 506         int index;
 507
 508         for (index = 0; index < MAX_HWIFS; ++index) {
 509                 hwif = &ide_hwifs[index];
 510                 if (hwif->io_ports[IDE_DATA_OFFSET] == dataport)
 511                         goto found;
 512         }
 513
 514         for (index = 0; index < MAX_HWIFS; ++index) {
 515                 hwif = &ide_hwifs[index];
 516                 if (!hwif->io_ports[IDE_DATA_OFFSET])
 517                         goto found;
 518         }
 519
 520         hwif = NULL;
 521 found:
 522         return hwif;
 523 }
 524
 525 static ide_hwif_t *
 526 icside_setup(void __iomem *base, struct cardinfo *info, struct expansion_card *ec)
 527 {
 528         unsigned long port = (unsigned long)base + info->dataoffset;
 529         ide_hwif_t *hwif;
 530
 531         hwif = icside_find_hwif(port);
 532         if (hwif) {
 533                 int i;
 534
 535                 memset(&hwif->hw, 0, sizeof(hw_regs_t));
 536
 537                 /*
 538                  * Ensure we're using MMIO
 539                  */
 540                 default_hwif_mmiops(hwif);
 541                 hwif->mmio = 1;
 542
 543                 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
 544                         hwif->hw.io_ports[i] = port;
 545                         hwif->io_ports[i] = port;
 546                         port += 1 << info->stepping;
 547                 }
 548                 hwif->hw.io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 549                 hwif->io_ports[IDE_CONTROL_OFFSET] = (unsigned long)base + info->ctrloffset;
 550                 hwif->hw.irq  = ec->irq;
 551                 hwif->irq     = ec->irq;
 552                 hwif->noprobe = 0;
 553                 hwif->chipset = ide_acorn;
 554                 hwif->gendev.parent = &ec->dev;
 555         }
 556
 557         return hwif;
 558 }
 559
 560 static int __init
 561 icside_register_v5(struct icside_state *state, struct expansion_card *ec)
 562 {
 563         ide_hwif_t *hwif;
 564         void __iomem *base;
 565
 566         base = ecardm_iomap(ec, ECARD_RES_MEMC, 0, 0);
 567         if (!base)
 568                 return -ENOMEM;
 569
 570         state->irq_port = base;
 571
 572         ec->irqaddr  = base + ICS_ARCIN_V5_INTRSTAT;
 573         ec->irqmask  = 1;
 574
 575         ecard_setirq(ec, &icside_ops_arcin_v5, state);
 576
 577         /*
 578          * Be on the safe side - disable interrupts
 579          */
 580         icside_irqdisable_arcin_v5(ec, 0);
 581
 582         hwif = icside_setup(base, &icside_cardinfo_v5, ec);
 583         if (!hwif)
 584                 return -ENODEV;
 585
 586         state->hwif[0] = hwif;
 587
 588         probe_hwif_init(hwif);
 589
 590         ide_proc_register_port(hwif);
 591
 592         return 0;
 593 }
 594
 595 static int __init
 596 icside_register_v6(struct icside_state *state, struct expansion_card *ec)
 597 {
 598         ide_hwif_t *hwif, *mate;
 599         void __iomem *ioc_base, *easi_base;
 600         unsigned int sel = 0;
 601         int ret;
 602
 603         ioc_base = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 604         if (!ioc_base) {
 605                 ret = -ENOMEM;
 606                 goto out;
 607         }
 608
 609         easi_base = ioc_base;
 610
 611         if (ecard_resource_flags(ec, ECARD_RES_EASI)) {
 612                 easi_base = ecardm_iomap(ec, ECARD_RES_EASI, 0, 0);
 613                 if (!easi_base) {
 614                         ret = -ENOMEM;
 615                         goto out;
 616                 }
 617
 618                 /*
 619                  * Enable access to the EASI region.
 620                  */
 621                 sel = 1 << 5;
 622         }
 623
 624         writeb(sel, ioc_base);
 625
 626         ecard_setirq(ec, &icside_ops_arcin_v6, state);
 627
 628         state->irq_port   = easi_base;
 629         state->ioc_base   = ioc_base;
 630
 631         /*
 632          * Be on the safe side - disable interrupts
 633          */
 634         icside_irqdisable_arcin_v6(ec, 0);
 635
 636         /*
 637          * Find and register the interfaces.
 638          */
 639         hwif = icside_setup(easi_base, &icside_cardinfo_v6_1, ec);
 640         mate = icside_setup(easi_base, &icside_cardinfo_v6_2, ec);
 641
 642         if (!hwif || !mate) {
 643                 ret = -ENODEV;
 644                 goto out;
 645         }
 646
 647         state->hwif[0]    = hwif;
 648         state->hwif[1]    = mate;
 649
 650         hwif->maskproc    = icside_maskproc;
 651         hwif->channel     = 0;
 652         hwif->hwif_data   = state;
 653         hwif->mate        = mate;
 654         hwif->serialized  = 1;
 655         hwif->config_data = (unsigned long)ioc_base;
 656         hwif->select_data = sel;
 657         hwif->hw.dma      = ec->dma;
 658
 659         mate->maskproc    = icside_maskproc;
 660         mate->channel     = 1;
 661         mate->hwif_data   = state;
 662         mate->mate        = hwif;
 663         mate->serialized  = 1;
 664         mate->config_data = (unsigned long)ioc_base;
 665         mate->select_data = sel | 1;
 666         mate->hw.dma      = ec->dma;
 667
 668         if (ec->dma != NO_DMA && !request_dma(ec->dma, hwif->name)) {
 669                 icside_dma_init(hwif);
 670                 icside_dma_init(mate);
 671         }
 672
 673         probe_hwif_init(hwif);
 674         probe_hwif_init(mate);
 675
 676         ide_proc_register_port(hwif);
 677         ide_proc_register_port(mate);
 678
 679         return 0;
 680
 681  out:
 682         return ret;
 683 }
 684
 685 static int __devinit
 686 icside_probe(struct expansion_card *ec, const struct ecard_id *id)
 687 {
 688         struct icside_state *state;
 689         void __iomem *idmem;
 690         int ret;
 691
 692         ret = ecard_request_resources(ec);
 693         if (ret)
 694                 goto out;
 695
 696         state = kmalloc(sizeof(struct icside_state), GFP_KERNEL);
 697         if (!state) {
 698                 ret = -ENOMEM;
 699                 goto release;
 700         }
 701
 702         memset(state, 0, sizeof(state));
 703         state->type     = ICS_TYPE_NOTYPE;
 704         state->dev      = &ec->dev;
 705
 706         idmem = ecardm_iomap(ec, ECARD_RES_IOCFAST, 0, 0);
 707         if (idmem) {
 708                 unsigned int type;
 709
 710                 type = readb(idmem + ICS_IDENT_OFFSET) & 1;
 711                 type |= (readb(idmem + ICS_IDENT_OFFSET + 4) & 1) << 1;
 712                 type |= (readb(idmem + ICS_IDENT_OFFSET + 8) & 1) << 2;
 713                 type |= (readb(idmem + ICS_IDENT_OFFSET + 12) & 1) << 3;
 714                 ecardm_iounmap(ec, idmem);
 715
 716                 state->type = type;
 717         }
 718
 719         switch (state->type) {
 720         case ICS_TYPE_A3IN:
 721                 dev_warn(&ec->dev, "A3IN unsupported\n");
 722                 ret = -ENODEV;
 723                 break;
 724
 725         case ICS_TYPE_A3USER:
 726                 dev_warn(&ec->dev, "A3USER unsupported\n");
 727                 ret = -ENODEV;
 728                 break;
 729
 730         case ICS_TYPE_V5:
 731                 ret = icside_register_v5(state, ec);
 732                 break;
 733
 734         case ICS_TYPE_V6:
 735                 ret = icside_register_v6(state, ec);
 736                 break;
 737
 738         default:
 739                 dev_warn(&ec->dev, "unknown interface type\n");
 740                 ret = -ENODEV;
 741                 break;
 742         }
 743
 744         if (ret == 0) {
 745                 ecard_set_drvdata(ec, state);
 746                 goto out;
 747         }
 748
 749         kfree(state);
 750  release:
 751         ecard_release_resources(ec);
 752  out:
 753         return ret;
 754 }
 755
 756 static void __devexit icside_remove(struct expansion_card *ec)
 757 {
 758         struct icside_state *state = ecard_get_drvdata(ec);
 759
 760         switch (state->type) {
 761         case ICS_TYPE_V5:
 762                 /* FIXME: tell IDE to stop using the interface */
 763
 764                 /* Disable interrupts */
 765                 icside_irqdisable_arcin_v5(ec, 0);
 766                 break;
 767
 768         case ICS_TYPE_V6:
 769                 /* FIXME: tell IDE to stop using the interface */
 770                 if (ec->dma != NO_DMA)
 771                         free_dma(ec->dma);
 772
 773                 /* Disable interrupts */
 774                 icside_irqdisable_arcin_v6(ec, 0);
 775
 776                 /* Reset the ROM pointer/EASI selection */
 777                 writeb(0, state->ioc_base);
 778                 break;
 779         }
 780
 781         ecard_set_drvdata(ec, NULL);
 782
 783         kfree(state);
 784         ecard_release_resources(ec);
 785 }
 786
 787 static void icside_shutdown(struct expansion_card *ec)
 788 {
 789         struct icside_state *state = ecard_get_drvdata(ec);
 790         unsigned long flags;
 791
 792         /*
 793          * Disable interrupts from this card.  We need to do
 794          * this before disabling EASI since we may be accessing
 795          * this register via that region.
 796          */
 797         local_irq_save(flags);
 798         ec->ops->irqdisable(ec, 0);
 799         local_irq_restore(flags);
 800
 801         /*
 802          * Reset the ROM pointer so that we can read the ROM
 803          * after a soft reboot.  This also disables access to
 804          * the IDE taskfile via the EASI region.
 805          */
 806         if (state->ioc_base)
 807                 writeb(0, state->ioc_base);
 808 }
 809
 810 static const struct ecard_id icside_ids[] = {
 811         { MANU_ICS,  PROD_ICS_IDE  },
 812         { MANU_ICS2, PROD_ICS2_IDE },
 813         { 0xffff, 0xffff }
 814 };
 815
 816 static struct ecard_driver icside_driver = {
 817         .probe          = icside_probe,
 818         .remove         = __devexit_p(icside_remove),
 819         .shutdown       = icside_shutdown,
 820         .id_table       = icside_ids,
 821         .drv = {
 822                 .name   = "icside",
 823         },
 824 };
 825
 826 static int __init icside_init(void)
 827 {
 828         return ecard_register_driver(&icside_driver);
 829 }
 830
 831 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
 832 MODULE_LICENSE("GPL");
 833 MODULE_DESCRIPTION("ICS IDE driver");
 834
 835 module_init(icside_init);