2 * linux/drivers/i2c/chips/twl4030_gpio.c
4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc.
7 * Code re-arranged and cleaned up by:
8 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * Andy Lowe / Nishanth Menon
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/module.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/init.h>
32 #include <linux/time.h>
33 #include <linux/interrupt.h>
34 #include <linux/random.h>
35 #include <linux/syscalls.h>
36 #include <linux/kthread.h>
37 #include <linux/irq.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c/twl4030.h>
41 #include <linux/slab.h>
43 #include <asm/arch/irqs.h>
44 #include <asm/mach/irq.h>
45 #include <asm/arch/gpio.h>
46 #include <asm/arch/mux.h>
48 #include <linux/device.h>
51 * GPIO Block Register definitions
54 #define REG_GPIODATAIN1 0x0
55 #define REG_GPIODATAIN2 0x1
56 #define REG_GPIODATAIN3 0x2
57 #define REG_GPIODATADIR1 0x3
58 #define REG_GPIODATADIR2 0x4
59 #define REG_GPIODATADIR3 0x5
60 #define REG_GPIODATAOUT1 0x6
61 #define REG_GPIODATAOUT2 0x7
62 #define REG_GPIODATAOUT3 0x8
63 #define REG_CLEARGPIODATAOUT1 0x9
64 #define REG_CLEARGPIODATAOUT2 0xA
65 #define REG_CLEARGPIODATAOUT3 0xB
66 #define REG_SETGPIODATAOUT1 0xC
67 #define REG_SETGPIODATAOUT2 0xD
68 #define REG_SETGPIODATAOUT3 0xE
69 #define REG_GPIO_DEBEN1 0xF
70 #define REG_GPIO_DEBEN2 0x10
71 #define REG_GPIO_DEBEN3 0x11
72 #define REG_GPIO_CTRL 0x12
73 #define REG_GPIOPUPDCTR1 0x13
74 #define REG_GPIOPUPDCTR2 0x14
75 #define REG_GPIOPUPDCTR3 0x15
76 #define REG_GPIOPUPDCTR4 0x16
77 #define REG_GPIOPUPDCTR5 0x17
78 #define REG_GPIO_ISR1A 0x19
79 #define REG_GPIO_ISR2A 0x1A
80 #define REG_GPIO_ISR3A 0x1B
81 #define REG_GPIO_IMR1A 0x1C
82 #define REG_GPIO_IMR2A 0x1D
83 #define REG_GPIO_IMR3A 0x1E
84 #define REG_GPIO_ISR1B 0x1F
85 #define REG_GPIO_ISR2B 0x20
86 #define REG_GPIO_ISR3B 0x21
87 #define REG_GPIO_IMR1B 0x22
88 #define REG_GPIO_IMR2B 0x23
89 #define REG_GPIO_IMR3B 0x24
90 #define REG_GPIO_EDR1 0x28
91 #define REG_GPIO_EDR2 0x29
92 #define REG_GPIO_EDR3 0x2A
93 #define REG_GPIO_EDR4 0x2B
94 #define REG_GPIO_EDR5 0x2C
95 #define REG_GPIO_SIH_CTRL 0x2D
97 /* BitField Definitions */
99 /* Data banks : 3 banks for 8 gpios each */
100 #define DATA_BANK_MAX 8
101 #define GET_GPIO_DATA_BANK(x) ((x)/DATA_BANK_MAX)
102 #define GET_GPIO_DATA_OFF(x) ((x)%DATA_BANK_MAX)
104 /* GPIODATADIR Fields each block 0-7 */
105 #define BIT_GPIODATADIR_GPIOxDIR(x) (x)
106 #define MASK_GPIODATADIR_GPIOxDIR(x) (0x01 << (x))
108 /* GPIODATAIN Fields each block 0-7 */
109 #define BIT_GPIODATAIN_GPIOxIN(x) (x)
110 #define MASK_GPIODATAIN_GPIOxIN(x) (0x01 << (x))
112 /* GPIODATAOUT Fields each block 0-7 */
113 #define BIT_GPIODATAOUT_GPIOxOUT(x) (x)
114 #define MASK_GPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
116 /* CLEARGPIODATAOUT Fields */
117 #define BIT_CLEARGPIODATAOUT_GPIOxOUT(x) (x)
118 #define MASK_CLEARGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
120 /* SETGPIODATAOUT Fields */
121 #define BIT_SETGPIODATAOUT_GPIOxOUT(x) (x)
122 #define MASK_SETGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
124 /* GPIO_DEBEN Fields */
125 #define BIT_GPIO_DEBEN_GPIOxDEB(x) (x)
126 #define MASK_GPIO_DEBEN_GPIOxDEB(x) (0x01 << (x))
128 /* GPIO_ISR1A Fields */
129 #define BIT_GPIO_ISR_GPIOxISR(x) (x)
130 #define MASK_GPIO_ISR_GPIOxISR(x) (0x01 << (x))
132 /* GPIO_IMR1A Fields */
133 #define BIT_GPIO_IMR1A_GPIOxIMR(x) (x)
134 #define MASK_GPIO_IMR1A_GPIOxIMR(x) (0x01 << (x))
136 /* GPIO_SIR1 Fields */
137 #define BIT_GPIO_SIR1_GPIOxSIR(x) (x)
138 #define MASK_GPIO_SIR1_GPIO0SIR (0x01 << (x))
141 /* Control banks : 5 banks for 4 gpios each */
142 #define DATA_CTL_MAX 4
143 #define GET_GPIO_CTL_BANK(x) ((x)/DATA_CTL_MAX)
144 #define GET_GPIO_CTL_OFF(x) ((x)%DATA_CTL_MAX)
145 #define GPIO_BANK_MAX GET_GPIO_CTL_BANK(TWL4030_GPIO_MAX)
147 /* GPIOPUPDCTRx Fields 5 banks of 4 gpios each */
148 #define BIT_GPIOPUPDCTR1_GPIOxPD(x) (2 * (x))
149 #define MASK_GPIOPUPDCTR1_GPIOxPD(x) (0x01 << (2 * (x)))
150 #define BIT_GPIOPUPDCTR1_GPIOxPU(x) ((x) + 1)
151 #define MASK_GPIOPUPDCTR1_GPIOxPU(x) (0x01 << (((2 * (x)) + 1)))
153 /* GPIO_EDR1 Fields */
154 #define BIT_GPIO_EDR1_GPIOxFALLING(x) (2 * (x))
155 #define MASK_GPIO_EDR1_GPIOxFALLING(x) (0x01 << (2 * (x)))
156 #define BIT_GPIO_EDR1_GPIOxRISING(x) ((x) + 1)
157 #define MASK_GPIO_EDR1_GPIOxRISING(x) (0x01 << (((2 * (x)) + 1)))
159 /* GPIO_SIH_CTRL Fields */
160 #define BIT_GPIO_SIH_CTRL_EXCLEN (0x000)
161 #define MASK_GPIO_SIH_CTRL_EXCLEN (0x00000001)
162 #define BIT_GPIO_SIH_CTRL_PENDDIS (0x001)
163 #define MASK_GPIO_SIH_CTRL_PENDDIS (0x00000002)
164 #define BIT_GPIO_SIH_CTRL_COR (0x002)
165 #define MASK_GPIO_SIH_CTRL_COR (0x00000004)
167 /* GPIO_CTRL Fields */
168 #define BIT_GPIO_CTRL_GPIO0CD1 (0x000)
169 #define MASK_GPIO_CTRL_GPIO0CD1 (0x00000001)
170 #define BIT_GPIO_CTRL_GPIO1CD2 (0x001)
171 #define MASK_GPIO_CTRL_GPIO1CD2 (0x00000002)
172 #define BIT_GPIO_CTRL_GPIO_ON (0x002)
173 #define MASK_GPIO_CTRL_GPIO_ON (0x00000004)
175 /* Mask for GPIO registers when aggregated into a 32-bit integer */
176 #define GPIO_32_MASK 0x0003ffff
178 /* Data structures */
179 static struct semaphore gpio_sem;
181 /* store usage of each GPIO. - each bit represents one GPIO */
182 static unsigned int gpio_usage_count;
184 /* shadow the imr register */
185 static unsigned int gpio_imr_shadow;
187 /* bitmask of pending requests to unmask gpio interrupts */
188 static unsigned int gpio_pending_unmask;
190 /* pointer to gpio unmask thread struct */
191 static struct task_struct *gpio_unmask_thread;
194 * Helper functions to read and write the GPIO ISR and IMR registers as
195 * 32-bit integers. Functions return 0 on success, non-zero otherwise.
196 * The caller must hold a lock on gpio_sem.
199 static int gpio_read_isr(unsigned int *isr)
204 ret = twl4030_i2c_read(TWL4030_MODULE_GPIO, (u8 *) isr,
207 *isr &= GPIO_32_MASK;
212 static int gpio_write_isr(unsigned int isr)
216 * The buffer passed to the twl4030_i2c_write() routine must have an
217 * extra byte at the beginning reserved for its internal use.
220 isr = cpu_to_le32(isr);
221 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &isr,
225 static int gpio_write_imr(unsigned int imr)
229 * The buffer passed to the twl4030_i2c_write() routine must have an
230 * extra byte at the beginning reserved for its internal use.
233 imr = cpu_to_le32(imr);
234 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &imr,
239 * These routines are analagous to the irqchip methods, but they are designed
240 * to be called from thread context with cpu interrupts enabled and with no
241 * locked spinlocks. We call these routines from our custom IRQ handler
242 * instead of the usual irqchip methods.
244 static void twl4030_gpio_mask_and_ack(unsigned int irq)
246 int gpio = irq - TWL4030_GPIO_IRQ_BASE;
250 gpio_imr_shadow |= (1 << gpio);
251 gpio_write_imr(gpio_imr_shadow);
253 gpio_write_isr(1 << gpio);
257 static void twl4030_gpio_unmask(unsigned int irq)
259 int gpio = irq - TWL4030_GPIO_IRQ_BASE;
262 gpio_imr_shadow &= ~(1 << gpio);
263 gpio_write_imr(gpio_imr_shadow);
268 * These are the irqchip methods for the TWL4030 GPIO interrupts.
269 * Our IRQ handle method doesn't call these, but they will be called by
270 * other routines such as setup_irq() and enable_irq(). They are called
271 * with cpu interrupts disabled and with a lock on the irq_controller_lock
272 * spinlock. This complicates matters, because accessing the TWL4030 GPIO
273 * interrupt controller requires I2C bus transactions that can't be initiated
274 * in this context. Our solution is to defer accessing the interrupt
275 * controller to a kernel thread. We only need to support the unmask method.
278 static void twl4030_gpio_mask_and_ack_irqchip(unsigned int irq) {}
279 static void twl4030_gpio_mask_irqchip(unsigned int irq) {}
281 static void twl4030_gpio_unmask_irqchip(unsigned int irq)
283 int gpio = irq - TWL4030_GPIO_IRQ_BASE;
285 gpio_pending_unmask |= (1 << gpio);
286 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
287 wake_up_process(gpio_unmask_thread);
290 static struct irq_chip twl4030_gpio_irq_chip = {
291 .name = "twl4030-gpio",
292 .ack = twl4030_gpio_mask_and_ack_irqchip,
293 .mask = twl4030_gpio_mask_irqchip,
294 .unmask = twl4030_gpio_unmask_irqchip,
298 * These are the irqchip methods for the TWL4030 PIH GPIO module interrupt.
299 * The PIH module doesn't have interrupt masking capability, so these
302 static void twl4030_gpio_module_ack(unsigned int irq) {}
303 static void twl4030_gpio_module_mask(unsigned int irq) {}
304 static void twl4030_gpio_module_unmask(unsigned int irq) {}
305 static struct irq_chip twl4030_gpio_module_irq_chip = {
306 .ack = twl4030_gpio_module_ack,
307 .mask = twl4030_gpio_module_mask,
308 .unmask = twl4030_gpio_module_unmask,
312 * To configure TWL4030 GPIO module registers
314 static inline int gpio_twl4030_write(u8 address, u8 data)
318 ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
323 * To read a TWL4030 GPIO module register
325 static inline int gpio_twl4030_read(u8 address)
330 ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
337 * twl4030 GPIO request function
339 int twl4030_request_gpio(int gpio)
343 if (unlikely(gpio >= TWL4030_GPIO_MAX))
347 if (gpio_usage_count & (0x1 << gpio))
350 u8 clear_pull[6] = { 0, 0, 0, 0, 0, 0 };
351 /* First time usage? - switch on GPIO module */
352 if (!gpio_usage_count) {
354 gpio_twl4030_write(REG_GPIO_CTRL,
355 MASK_GPIO_CTRL_GPIO_ON);
356 ret = gpio_twl4030_write(REG_GPIO_SIH_CTRL, 0x00);
359 gpio_usage_count |= (0x1 << gpio);
362 twl4030_i2c_write(TWL4030_MODULE_GPIO, clear_pull,
363 REG_GPIOPUPDCTR1, 5);
368 EXPORT_SYMBOL(twl4030_request_gpio);
371 * TWL4030 GPIO free module
373 int twl4030_free_gpio(int gpio)
377 if (unlikely(gpio >= TWL4030_GPIO_MAX))
382 if ((gpio_usage_count & (0x1 << gpio)) == 0)
385 gpio_usage_count &= ~(0x1 << gpio);
387 /* Last time usage? - switch off GPIO module */
388 if (!gpio_usage_count)
389 ret = gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
394 EXPORT_SYMBOL(twl4030_free_gpio);
397 * Set direction for TWL4030 GPIO
399 int twl4030_set_gpio_direction(int gpio, int is_input)
401 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
402 u8 d_msk = MASK_GPIODATADIR_GPIOxDIR(GET_GPIO_DATA_OFF(gpio));
407 if (unlikely((gpio >= TWL4030_GPIO_MAX)
408 || !(gpio_usage_count & (0x1 << gpio))))
411 base = REG_GPIODATADIR1 + d_bnk;
414 ret = gpio_twl4030_read(base);
417 reg = (u8) ((ret) & ~(d_msk));
419 reg = (u8) ((ret) | (d_msk));
421 ret = gpio_twl4030_write(base, reg);
426 EXPORT_SYMBOL(twl4030_set_gpio_direction);
429 * To enable/disable GPIO pin on TWL4030
431 int twl4030_set_gpio_dataout(int gpio, int enable)
433 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
434 u8 d_msk = MASK_GPIODATAOUT_GPIOxOUT(GET_GPIO_DATA_OFF(gpio));
438 if (unlikely((gpio >= TWL4030_GPIO_MAX)
439 || !(gpio_usage_count & (0x1 << gpio))))
443 base = REG_SETGPIODATAOUT1 + d_bnk;
445 base = REG_CLEARGPIODATAOUT1 + d_bnk;
448 ret = gpio_twl4030_write(base, d_msk);
452 EXPORT_SYMBOL(twl4030_set_gpio_dataout);
455 * To get the status of a GPIO pin on TWL4030
457 int twl4030_get_gpio_datain(int gpio)
459 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
460 u8 d_off = BIT_GPIODATAIN_GPIOxIN(GET_GPIO_DATA_OFF(gpio));
464 if (unlikely((gpio >= TWL4030_GPIO_MAX)
465 || !(gpio_usage_count & (0x1 << gpio))))
468 base = REG_GPIODATAIN1 + d_bnk;
470 ret = gpio_twl4030_read(base);
473 ret = (ret >> d_off) & 0x1;
477 EXPORT_SYMBOL(twl4030_get_gpio_datain);
480 * Configure PULL type for a GPIO pin on TWL4030
482 int twl4030_set_gpio_pull(int gpio, int pull_dircn)
484 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
485 u8 c_off = GET_GPIO_CTL_OFF(gpio);
491 if (unlikely((gpio >= TWL4030_GPIO_MAX) ||
492 !(gpio_usage_count & (0x1 << gpio))))
495 base = REG_GPIOPUPDCTR1 + c_bnk;
496 if (pull_dircn == TWL4030_GPIO_PULL_DOWN)
497 c_msk = MASK_GPIOPUPDCTR1_GPIOxPD(c_off);
498 else if (pull_dircn == TWL4030_GPIO_PULL_UP)
499 c_msk = MASK_GPIOPUPDCTR1_GPIOxPU(c_off);
502 ret = gpio_twl4030_read(base);
504 /* clear the previous up/down values */
506 reg &= ~(MASK_GPIOPUPDCTR1_GPIOxPU(c_off) |
507 MASK_GPIOPUPDCTR1_GPIOxPD(c_off));
509 ret = gpio_twl4030_write(base, reg);
514 EXPORT_SYMBOL(twl4030_set_gpio_pull);
517 * Configure Edge control for a GPIO pin on TWL4030
519 int twl4030_set_gpio_edge_ctrl(int gpio, int edge)
521 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
522 u8 c_off = GET_GPIO_CTL_OFF(gpio);
528 if (unlikely((gpio >= TWL4030_GPIO_MAX)
529 || !(gpio_usage_count & (0x1 << gpio))))
532 base = REG_GPIO_EDR1 + c_bnk;
534 if (edge & TWL4030_GPIO_EDGE_RISING)
535 c_msk |= MASK_GPIO_EDR1_GPIOxRISING(c_off);
537 if (edge & TWL4030_GPIO_EDGE_FALLING)
538 c_msk |= MASK_GPIO_EDR1_GPIOxFALLING(c_off);
541 ret = gpio_twl4030_read(base);
543 /* clear the previous rising/falling values */
546 ~(MASK_GPIO_EDR1_GPIOxFALLING(c_off) |
547 MASK_GPIO_EDR1_GPIOxRISING(c_off)));
549 ret = gpio_twl4030_write(base, reg);
554 EXPORT_SYMBOL(twl4030_set_gpio_edge_ctrl);
557 * Configure debounce timing value for a GPIO pin on TWL4030
559 int twl4030_set_gpio_debounce(int gpio, int enable)
561 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
562 u8 d_msk = MASK_GPIO_DEBEN_GPIOxDEB(GET_GPIO_DATA_OFF(gpio));
567 if (unlikely((gpio >= TWL4030_GPIO_MAX)
568 || !(gpio_usage_count & (0x1 << gpio))))
571 base = REG_GPIO_DEBEN1 + d_bnk;
573 ret = gpio_twl4030_read(base);
576 reg = (u8) ((ret) | (d_msk));
578 reg = (u8) ((ret) & ~(d_msk));
580 ret = gpio_twl4030_write(base, reg);
585 EXPORT_SYMBOL(twl4030_set_gpio_debounce);
588 * Configure Card detect for GPIO pin on TWL4030
590 int twl4030_set_gpio_card_detect(int gpio, int enable)
593 u8 msk = (1 << gpio);
596 /* Only GPIO 0 or 1 can be used for CD feature.. */
597 if (unlikely((gpio >= TWL4030_GPIO_MAX)
598 || !(gpio_usage_count & (0x1 << gpio))
599 || (gpio >= TWL4030_GPIO_MAX_CD))) {
604 ret = gpio_twl4030_read(REG_GPIO_CTRL);
607 reg = (u8) (ret | msk);
609 reg = (u8) (ret & ~msk);
611 ret = gpio_twl4030_write(REG_GPIO_CTRL, reg);
616 EXPORT_SYMBOL(twl4030_set_gpio_card_detect);
618 /* MODULE FUNCTIONS */
621 * gpio_unmask_thread() runs as a kernel thread. It is awakened by the unmask
622 * method for the GPIO interrupts. It unmasks all of the GPIO interrupts
623 * specified in the gpio_pending_unmask bitmask. We have to do the unmasking
624 * in a kernel thread rather than directly in the unmask method because of the
625 * need to access the TWL4030 via the I2C bus. Note that we don't need to be
626 * concerned about race conditions where the request to unmask a GPIO interrupt
627 * has already been cancelled before this thread does the unmasking. If a GPIO
628 * interrupt is improperly unmasked, then the IRQ handler for it will mask it
629 * when an interrupt occurs.
631 static int twl4030_gpio_unmask_thread(void *data)
633 current->flags |= PF_NOFREEZE;
635 while (!kthread_should_stop()) {
637 unsigned int gpio_unmask;
640 gpio_unmask = gpio_pending_unmask;
641 gpio_pending_unmask = 0;
644 for (irq = TWL4030_GPIO_IRQ_BASE; 0 != gpio_unmask;
645 gpio_unmask >>= 1, irq++) {
646 if (gpio_unmask & 0x1)
647 twl4030_gpio_unmask(irq);
651 if (!gpio_pending_unmask)
652 set_current_state(TASK_INTERRUPTIBLE);
657 set_current_state(TASK_RUNNING);
662 * do_twl4030_gpio_irq() is the desc->handle method for each of the twl4030
663 * gpio interrupts. It executes in kernel thread context.
664 * On entry, cpu interrupts are enabled.
666 static void do_twl4030_gpio_irq(unsigned int irq, irq_desc_t *desc)
668 struct irqaction *action;
669 const unsigned int cpu = smp_processor_id();
671 desc->status |= IRQ_LEVEL;
674 * Acknowledge, clear _AND_ disable the interrupt.
676 twl4030_gpio_mask_and_ack(irq);
679 kstat_cpu(cpu).irqs[irq]++;
681 action = desc->action;
687 /* Call the ISR with cpu interrupts enabled. */
688 ret = action->handler(irq, action->dev_id);
689 if (ret == IRQ_HANDLED)
690 status |= action->flags;
692 action = action->next;
695 if (retval != IRQ_HANDLED)
696 printk(KERN_ERR "ISR for TWL4030 GPIO"
697 " irq %d can't handle interrupt\n",
701 twl4030_gpio_unmask(irq);
707 * do_twl4030_gpio_module_irq() is the desc->handle method for the twl4030 gpio
708 * module interrupt. It executes in kernel thread context.
709 * This is a chained interrupt, so there is no desc->action method for it.
710 * We query the gpio module interrupt controller in the twl4030 to determine
711 * which gpio lines are generating interrupt requests, and then call the
712 * desc->handle method for each gpio that needs service.
713 * On entry, cpu interrupts are disabled.
715 static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
717 const unsigned int cpu = smp_processor_id();
719 desc->status |= IRQ_LEVEL;
721 * The desc->handle method would normally call the desc->chip->ack
722 * method here, but we won't bother since our ack method is NULL.
726 unsigned int gpio_isr;
728 kstat_cpu(cpu).irqs[irq]++;
732 if (gpio_read_isr(&gpio_isr))
736 for (gpio_irq = TWL4030_GPIO_IRQ_BASE; 0 != gpio_isr;
737 gpio_isr >>= 1, gpio_irq++) {
738 if (gpio_isr & 0x1) {
739 irq_desc_t *d = irq_desc + gpio_irq;
740 d->handle_irq(gpio_irq, d);
746 * Here is where we should call the unmask method, but again we
747 * won't bother since it is NULL.
752 /* TWL4030 Initialization module */
753 static int __init gpio_twl4030_init(void)
758 /* init the global locking sem */
759 sema_init(&gpio_sem, 1);
761 /* All GPIO interrupts are initially masked */
762 gpio_pending_unmask = 0;
763 gpio_imr_shadow = GPIO_32_MASK;
764 ret = gpio_write_imr(gpio_imr_shadow);
767 * Create a kernel thread to handle deferred unmasking of gpio
770 gpio_unmask_thread = kthread_create(twl4030_gpio_unmask_thread,
771 NULL, "twl4030 gpio");
772 if (!gpio_unmask_thread) {
774 "%s: could not create twl4030 gpio unmask"
775 " thread!\n", __func__);
781 /* install an irq handler for each of the gpio interrupts */
782 for (irq = TWL4030_GPIO_IRQ_BASE; irq < TWL4030_GPIO_IRQ_END;
784 set_irq_chip(irq, &twl4030_gpio_irq_chip);
785 set_irq_handler(irq, do_twl4030_gpio_irq);
786 set_irq_flags(irq, IRQF_VALID);
790 * Install an irq handler to demultiplex the gpio module
793 set_irq_chip(TWL4030_MODIRQ_GPIO,
794 &twl4030_gpio_module_irq_chip);
795 set_irq_chained_handler(TWL4030_MODIRQ_GPIO,
796 do_twl4030_gpio_module_irq);
799 printk(KERN_INFO "TWL4030 GPIO Demux: IRQ Range %d to %d,"
800 " Initialization %s\n", TWL4030_GPIO_IRQ_BASE,
801 TWL4030_GPIO_IRQ_END, (ret) ? "Failed" : "Success");
805 /* TWL GPIO exit module */
806 static void __exit gpio_twl4030_exit(void)
810 /* uninstall the gpio demultiplexing interrupt handler */
811 set_irq_handler(TWL4030_MODIRQ_GPIO, NULL);
812 set_irq_flags(TWL4030_MODIRQ_GPIO, 0);
814 /* uninstall the irq handler for each of the gpio interrupts */
815 for (irq = TWL4030_GPIO_IRQ_BASE; irq < TWL4030_GPIO_IRQ_END; irq++) {
816 set_irq_handler(irq, NULL);
817 set_irq_flags(irq, 0);
820 /* stop the gpio unmask kernel thread */
821 if (gpio_unmask_thread) {
822 kthread_stop(gpio_unmask_thread);
823 gpio_unmask_thread = NULL;
827 module_init(gpio_twl4030_init);
828 module_exit(gpio_twl4030_exit);
830 MODULE_AUTHOR("Texas Instruments, Inc.");
831 MODULE_DESCRIPTION("GPIO interface for TWL4030");
832 MODULE_LICENSE("GPL");