2 * linux/drivers/i2c/chips/twl4030_gpio.c
4 * Copyright (C) 2006-2007 Texas Instruments, Inc.
5 * Copyright (C) 2006 MontaVista Software, Inc.
7 * Code re-arranged and cleaned up by:
8 * Syed Mohammed Khasim <x0khasim@ti.com>
11 * Andy Lowe / Nishanth Menon
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
29 #include <linux/module.h>
30 #include <linux/kernel_stat.h>
31 #include <linux/init.h>
32 #include <linux/time.h>
33 #include <linux/interrupt.h>
34 #include <linux/device.h>
35 #include <linux/kthread.h>
36 #include <linux/irq.h>
37 #include <linux/gpio.h>
38 #include <linux/platform_device.h>
39 #include <linux/slab.h>
41 #include <linux/i2c/twl4030.h>
42 #include <linux/i2c/twl4030-gpio.h>
44 #include <mach/irqs.h>
45 #include <asm/mach/irq.h>
46 #include <mach/gpio.h>
50 /* REVISIT when these symbols vanish elsewhere, remove them here too */
51 #undef TWL4030_GPIO_IRQ_BASE
52 #undef TWL4030_GPIO_IRQ_END
53 #undef TWL4030_MODIRQ_GPIO
55 static struct gpio_chip twl_gpiochip;
56 static int twl4030_gpio_irq_base;
57 static int twl4030_gpio_irq_end;
60 /* BitField Definitions */
62 /* Data banks : 3 banks for 8 gpios each */
63 #define DATA_BANK_MAX 8
64 #define GET_GPIO_DATA_BANK(x) ((x)/DATA_BANK_MAX)
65 #define GET_GPIO_DATA_OFF(x) ((x)%DATA_BANK_MAX)
67 /* GPIODATADIR Fields each block 0-7 */
68 #define BIT_GPIODATADIR_GPIOxDIR(x) (x)
69 #define MASK_GPIODATADIR_GPIOxDIR(x) (0x01 << (x))
71 /* GPIODATAIN Fields each block 0-7 */
72 #define BIT_GPIODATAIN_GPIOxIN(x) (x)
73 #define MASK_GPIODATAIN_GPIOxIN(x) (0x01 << (x))
75 /* GPIODATAOUT Fields each block 0-7 */
76 #define BIT_GPIODATAOUT_GPIOxOUT(x) (x)
77 #define MASK_GPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
79 /* CLEARGPIODATAOUT Fields */
80 #define BIT_CLEARGPIODATAOUT_GPIOxOUT(x) (x)
81 #define MASK_CLEARGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
83 /* SETGPIODATAOUT Fields */
84 #define BIT_SETGPIODATAOUT_GPIOxOUT(x) (x)
85 #define MASK_SETGPIODATAOUT_GPIOxOUT(x) (0x01 << (x))
87 /* GPIO_DEBEN Fields */
88 #define BIT_GPIO_DEBEN_GPIOxDEB(x) (x)
89 #define MASK_GPIO_DEBEN_GPIOxDEB(x) (0x01 << (x))
91 /* GPIO_ISR1A Fields */
92 #define BIT_GPIO_ISR_GPIOxISR(x) (x)
93 #define MASK_GPIO_ISR_GPIOxISR(x) (0x01 << (x))
95 /* GPIO_IMR1A Fields */
96 #define BIT_GPIO_IMR1A_GPIOxIMR(x) (x)
97 #define MASK_GPIO_IMR1A_GPIOxIMR(x) (0x01 << (x))
99 /* GPIO_SIR1 Fields */
100 #define BIT_GPIO_SIR1_GPIOxSIR(x) (x)
101 #define MASK_GPIO_SIR1_GPIO0SIR (0x01 << (x))
104 /* Control banks : 5 banks for 4 gpios each */
105 #define DATA_CTL_MAX 4
106 #define GET_GPIO_CTL_BANK(x) ((x)/DATA_CTL_MAX)
107 #define GET_GPIO_CTL_OFF(x) ((x)%DATA_CTL_MAX)
108 #define GPIO_BANK_MAX GET_GPIO_CTL_BANK(TWL4030_GPIO_MAX)
110 /* GPIOPUPDCTRx Fields 5 banks of 4 gpios each */
111 #define BIT_GPIOPUPDCTR1_GPIOxPD(x) (2 * (x))
112 #define MASK_GPIOPUPDCTR1_GPIOxPD(x) (0x01 << (2 * (x)))
113 #define BIT_GPIOPUPDCTR1_GPIOxPU(x) ((x) + 1)
114 #define MASK_GPIOPUPDCTR1_GPIOxPU(x) (0x01 << (((2 * (x)) + 1)))
116 /* GPIO_EDR1 Fields */
117 #define BIT_GPIO_EDR1_GPIOxFALLING(x) (2 * (x))
118 #define MASK_GPIO_EDR1_GPIOxFALLING(x) (0x01 << (2 * (x)))
119 #define BIT_GPIO_EDR1_GPIOxRISING(x) ((x) + 1)
120 #define MASK_GPIO_EDR1_GPIOxRISING(x) (0x01 << (((2 * (x)) + 1)))
122 /* GPIO_SIH_CTRL Fields */
123 #define BIT_GPIO_SIH_CTRL_EXCLEN (0x000)
124 #define MASK_GPIO_SIH_CTRL_EXCLEN (0x00000001)
125 #define BIT_GPIO_SIH_CTRL_PENDDIS (0x001)
126 #define MASK_GPIO_SIH_CTRL_PENDDIS (0x00000002)
127 #define BIT_GPIO_SIH_CTRL_COR (0x002)
128 #define MASK_GPIO_SIH_CTRL_COR (0x00000004)
130 /* GPIO_CTRL Fields */
131 #define BIT_GPIO_CTRL_GPIO0CD1 (0x000)
132 #define MASK_GPIO_CTRL_GPIO0CD1 (0x00000001)
133 #define BIT_GPIO_CTRL_GPIO1CD2 (0x001)
134 #define MASK_GPIO_CTRL_GPIO1CD2 (0x00000002)
135 #define BIT_GPIO_CTRL_GPIO_ON (0x002)
136 #define MASK_GPIO_CTRL_GPIO_ON (0x00000004)
138 /* Mask for GPIO registers when aggregated into a 32-bit integer */
139 #define GPIO_32_MASK 0x0003ffff
141 /* Data structures */
142 static DEFINE_MUTEX(gpio_lock);
144 /* store usage of each GPIO. - each bit represents one GPIO */
145 static unsigned int gpio_usage_count;
147 /* shadow the imr register */
148 static unsigned int gpio_imr_shadow;
150 /* bitmask of pending requests to unmask gpio interrupts */
151 static unsigned int gpio_pending_unmask;
153 /* pointer to gpio unmask thread struct */
154 static struct task_struct *gpio_unmask_thread;
157 * Helper functions to read and write the GPIO ISR and IMR registers as
158 * 32-bit integers. Functions return 0 on success, non-zero otherwise.
159 * The caller must hold gpio_lock.
162 static int gpio_read_isr(unsigned int *isr)
167 ret = twl4030_i2c_read(TWL4030_MODULE_GPIO, (u8 *) isr,
170 *isr &= GPIO_32_MASK;
175 static int gpio_write_isr(unsigned int isr)
179 * The buffer passed to the twl4030_i2c_write() routine must have an
180 * extra byte at the beginning reserved for its internal use.
183 isr = cpu_to_le32(isr);
184 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &isr,
188 static int gpio_write_imr(unsigned int imr)
192 * The buffer passed to the twl4030_i2c_write() routine must have an
193 * extra byte at the beginning reserved for its internal use.
196 imr = cpu_to_le32(imr);
197 return twl4030_i2c_write(TWL4030_MODULE_GPIO, (u8 *) &imr,
202 * These routines are analagous to the irqchip methods, but they are designed
203 * to be called from thread context with cpu interrupts enabled and with no
204 * locked spinlocks. We call these routines from our custom IRQ handler
205 * instead of the usual irqchip methods.
207 static void twl4030_gpio_mask_and_ack(unsigned int irq)
209 int gpio = irq - twl4030_gpio_irq_base;
211 mutex_lock(&gpio_lock);
213 gpio_imr_shadow |= (1 << gpio);
214 gpio_write_imr(gpio_imr_shadow);
216 gpio_write_isr(1 << gpio);
217 mutex_unlock(&gpio_lock);
220 static void twl4030_gpio_unmask(unsigned int irq)
222 int gpio = irq - twl4030_gpio_irq_base;
224 mutex_lock(&gpio_lock);
225 gpio_imr_shadow &= ~(1 << gpio);
226 gpio_write_imr(gpio_imr_shadow);
227 mutex_unlock(&gpio_lock);
231 * These are the irqchip methods for the TWL4030 GPIO interrupts.
232 * Our IRQ handle method doesn't call these, but they will be called by
233 * other routines such as setup_irq() and enable_irq(). They are called
234 * with cpu interrupts disabled and with a lock on the irq_controller_lock
235 * spinlock. This complicates matters, because accessing the TWL4030 GPIO
236 * interrupt controller requires I2C bus transactions that can't be initiated
237 * in this context. Our solution is to defer accessing the interrupt
238 * controller to a kernel thread. We only need to support the unmask method.
241 static void twl4030_gpio_mask_and_ack_irqchip(unsigned int irq) {}
242 static void twl4030_gpio_mask_irqchip(unsigned int irq) {}
244 static void twl4030_gpio_unmask_irqchip(unsigned int irq)
246 int gpio = irq - twl4030_gpio_irq_base;
248 gpio_pending_unmask |= (1 << gpio);
249 if (gpio_unmask_thread && gpio_unmask_thread->state != TASK_RUNNING)
250 wake_up_process(gpio_unmask_thread);
253 static struct irq_chip twl4030_gpio_irq_chip = {
255 .ack = twl4030_gpio_mask_and_ack_irqchip,
256 .mask = twl4030_gpio_mask_irqchip,
257 .unmask = twl4030_gpio_unmask_irqchip,
261 * These are the irqchip methods for the TWL4030 PIH GPIO module interrupt.
262 * The PIH module doesn't have interrupt masking capability, so these
265 static void twl4030_gpio_module_ack(unsigned int irq) {}
266 static void twl4030_gpio_module_mask(unsigned int irq) {}
267 static void twl4030_gpio_module_unmask(unsigned int irq) {}
268 static struct irq_chip twl4030_gpio_module_irq_chip = {
269 .ack = twl4030_gpio_module_ack,
270 .mask = twl4030_gpio_module_mask,
271 .unmask = twl4030_gpio_module_unmask,
275 * To configure TWL4030 GPIO module registers
277 static inline int gpio_twl4030_write(u8 address, u8 data)
281 ret = twl4030_i2c_write_u8(TWL4030_MODULE_GPIO, data, address);
286 * To read a TWL4030 GPIO module register
288 static inline int gpio_twl4030_read(u8 address)
293 ret = twl4030_i2c_read_u8(TWL4030_MODULE_GPIO, &data, address);
300 * twl4030 GPIO request function
302 int twl4030_request_gpio(int gpio)
306 if (unlikely(gpio >= TWL4030_GPIO_MAX))
309 ret = gpio_request(twl_gpiochip.base + gpio, NULL);
313 mutex_lock(&gpio_lock);
314 if (gpio_usage_count & (0x1 << gpio)) {
317 /* First time usage? - switch on GPIO module */
318 if (!gpio_usage_count) {
319 ret = gpio_twl4030_write(REG_GPIO_CTRL,
320 MASK_GPIO_CTRL_GPIO_ON);
321 ret = gpio_twl4030_write(REG_GPIO_SIH_CTRL, 0x00);
324 gpio_usage_count |= (0x1 << gpio);
326 gpio_free(twl_gpiochip.base + gpio);
328 mutex_unlock(&gpio_lock);
331 EXPORT_SYMBOL(twl4030_request_gpio);
334 * TWL4030 GPIO free module
336 int twl4030_free_gpio(int gpio)
340 if (unlikely(gpio >= TWL4030_GPIO_MAX))
343 mutex_lock(&gpio_lock);
345 if ((gpio_usage_count & (0x1 << gpio)) == 0) {
348 gpio_usage_count &= ~(0x1 << gpio);
349 gpio_free(twl_gpiochip.base + gpio);
352 /* Last time usage? - switch off GPIO module */
353 if (ret == 0 && !gpio_usage_count)
354 ret = gpio_twl4030_write(REG_GPIO_CTRL, 0x0);
356 mutex_unlock(&gpio_lock);
359 EXPORT_SYMBOL(twl4030_free_gpio);
362 * Set direction for TWL4030 GPIO
364 static int twl4030_set_gpio_direction(int gpio, int is_input)
366 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
367 u8 d_msk = MASK_GPIODATADIR_GPIOxDIR(GET_GPIO_DATA_OFF(gpio));
369 u8 base = REG_GPIODATADIR1 + d_bnk;
372 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
375 mutex_lock(&gpio_lock);
376 ret = gpio_twl4030_read(base);
379 reg = (u8) ((ret) & ~(d_msk));
381 reg = (u8) ((ret) | (d_msk));
383 ret = gpio_twl4030_write(base, reg);
385 mutex_unlock(&gpio_lock);
390 * To enable/disable GPIO pin on TWL4030
392 static int twl4030_set_gpio_dataout(int gpio, int enable)
394 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
395 u8 d_msk = MASK_GPIODATAOUT_GPIOxOUT(GET_GPIO_DATA_OFF(gpio));
399 if (unlikely(!(gpio_usage_count & (0x1 << gpio))))
403 base = REG_SETGPIODATAOUT1 + d_bnk;
405 base = REG_CLEARGPIODATAOUT1 + d_bnk;
407 mutex_lock(&gpio_lock);
408 ret = gpio_twl4030_write(base, d_msk);
409 mutex_unlock(&gpio_lock);
414 * To get the status of a GPIO pin on TWL4030
416 int twl4030_get_gpio_datain(int gpio)
418 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
419 u8 d_off = BIT_GPIODATAIN_GPIOxIN(GET_GPIO_DATA_OFF(gpio));
423 if (unlikely((gpio >= TWL4030_GPIO_MAX)
424 || !(gpio_usage_count & (0x1 << gpio))))
427 base = REG_GPIODATAIN1 + d_bnk;
428 mutex_lock(&gpio_lock);
429 ret = gpio_twl4030_read(base);
430 mutex_unlock(&gpio_lock);
432 ret = (ret >> d_off) & 0x1;
436 EXPORT_SYMBOL(twl4030_get_gpio_datain);
440 * Configure PULL type for a GPIO pin on TWL4030
442 int twl4030_set_gpio_pull(int gpio, int pull_dircn)
444 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
445 u8 c_off = GET_GPIO_CTL_OFF(gpio);
451 if (unlikely((gpio >= TWL4030_GPIO_MAX) ||
452 !(gpio_usage_count & (0x1 << gpio))))
455 base = REG_GPIOPUPDCTR1 + c_bnk;
456 if (pull_dircn == TWL4030_GPIO_PULL_DOWN)
457 c_msk = MASK_GPIOPUPDCTR1_GPIOxPD(c_off);
458 else if (pull_dircn == TWL4030_GPIO_PULL_UP)
459 c_msk = MASK_GPIOPUPDCTR1_GPIOxPU(c_off);
461 mutex_lock(&gpio_lock);
462 ret = gpio_twl4030_read(base);
464 /* clear the previous up/down values */
466 reg &= ~(MASK_GPIOPUPDCTR1_GPIOxPU(c_off) |
467 MASK_GPIOPUPDCTR1_GPIOxPD(c_off));
469 ret = gpio_twl4030_write(base, reg);
471 mutex_unlock(&gpio_lock);
477 * Configure Edge control for a GPIO pin on TWL4030
479 * FIXME this should just be the irq_chip.set_type() method
481 int twl4030_set_gpio_edge_ctrl(int gpio, int edge)
483 u8 c_bnk = GET_GPIO_CTL_BANK(gpio);
484 u8 c_off = GET_GPIO_CTL_OFF(gpio);
490 if (unlikely((gpio >= TWL4030_GPIO_MAX)
491 || !(gpio_usage_count & (0x1 << gpio))))
494 base = REG_GPIO_EDR1 + c_bnk;
496 if (edge & TWL4030_GPIO_EDGE_RISING)
497 c_msk |= MASK_GPIO_EDR1_GPIOxRISING(c_off);
499 if (edge & TWL4030_GPIO_EDGE_FALLING)
500 c_msk |= MASK_GPIO_EDR1_GPIOxFALLING(c_off);
502 mutex_lock(&gpio_lock);
503 ret = gpio_twl4030_read(base);
505 /* clear the previous rising/falling values */
508 ~(MASK_GPIO_EDR1_GPIOxFALLING(c_off) |
509 MASK_GPIO_EDR1_GPIOxRISING(c_off)));
511 ret = gpio_twl4030_write(base, reg);
513 mutex_unlock(&gpio_lock);
516 EXPORT_SYMBOL(twl4030_set_gpio_edge_ctrl);
519 * Configure debounce timing value for a GPIO pin on TWL4030
521 int twl4030_set_gpio_debounce(int gpio, int enable)
523 u8 d_bnk = GET_GPIO_DATA_BANK(gpio);
524 u8 d_msk = MASK_GPIO_DEBEN_GPIOxDEB(GET_GPIO_DATA_OFF(gpio));
529 if (unlikely((gpio >= TWL4030_GPIO_MAX)
530 || !(gpio_usage_count & (0x1 << gpio))))
533 base = REG_GPIO_DEBEN1 + d_bnk;
534 mutex_lock(&gpio_lock);
535 ret = gpio_twl4030_read(base);
538 reg = (u8) ((ret) | (d_msk));
540 reg = (u8) ((ret) & ~(d_msk));
542 ret = gpio_twl4030_write(base, reg);
544 mutex_unlock(&gpio_lock);
547 EXPORT_SYMBOL(twl4030_set_gpio_debounce);
551 * Configure Card detect for GPIO pin on TWL4030
553 int twl4030_set_gpio_card_detect(int gpio, int enable)
556 u8 msk = (1 << gpio);
559 /* Only GPIO 0 or 1 can be used for CD feature.. */
560 if (unlikely((gpio >= TWL4030_GPIO_MAX)
561 || !(gpio_usage_count & (0x1 << gpio))
562 || (gpio >= TWL4030_GPIO_MAX_CD))) {
566 mutex_lock(&gpio_lock);
567 ret = gpio_twl4030_read(REG_GPIO_CTRL);
570 reg = (u8) (ret | msk);
572 reg = (u8) (ret & ~msk);
574 ret = gpio_twl4030_write(REG_GPIO_CTRL, reg);
576 mutex_unlock(&gpio_lock);
581 /* MODULE FUNCTIONS */
584 * gpio_unmask_thread() runs as a kernel thread. It is awakened by the unmask
585 * method for the GPIO interrupts. It unmasks all of the GPIO interrupts
586 * specified in the gpio_pending_unmask bitmask. We have to do the unmasking
587 * in a kernel thread rather than directly in the unmask method because of the
588 * need to access the TWL4030 via the I2C bus. Note that we don't need to be
589 * concerned about race conditions where the request to unmask a GPIO interrupt
590 * has already been cancelled before this thread does the unmasking. If a GPIO
591 * interrupt is improperly unmasked, then the IRQ handler for it will mask it
592 * when an interrupt occurs.
594 static int twl4030_gpio_unmask_thread(void *data)
596 current->flags |= PF_NOFREEZE;
598 while (!kthread_should_stop()) {
600 unsigned int gpio_unmask;
603 gpio_unmask = gpio_pending_unmask;
604 gpio_pending_unmask = 0;
607 for (irq = twl4030_gpio_irq_base; 0 != gpio_unmask;
608 gpio_unmask >>= 1, irq++) {
609 if (gpio_unmask & 0x1)
610 twl4030_gpio_unmask(irq);
614 if (!gpio_pending_unmask)
615 set_current_state(TASK_INTERRUPTIBLE);
620 set_current_state(TASK_RUNNING);
625 * do_twl4030_gpio_irq() is the desc->handle method for each of the twl4030
626 * gpio interrupts. It executes in kernel thread context.
627 * On entry, cpu interrupts are enabled.
629 static void do_twl4030_gpio_irq(unsigned int irq, irq_desc_t *desc)
631 struct irqaction *action;
632 const unsigned int cpu = smp_processor_id();
634 desc->status |= IRQ_LEVEL;
637 * Acknowledge, clear _AND_ disable the interrupt.
639 twl4030_gpio_mask_and_ack(irq);
642 kstat_cpu(cpu).irqs[irq]++;
644 action = desc->action;
650 /* Call the ISR with cpu interrupts enabled. */
651 ret = action->handler(irq, action->dev_id);
652 if (ret == IRQ_HANDLED)
653 status |= action->flags;
655 action = action->next;
658 if (retval != IRQ_HANDLED)
659 printk(KERN_ERR "ISR for TWL4030 GPIO"
660 " irq %d can't handle interrupt\n",
664 twl4030_gpio_unmask(irq);
670 * do_twl4030_gpio_module_irq() is the desc->handle method for the twl4030 gpio
671 * module interrupt. It executes in kernel thread context.
672 * This is a chained interrupt, so there is no desc->action method for it.
673 * We query the gpio module interrupt controller in the twl4030 to determine
674 * which gpio lines are generating interrupt requests, and then call the
675 * desc->handle method for each gpio that needs service.
676 * On entry, cpu interrupts are disabled.
678 static void do_twl4030_gpio_module_irq(unsigned int irq, irq_desc_t *desc)
680 const unsigned int cpu = smp_processor_id();
682 desc->status |= IRQ_LEVEL;
684 * The desc->handle method would normally call the desc->chip->ack
685 * method here, but we won't bother since our ack method is NULL.
689 unsigned int gpio_isr;
691 kstat_cpu(cpu).irqs[irq]++;
694 mutex_lock(&gpio_lock);
695 if (gpio_read_isr(&gpio_isr))
697 mutex_unlock(&gpio_lock);
699 for (gpio_irq = twl4030_gpio_irq_base; 0 != gpio_isr;
700 gpio_isr >>= 1, gpio_irq++) {
701 if (gpio_isr & 0x1) {
702 irq_desc_t *d = irq_desc + gpio_irq;
703 d->handle_irq(gpio_irq, d);
709 * Here is where we should call the unmask method, but again we
710 * won't bother since it is NULL.
715 /*----------------------------------------------------------------------*/
717 static int twl_direction_in(struct gpio_chip *chip, unsigned offset)
719 return twl4030_set_gpio_direction(offset, 1);
722 static int twl_get(struct gpio_chip *chip, unsigned offset)
724 int status = twl4030_get_gpio_datain(offset);
726 return (status < 0) ? 0 : status;
729 static int twl_direction_out(struct gpio_chip *chip, unsigned offset, int value)
731 twl4030_set_gpio_dataout(offset, value);
732 return twl4030_set_gpio_direction(offset, 0);
735 static void twl_set(struct gpio_chip *chip, unsigned offset, int value)
737 twl4030_set_gpio_dataout(offset, value);
740 static struct gpio_chip twl_gpiochip = {
742 .owner = THIS_MODULE,
743 .direction_input = twl_direction_in,
745 .direction_output = twl_direction_out,
750 /*----------------------------------------------------------------------*/
752 static int gpio_twl4030_remove(struct platform_device *pdev);
754 static int __devinit gpio_twl4030_probe(struct platform_device *pdev)
756 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
760 /* All GPIO interrupts are initially masked */
761 gpio_pending_unmask = 0;
762 gpio_imr_shadow = GPIO_32_MASK;
763 ret = gpio_write_imr(gpio_imr_shadow);
765 twl4030_gpio_irq_base = pdata->irq_base;
766 twl4030_gpio_irq_end = pdata->irq_end;
768 /* REVISIT skip most of this if the irq range is empty... */
771 * Create a kernel thread to handle deferred unmasking of gpio
774 gpio_unmask_thread = kthread_create(twl4030_gpio_unmask_thread,
775 NULL, "twl4030 gpio");
776 if (!gpio_unmask_thread) {
778 "could not create twl4030 gpio unmask"
785 /* install an irq handler for each of the gpio interrupts */
786 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end;
788 set_irq_chip(irq, &twl4030_gpio_irq_chip);
789 set_irq_handler(irq, do_twl4030_gpio_irq);
790 set_irq_flags(irq, IRQF_VALID);
793 /* gpio module IRQ */
794 irq = platform_get_irq(pdev, 0);
797 * Install an irq handler to demultiplex the gpio module
800 set_irq_chip(irq, &twl4030_gpio_module_irq_chip);
801 set_irq_chained_handler(irq, do_twl4030_gpio_module_irq);
802 wake_up_process(gpio_unmask_thread);
804 dev_info(&pdev->dev, "IRQ %d chains IRQs %d..%d\n", irq,
805 twl4030_gpio_irq_base, twl4030_gpio_irq_end - 1);
809 twl_gpiochip.base = pdata->gpio_base;
810 twl_gpiochip.ngpio = TWL4030_GPIO_MAX;
811 twl_gpiochip.dev = &pdev->dev;
813 ret = gpiochip_add(&twl_gpiochip);
816 "could not register gpiochip, %d\n",
818 twl_gpiochip.ngpio = 0;
819 gpio_twl4030_remove(pdev);
820 } else if (pdata->setup) {
823 status = pdata->setup(&pdev->dev,
824 pdata->gpio_base, TWL4030_GPIO_MAX);
826 dev_dbg(&pdev->dev, "setup --> %d\n", status);
833 static int __devexit gpio_twl4030_remove(struct platform_device *pdev)
835 struct twl4030_gpio_platform_data *pdata = pdev->dev.platform_data;
839 if (pdata->teardown) {
840 status = pdata->teardown(&pdev->dev,
841 pdata->gpio_base, TWL4030_GPIO_MAX);
843 dev_dbg(&pdev->dev, "teardown --> %d\n", status);
848 status = gpiochip_remove(&twl_gpiochip);
852 /* uninstall the gpio demultiplexing interrupt handler */
853 irq = platform_get_irq(pdev, 0);
854 set_irq_handler(irq, NULL);
855 set_irq_flags(irq, 0);
857 /* uninstall the irq handler for each of the gpio interrupts */
858 for (irq = twl4030_gpio_irq_base; irq < twl4030_gpio_irq_end; irq++) {
859 set_irq_handler(irq, NULL);
860 set_irq_flags(irq, 0);
863 /* stop the gpio unmask kernel thread */
864 if (gpio_unmask_thread) {
865 kthread_stop(gpio_unmask_thread);
866 gpio_unmask_thread = NULL;
872 /* Note: this hardware lives inside an I2C-based multi-function device. */
873 MODULE_ALIAS("platform:twl4030_gpio");
875 static struct platform_driver gpio_twl4030_driver = {
876 .driver.name = "twl4030_gpio",
877 .driver.owner = THIS_MODULE,
878 .probe = gpio_twl4030_probe,
879 .remove = __devexit_p(gpio_twl4030_remove),
882 static int __init gpio_twl4030_init(void)
884 return platform_driver_register(&gpio_twl4030_driver);
886 module_init(gpio_twl4030_init);
888 static void __exit gpio_twl4030_exit(void)
890 platform_driver_unregister(&gpio_twl4030_driver);
892 module_exit(gpio_twl4030_exit);
894 MODULE_AUTHOR("Texas Instruments, Inc.");
895 MODULE_DESCRIPTION("GPIO interface for TWL4030");
896 MODULE_LICENSE("GPL");