1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
26 #include <linux/i2c.h>
27 #include <linux/i2c-id.h>
28 #include <linux/init.h>
29 #include <linux/time.h>
30 #include <linux/interrupt.h>
31 #include <linux/delay.h>
32 #include <linux/errno.h>
33 #include <linux/err.h>
34 #include <linux/platform_device.h>
35 #include <linux/clk.h>
36 #include <linux/cpufreq.h>
41 #include <asm/plat-s3c/regs-iic.h>
42 #include <asm/plat-s3c/iic.h>
44 /* i2c controller state */
46 enum s3c24xx_i2c_state {
56 wait_queue_head_t wait;
63 unsigned int tx_setup;
65 enum s3c24xx_i2c_state state;
66 unsigned long clkrate;
72 struct resource *ioarea;
73 struct i2c_adapter adap;
75 #ifdef CONFIG_CPU_FREQ
76 struct notifier_block freq_transition;
80 /* default platform data to use if not supplied in the platform_device
83 static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
88 .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
91 /* s3c24xx_i2c_is2440()
93 * return true is this is an s3c2440
96 static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
98 struct platform_device *pdev = to_platform_device(i2c->dev);
100 return !strcmp(pdev->name, "s3c2440-i2c");
104 /* s3c24xx_i2c_get_platformdata
106 * get the platform data associated with the given device, or return
107 * the default if there is none
110 static inline struct s3c2410_platform_i2c *
111 s3c24xx_i2c_get_platformdata(struct device *dev)
113 if (dev->platform_data != NULL)
114 return (struct s3c2410_platform_i2c *)dev->platform_data;
116 return &s3c24xx_i2c_default_platform;
119 /* s3c24xx_i2c_master_complete
121 * complete the message and wake up the caller, using the given return code,
122 * or zero to mean ok.
125 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
127 dev_dbg(i2c->dev, "master_complete %d\n", ret);
139 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
143 tmp = readl(i2c->regs + S3C2410_IICCON);
144 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
147 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
151 tmp = readl(i2c->regs + S3C2410_IICCON);
152 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
155 /* irq enable/disable functions */
157 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
161 tmp = readl(i2c->regs + S3C2410_IICCON);
162 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
165 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
169 tmp = readl(i2c->regs + S3C2410_IICCON);
170 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
174 /* s3c24xx_i2c_message_start
176 * put the start of a message onto the bus
179 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
182 unsigned int addr = (msg->addr & 0x7f) << 1;
184 unsigned long iiccon;
187 stat |= S3C2410_IICSTAT_TXRXEN;
189 if (msg->flags & I2C_M_RD) {
190 stat |= S3C2410_IICSTAT_MASTER_RX;
193 stat |= S3C2410_IICSTAT_MASTER_TX;
195 if (msg->flags & I2C_M_REV_DIR_ADDR)
198 /* todo - check for wether ack wanted or not */
199 s3c24xx_i2c_enable_ack(i2c);
201 iiccon = readl(i2c->regs + S3C2410_IICCON);
202 writel(stat, i2c->regs + S3C2410_IICSTAT);
204 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
205 writeb(addr, i2c->regs + S3C2410_IICDS);
207 /* delay here to ensure the data byte has gotten onto the bus
208 * before the transaction is started */
210 ndelay(i2c->tx_setup);
212 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
213 writel(iiccon, i2c->regs + S3C2410_IICCON);
215 stat |= S3C2410_IICSTAT_START;
216 writel(stat, i2c->regs + S3C2410_IICSTAT);
219 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
221 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
223 dev_dbg(i2c->dev, "STOP\n");
225 /* stop the transfer */
226 iicstat &= ~S3C2410_IICSTAT_START;
227 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
229 i2c->state = STATE_STOP;
231 s3c24xx_i2c_master_complete(i2c, ret);
232 s3c24xx_i2c_disable_irq(i2c);
235 /* helper functions to determine the current state in the set of
236 * messages we are sending */
240 * returns TRUE if the current message is the last in the set
243 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
245 return i2c->msg_idx >= (i2c->msg_num - 1);
250 * returns TRUE if we this is the last byte in the current message
253 static inline int is_msglast(struct s3c24xx_i2c *i2c)
255 return i2c->msg_ptr == i2c->msg->len-1;
260 * returns TRUE if we reached the end of the current message
263 static inline int is_msgend(struct s3c24xx_i2c *i2c)
265 return i2c->msg_ptr >= i2c->msg->len;
268 /* i2s_s3c_irq_nextbyte
270 * process an interrupt and work out what to do
273 static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
279 switch (i2c->state) {
282 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
287 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
288 s3c24xx_i2c_disable_irq(i2c);
292 /* last thing we did was send a start condition on the
293 * bus, or started a new i2c message
296 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
297 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
298 /* ack was not received... */
300 dev_dbg(i2c->dev, "ack was not received\n");
301 s3c24xx_i2c_stop(i2c, -ENXIO);
305 if (i2c->msg->flags & I2C_M_RD)
306 i2c->state = STATE_READ;
308 i2c->state = STATE_WRITE;
310 /* terminate the transfer if there is nothing to do
311 * as this is used by the i2c probe to find devices. */
313 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
314 s3c24xx_i2c_stop(i2c, 0);
318 if (i2c->state == STATE_READ)
321 /* fall through to the write state, as we will need to
322 * send a byte as well */
325 /* we are writing data to the device... check for the
326 * end of the message, and if so, work out what to do
329 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
330 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
331 dev_dbg(i2c->dev, "WRITE: No Ack\n");
333 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
340 if (!is_msgend(i2c)) {
341 byte = i2c->msg->buf[i2c->msg_ptr++];
342 writeb(byte, i2c->regs + S3C2410_IICDS);
344 /* delay after writing the byte to allow the
345 * data setup time on the bus, as writing the
346 * data to the register causes the first bit
347 * to appear on SDA, and SCL will change as
348 * soon as the interrupt is acknowledged */
350 ndelay(i2c->tx_setup);
352 } else if (!is_lastmsg(i2c)) {
353 /* we need to go to the next i2c message */
355 dev_dbg(i2c->dev, "WRITE: Next Message\n");
361 /* check to see if we need to do another message */
362 if (i2c->msg->flags & I2C_M_NOSTART) {
364 if (i2c->msg->flags & I2C_M_RD) {
365 /* cannot do this, the controller
366 * forces us to send a new START
367 * when we change direction */
369 s3c24xx_i2c_stop(i2c, -EINVAL);
374 /* send the new start */
375 s3c24xx_i2c_message_start(i2c, i2c->msg);
376 i2c->state = STATE_START;
382 s3c24xx_i2c_stop(i2c, 0);
387 /* we have a byte of data in the data register, do
388 * something with it, and then work out wether we are
389 * going to do any more read/write
392 byte = readb(i2c->regs + S3C2410_IICDS);
393 i2c->msg->buf[i2c->msg_ptr++] = byte;
396 if (is_msglast(i2c)) {
397 /* last byte of buffer */
400 s3c24xx_i2c_disable_ack(i2c);
402 } else if (is_msgend(i2c)) {
403 /* ok, we've read the entire buffer, see if there
404 * is anything else we need to do */
406 if (is_lastmsg(i2c)) {
407 /* last message, send stop and complete */
408 dev_dbg(i2c->dev, "READ: Send Stop\n");
410 s3c24xx_i2c_stop(i2c, 0);
412 /* go to the next transfer */
413 dev_dbg(i2c->dev, "READ: Next Transfer\n");
424 /* acknowlegde the IRQ and get back on with the work */
427 tmp = readl(i2c->regs + S3C2410_IICCON);
428 tmp &= ~S3C2410_IICCON_IRQPEND;
429 writel(tmp, i2c->regs + S3C2410_IICCON);
436 * top level IRQ servicing routine
439 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
441 struct s3c24xx_i2c *i2c = dev_id;
442 unsigned long status;
445 status = readl(i2c->regs + S3C2410_IICSTAT);
447 if (status & S3C2410_IICSTAT_ARBITR) {
448 /* deal with arbitration loss */
449 dev_err(i2c->dev, "deal with arbitration loss\n");
452 if (i2c->state == STATE_IDLE) {
453 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
455 tmp = readl(i2c->regs + S3C2410_IICCON);
456 tmp &= ~S3C2410_IICCON_IRQPEND;
457 writel(tmp, i2c->regs + S3C2410_IICCON);
461 /* pretty much this leaves us with the fact that we've
462 * transmitted or received whatever byte we last sent */
464 i2s_s3c_irq_nextbyte(i2c, status);
471 /* s3c24xx_i2c_set_master
473 * get the i2c bus for a master transaction
476 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
478 unsigned long iicstat;
481 while (timeout-- > 0) {
482 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
484 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
493 /* s3c24xx_i2c_doxfer
495 * this starts an i2c transfer
498 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
499 struct i2c_msg *msgs, int num)
501 unsigned long timeout;
504 if (!(readl(i2c->regs + S3C2410_IICCON) & S3C2410_IICCON_IRQEN))
507 ret = s3c24xx_i2c_set_master(i2c);
509 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
514 spin_lock_irq(&i2c->lock);
520 i2c->state = STATE_START;
522 s3c24xx_i2c_enable_irq(i2c);
523 s3c24xx_i2c_message_start(i2c, msgs);
524 spin_unlock_irq(&i2c->lock);
526 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
530 /* having these next two as dev_err() makes life very
531 * noisy when doing an i2cdetect */
534 dev_dbg(i2c->dev, "timeout\n");
536 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
538 /* ensure the stop has been through the bus */
548 * first port of call from the i2c bus code when an message needs
549 * transferring across the i2c bus.
552 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
553 struct i2c_msg *msgs, int num)
555 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
559 for (retry = 0; retry < adap->retries; retry++) {
561 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
566 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
574 /* declare our i2c functionality */
575 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
577 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
580 /* i2c bus registration info */
582 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
583 .master_xfer = s3c24xx_i2c_xfer,
584 .functionality = s3c24xx_i2c_func,
587 static struct s3c24xx_i2c s3c24xx_i2c = {
588 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_i2c.lock),
589 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
592 .name = "s3c2410-i2c",
593 .owner = THIS_MODULE,
594 .algo = &s3c24xx_i2c_algorithm,
596 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
600 /* s3c24xx_i2c_calcdivisor
602 * return the divisor settings for a given frequency
605 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
606 unsigned int *div1, unsigned int *divs)
608 unsigned int calc_divs = clkin / wanted;
609 unsigned int calc_div1;
611 if (calc_divs > (16*16))
616 calc_divs += calc_div1-1;
617 calc_divs /= calc_div1;
627 return clkin / (calc_divs * calc_div1);
632 * test wether a frequency is within the acceptable range of error
635 static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
637 int diff = freq - wanted;
639 return diff >= -2 && diff <= 2;
642 /* s3c24xx_i2c_clockrate
644 * work out a divisor for the user requested frequency setting,
645 * either by the requested frequency, or scanning the acceptable
646 * range of frequencies until something is found
649 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
651 struct s3c2410_platform_i2c *pdata;
652 unsigned long clkin = clk_get_rate(i2c->clk);
653 unsigned int divs, div1;
658 i2c->clkrate = clkin;
660 pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
661 clkin /= 1000; /* clkin now in KHz */
663 dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
664 pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
666 if (pdata->bus_freq != 0) {
667 freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
669 if (freq_acceptable(freq, pdata->bus_freq/1000))
673 /* ok, we may have to search for something suitable... */
675 start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
676 end = pdata->min_freq;
683 for (; start > end; start--) {
684 freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
685 if (freq_acceptable(freq, start))
689 /* cannot find frequency spec */
696 iiccon = readl(i2c->regs + S3C2410_IICCON);
697 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
701 iiccon |= S3C2410_IICCON_TXDIV_512;
703 writel(iiccon, i2c->regs + S3C2410_IICCON);
708 #ifdef CONFIG_CPU_FREQ
710 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
712 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
713 unsigned long val, void *data)
715 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
721 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
723 /* if we're post-change and the input clock has slowed down
724 * or at pre-change and the clock is about to speed up, then
725 * adjust our clock rate. <0 is slow, >0 speedup.
728 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
729 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
730 spin_lock_irqsave(&i2c->lock, flags);
731 ret = s3c24xx_i2c_clockrate(i2c, &got);
732 spin_unlock_irqrestore(&i2c->lock, flags);
735 dev_err(i2c->dev, "cannot find frequency\n");
737 dev_info(i2c->dev, "setting freq %d\n", got);
743 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
745 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
747 return cpufreq_register_notifier(&i2c->freq_transition,
748 CPUFREQ_TRANSITION_NOTIFIER);
751 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
753 cpufreq_unregister_notifier(&i2c->freq_transition,
754 CPUFREQ_TRANSITION_NOTIFIER);
758 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
763 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
770 * initialise the controller, set the IO lines and frequency
773 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
775 unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
776 struct s3c2410_platform_i2c *pdata;
779 /* get the plafrom data */
781 pdata = s3c24xx_i2c_get_platformdata(i2c->dev);
783 /* inititalise the gpio */
786 pdata->cfg_gpio(to_platform_device(i2c->dev));
788 /* write slave address */
790 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
792 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
794 writel(iicon, i2c->regs + S3C2410_IICCON);
796 /* we need to work out the divisors for the clock... */
798 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
799 writel(0, i2c->regs + S3C2410_IICCON);
800 dev_err(i2c->dev, "cannot meet bus frequency required\n");
804 /* todo - check that the i2c lines aren't being dragged anywhere */
806 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
807 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
809 /* check for s3c2440 i2c controller */
811 if (s3c24xx_i2c_is2440(i2c)) {
812 dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
814 writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
822 * called by the bus driver when a suitable device is found
825 static int s3c24xx_i2c_probe(struct platform_device *pdev)
827 struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
828 struct s3c2410_platform_i2c *pdata;
829 struct resource *res;
832 pdata = s3c24xx_i2c_get_platformdata(&pdev->dev);
834 /* find the clock and enable it */
836 i2c->dev = &pdev->dev;
837 i2c->clk = clk_get(&pdev->dev, "i2c");
838 if (IS_ERR(i2c->clk)) {
839 dev_err(&pdev->dev, "cannot get clock\n");
844 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
846 clk_enable(i2c->clk);
848 /* map the registers */
850 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
852 dev_err(&pdev->dev, "cannot find IO resource\n");
857 i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
860 if (i2c->ioarea == NULL) {
861 dev_err(&pdev->dev, "cannot request IO\n");
866 i2c->regs = ioremap(res->start, (res->end-res->start)+1);
868 if (i2c->regs == NULL) {
869 dev_err(&pdev->dev, "cannot map IO\n");
874 dev_dbg(&pdev->dev, "registers %p (%p, %p)\n",
875 i2c->regs, i2c->ioarea, res);
877 /* setup info block for the i2c core */
879 i2c->adap.algo_data = i2c;
880 i2c->adap.dev.parent = &pdev->dev;
882 /* initialise the i2c controller */
884 ret = s3c24xx_i2c_init(i2c);
888 /* find the IRQ for this unit (note, this relies on the init call to
889 * ensure no current IRQs pending
892 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
894 dev_err(&pdev->dev, "cannot find IRQ\n");
899 ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
903 dev_err(&pdev->dev, "cannot claim IRQ\n");
909 dev_dbg(&pdev->dev, "irq resource %p (%lu)\n", res,
910 (unsigned long)res->start);
912 ret = s3c24xx_i2c_register_cpufreq(i2c);
914 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
918 /* Note, previous versions of the driver used i2c_add_adapter()
919 * to add the bus at any number. We now pass the bus number via
920 * the platform data, so if unset it will now default to always
924 i2c->adap.nr = pdata->bus_num;
926 ret = i2c_add_numbered_adapter(&i2c->adap);
928 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
932 platform_set_drvdata(pdev, i2c);
934 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
938 s3c24xx_i2c_deregister_cpufreq(i2c);
941 free_irq(i2c->irq->start, i2c);
947 release_resource(i2c->ioarea);
951 clk_disable(i2c->clk);
958 /* s3c24xx_i2c_remove
960 * called when device is removed from the bus
963 static int s3c24xx_i2c_remove(struct platform_device *pdev)
965 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
967 s3c24xx_i2c_deregister_cpufreq(i2c);
969 i2c_del_adapter(&i2c->adap);
970 free_irq(i2c->irq->start, i2c);
972 clk_disable(i2c->clk);
977 release_resource(i2c->ioarea);
984 static int s3c24xx_i2c_resume(struct platform_device *dev)
986 struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
989 s3c24xx_i2c_init(i2c);
995 #define s3c24xx_i2c_resume NULL
998 /* device driver for platform bus bits */
1000 static struct platform_driver s3c2410_i2c_driver = {
1001 .probe = s3c24xx_i2c_probe,
1002 .remove = s3c24xx_i2c_remove,
1003 .resume = s3c24xx_i2c_resume,
1005 .owner = THIS_MODULE,
1006 .name = "s3c2410-i2c",
1010 static struct platform_driver s3c2440_i2c_driver = {
1011 .probe = s3c24xx_i2c_probe,
1012 .remove = s3c24xx_i2c_remove,
1013 .resume = s3c24xx_i2c_resume,
1015 .owner = THIS_MODULE,
1016 .name = "s3c2440-i2c",
1020 static int __init i2c_adap_s3c_init(void)
1024 ret = platform_driver_register(&s3c2410_i2c_driver);
1026 ret = platform_driver_register(&s3c2440_i2c_driver);
1028 platform_driver_unregister(&s3c2410_i2c_driver);
1034 static void __exit i2c_adap_s3c_exit(void)
1036 platform_driver_unregister(&s3c2410_i2c_driver);
1037 platform_driver_unregister(&s3c2440_i2c_driver);
1040 module_init(i2c_adap_s3c_init);
1041 module_exit(i2c_adap_s3c_exit);
1043 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1044 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1045 MODULE_LICENSE("GPL");
1046 MODULE_ALIAS("platform:s3c2410-i2c");
1047 MODULE_ALIAS("platform:s3c2440-i2c");