drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@nokia.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/delay.h>
  32 #include <linux/i2c.h>
  33 #include <linux/err.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/completion.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/clk.h>
  38
  39 #include <asm/io.h>
  40
  41 /* Hack to enable zero length transfers and smbus quick until clean fix
  42    is available */
  43 #define OMAP_HACK
  44
  45 /* timeout waiting for the controller to respond */
  46 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  47
  48 #define OMAP_I2C_REV_REG                0x00
  49 #define OMAP_I2C_IE_REG                 0x04
  50 #define OMAP_I2C_STAT_REG               0x08
  51 #define OMAP_I2C_IV_REG                 0x0c
  52 #define OMAP_I2C_SYSS_REG               0x10
  53 #define OMAP_I2C_BUF_REG                0x14
  54 #define OMAP_I2C_CNT_REG                0x18
  55 #define OMAP_I2C_DATA_REG               0x1c
  56 #define OMAP_I2C_SYSC_REG               0x20
  57 #define OMAP_I2C_CON_REG                0x24
  58 #define OMAP_I2C_OA_REG                 0x28
  59 #define OMAP_I2C_SA_REG                 0x2c
  60 #define OMAP_I2C_PSC_REG                0x30
  61 #define OMAP_I2C_SCLL_REG               0x34
  62 #define OMAP_I2C_SCLH_REG               0x38
  63 #define OMAP_I2C_SYSTEST_REG            0x3c
  64 #define OMAP_I2C_BUFSTAT_REG            0x40
  65
  66 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  67 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer draining int enable */
  68 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer draining int enable */
  69 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  70 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  71 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  72 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  73 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  74
  75 /* I2C Status Register (OMAP_I2C_STAT): */
  76 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  77 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  78 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  79 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  80 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  81 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  82 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  83 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  84 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  85 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  86 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  87 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  88
  89 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  90 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  91 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
  92 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  93 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
  94
  95 /* I2C Configuration Register (OMAP_I2C_CON): */
  96 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  97 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  98 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
  99 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 100 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 101 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 102 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 103 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 104 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 105 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 106
 107 /* I2C SCL time value when Master */
 108 #define OMAP_I2C_SCLL_HSSCLL    8
 109 #define OMAP_I2C_SCLH_HSSCLH    8
 110
 111 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 112 #ifdef DEBUG
 113 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 114 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 115 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 116 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 117 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 118 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 119 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 120 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 121 #endif
 122
 123 /* I2C System Status register (OMAP_I2C_SYSS): */
 124 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 125
 126 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 127 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 128
 129 struct omap_i2c_dev {
 130         struct device           *dev;
 131         void __iomem            *base;          /* virtual */
 132         int                     irq;
 133         struct clk              *iclk;          /* Interface clock */
 134         struct clk              *fclk;          /* Functional clock */
 135         struct completion       cmd_complete;
 136         struct resource         *ioarea;
 137         u32                     speed;          /* Speed of bus in Khz */
 138         u16                     cmd_err;
 139         u8                      *buf;
 140         size_t                  buf_len;
 141         struct i2c_adapter      adapter;
 142         u8                      fifo_size;      /* use as flag and value
 143                                                  * fifo_size==0 implies no fifo
 144                                                  * if set, should be trsh+1
 145                                                  */
 146         unsigned                rev1:1;
 147         unsigned                b_hw:1;         /* bad h/w fixes */
 148 };
 149
 150 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 151                                       int reg, u16 val)
 152 {
 153         __raw_writew(val, i2c_dev->base + reg);
 154 }
 155
 156 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 157 {
 158         return __raw_readw(i2c_dev->base + reg);
 159 }
 160
 161 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 162 {
 163         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 164                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 165                 if (IS_ERR(dev->iclk)) {
 166                         dev->iclk = NULL;
 167                         return -ENODEV;
 168                 }
 169         }
 170         /* For I2C operations on 2430 we need 96Mhz clock */
 171         if (cpu_is_omap2430()) {
 172                 dev->fclk = clk_get(dev->dev, "i2chs_fck");
 173                 if (IS_ERR(dev->fclk)) {
 174                         if (dev->iclk != NULL) {
 175                                 clk_put(dev->iclk);
 176                                 dev->iclk = NULL;
 177                         }
 178                         dev->fclk = NULL;
 179                         return -ENODEV;
 180                 }
 181         } else {
 182                 dev->fclk = clk_get(dev->dev, "i2c_fck");
 183                 if (IS_ERR(dev->fclk)) {
 184                         if (dev->iclk != NULL) {
 185                                 clk_put(dev->iclk);
 186                                 dev->iclk = NULL;
 187                         }
 188                         dev->fclk = NULL;
 189                         return -ENODEV;
 190                 }
 191         }
 192         return 0;
 193 }
 194
 195 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 196 {
 197         clk_put(dev->fclk);
 198         dev->fclk = NULL;
 199         if (dev->iclk != NULL) {
 200                 clk_put(dev->iclk);
 201                 dev->iclk = NULL;
 202         }
 203 }
 204
 205 static void omap_i2c_enable_clocks(struct omap_i2c_dev *dev)
 206 {
 207         if (dev->iclk != NULL)
 208                 clk_enable(dev->iclk);
 209         clk_enable(dev->fclk);
 210 }
 211
 212 static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
 213 {
 214         if (dev->iclk != NULL)
 215                 clk_disable(dev->iclk);
 216         clk_disable(dev->fclk);
 217 }
 218
 219 static int omap_i2c_init(struct omap_i2c_dev *dev)
 220 {
 221         u16 psc = 0, scll = 0, sclh = 0;
 222         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 223         unsigned long fclk_rate = 12000000;
 224         unsigned long timeout;
 225         unsigned long internal_clk = 0;
 226
 227         if (!dev->rev1) {
 228                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 229                 /* For some reason we need to set the EN bit before the
 230                  * reset done bit gets set. */
 231                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 232                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 233                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 234                          OMAP_I2C_SYSS_RDONE)) {
 235                         if (time_after(jiffies, timeout)) {
 236                                 dev_warn(dev->dev, "timeout waiting "
 237                                                 "for controller reset\n");
 238                                 return -ETIMEDOUT;
 239                         }
 240                         msleep(1);
 241                 }
 242         }
 243         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 244
 245         if (cpu_class_is_omap1()) {
 246                 struct clk *armxor_ck;
 247
 248                 armxor_ck = clk_get(NULL, "armxor_ck");
 249                 if (IS_ERR(armxor_ck))
 250                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 251                 else {
 252                         fclk_rate = clk_get_rate(armxor_ck);
 253                         clk_put(armxor_ck);
 254                 }
 255                 /* TRM for 5912 says the I2C clock must be prescaled to be
 256                  * between 7 - 12 MHz. The XOR input clock is typically
 257                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 258                  *
 259                  * XOR MHz      Divider         Prescaler
 260                  * 12           1               0
 261                  * 13           2               1
 262                  * 19.2         2               1
 263                  */
 264                 if (fclk_rate > 12000000)
 265                         psc = fclk_rate / 12000000;
 266         }
 267
 268         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 269
 270                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
 271                 internal_clk = 19200;
 272                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 273
 274                 /* Compute prescaler divisor */
 275                 psc = fclk_rate / internal_clk;
 276                 psc = psc - 1;
 277
 278                 /* If configured for High Speed */
 279                 if (dev->speed > 400) {
 280                         /* For first phase of HS mode */
 281                         fsscll = internal_clk / (400 * 2) - 6;
 282                         fssclh = internal_clk / (400 * 2) - 6;
 283
 284                         /* For second phase of HS mode */
 285                         hsscll = fclk_rate / (dev->speed * 2) - 6;
 286                         hssclh = fclk_rate / (dev->speed * 2) - 6;
 287                 } else {
 288                         /* To handle F/S modes */
 289                         fsscll = internal_clk / (dev->speed * 2) - 6;
 290                         fssclh = internal_clk / (dev->speed * 2) - 6;
 291                 }
 292                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 293                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 294         } else {
 295                 /* Program desired operating rate */
 296                 fclk_rate /= (psc + 1) * 1000;
 297                 if (psc > 2)
 298                         psc = 2;
 299                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 300                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 301         }
 302
 303         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 304         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 305
 306         /* SCL low and high time values */
 307         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 308         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 309
 310         if (dev->fifo_size)
 311                 /* Note: setup required fifo size - 1 */
 312                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
 313                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
 314                                         OMAP_I2C_BUF_RXFIF_CLR |
 315                                         (dev->fifo_size - 1) | /* XTRSH */
 316                                         OMAP_I2C_BUF_TXFIF_CLR);
 317
 318         /* Take the I2C module out of reset: */
 319         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 320
 321         /* Enable interrupts */
 322         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 323                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 324                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 325                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 326                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
 327         return 0;
 328 }
 329
 330 /*
 331  * Waiting on Bus Busy
 332  */
 333 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 334 {
 335         unsigned long timeout;
 336
 337         timeout = jiffies + OMAP_I2C_TIMEOUT;
 338         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 339                 if (time_after(jiffies, timeout)) {
 340                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 341                         return -ETIMEDOUT;
 342                 }
 343                 msleep(1);
 344         }
 345
 346         return 0;
 347 }
 348
 349 /*
 350  * Low level master read/write transaction.
 351  */
 352 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 353                              struct i2c_msg *msg, int stop)
 354 {
 355         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 356 #ifdef OMAP_HACK
 357         u8 zero_byte = 0;
 358 #endif
 359         int r;
 360         u16 w;
 361
 362         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 363                 msg->addr, msg->len, msg->flags, stop);
 364
 365 #ifndef OMAP_HACK
 366         if (msg->len == 0)
 367                 return -EINVAL;
 368
 369         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 370
 371         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 372         dev->buf = msg->buf;
 373         dev->buf_len = msg->len;
 374
 375 #else
 376
 377         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 378         /* REVISIT: Remove this hack when we can get I2C chips from board-*.c
 379          *          files
 380          * Sigh, seems we can't do zero length transactions. Thus, we
 381          * can't probe for devices w/o actually sending/receiving at least
 382          * a single byte. So we'll set count to 1 for the zero length
 383          * transaction case and hope we don't cause grief for some
 384          * arbitrary device due to random byte write/read during
 385          * probes.
 386          */
 387         if (msg->len == 0) {
 388                 dev->buf = &zero_byte;
 389                 dev->buf_len = 1;
 390         } else {
 391                 dev->buf = msg->buf;
 392                 dev->buf_len = msg->len;
 393         }
 394 #endif
 395
 396         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 397
 398         /* Clear the FIFO Buffers */
 399         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 400         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 401         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 402
 403         init_completion(&dev->cmd_complete);
 404         dev->cmd_err = 0;
 405
 406         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 407
 408         /* High speed configuration */
 409         if (dev->speed > 400)
 410                 w |= OMAP_I2C_CON_OPMODE_HS;
 411
 412         if (msg->flags & I2C_M_TEN)
 413                 w |= OMAP_I2C_CON_XA;
 414         if (!(msg->flags & I2C_M_RD))
 415                 w |= OMAP_I2C_CON_TRX;
 416
 417         if (!dev->b_hw && stop)
 418                 w |= OMAP_I2C_CON_STP;
 419
 420         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 421
 422         if (dev->b_hw && stop) {
 423                 /* H/w behavior: dont write stt and stp together.. */
 424                 while (omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & OMAP_I2C_CON_STT) {
 425                         /* Dont do anything - this will come in a couple of loops at max*/
 426                 }
 427                 w |= OMAP_I2C_CON_STP;
 428                 w &= ~OMAP_I2C_CON_STT;
 429                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 430         }
 431         r = wait_for_completion_timeout(&dev->cmd_complete,
 432                                         OMAP_I2C_TIMEOUT);
 433         dev->buf_len = 0;
 434         if (r < 0)
 435                 return r;
 436         if (r == 0) {
 437                 dev_err(dev->dev, "controller timed out\n");
 438                 omap_i2c_init(dev);
 439                 return -ETIMEDOUT;
 440         }
 441
 442         if (likely(!dev->cmd_err))
 443                 return 0;
 444
 445         /* We have an error */
 446         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 447                             OMAP_I2C_STAT_XUDF)) {
 448                 omap_i2c_init(dev);
 449                 return -EIO;
 450         }
 451
 452         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 453                 if (msg->flags & I2C_M_IGNORE_NAK)
 454                         return 0;
 455                 if (stop) {
 456                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 457                         w |= OMAP_I2C_CON_STP;
 458                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 459                 }
 460                 return -EREMOTEIO;
 461         }
 462         return -EIO;
 463 }
 464
 465
 466 /*
 467  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 468  * to do the work during IRQ processing.
 469  */
 470 static int
 471 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 472 {
 473         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 474         int i;
 475         int r;
 476
 477         omap_i2c_enable_clocks(dev);
 478
 479         /* REVISIT: initialize and use adap->retries. This is an optional
 480          * feature */
 481         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 482                 goto out;
 483
 484         for (i = 0; i < num; i++) {
 485                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 486                 if (r != 0)
 487                         break;
 488         }
 489
 490         if (r == 0)
 491                 r = num;
 492 out:
 493         omap_i2c_disable_clocks(dev);
 494         return r;
 495 }
 496
 497 static u32
 498 omap_i2c_func(struct i2c_adapter *adap)
 499 {
 500 #ifndef OMAP_HACK
 501         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 502 #else
 503         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 504 #endif
 505 }
 506
 507 static inline void
 508 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 509 {
 510         dev->cmd_err |= err;
 511         complete(&dev->cmd_complete);
 512 }
 513
 514 static inline void
 515 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 516 {
 517         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 518 }
 519
 520 static irqreturn_t
 521 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 522 {
 523         struct omap_i2c_dev *dev = dev_id;
 524         u16 iv, w;
 525
 526         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 527         switch (iv) {
 528         case 0x00:      /* None */
 529                 break;
 530         case 0x01:      /* Arbitration lost */
 531                 dev_err(dev->dev, "Arbitration lost\n");
 532                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 533                 break;
 534         case 0x02:      /* No acknowledgement */
 535                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 536                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 537                 break;
 538         case 0x03:      /* Register access ready */
 539                 omap_i2c_complete_cmd(dev, 0);
 540                 break;
 541         case 0x04:      /* Receive data ready */
 542                 if (dev->buf_len) {
 543                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 544                         *dev->buf++ = w;
 545                         dev->buf_len--;
 546                         if (dev->buf_len) {
 547                                 *dev->buf++ = w >> 8;
 548                                 dev->buf_len--;
 549                         }
 550                 } else
 551                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 552                 break;
 553         case 0x05:      /* Transmit data ready */
 554                 if (dev->buf_len) {
 555                         w = *dev->buf++;
 556                         dev->buf_len--;
 557                         if (dev->buf_len) {
 558                                 w |= *dev->buf++ << 8;
 559                                 dev->buf_len--;
 560                         }
 561                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 562                 } else
 563                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 564                 break;
 565         default:
 566                 return IRQ_NONE;
 567         }
 568
 569         return IRQ_HANDLED;
 570 }
 571
 572 static irqreturn_t
 573 omap_i2c_isr(int this_irq, void *dev_id)
 574 {
 575         struct omap_i2c_dev *dev = dev_id;
 576         u16 bits;
 577         u16 stat, w;
 578         int count = 0;
 579
 580         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 581         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 582                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 583                 if (count++ == 100) {
 584                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 585                         break;
 586                 }
 587
 588                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 589
 590                 if (stat & OMAP_I2C_STAT_ARDY) {
 591                         omap_i2c_complete_cmd(dev, 0);
 592                         continue;
 593                 }
 594                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 595                         u8 num_bytes = 1;
 596                         if (dev->fifo_size) {
 597                                 num_bytes = (stat & OMAP_I2C_STAT_RRDY) ? dev->fifo_size :
 598                                                 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
 599                         }
 600                         while (num_bytes) {
 601                                 num_bytes--;
 602                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 603                                 if (dev->buf_len) {
 604                                         *dev->buf++ = w;
 605                                         dev->buf_len--;
 606                                         /* Data reg from 2430 is 8 bit wide */
 607                                         if (!cpu_is_omap2430() &&
 608                                                         !cpu_is_omap34xx()) {
 609                                                 if (dev->buf_len) {
 610                                                         *dev->buf++ = w >> 8;
 611                                                         dev->buf_len--;
 612                                                 }
 613                                         }
 614                                 } else {
 615                                         if (stat & OMAP_I2C_STAT_RRDY)
 616                                                 dev_err(dev->dev, "RRDY IRQ while no data "
 617                                                                 "requested\n");
 618                                         if (stat & OMAP_I2C_STAT_RDR)
 619                                                 dev_err(dev->dev, "RDR IRQ while no data "
 620                                                                 "requested\n");
 621                                         break;
 622                                 }
 623                         }
 624                         omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 625                         continue;
 626                 }
 627                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 628                         u8 num_bytes = 1;
 629                         if (dev->fifo_size) {
 630                                 num_bytes = (stat & OMAP_I2C_STAT_XRDY) ? dev->fifo_size :
 631                                                 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
 632                         }
 633                         while (num_bytes) {
 634                                 num_bytes--;
 635                                 w = 0;
 636                                 if (dev->buf_len) {
 637                                         w = *dev->buf++;
 638                                         dev->buf_len--;
 639                                         /* Data reg from  2430 is 8 bit wide */
 640                                         if (!cpu_is_omap2430() &&
 641                                                         !cpu_is_omap34xx()) {
 642                                                 if (dev->buf_len) {
 643                                                         w |= *dev->buf++ << 8;
 644                                                         dev->buf_len--;
 645                                                 }
 646                                         }
 647                                 } else {
 648                                         if (stat & OMAP_I2C_STAT_XRDY)
 649                                                 dev_err(dev->dev, "XRDY IRQ while no "
 650                                                                 "data to send\n");
 651                                         if (stat & OMAP_I2C_STAT_XDR)
 652                                                 dev_err(dev->dev, "XDR IRQ while no "
 653                                                                 "data to send\n");
 654                                         break;
 655                                 }
 656                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 657                         }
 658                         omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 659                         continue;
 660                 }
 661                 if (stat & OMAP_I2C_STAT_ROVR) {
 662                         dev_err(dev->dev, "Receive overrun\n");
 663                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 664                 }
 665                 if (stat & OMAP_I2C_STAT_XUDF) {
 666                         dev_err(dev->dev, "Transmit overflow\n");
 667                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 668                 }
 669                 if (stat & OMAP_I2C_STAT_NACK) {
 670                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 671                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 672                                            OMAP_I2C_CON_STP);
 673                 }
 674                 if (stat & OMAP_I2C_STAT_AL) {
 675                         dev_err(dev->dev, "Arbitration lost\n");
 676                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 677                 }
 678         }
 679
 680         return count ? IRQ_HANDLED : IRQ_NONE;
 681 }
 682
 683 static const struct i2c_algorithm omap_i2c_algo = {
 684         .master_xfer    = omap_i2c_xfer,
 685         .functionality  = omap_i2c_func,
 686 };
 687
 688 static int
 689 omap_i2c_probe(struct platform_device *pdev)
 690 {
 691         struct omap_i2c_dev     *dev;
 692         struct i2c_adapter      *adap;
 693         struct resource         *mem, *irq, *ioarea;
 694         int r;
 695         u32 *speed = NULL;
 696
 697         /* NOTE: driver uses the static register mapping */
 698         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 699         if (!mem) {
 700                 dev_err(&pdev->dev, "no mem resource?\n");
 701                 return -ENODEV;
 702         }
 703         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 704         if (!irq) {
 705                 dev_err(&pdev->dev, "no irq resource?\n");
 706                 return -ENODEV;
 707         }
 708
 709         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 710                         pdev->name);
 711         if (!ioarea) {
 712                 dev_err(&pdev->dev, "I2C region already claimed\n");
 713                 return -EBUSY;
 714         }
 715
 716         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 717         if (!dev) {
 718                 r = -ENOMEM;
 719                 goto err_release_region;
 720         }
 721
 722         if (pdev->dev.platform_data != NULL)
 723                 speed = (u32 *) pdev->dev.platform_data;
 724         else
 725                 *speed = 100; /* Defualt speed */
 726
 727         dev->speed = *speed;
 728         dev->dev = &pdev->dev;
 729         dev->irq = irq->start;
 730         dev->base = (void __iomem *) IO_ADDRESS(mem->start);
 731         platform_set_drvdata(pdev, dev);
 732
 733         if ((r = omap_i2c_get_clocks(dev)) != 0)
 734                 goto err_free_mem;
 735
 736         omap_i2c_enable_clocks(dev);
 737
 738         if (cpu_is_omap15xx())
 739                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 740
 741         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 742                 /* Set up the fifo size - Get total size */
 743                 dev->fifo_size = 0x8 <<
 744                         ((omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3);
 745                 /*
 746                  * Set up notification threshold as half the total available size
 747                  * This is to ensure that we can handle the status on int call back
 748                  * latencies
 749                  */
 750                 dev->fifo_size = (dev->fifo_size / 2);
 751                 dev->b_hw = 1; /* Enable hardware fixes */
 752         }
 753
 754         /* reset ASAP, clearing any IRQs */
 755         omap_i2c_init(dev);
 756
 757         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 758                         0, pdev->name, dev);
 759
 760         if (r) {
 761                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 762                 goto err_unuse_clocks;
 763         }
 764         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 765         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 766                  pdev->id, r >> 4, r & 0xf, dev->speed);
 767
 768         adap = &dev->adapter;
 769         i2c_set_adapdata(adap, dev);
 770         adap->owner = THIS_MODULE;
 771         adap->class = I2C_CLASS_HWMON;
 772         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 773         adap->algo = &omap_i2c_algo;
 774         adap->dev.parent = &pdev->dev;
 775
 776         /* i2c device drivers may be active on return from add_adapter() */
 777         adap->nr = pdev->id;
 778         r = i2c_add_numbered_adapter(adap);
 779         if (r) {
 780                 dev_err(dev->dev, "failure adding adapter\n");
 781                 goto err_free_irq;
 782         }
 783
 784         omap_i2c_disable_clocks(dev);
 785
 786         return 0;
 787
 788 err_free_irq:
 789         free_irq(dev->irq, dev);
 790 err_unuse_clocks:
 791         omap_i2c_disable_clocks(dev);
 792         omap_i2c_put_clocks(dev);
 793 err_free_mem:
 794         platform_set_drvdata(pdev, NULL);
 795         kfree(dev);
 796 err_release_region:
 797         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 798         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 799
 800         return r;
 801 }
 802
 803 static int
 804 omap_i2c_remove(struct platform_device *pdev)
 805 {
 806         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 807         struct resource         *mem;
 808
 809         platform_set_drvdata(pdev, NULL);
 810
 811         free_irq(dev->irq, dev);
 812         i2c_del_adapter(&dev->adapter);
 813         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 814         omap_i2c_put_clocks(dev);
 815         kfree(dev);
 816         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 817         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 818         return 0;
 819 }
 820
 821 static struct platform_driver omap_i2c_driver = {
 822         .probe          = omap_i2c_probe,
 823         .remove         = omap_i2c_remove,
 824         .driver         = {
 825                 .name   = "i2c_omap",
 826                 .owner  = THIS_MODULE,
 827         },
 828 };
 829
 830 /* I2C may be needed to bring up other drivers */
 831 static int __init
 832 omap_i2c_init_driver(void)
 833 {
 834         return platform_driver_register(&omap_i2c_driver);
 835 }
 836 subsys_initcall(omap_i2c_init_driver);
 837
 838 static void __exit omap_i2c_exit_driver(void)
 839 {
 840         platform_driver_unregister(&omap_i2c_driver);
 841 }
 842 module_exit(omap_i2c_exit_driver);
 843
 844 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 845 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 846 MODULE_LICENSE("GPL");