drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2004 Texas Instruments.
   6  *
   7  * Updated to work with multiple I2C interfaces on 24xx by
   8  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
   9  * Copyright (C) 2005 Nokia Corporation
  10  *
  11  * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License as published by
  15  * the Free Software Foundation; either version 2 of the License, or
  16  * (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/delay.h>
  30 #include <linux/i2c.h>
  31 #include <linux/err.h>
  32 #include <linux/interrupt.h>
  33 #include <linux/completion.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/clk.h>
  36
  37 #include <asm/io.h>
  38
  39 /* Hack to enable zero length transfers and smbus quick until clean fix
  40    is available */
  41 #define OMAP_HACK
  42
  43 /* timeout waiting for the controller to respond */
  44 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  45
  46 #define OMAP_I2C_REV_REG                0x00
  47 #define OMAP_I2C_IE_REG                 0x04
  48 #define OMAP_I2C_STAT_REG               0x08
  49 #define OMAP_I2C_IV_REG                 0x0c
  50 #define OMAP_I2C_SYSS_REG               0x10
  51 #define OMAP_I2C_BUF_REG                0x14
  52 #define OMAP_I2C_CNT_REG                0x18
  53 #define OMAP_I2C_DATA_REG               0x1c
  54 #define OMAP_I2C_SYSC_REG               0x20
  55 #define OMAP_I2C_CON_REG                0x24
  56 #define OMAP_I2C_OA_REG                 0x28
  57 #define OMAP_I2C_SA_REG                 0x2c
  58 #define OMAP_I2C_PSC_REG                0x30
  59 #define OMAP_I2C_SCLL_REG               0x34
  60 #define OMAP_I2C_SCLH_REG               0x38
  61 #define OMAP_I2C_SYSTEST_REG            0x3c
  62
  63 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  64 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  65 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  66 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  67 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  68 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  69
  70 /* I2C Status Register (OMAP_I2C_STAT): */
  71 #define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
  72 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  73 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  74 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  75 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  76 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  77 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  78 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  79 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  80 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  81 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  82
  83 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  84 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  85 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  86
  87 /* I2C Configuration Register (OMAP_I2C_CON): */
  88 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  89 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  90 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
  91 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
  92 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
  93 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
  94 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
  95 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
  96 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
  97
  98 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
  99 #ifdef DEBUG
 100 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 101 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 102 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 103 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 104 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 105 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 106 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 107 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 108 #endif
 109
 110 /* I2C System Status register (OMAP_I2C_SYSS): */
 111 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 112
 113 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 114 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 115
 116 /* REVISIT: Use platform_data instead of module parameters */
 117 /* Fast Mode = 400 kHz, Standard = 100 kHz */
 118 static int clock = 100; /* Default: 100 kHz */
 119 module_param(clock, int, 0);
 120 MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 400=fast mode (default == 100)");
 121
 122 struct omap_i2c_dev {
 123         struct device           *dev;
 124         void __iomem            *base;          /* virtual */
 125         int                     irq;
 126         struct clk              *iclk;          /* Interface clock */
 127         struct clk              *fclk;          /* Functional clock */
 128         struct completion       cmd_complete;
 129         struct resource         *ioarea;
 130         u16                     cmd_err;
 131         u8                      *buf;
 132         size_t                  buf_len;
 133         struct i2c_adapter      adapter;
 134         unsigned                rev1:1;
 135 };
 136
 137 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 138                                       int reg, u16 val)
 139 {
 140         __raw_writew(val, i2c_dev->base + reg);
 141 }
 142
 143 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 144 {
 145         return __raw_readw(i2c_dev->base + reg);
 146 }
 147
 148 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 149 {
 150         if (cpu_is_omap16xx() || cpu_is_omap24xx()) {
 151                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 152                 if (IS_ERR(dev->iclk)) {
 153                         dev->iclk = NULL;
 154                         return -ENODEV;
 155                 }
 156         }
 157
 158         dev->fclk = clk_get(dev->dev, "i2c_fck");
 159         if (IS_ERR(dev->fclk)) {
 160                 if (dev->iclk != NULL) {
 161                         clk_put(dev->iclk);
 162                         dev->iclk = NULL;
 163                 }
 164                 dev->fclk = NULL;
 165                 return -ENODEV;
 166         }
 167
 168         return 0;
 169 }
 170
 171 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 172 {
 173         clk_put(dev->fclk);
 174         dev->fclk = NULL;
 175         if (dev->iclk != NULL) {
 176                 clk_put(dev->iclk);
 177                 dev->iclk = NULL;
 178         }
 179 }
 180
 181 static void omap_i2c_enable_clocks(struct omap_i2c_dev *dev)
 182 {
 183         if (dev->iclk != NULL)
 184                 clk_enable(dev->iclk);
 185         clk_enable(dev->fclk);
 186 }
 187
 188 static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
 189 {
 190         if (dev->iclk != NULL)
 191                 clk_disable(dev->iclk);
 192         clk_disable(dev->fclk);
 193 }
 194
 195 static int omap_i2c_init(struct omap_i2c_dev *dev)
 196 {
 197         u16 psc = 0;
 198         unsigned long fclk_rate = 12000000;
 199         unsigned long timeout;
 200
 201         if (!dev->rev1) {
 202                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 203                 /* For some reason we need to set the EN bit before the
 204                  * reset done bit gets set. */
 205                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 206                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 207                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 208                          OMAP_I2C_SYSS_RDONE)) {
 209                         if (time_after(jiffies, timeout)) {
 210                                 dev_warn(dev->dev, "timeout waiting"
 211                                                 "for controller reset\n");
 212                                 return -ETIMEDOUT;
 213                         }
 214                         msleep(1);
 215                 }
 216         }
 217         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 218
 219         if (cpu_class_is_omap1()) {
 220                 struct clk *armxor_ck;
 221
 222                 armxor_ck = clk_get(NULL, "armxor_ck");
 223                 if (IS_ERR(armxor_ck))
 224                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 225                 else {
 226                         fclk_rate = clk_get_rate(armxor_ck);
 227                         clk_put(armxor_ck);
 228                 }
 229                 /* TRM for 5912 says the I2C clock must be prescaled to be
 230                  * between 7 - 12 MHz. The XOR input clock is typically
 231                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 232                  *
 233                  * XOR MHz      Divider         Prescaler
 234                  * 12           1               0
 235                  * 13           2               1
 236                  * 19.2         2               1
 237                  */
 238                 if (fclk_rate > 12000000)
 239                         psc = fclk_rate / 12000000;
 240         }
 241
 242         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 243         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 244
 245         /* Program desired operating rate */
 246         fclk_rate /= (psc + 1) * 1000;
 247         if (psc > 2)
 248                 psc = 2;
 249
 250         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
 251                            fclk_rate / (clock * 2) - 7 + psc);
 252         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
 253                            fclk_rate / (clock * 2) - 7 + psc);
 254
 255         /* Take the I2C module out of reset: */
 256         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 257
 258         /* Enable interrupts */
 259         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 260                            (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 261                             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 262                             OMAP_I2C_IE_AL));
 263         return 0;
 264 }
 265
 266 /*
 267  * Waiting on Bus Busy
 268  */
 269 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 270 {
 271         unsigned long timeout;
 272
 273         timeout = jiffies + OMAP_I2C_TIMEOUT;
 274         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 275                 if (time_after(jiffies, timeout)) {
 276                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 277                         return -ETIMEDOUT;
 278                 }
 279                 msleep(1);
 280         }
 281
 282         return 0;
 283 }
 284
 285 /*
 286  * Low level master read/write transaction.
 287  */
 288 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 289                              struct i2c_msg *msg, int stop)
 290 {
 291         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 292 #ifdef OMAP_HACK
 293         u8 zero_byte = 0;
 294 #endif
 295         int r;
 296         u16 w;
 297
 298         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 299                 msg->addr, msg->len, msg->flags, stop);
 300
 301 #ifndef OMAP_HACK
 302         if (msg->len == 0)
 303                 return -EINVAL;
 304
 305         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 306
 307         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 308         dev->buf = msg->buf;
 309         dev->buf_len = msg->len;
 310
 311 #else
 312
 313         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 314         /* REVISIT: Remove this hack when we can get I2C chips from board-*.c
 315          *          files
 316          * Sigh, seems we can't do zero length transactions. Thus, we
 317          * can't probe for devices w/o actually sending/receiving at least
 318          * a single byte. So we'll set count to 1 for the zero length
 319          * transaction case and hope we don't cause grief for some
 320          * arbitrary device due to random byte write/read during
 321          * probes.
 322          */
 323         if (msg->len == 0) {
 324                 dev->buf = &zero_byte;
 325                 dev->buf_len = 1;
 326         } else {
 327                 dev->buf = msg->buf;
 328                 dev->buf_len = msg->len;
 329         }
 330 #endif
 331
 332         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 333
 334         init_completion(&dev->cmd_complete);
 335         dev->cmd_err = 0;
 336
 337         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 338         if (msg->flags & I2C_M_TEN)
 339                 w |= OMAP_I2C_CON_XA;
 340         if (!(msg->flags & I2C_M_RD))
 341                 w |= OMAP_I2C_CON_TRX;
 342         if (stop)
 343                 w |= OMAP_I2C_CON_STP;
 344         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 345
 346         r = wait_for_completion_timeout(&dev->cmd_complete,
 347                                         OMAP_I2C_TIMEOUT);
 348         dev->buf_len = 0;
 349         if (r < 0)
 350                 return r;
 351         if (r == 0) {
 352                 dev_err(dev->dev, "controller timed out\n");
 353                 omap_i2c_init(dev);
 354                 return -ETIMEDOUT;
 355         }
 356
 357         if (likely(!dev->cmd_err))
 358                 return 0;
 359
 360         /* We have an error */
 361         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 362                             OMAP_I2C_STAT_XUDF)) {
 363                 omap_i2c_init(dev);
 364                 return -EIO;
 365         }
 366
 367         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 368                 if (msg->flags & I2C_M_IGNORE_NAK)
 369                         return 0;
 370                 if (stop) {
 371                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 372                         w |= OMAP_I2C_CON_STP;
 373                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 374                 }
 375                 return -EREMOTEIO;
 376         }
 377         return -EIO;
 378 }
 379
 380
 381 /*
 382  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 383  * to do the work during IRQ processing.
 384  */
 385 static int
 386 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 387 {
 388         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 389         int i;
 390         int r;
 391
 392         omap_i2c_enable_clocks(dev);
 393
 394         /* REVISIT: initialize and use adap->retries. This is an optional
 395          * feature */
 396         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 397                 goto out;
 398
 399         for (i = 0; i < num; i++) {
 400                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 401                 if (r != 0)
 402                         break;
 403         }
 404
 405         if (r == 0)
 406                 r = num;
 407 out:
 408         omap_i2c_disable_clocks(dev);
 409         return r;
 410 }
 411
 412 static u32
 413 omap_i2c_func(struct i2c_adapter *adap)
 414 {
 415 #ifndef OMAP_HACK
 416         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 417 #else
 418         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 419 #endif
 420 }
 421
 422 static inline void
 423 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 424 {
 425         dev->cmd_err |= err;
 426         complete(&dev->cmd_complete);
 427 }
 428
 429 static inline void
 430 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 431 {
 432         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 433 }
 434
 435 static irqreturn_t
 436 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 437 {
 438         struct omap_i2c_dev *dev = dev_id;
 439         u16 iv, w;
 440
 441         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 442         switch (iv) {
 443         case 0x00:      /* None */
 444                 break;
 445         case 0x01:      /* Arbitration lost */
 446                 dev_err(dev->dev, "Arbitration lost\n");
 447                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 448                 break;
 449         case 0x02:      /* No acknowledgement */
 450                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 451                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 452                 break;
 453         case 0x03:      /* Register access ready */
 454                 omap_i2c_complete_cmd(dev, 0);
 455                 break;
 456         case 0x04:      /* Receive data ready */
 457                 if (dev->buf_len) {
 458                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 459                         *dev->buf++ = w;
 460                         dev->buf_len--;
 461                         if (dev->buf_len) {
 462                                 *dev->buf++ = w >> 8;
 463                                 dev->buf_len--;
 464                         }
 465                 } else
 466                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 467                 break;
 468         case 0x05:      /* Transmit data ready */
 469                 if (dev->buf_len) {
 470                         w = *dev->buf++;
 471                         dev->buf_len--;
 472                         if (dev->buf_len) {
 473                                 w |= *dev->buf++ << 8;
 474                                 dev->buf_len--;
 475                         }
 476                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 477                 } else
 478                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 479                 break;
 480         default:
 481                 return IRQ_NONE;
 482         }
 483
 484         return IRQ_HANDLED;
 485 }
 486
 487 static irqreturn_t
 488 omap_i2c_isr(int this_irq, void *dev_id)
 489 {
 490         struct omap_i2c_dev *dev = dev_id;
 491         u16 bits;
 492         u16 stat, w;
 493         int count = 0;
 494
 495         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 496         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 497                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 498                 if (count++ == 100) {
 499                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 500                         break;
 501                 }
 502
 503                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 504
 505                 if (stat & OMAP_I2C_STAT_ARDY) {
 506                         omap_i2c_complete_cmd(dev, 0);
 507                         continue;
 508                 }
 509                 if (stat & OMAP_I2C_STAT_RRDY) {
 510                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 511                         if (dev->buf_len) {
 512                                 *dev->buf++ = w;
 513                                 dev->buf_len--;
 514                                 /*
 515                                  * Data reg in 2430 is 8 bit wide,
 516                                  */
 517                                 if (!cpu_is_omap2430()) {
 518                                         if (dev->buf_len) {
 519                                                 *dev->buf++ = w >> 8;
 520                                                 dev->buf_len--;
 521                                         }
 522                                 }
 523                         } else
 524                                 dev_err(dev->dev, "RRDY IRQ while no data"
 525                                                 "requested\n");
 526                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 527                         continue;
 528                 }
 529                 if (stat & OMAP_I2C_STAT_XRDY) {
 530                         w = 0;
 531                         if (dev->buf_len) {
 532                                 w = *dev->buf++;
 533                                 dev->buf_len--;
 534                                 /*
 535                                  * Data reg in 2430 is 8 bit wide,
 536                                  */
 537                                 if (!cpu_is_omap2430()) {
 538                                         if (dev->buf_len) {
 539                                                 w |= *dev->buf++ << 8;
 540                                                 dev->buf_len--;
 541                                         }
 542                                 }
 543                         } else
 544                                 dev_err(dev->dev, "XRDY IRQ while no"
 545                                         "data to send\n");
 546                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 547                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 548                         continue;
 549                 }
 550                 if (stat & OMAP_I2C_STAT_ROVR) {
 551                         dev_err(dev->dev, "Receive overrun\n");
 552                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 553                 }
 554                 if (stat & OMAP_I2C_STAT_XUDF) {
 555                         dev_err(dev->dev, "Transmit overflow\n");
 556                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 557                 }
 558                 if (stat & OMAP_I2C_STAT_NACK) {
 559                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 560                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 561                                            OMAP_I2C_CON_STP);
 562                 }
 563                 if (stat & OMAP_I2C_STAT_AL) {
 564                         dev_err(dev->dev, "Arbitration lost\n");
 565                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 566                 }
 567         }
 568
 569         return count ? IRQ_HANDLED : IRQ_NONE;
 570 }
 571
 572 static const struct i2c_algorithm omap_i2c_algo = {
 573         .master_xfer    = omap_i2c_xfer,
 574         .functionality  = omap_i2c_func,
 575 };
 576
 577 static int
 578 omap_i2c_probe(struct platform_device *pdev)
 579 {
 580         struct omap_i2c_dev     *dev;
 581         struct i2c_adapter      *adap;
 582         struct resource         *mem, *irq, *ioarea;
 583         int r;
 584
 585         /* NOTE: driver uses the static register mapping */
 586         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 587         if (!mem) {
 588                 dev_err(&pdev->dev, "no mem resource?\n");
 589                 return -ENODEV;
 590         }
 591         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 592         if (!irq) {
 593                 dev_err(&pdev->dev, "no irq resource?\n");
 594                 return -ENODEV;
 595         }
 596
 597         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 598                         pdev->name);
 599         if (!ioarea) {
 600                 dev_err(&pdev->dev, "I2C region already claimed\n");
 601                 return -EBUSY;
 602         }
 603
 604         if (clock > 200)
 605                 clock = 400;    /* Fast mode */
 606         else
 607                 clock = 100;    /* Standard mode */
 608
 609         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 610         if (!dev) {
 611                 r = -ENOMEM;
 612                 goto err_release_region;
 613         }
 614
 615         dev->dev = &pdev->dev;
 616         dev->irq = irq->start;
 617         dev->base = (void __iomem *) IO_ADDRESS(mem->start);
 618         platform_set_drvdata(pdev, dev);
 619
 620         if ((r = omap_i2c_get_clocks(dev)) != 0)
 621                 goto err_free_mem;
 622
 623         omap_i2c_enable_clocks(dev);
 624
 625         if (cpu_is_omap15xx())
 626                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 627
 628         /* reset ASAP, clearing any IRQs */
 629         omap_i2c_init(dev);
 630
 631         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 632                         0, pdev->name, dev);
 633
 634         if (r) {
 635                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 636                 goto err_unuse_clocks;
 637         }
 638         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 639         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 640                  pdev->id, r >> 4, r & 0xf, clock);
 641
 642         adap = &dev->adapter;
 643         i2c_set_adapdata(adap, dev);
 644         adap->owner = THIS_MODULE;
 645         adap->class = I2C_CLASS_HWMON;
 646         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 647         adap->algo = &omap_i2c_algo;
 648         adap->dev.parent = &pdev->dev;
 649
 650         /* i2c device drivers may be active on return from add_adapter() */
 651         adap->nr = pdev->id;
 652         r = i2c_add_numbered_adapter(adap);
 653         if (r) {
 654                 dev_err(dev->dev, "failure adding adapter\n");
 655                 goto err_free_irq;
 656         }
 657
 658         omap_i2c_disable_clocks(dev);
 659
 660         return 0;
 661
 662 err_free_irq:
 663         free_irq(dev->irq, dev);
 664 err_unuse_clocks:
 665         omap_i2c_disable_clocks(dev);
 666         omap_i2c_put_clocks(dev);
 667 err_free_mem:
 668         platform_set_drvdata(pdev, NULL);
 669         kfree(dev);
 670 err_release_region:
 671         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 672         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 673
 674         return r;
 675 }
 676
 677 static int
 678 omap_i2c_remove(struct platform_device *pdev)
 679 {
 680         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 681         struct resource         *mem;
 682
 683         platform_set_drvdata(pdev, NULL);
 684
 685         free_irq(dev->irq, dev);
 686         i2c_del_adapter(&dev->adapter);
 687         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 688         omap_i2c_put_clocks(dev);
 689         kfree(dev);
 690         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 691         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 692         return 0;
 693 }
 694
 695 static struct platform_driver omap_i2c_driver = {
 696         .probe          = omap_i2c_probe,
 697         .remove         = omap_i2c_remove,
 698         .driver         = {
 699                 .name   = "i2c_omap",
 700                 .owner  = THIS_MODULE,
 701         },
 702 };
 703
 704 /* I2C may be needed to bring up other drivers */
 705 static int __init
 706 omap_i2c_init_driver(void)
 707 {
 708         return platform_driver_register(&omap_i2c_driver);
 709 }
 710 subsys_initcall(omap_i2c_init_driver);
 711
 712 static void __exit omap_i2c_exit_driver(void)
 713 {
 714         platform_driver_unregister(&omap_i2c_driver);
 715 }
 716 module_exit(omap_i2c_exit_driver);
 717
 718 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 719 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 720 MODULE_LICENSE("GPL");