drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * TI OMAP I2C master mode driver
   3  *
   4  * Copyright (C) 2003 MontaVista Software, Inc.
   5  * Copyright (C) 2005 Nokia Corporation
   6  * Copyright (C) 2004 - 2007 Texas Instruments.
   7  *
   8  * Originally written by MontaVista Software, Inc.
   9  * Additional contributions by:
  10  *      Tony Lindgren <tony@atomide.com>
  11  *      Imre Deak <imre.deak@nokia.com>
  12  *      Juha Yrjölä <juha.yrjola@nokia.com>
  13  *      Syed Khasim <x0khasim@ti.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28  */
  29
  30 #include <linux/module.h>
  31 #include <linux/delay.h>
  32 #include <linux/i2c.h>
  33 #include <linux/err.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/completion.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/clk.h>
  38
  39 #include <asm/io.h>
  40
  41 /* Hack to enable zero length transfers and smbus quick until clean fix
  42    is available */
  43 #define OMAP_HACK
  44
  45 /* timeout waiting for the controller to respond */
  46 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
  47
  48 #define OMAP_I2C_REV_REG                0x00
  49 #define OMAP_I2C_IE_REG                 0x04
  50 #define OMAP_I2C_STAT_REG               0x08
  51 #define OMAP_I2C_IV_REG                 0x0c
  52 #define OMAP_I2C_SYSS_REG               0x10
  53 #define OMAP_I2C_BUF_REG                0x14
  54 #define OMAP_I2C_CNT_REG                0x18
  55 #define OMAP_I2C_DATA_REG               0x1c
  56 #define OMAP_I2C_SYSC_REG               0x20
  57 #define OMAP_I2C_CON_REG                0x24
  58 #define OMAP_I2C_OA_REG                 0x28
  59 #define OMAP_I2C_SA_REG                 0x2c
  60 #define OMAP_I2C_PSC_REG                0x30
  61 #define OMAP_I2C_SCLL_REG               0x34
  62 #define OMAP_I2C_SCLH_REG               0x38
  63 #define OMAP_I2C_SYSTEST_REG            0x3c
  64 #define OMAP_I2C_BUFSTAT_REG            0x40
  65
  66 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  67 #define OMAP_I2C_IE_XDR         (1 << 14)       /* TX Buffer draining int enable */
  68 #define OMAP_I2C_IE_RDR         (1 << 13)       /* RX Buffer draining int enable */
  69 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  70 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  71 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  72 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  73 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  74
  75 /* I2C Status Register (OMAP_I2C_STAT): */
  76 #define OMAP_I2C_STAT_XDR       (1 << 14)       /* TX Buffer draining */
  77 #define OMAP_I2C_STAT_RDR       (1 << 13)       /* RX Buffer draining */
  78 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  79 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  80 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  81 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  82 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  83 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  84 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  85 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  86 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  87 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  88
  89 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  90 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
  91 #define OMAP_I2C_BUF_RXFIF_CLR  (1 << 14)       /* RX FIFO Clear */
  92 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
  93 #define OMAP_I2C_BUF_TXFIF_CLR  (1 << 6)        /* TX FIFO Clear */
  94
  95 /* I2C Configuration Register (OMAP_I2C_CON): */
  96 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
  97 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
  98 #define OMAP_I2C_CON_OPMODE_HS  (1 << 12)       /* High Speed support */
  99 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 100 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 101 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 102 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 103 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 104 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 105 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 106
 107 /* I2C SCL time value when Master */
 108 #define OMAP_I2C_SCLL_HSSCLL    8
 109 #define OMAP_I2C_SCLH_HSSCLH    8
 110
 111 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 112 #ifdef DEBUG
 113 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 114 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 115 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 116 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 117 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 118 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 119 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 120 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 121 #endif
 122
 123 /* I2C System Status register (OMAP_I2C_SYSS): */
 124 #define OMAP_I2C_SYSS_RDONE             (1 << 0)        /* Reset Done */
 125
 126 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 127 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 128
 129 struct omap_i2c_dev {
 130         struct device           *dev;
 131         void __iomem            *base;          /* virtual */
 132         int                     irq;
 133         struct clk              *iclk;          /* Interface clock */
 134         struct clk              *fclk;          /* Functional clock */
 135         struct completion       cmd_complete;
 136         struct resource         *ioarea;
 137         u32                     speed;          /* Speed of bus in Khz */
 138         u16                     cmd_err;
 139         u8                      *buf;
 140         size_t                  buf_len;
 141         struct i2c_adapter      adapter;
 142         u8                      fifo_size;      /* use as flag and value
 143                                                  * fifo_size==0 implies no fifo
 144                                                  * if set, should be trsh+1
 145                                                  */
 146         unsigned                rev1:1;
 147         unsigned                b_hw:1;         /* bad h/w fixes */
 148         unsigned                idle:1;
 149         u16                     iestate;        /* Saved interrupt register */
 150 };
 151
 152 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 153                                       int reg, u16 val)
 154 {
 155         __raw_writew(val, i2c_dev->base + reg);
 156 }
 157
 158 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 159 {
 160         return __raw_readw(i2c_dev->base + reg);
 161 }
 162
 163 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
 164 {
 165         if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
 166                 dev->iclk = clk_get(dev->dev, "i2c_ick");
 167                 if (IS_ERR(dev->iclk)) {
 168                         dev->iclk = NULL;
 169                         return -ENODEV;
 170                 }
 171         }
 172         /* For I2C operations on 2430 we need 96Mhz clock */
 173         if (cpu_is_omap2430()) {
 174                 dev->fclk = clk_get(dev->dev, "i2chs_fck");
 175                 if (IS_ERR(dev->fclk)) {
 176                         if (dev->iclk != NULL) {
 177                                 clk_put(dev->iclk);
 178                                 dev->iclk = NULL;
 179                         }
 180                         dev->fclk = NULL;
 181                         return -ENODEV;
 182                 }
 183         } else {
 184                 dev->fclk = clk_get(dev->dev, "i2c_fck");
 185                 if (IS_ERR(dev->fclk)) {
 186                         if (dev->iclk != NULL) {
 187                                 clk_put(dev->iclk);
 188                                 dev->iclk = NULL;
 189                         }
 190                         dev->fclk = NULL;
 191                         return -ENODEV;
 192                 }
 193         }
 194         return 0;
 195 }
 196
 197 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 198 {
 199         clk_put(dev->fclk);
 200         dev->fclk = NULL;
 201         if (dev->iclk != NULL) {
 202                 clk_put(dev->iclk);
 203                 dev->iclk = NULL;
 204         }
 205 }
 206
 207 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
 208 {
 209         if (dev->iclk != NULL)
 210                 clk_enable(dev->iclk);
 211         clk_enable(dev->fclk);
 212         dev->idle = 0;
 213         if (dev->iestate)
 214                 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
 215 }
 216
 217 static void omap_i2c_idle(struct omap_i2c_dev *dev)
 218 {
 219         u16 iv;
 220
 221         dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 222         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
 223         if (dev->rev1)
 224                 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 225         else
 226                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
 227         /*
 228          * The wmb() is to ensure that the I2C interrupt mask write
 229          * reaches the I2C controller before the dev->idle store
 230          * occurs.
 231          */
 232         wmb();
 233         dev->idle = 1;
 234         clk_disable(dev->fclk);
 235         if (dev->iclk != NULL)
 236                 clk_disable(dev->iclk);
 237 }
 238
 239 static int omap_i2c_init(struct omap_i2c_dev *dev)
 240 {
 241         u16 psc = 0, scll = 0, sclh = 0;
 242         u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
 243         unsigned long fclk_rate = 12000000;
 244         unsigned long timeout;
 245         unsigned long internal_clk = 0;
 246
 247         if (!dev->rev1) {
 248                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 249                 /* For some reason we need to set the EN bit before the
 250                  * reset done bit gets set. */
 251                 timeout = jiffies + OMAP_I2C_TIMEOUT;
 252                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 253                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
 254                          OMAP_I2C_SYSS_RDONE)) {
 255                         if (time_after(jiffies, timeout)) {
 256                                 dev_warn(dev->dev, "timeout waiting "
 257                                                 "for controller reset\n");
 258                                 return -ETIMEDOUT;
 259                         }
 260                         msleep(1);
 261                 }
 262         }
 263         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 264
 265         if (cpu_class_is_omap1()) {
 266                 struct clk *armxor_ck;
 267
 268                 armxor_ck = clk_get(NULL, "armxor_ck");
 269                 if (IS_ERR(armxor_ck))
 270                         dev_warn(dev->dev, "Could not get armxor_ck\n");
 271                 else {
 272                         fclk_rate = clk_get_rate(armxor_ck);
 273                         clk_put(armxor_ck);
 274                 }
 275                 /* TRM for 5912 says the I2C clock must be prescaled to be
 276                  * between 7 - 12 MHz. The XOR input clock is typically
 277                  * 12, 13 or 19.2 MHz. So we should have code that produces:
 278                  *
 279                  * XOR MHz      Divider         Prescaler
 280                  * 12           1               0
 281                  * 13           2               1
 282                  * 19.2         2               1
 283                  */
 284                 if (fclk_rate > 12000000)
 285                         psc = fclk_rate / 12000000;
 286         }
 287
 288         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 289
 290                 /* HSI2C controller internal clk rate should be 19.2 Mhz */
 291                 internal_clk = 19200;
 292                 fclk_rate = clk_get_rate(dev->fclk) / 1000;
 293
 294                 /* Compute prescaler divisor */
 295                 psc = fclk_rate / internal_clk;
 296                 psc = psc - 1;
 297
 298                 /* If configured for High Speed */
 299                 if (dev->speed > 400) {
 300                         /* For first phase of HS mode */
 301                         fsscll = internal_clk / (400 * 2) - 6;
 302                         fssclh = internal_clk / (400 * 2) - 6;
 303
 304                         /* For second phase of HS mode */
 305                         hsscll = fclk_rate / (dev->speed * 2) - 6;
 306                         hssclh = fclk_rate / (dev->speed * 2) - 6;
 307                 } else {
 308                         /* To handle F/S modes */
 309                         fsscll = internal_clk / (dev->speed * 2) - 6;
 310                         fssclh = internal_clk / (dev->speed * 2) - 6;
 311                 }
 312                 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
 313                 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
 314         } else {
 315                 /* Program desired operating rate */
 316                 fclk_rate /= (psc + 1) * 1000;
 317                 if (psc > 2)
 318                         psc = 2;
 319                 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
 320                 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
 321         }
 322
 323         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 324         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 325
 326         /* SCL low and high time values */
 327         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
 328         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
 329
 330         if (dev->fifo_size)
 331                 /* Note: setup required fifo size - 1 */
 332                 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG,
 333                                         (dev->fifo_size - 1) << 8 | /* RTRSH */
 334                                         OMAP_I2C_BUF_RXFIF_CLR |
 335                                         (dev->fifo_size - 1) | /* XTRSH */
 336                                         OMAP_I2C_BUF_TXFIF_CLR);
 337
 338         /* Take the I2C module out of reset: */
 339         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 340
 341         /* Enable interrupts */
 342         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 343                         (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 344                         OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 345                         OMAP_I2C_IE_AL)  | ((dev->fifo_size) ?
 346                                 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0));
 347         return 0;
 348 }
 349
 350 /*
 351  * Waiting on Bus Busy
 352  */
 353 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 354 {
 355         unsigned long timeout;
 356
 357         timeout = jiffies + OMAP_I2C_TIMEOUT;
 358         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 359                 if (time_after(jiffies, timeout)) {
 360                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 361                         return -ETIMEDOUT;
 362                 }
 363                 msleep(1);
 364         }
 365
 366         return 0;
 367 }
 368
 369 /*
 370  * Low level master read/write transaction.
 371  */
 372 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 373                              struct i2c_msg *msg, int stop)
 374 {
 375         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 376 #ifdef OMAP_HACK
 377         u8 zero_byte = 0;
 378 #endif
 379         int r;
 380         u16 w;
 381
 382         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 383                 msg->addr, msg->len, msg->flags, stop);
 384
 385 #ifndef OMAP_HACK
 386         if (msg->len == 0)
 387                 return -EINVAL;
 388
 389         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 390
 391         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 392         dev->buf = msg->buf;
 393         dev->buf_len = msg->len;
 394
 395 #else
 396
 397         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 398         /* REVISIT: Remove this hack when we can get I2C chips from board-*.c
 399          *          files
 400          * Sigh, seems we can't do zero length transactions. Thus, we
 401          * can't probe for devices w/o actually sending/receiving at least
 402          * a single byte. So we'll set count to 1 for the zero length
 403          * transaction case and hope we don't cause grief for some
 404          * arbitrary device due to random byte write/read during
 405          * probes.
 406          */
 407         if (msg->len == 0) {
 408                 dev->buf = &zero_byte;
 409                 dev->buf_len = 1;
 410         } else {
 411                 dev->buf = msg->buf;
 412                 dev->buf_len = msg->len;
 413         }
 414 #endif
 415
 416         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 417
 418         /* Clear the FIFO Buffers */
 419         w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
 420         w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
 421         omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
 422
 423         init_completion(&dev->cmd_complete);
 424         dev->cmd_err = 0;
 425
 426         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 427
 428         /* High speed configuration */
 429         if (dev->speed > 400)
 430                 w |= OMAP_I2C_CON_OPMODE_HS;
 431
 432         if (msg->flags & I2C_M_TEN)
 433                 w |= OMAP_I2C_CON_XA;
 434         if (!(msg->flags & I2C_M_RD))
 435                 w |= OMAP_I2C_CON_TRX;
 436
 437         if (!dev->b_hw && stop)
 438                 w |= OMAP_I2C_CON_STP;
 439
 440         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 441
 442         if (dev->b_hw && stop) {
 443                 /* H/w behavior: dont write stt and stp together.. */
 444                 while (omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) & OMAP_I2C_CON_STT) {
 445                         /* Dont do anything - this will come in a couple of loops at max*/
 446                 }
 447                 w |= OMAP_I2C_CON_STP;
 448                 w &= ~OMAP_I2C_CON_STT;
 449                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 450         }
 451         r = wait_for_completion_timeout(&dev->cmd_complete,
 452                                         OMAP_I2C_TIMEOUT);
 453         dev->buf_len = 0;
 454         if (r < 0)
 455                 return r;
 456         if (r == 0) {
 457                 dev_err(dev->dev, "controller timed out\n");
 458                 omap_i2c_init(dev);
 459                 return -ETIMEDOUT;
 460         }
 461
 462         if (likely(!dev->cmd_err))
 463                 return 0;
 464
 465         /* We have an error */
 466         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 467                             OMAP_I2C_STAT_XUDF)) {
 468                 omap_i2c_init(dev);
 469                 return -EIO;
 470         }
 471
 472         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 473                 if (msg->flags & I2C_M_IGNORE_NAK)
 474                         return 0;
 475                 if (stop) {
 476                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 477                         w |= OMAP_I2C_CON_STP;
 478                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 479                 }
 480                 return -EREMOTEIO;
 481         }
 482         return -EIO;
 483 }
 484
 485
 486 /*
 487  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 488  * to do the work during IRQ processing.
 489  */
 490 static int
 491 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 492 {
 493         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 494         int i;
 495         int r;
 496
 497         omap_i2c_unidle(dev);
 498
 499         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 500                 goto out;
 501
 502         for (i = 0; i < num; i++) {
 503                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 504                 if (r != 0)
 505                         break;
 506         }
 507
 508         if (r == 0)
 509                 r = num;
 510 out:
 511         omap_i2c_idle(dev);
 512         return r;
 513 }
 514
 515 static u32
 516 omap_i2c_func(struct i2c_adapter *adap)
 517 {
 518 #ifndef OMAP_HACK
 519         return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
 520 #else
 521         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 522 #endif
 523 }
 524
 525 static inline void
 526 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 527 {
 528         dev->cmd_err |= err;
 529         complete(&dev->cmd_complete);
 530 }
 531
 532 static inline void
 533 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 534 {
 535         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 536 }
 537
 538 /* rev1 devices are apparently only on some 15xx */
 539 #ifdef CONFIG_ARCH_OMAP15XX
 540
 541 static irqreturn_t
 542 omap_i2c_rev1_isr(int this_irq, void *dev_id)
 543 {
 544         struct omap_i2c_dev *dev = dev_id;
 545         u16 iv, w;
 546
 547         if (dev->idle)
 548                 return IRQ_NONE;
 549
 550         iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 551         switch (iv) {
 552         case 0x00:      /* None */
 553                 break;
 554         case 0x01:      /* Arbitration lost */
 555                 dev_err(dev->dev, "Arbitration lost\n");
 556                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 557                 break;
 558         case 0x02:      /* No acknowledgement */
 559                 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 560                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 561                 break;
 562         case 0x03:      /* Register access ready */
 563                 omap_i2c_complete_cmd(dev, 0);
 564                 break;
 565         case 0x04:      /* Receive data ready */
 566                 if (dev->buf_len) {
 567                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 568                         *dev->buf++ = w;
 569                         dev->buf_len--;
 570                         if (dev->buf_len) {
 571                                 *dev->buf++ = w >> 8;
 572                                 dev->buf_len--;
 573                         }
 574                 } else
 575                         dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 576                 break;
 577         case 0x05:      /* Transmit data ready */
 578                 if (dev->buf_len) {
 579                         w = *dev->buf++;
 580                         dev->buf_len--;
 581                         if (dev->buf_len) {
 582                                 w |= *dev->buf++ << 8;
 583                                 dev->buf_len--;
 584                         }
 585                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 586                 } else
 587                         dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 588                 break;
 589         default:
 590                 return IRQ_NONE;
 591         }
 592
 593         return IRQ_HANDLED;
 594 }
 595 #else
 596 #define omap_i2c_rev1_isr               0
 597 #endif
 598
 599 static irqreturn_t
 600 omap_i2c_isr(int this_irq, void *dev_id)
 601 {
 602         struct omap_i2c_dev *dev = dev_id;
 603         u16 bits;
 604         u16 stat, w;
 605         int err, count = 0;
 606
 607         if (dev->idle)
 608                 return IRQ_NONE;
 609
 610         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 611         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 612                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 613                 if (count++ == 100) {
 614                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 615                         break;
 616                 }
 617
 618                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 619
 620                 err = 0;
 621                 if (stat & OMAP_I2C_STAT_NACK) {
 622                         err |= OMAP_I2C_STAT_NACK;
 623                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
 624                                            OMAP_I2C_CON_STP);
 625                 }
 626                 if (stat & OMAP_I2C_STAT_AL) {
 627                         dev_err(dev->dev, "Arbitration lost\n");
 628                         err |= OMAP_I2C_STAT_AL;
 629                 }
 630                 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
 631                                         OMAP_I2C_STAT_AL))
 632                         omap_i2c_complete_cmd(dev, err);
 633                 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
 634                         u8 num_bytes = 1;
 635                         if (dev->fifo_size) {
 636                                 num_bytes = (stat & OMAP_I2C_STAT_RRDY) ? dev->fifo_size :
 637                                                 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
 638                         }
 639                         while (num_bytes) {
 640                                 num_bytes--;
 641                                 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 642                                 if (dev->buf_len) {
 643                                         *dev->buf++ = w;
 644                                         dev->buf_len--;
 645                                         /* Data reg from 2430 is 8 bit wide */
 646                                         if (!cpu_is_omap2430() &&
 647                                                         !cpu_is_omap34xx()) {
 648                                                 if (dev->buf_len) {
 649                                                         *dev->buf++ = w >> 8;
 650                                                         dev->buf_len--;
 651                                                 }
 652                                         }
 653                                 } else {
 654                                         if (stat & OMAP_I2C_STAT_RRDY)
 655                                                 dev_err(dev->dev, "RRDY IRQ while no data "
 656                                                                 "requested\n");
 657                                         if (stat & OMAP_I2C_STAT_RDR)
 658                                                 dev_err(dev->dev, "RDR IRQ while no data "
 659                                                                 "requested\n");
 660                                         break;
 661                                 }
 662                         }
 663                         omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
 664                 }
 665                 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
 666                         u8 num_bytes = 1;
 667                         if (dev->fifo_size) {
 668                                 num_bytes = (stat & OMAP_I2C_STAT_XRDY) ? dev->fifo_size :
 669                                                 omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG);
 670                         }
 671                         while (num_bytes) {
 672                                 num_bytes--;
 673                                 w = 0;
 674                                 if (dev->buf_len) {
 675                                         w = *dev->buf++;
 676                                         dev->buf_len--;
 677                                         /* Data reg from  2430 is 8 bit wide */
 678                                         if (!cpu_is_omap2430() &&
 679                                                         !cpu_is_omap34xx()) {
 680                                                 if (dev->buf_len) {
 681                                                         w |= *dev->buf++ << 8;
 682                                                         dev->buf_len--;
 683                                                 }
 684                                         }
 685                                 } else {
 686                                         if (stat & OMAP_I2C_STAT_XRDY)
 687                                                 dev_err(dev->dev, "XRDY IRQ while no "
 688                                                                 "data to send\n");
 689                                         if (stat & OMAP_I2C_STAT_XDR)
 690                                                 dev_err(dev->dev, "XDR IRQ while no "
 691                                                                 "data to send\n");
 692                                         break;
 693                                 }
 694                                 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 695                         }
 696                         omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
 697                 }
 698                 if (stat & OMAP_I2C_STAT_ROVR) {
 699                         dev_err(dev->dev, "Receive overrun\n");
 700                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 701                 }
 702                 if (stat & OMAP_I2C_STAT_XUDF) {
 703                         dev_err(dev->dev, "Transmit overflow\n");
 704                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 705                 }
 706         }
 707
 708         return count ? IRQ_HANDLED : IRQ_NONE;
 709 }
 710
 711 static const struct i2c_algorithm omap_i2c_algo = {
 712         .master_xfer    = omap_i2c_xfer,
 713         .functionality  = omap_i2c_func,
 714 };
 715
 716 static int __init
 717 omap_i2c_probe(struct platform_device *pdev)
 718 {
 719         struct omap_i2c_dev     *dev;
 720         struct i2c_adapter      *adap;
 721         struct resource         *mem, *irq, *ioarea;
 722         int r;
 723         u32 *speed = NULL;
 724
 725         /* NOTE: driver uses the static register mapping */
 726         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 727         if (!mem) {
 728                 dev_err(&pdev->dev, "no mem resource?\n");
 729                 return -ENODEV;
 730         }
 731         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 732         if (!irq) {
 733                 dev_err(&pdev->dev, "no irq resource?\n");
 734                 return -ENODEV;
 735         }
 736
 737         ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1,
 738                         pdev->name);
 739         if (!ioarea) {
 740                 dev_err(&pdev->dev, "I2C region already claimed\n");
 741                 return -EBUSY;
 742         }
 743
 744         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 745         if (!dev) {
 746                 r = -ENOMEM;
 747                 goto err_release_region;
 748         }
 749
 750         if (pdev->dev.platform_data != NULL)
 751                 speed = (u32 *) pdev->dev.platform_data;
 752         else
 753                 *speed = 100; /* Defualt speed */
 754
 755         dev->speed = *speed;
 756         dev->dev = &pdev->dev;
 757         dev->irq = irq->start;
 758         dev->base = (void __iomem *) IO_ADDRESS(mem->start);
 759         platform_set_drvdata(pdev, dev);
 760
 761         if ((r = omap_i2c_get_clocks(dev)) != 0)
 762                 goto err_free_mem;
 763
 764         omap_i2c_unidle(dev);
 765
 766         if (cpu_is_omap15xx())
 767                 dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 768
 769         if (cpu_is_omap2430() || cpu_is_omap34xx()) {
 770                 /* Set up the fifo size - Get total size */
 771                 dev->fifo_size = 0x8 <<
 772                         ((omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3);
 773                 /*
 774                  * Set up notification threshold as half the total available size
 775                  * This is to ensure that we can handle the status on int call back
 776                  * latencies
 777                  */
 778                 dev->fifo_size = (dev->fifo_size / 2);
 779                 dev->b_hw = 1; /* Enable hardware fixes */
 780         }
 781
 782         /* reset ASAP, clearing any IRQs */
 783         omap_i2c_init(dev);
 784
 785         r = request_irq(dev->irq, dev->rev1 ? omap_i2c_rev1_isr : omap_i2c_isr,
 786                         0, pdev->name, dev);
 787
 788         if (r) {
 789                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 790                 goto err_unuse_clocks;
 791         }
 792         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 793         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 794                  pdev->id, r >> 4, r & 0xf, dev->speed);
 795
 796         adap = &dev->adapter;
 797         i2c_set_adapdata(adap, dev);
 798         adap->owner = THIS_MODULE;
 799         adap->class = I2C_CLASS_HWMON;
 800         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 801         adap->algo = &omap_i2c_algo;
 802         adap->dev.parent = &pdev->dev;
 803
 804         /* i2c device drivers may be active on return from add_adapter() */
 805         adap->nr = pdev->id;
 806         r = i2c_add_numbered_adapter(adap);
 807         if (r) {
 808                 dev_err(dev->dev, "failure adding adapter\n");
 809                 goto err_free_irq;
 810         }
 811
 812         omap_i2c_idle(dev);
 813
 814         return 0;
 815
 816 err_free_irq:
 817         free_irq(dev->irq, dev);
 818 err_unuse_clocks:
 819         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 820         omap_i2c_idle(dev);
 821         omap_i2c_put_clocks(dev);
 822 err_free_mem:
 823         platform_set_drvdata(pdev, NULL);
 824         kfree(dev);
 825 err_release_region:
 826         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 827
 828         return r;
 829 }
 830
 831 static int
 832 omap_i2c_remove(struct platform_device *pdev)
 833 {
 834         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 835         struct resource         *mem;
 836
 837         platform_set_drvdata(pdev, NULL);
 838
 839         free_irq(dev->irq, dev);
 840         i2c_del_adapter(&dev->adapter);
 841         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 842         omap_i2c_put_clocks(dev);
 843         kfree(dev);
 844         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 845         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 846         return 0;
 847 }
 848
 849 static struct platform_driver omap_i2c_driver = {
 850         .probe          = omap_i2c_probe,
 851         .remove         = omap_i2c_remove,
 852         .driver         = {
 853                 .name   = "i2c_omap",
 854                 .owner  = THIS_MODULE,
 855         },
 856 };
 857
 858 /* I2C may be needed to bring up other drivers */
 859 static int __devinit
 860 omap_i2c_init_driver(void)
 861 {
 862         return platform_driver_register(&omap_i2c_driver);
 863 }
 864 subsys_initcall(omap_i2c_init_driver);
 865
 866 static void __devexit omap_i2c_exit_driver(void)
 867 {
 868         platform_driver_unregister(&omap_i2c_driver);
 869 }
 870 module_exit(omap_i2c_exit_driver);
 871
 872 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 873 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 874 MODULE_LICENSE("GPL");
 875 MODULE_ALIAS("platform:i2c_omap");