2 * linux/drivers/i2c/i2c-omap.c
4 * TI OMAP I2C master mode driver
6 * Copyright (C) 2003 MontaVista Software, Inc.
7 * Copyright (C) 2004 Texas Instruments.
9 * ----------------------------------------------------------------------------
10 * This file was highly leveraged from i2c-elektor.c:
12 * Copyright 1995-97 Simon G. Vogl
13 * 1998-99 Hans Berglund
15 * With some changes from Kysti M�kki <kmalkki@cc.hut.fi> and even
16 * Frodo Looijaard <frodol@dds.nl>
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <linux/ioport.h>
39 #include <linux/version.h>
40 #include <linux/i2c.h>
43 #include <asm/hardware/clock.h>
45 #include <asm/uaccess.h>
46 #include <asm/hardware/clock.h>
47 #include <linux/errno.h>
48 #include <linux/sched.h>
49 #include <asm/arch/hardware.h>
50 #include <linux/interrupt.h>
51 #include <linux/moduleparam.h>
52 #include <asm/arch/mux.h>
53 #include <linux/err.h>
59 /* ----- debug defines ----------------------------------------------- */
62 static int i2c_debug = 0;
64 module_param(i2c_debug, int, 0);
65 MODULE_PARM_DESC(i2c_debug,
66 "debug level - 0 off; 1 normal; 2,3 more verbose; "
69 #define DEB0(format, arg...) printk(KERN_DEBUG MODULE_NAME " DEBUG: " format "\n", ## arg )
70 #define DEB1(format, arg...) \
72 printk(KERN_DEBUG MODULE_NAME " DEBUG: " format "\n", ## arg ); \
74 #define DEB2(format, arg...) \
76 printk(KERN_DEBUG MODULE_NAME " DEBUG: " format "\n", ## arg ); \
78 #define DEB3(format, arg...) \
80 printk(KERN_DEBUG MODULE_NAME " DEBUG: " format "\n", ## arg ); \
82 #define DEB9(format, arg...) \
83 /* debug the protocol by showing transferred bits */ \
85 printk(KERN_DEBUG MODULE_NAME " DEBUG: " format "\n", ## arg ); \
88 #define DEB0(fmt, args...)
89 #define DEB1(fmt, args...)
90 #define DEB2(fmt, args...)
91 #define DEB3(fmt, args...)
92 #define DEB9(fmt, args...)
95 /* ----- global defines ----------------------------------------------- */
96 static const char driver_name[] = "i2c_omap";
98 #define MODULE_NAME "OMAP I2C"
99 #define OMAP_I2C_TIMEOUT (1*HZ) /* timeout waiting for an I2C transaction */
101 #define err(format, arg...) printk(KERN_ERR MODULE_NAME " ERROR: " format "\n", ## arg )
103 #ifdef CONFIG_ARCH_OMAP1510
104 #define omap_i2c_rev1() (readw(OMAP_I2C_REV) < 0x20)
106 #define omap_i2c_rev1() 0
109 #define DEFAULT_OWN 1 /* default own I2C address */
110 #define MAX_MESSAGES 65536 /* max number of messages */
112 static int clock = 100; /* Default: Fast Mode = 400 KHz, Standard Mode = 100 KHz */
113 module_param(clock, int, 0);
114 MODULE_PARM_DESC(clock,
115 "Set I2C clock in KHz: 100 (Standard Mode) or 400 (Fast Mode)");
118 module_param(own, int, 0);
119 MODULE_PARM_DESC(own, "Address of OMAP i2c master (0 for default == 1)");
122 static struct omap_i2c_dev {
123 int cmd_complete, cmd_err;
124 wait_queue_head_t cmd_wait;
129 /* FIXME pass "sparse": convert {read,write}w() with iomapped addresses
130 * to omap_{read,write}w() with physical addresses.
133 static void omap_i2c_reset(void)
135 unsigned long timeout;
137 struct clk *armxor_ck;
138 unsigned long armxor_rate;
140 if (!omap_i2c_rev1())
141 writew(OMAP_I2C_SYSC_SRST, OMAP_I2C_SYSC); /*soft reset */
143 writew(OMAP_I2C_CON_RST, OMAP_I2C_CON); /* reset */
145 armxor_ck = clk_get(NULL, "armxor_ck");
146 if (IS_ERR(armxor_ck)) {
147 printk(KERN_WARNING "i2c: Could not obtain armxor_ck rate.\n");
148 armxor_rate = 12000000;
150 armxor_rate = clk_get_rate(armxor_ck);
154 if (armxor_rate <= 16000000)
157 psc = (armxor_rate + 8000000) / 12000000;
159 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
160 writew(psc, OMAP_I2C_PSC);
162 /* Program desired operating rate */
163 armxor_rate /= (psc + 1) * 1000;
166 writew(armxor_rate / (clock * 2) - 7 + psc, OMAP_I2C_SCLL);
167 writew(armxor_rate / (clock * 2) - 7 + psc, OMAP_I2C_SCLH);
170 /* Set Own Address: */
171 writew(own, OMAP_I2C_OA);
173 /* Enable interrupts */
174 writew((OMAP_I2C_IE_XRDY_IE | OMAP_I2C_IE_RRDY_IE | OMAP_I2C_IE_ARDY_IE |
175 OMAP_I2C_IE_NACK_IE | OMAP_I2C_IE_AL_IE), OMAP_I2C_IE);
177 /* Take the I2C module out of reset: */
178 writew(OMAP_I2C_CON_EN, OMAP_I2C_CON);
180 if (!omap_i2c_rev1()){
181 timeout = jiffies + OMAP_I2C_TIMEOUT;
182 while (!(readw(OMAP_I2C_SYSS) & OMAP_I2C_SYSS_RDONE)) {
183 if (time_after(jiffies, timeout)) {
184 err("timeout waiting for I2C reset complete");
193 * Waiting on Bus Busy
196 omap_i2c_wait_for_bb(char allow_sleep)
198 unsigned long timeout;
200 timeout = jiffies + OMAP_I2C_TIMEOUT;
201 while (readw(OMAP_I2C_STAT) & OMAP_I2C_STAT_BB) {
202 if (time_after(jiffies, timeout)) {
203 printk(KERN_WARNING "timeout waiting for bus ready\n");
214 * Low level master read/write transaction.
217 omap_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg, int stop)
219 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
224 DEB2("addr: 0x%04x, len: %d, flags: 0x%x, stop: %d",
225 msg->addr, msg->len, msg->flags, stop);
227 writew(msg->addr, OMAP_I2C_SA);
229 /* Sigh, seems we can't do zero length transactions. Thus, we
230 * can't probe for devices w/o actually sending/receiving at least
231 * a single byte. So we'll set count to 1 for the zero length
232 * transaction case and hope we don't cause grief for some
233 * arbitrary device due to random byte write/read during
237 dev->buf = &zero_byte;
241 dev->buf_len = msg->len;
243 writew(dev->buf_len, OMAP_I2C_CNT);
244 dev->cmd_complete = 0;
246 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
247 if (msg->flags & I2C_M_TEN)
248 w |= OMAP_I2C_CON_XA;
249 if (!(msg->flags & I2C_M_RD))
250 w |= OMAP_I2C_CON_TRX;
252 w |= OMAP_I2C_CON_STP;
253 writew(w, OMAP_I2C_CON);
255 r = wait_event_interruptible_timeout(dev->cmd_wait,
261 if (!dev->cmd_complete) {
268 /* We have an error */
269 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
270 if (msg->flags & I2C_M_IGNORE_NAK)
273 writew(readw(OMAP_I2C_CON) | OMAP_I2C_CON_STP,
277 if ((OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR | OMAP_I2C_STAT_XUDF)
286 * Prepare controller for a transaction and call omap_i2c_xfer_msg
287 * to do the work during IRQ processing.
290 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
295 DEB1("msgs: %d", num);
297 if (num < 1 || num > MAX_MESSAGES)
300 /* Check for valid parameters in messages */
301 for (i = 0; i < num; i++)
302 if (msgs[i].buf == NULL)
305 // REVISIT: initialize and use adap->retries
307 if ((r = omap_i2c_wait_for_bb(1)) < 0)
310 for (i = 0; i < num; i++) {
311 DEB2("msg: %d, addr: 0x%04x, len: %d, flags: 0x%x",
312 i, msgs[i].addr, msgs[i].len, msgs[i].flags);
314 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
318 if (r != msgs[i].len)
322 if (r >= 0 && num > 1)
331 omap_i2c_func(struct i2c_adapter *adap)
333 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
337 omap_i2c_complete_cmd(struct omap_i2c_dev *dev)
339 dev->cmd_complete = 1;
340 wake_up(&dev->cmd_wait);
344 omap_i2c_isr(int this_irq, void *dev_id, struct pt_regs *regs)
346 struct omap_i2c_dev *dev = dev_id;
352 bits = readw(OMAP_I2C_IE);
353 while ((stat = readw(OMAP_I2C_STAT)) & bits) {
355 if (count++ == 100) {
356 printk(KERN_WARNING "Too much work in one IRQ\n");
360 writew(stat, OMAP_I2C_STAT);
361 if (stat & OMAP_I2C_STAT_ARDY) {
362 omap_i2c_complete_cmd(dev);
363 writew(OMAP_I2C_STAT_ARDY, OMAP_I2C_STAT);
365 iv_read = readw(OMAP_I2C_IV);
368 if (stat & OMAP_I2C_STAT_RRDY) {
369 w = readw(OMAP_I2C_DATA);
374 *dev->buf++ = w >> 8;
377 if (omap_i2c_rev1() && !dev->buf_len)
378 omap_i2c_complete_cmd(dev);
380 err("RRDY IRQ while no data requested");
381 writew(OMAP_I2C_STAT_RRDY, OMAP_I2C_STAT);
383 iv_read = readw(OMAP_I2C_IV);
386 if (stat & OMAP_I2C_STAT_XRDY) {
392 w |= *dev->buf++ << 8;
396 err("XRDY IRQ while no data to send");
398 writew(w, OMAP_I2C_DATA);
399 /* We have to make sure the XRDY bit is reset */
400 writew(OMAP_I2C_STAT_XRDY, OMAP_I2C_STAT);
401 if (omap_i2c_rev1()) {
402 iv_read = readw(OMAP_I2C_IV);
404 omap_i2c_complete_cmd(dev);
408 if (stat & OMAP_I2C_STAT_ROVR) {
409 pr_debug("Receive overrun\n");
410 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
412 if (stat & OMAP_I2C_STAT_XUDF) {
413 pr_debug("Transmit overflow\n");
414 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
416 if (stat & OMAP_I2C_STAT_NACK) {
417 dev->cmd_err |= OMAP_I2C_STAT_NACK;
418 omap_i2c_complete_cmd(dev);
419 writew(OMAP_I2C_CON_STP, OMAP_I2C_CON);
421 if (stat & OMAP_I2C_STAT_AL) {
422 pr_debug("Arbitration lost\n");
423 dev->cmd_err |= OMAP_I2C_STAT_AL;
424 omap_i2c_complete_cmd(dev);
427 iv_read = readw(OMAP_I2C_IV);
433 static struct i2c_algorithm omap_i2c_algo = {
434 .name = "OMAP I2C algorithm",
436 .master_xfer = omap_i2c_xfer,
437 .functionality = omap_i2c_func,
440 static struct i2c_adapter omap_i2c_adap = {
441 .owner = THIS_MODULE,
442 .class = I2C_CLASS_HWMON,
443 .name = "OMAP I2C adapter",
444 .algo = &omap_i2c_algo,
448 omap_i2c_probe(struct device *dev)
450 struct platform_device *pdev = to_platform_device(dev);
451 struct resource *mem;
454 /* NOTE: driver uses the static register mapping */
455 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 pr_debug("%s: no mem resource?\n", driver_name);
460 r = (int) request_mem_region(mem->start, (mem->end - mem->start) + 1,
463 pr_debug("%s: I2C region already claimed\n", driver_name);
468 clock = 400; /*Fast mode */
470 clock = 100; /*Standard mode */
472 if (own < 1 || own > 0x7f)
475 memset(&omap_i2c_dev, 0, sizeof(omap_i2c_dev));
476 init_waitqueue_head(&omap_i2c_dev.cmd_wait);
478 /* reset ASAP, clearing any IRQs */
481 r = request_irq(INT_I2C, omap_i2c_isr, 0, driver_name, &omap_i2c_dev);
483 pr_debug("%s: failure requesting irq\n", driver_name);
484 goto do_release_region;
487 r = readw(OMAP_I2C_REV) & 0xff;
488 pr_info("%s: rev%d.%d at %d KHz\n", driver_name,
489 r >> 4, r & 0xf, clock);
491 /* i2c device drivers may be active on return from add_adapter() */
492 i2c_set_adapdata(&omap_i2c_adap, &omap_i2c_dev);
493 omap_i2c_adap.dev.parent = dev;
494 r = i2c_add_adapter(&omap_i2c_adap);
496 pr_debug("%s: failure adding adapter\n", driver_name);
503 free_irq(INT_I2C, &omap_i2c_dev);
505 writew(0, OMAP_I2C_CON);
506 release_mem_region(mem->start, (mem->end - mem->start) + 1);
512 omap_i2c_remove(struct device *dev)
514 struct platform_device *pdev = to_platform_device(dev);
515 struct resource *mem;
517 writew(0, OMAP_I2C_CON);
518 i2c_del_adapter(&omap_i2c_adap);
519 free_irq(INT_I2C, &omap_i2c_dev);
520 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
521 release_mem_region(mem->start, (mem->end - mem->start) + 1);
525 static struct device_driver omap_i2c_driver = {
526 .name = (char *)driver_name,
527 .bus = &platform_bus_type,
528 .probe = omap_i2c_probe,
529 .remove = __exit_p(omap_i2c_remove),
532 /* i2c may be needed to bring up other drivers */
534 omap_i2c_init_driver(void)
536 return driver_register(&omap_i2c_driver);
538 subsys_initcall(omap_i2c_init_driver);
540 static void __exit omap_i2c_exit_driver(void)
542 driver_unregister(&omap_i2c_driver);
544 module_exit(omap_i2c_exit_driver);
546 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
547 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
548 MODULE_LICENSE("GPL");