drivers/i2c/busses/i2c-omap.c

   1 /*
   2  * linux/drivers/i2c/i2c-omap.c
   3  *
   4  * TI OMAP I2C master mode driver
   5  *
   6  * Copyright (C) 2003 MontaVista Software, Inc.
   7  * Copyright (C) 2004 Texas Instruments.
   8  *
   9  * Updated to work with multiple I2C interfaces on 24xx by
  10  * Tony Lindgren <tony@atomide.com> and Imre Deak <imre.deak@nokia.com>
  11  * Copyright (C) 2005 Nokia Corporation
  12  *
  13  * Cleaned up by Juha Yrjölä <juha.yrjola@nokia.com>
  14  *
  15  * ----------------------------------------------------------------------------
  16  * This file was highly leveraged from i2c-elektor.c:
  17  *
  18  * Copyright 1995-97 Simon G. Vogl
  19  *           1998-99 Hans Berglund
  20  *
  21  * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi> and even
  22  * Frodo Looijaard <frodol@dds.nl>
  23  *
  24  * This program is free software; you can redistribute it and/or modify
  25  * it under the terms of the GNU General Public License as published by
  26  * the Free Software Foundation; either version 2 of the License, or
  27  * (at your option) any later version.
  28  *
  29  * This program is distributed in the hope that it will be useful,
  30  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  31  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  32  * GNU General Public License for more details.
  33  *
  34  * You should have received a copy of the GNU General Public License
  35  * along with this program; if not, write to the Free Software
  36  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  37  */
  38
  39 // #define DEBUG
  40
  41 #include <linux/module.h>
  42 #include <linux/delay.h>
  43 #include <linux/i2c.h>
  44 #include <linux/err.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/completion.h>
  47 #include <linux/platform_device.h>
  48
  49 #include <asm/io.h>
  50 #include <asm/hardware/clock.h>
  51
  52 /* ----- global defines ----------------------------------------------- */
  53 static const char driver_name[] = "i2c_omap";
  54
  55 #define MODULE_NAME "OMAP I2C"
  56 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(500)) /* timeout waiting for the controller to respond */
  57
  58 #define DEFAULT_OWN             1       /* default own I2C address */
  59 #define MAX_MESSAGES            65536   /* max number of messages */
  60
  61 #define OMAP_I2C_REV_REG                0x00
  62 #define OMAP_I2C_IE_REG                 0x04
  63 #define OMAP_I2C_STAT_REG               0x08
  64 #define OMAP_I2C_IV_REG                 0x0c
  65 #define OMAP_I2C_SYSS_REG               0x10
  66 #define OMAP_I2C_BUF_REG                0x14
  67 #define OMAP_I2C_CNT_REG                0x18
  68 #define OMAP_I2C_DATA_REG               0x1c
  69 #define OMAP_I2C_SYSC_REG               0x20
  70 #define OMAP_I2C_CON_REG                0x24
  71 #define OMAP_I2C_OA_REG                 0x28
  72 #define OMAP_I2C_SA_REG                 0x2c
  73 #define OMAP_I2C_PSC_REG                0x30
  74 #define OMAP_I2C_SCLL_REG               0x34
  75 #define OMAP_I2C_SCLH_REG               0x38
  76 #define OMAP_I2C_SYSTEST_REG            0x3c
  77
  78 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
  79 #define OMAP_I2C_IE_XRDY        (1 << 4)        /* TX data ready int enable */
  80 #define OMAP_I2C_IE_RRDY        (1 << 3)        /* RX data ready int enable */
  81 #define OMAP_I2C_IE_ARDY        (1 << 2)        /* Access ready int enable */
  82 #define OMAP_I2C_IE_NACK        (1 << 1)        /* No ack interrupt enable */
  83 #define OMAP_I2C_IE_AL          (1 << 0)        /* Arbitration lost int ena */
  84
  85 /* I2C Status Register (OMAP_I2C_STAT): */
  86 #define OMAP_I2C_STAT_SBD       (1 << 15)       /* Single byte data */
  87 #define OMAP_I2C_STAT_BB        (1 << 12)       /* Bus busy */
  88 #define OMAP_I2C_STAT_ROVR      (1 << 11)       /* Receive overrun */
  89 #define OMAP_I2C_STAT_XUDF      (1 << 10)       /* Transmit underflow */
  90 #define OMAP_I2C_STAT_AAS       (1 << 9)        /* Address as slave */
  91 #define OMAP_I2C_STAT_AD0       (1 << 8)        /* Address zero */
  92 #define OMAP_I2C_STAT_XRDY      (1 << 4)        /* Transmit data ready */
  93 #define OMAP_I2C_STAT_RRDY      (1 << 3)        /* Receive data ready */
  94 #define OMAP_I2C_STAT_ARDY      (1 << 2)        /* Register access ready */
  95 #define OMAP_I2C_STAT_NACK      (1 << 1)        /* No ack interrupt enable */
  96 #define OMAP_I2C_STAT_AL        (1 << 0)        /* Arbitration lost int ena */
  97
  98 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
  99 #define OMAP_I2C_BUF_RDMA_EN    (1 << 15)       /* RX DMA channel enable */
 100 #define OMAP_I2C_BUF_XDMA_EN    (1 << 7)        /* TX DMA channel enable */
 101
 102 /* I2C Configuration Register (OMAP_I2C_CON): */
 103 #define OMAP_I2C_CON_EN         (1 << 15)       /* I2C module enable */
 104 #define OMAP_I2C_CON_BE         (1 << 14)       /* Big endian mode */
 105 #define OMAP_I2C_CON_STB        (1 << 11)       /* Start byte mode (master) */
 106 #define OMAP_I2C_CON_MST        (1 << 10)       /* Master/slave mode */
 107 #define OMAP_I2C_CON_TRX        (1 << 9)        /* TX/RX mode (master only) */
 108 #define OMAP_I2C_CON_XA         (1 << 8)        /* Expand address */
 109 #define OMAP_I2C_CON_RM         (1 << 2)        /* Repeat mode (master only) */
 110 #define OMAP_I2C_CON_STP        (1 << 1)        /* Stop cond (master only) */
 111 #define OMAP_I2C_CON_STT        (1 << 0)        /* Start condition (master) */
 112
 113 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
 114 #define OMAP_I2C_SYSTEST_ST_EN          (1 << 15)       /* System test enable */
 115 #define OMAP_I2C_SYSTEST_FREE           (1 << 14)       /* Free running mode */
 116 #define OMAP_I2C_SYSTEST_TMODE_MASK     (3 << 12)       /* Test mode select */
 117 #define OMAP_I2C_SYSTEST_TMODE_SHIFT    (12)            /* Test mode select */
 118 #define OMAP_I2C_SYSTEST_SCL_I          (1 << 3)        /* SCL line sense in */
 119 #define OMAP_I2C_SYSTEST_SCL_O          (1 << 2)        /* SCL line drive out */
 120 #define OMAP_I2C_SYSTEST_SDA_I          (1 << 1)        /* SDA line sense in */
 121 #define OMAP_I2C_SYSTEST_SDA_O          (1 << 0)        /* SDA line drive out */
 122
 123 /* I2C System Status register (OMAP_I2C_SYSS): */
 124 #define OMAP_I2C_SYSS_RDONE             1               /* Reset Done */
 125
 126 /* I2C System Configuration Register (OMAP_I2C_SYSC): */
 127 #define OMAP_I2C_SYSC_SRST              (1 << 1)        /* Soft Reset */
 128
 129 /* REVISIT: Use platform_data instead of module parameters */
 130 static int clock = 100; /* Default: Fast Mode = 400 KHz, Standard = 100 KHz */
 131 module_param(clock, int, 0);
 132 MODULE_PARM_DESC(clock, "Set I2C clock in kHz: 100 or 400 (Fast Mode)");
 133
 134 static int own;
 135 module_param(own, int, 0);
 136 MODULE_PARM_DESC(own, "Address of OMAP I2C master (0 for default == 1)");
 137
 138 struct omap_i2c_dev {
 139         struct device           *dev;
 140         void __iomem            *base;          /* virtual */
 141         int                     irq;
 142         struct clk              *iclk;          /* Interface clock */
 143         struct clk              *fclk;          /* Functional clock */
 144         struct completion       cmd_complete;
 145         u16                     cmd_err;
 146         u8                      *buf;
 147         size_t                  buf_len;
 148         struct i2c_adapter      adapter;
 149         unsigned                rev1:1;
 150         u8                      own_address;
 151 };
 152
 153 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
 154                                       int reg, u16 val)
 155 {
 156         __raw_writew(val, i2c_dev->base + reg);
 157 }
 158
 159 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
 160 {
 161         return __raw_readw(i2c_dev->base + reg);
 162 }
 163
 164 #ifdef CONFIG_ARCH_OMAP24XX
 165 static int omap_i2c_get_clocks(struct omap_i2c_dev *dev, int bus)
 166 {
 167         if (!cpu_is_omap24xx())
 168                 return 0;
 169
 170         dev->iclk = clk_get(NULL,
 171                 bus == 1 ? "i2c1_ick" : "i2c2_ick");
 172         if (IS_ERR(dev->iclk)) {
 173                 return -ENODEV;
 174         }
 175
 176         dev->fclk = clk_get(NULL,
 177                 bus == 1 ? "i2c1_fck" : "i2c2_fck");
 178         if (IS_ERR(dev->fclk)) {
 179                 clk_put(dev->fclk);
 180                 return -ENODEV;
 181         }
 182
 183         return 0;
 184 }
 185
 186 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
 187 {
 188         clk_put(dev->fclk);
 189         clk_put(dev->iclk);
 190 }
 191
 192 static void omap_i2c_enable_clocks(struct omap_i2c_dev *dev)
 193 {
 194         clk_enable(dev->iclk);
 195         clk_enable(dev->fclk);
 196 }
 197
 198 static void omap_i2c_disable_clocks(struct omap_i2c_dev *dev)
 199 {
 200         clk_disable(dev->iclk);
 201         clk_disable(dev->fclk);
 202 }
 203
 204 #else
 205 #define omap_i2c_get_clocks(x, y)               0
 206 #define omap_i2c_enable_clocks(x, y)    do {} while (0)
 207 #define omap_i2c_disable_clocks(x, y)   do {} while (0)
 208 #define omap_i2c_put_clocks(x)          do {} while (0)
 209 #endif
 210
 211 static void omap_i2c_reset(struct omap_i2c_dev *dev)
 212 {
 213         u16 psc;
 214         unsigned long fclk_rate;
 215
 216         if (!dev->rev1) {
 217                 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, OMAP_I2C_SYSC_SRST);
 218                 /* For some reason we need to set the EN bit before the
 219                  * reset done bit gets set. */
 220                 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 221                 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) & 0x01));
 222         }
 223         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 224
 225         if (cpu_class_is_omap1()) {
 226                 struct clk *armxor_ck;
 227                 unsigned long armxor_rate;
 228
 229                 armxor_ck = clk_get(NULL, "armxor_ck");
 230                 if (IS_ERR(armxor_ck)) {
 231                         printk(KERN_WARNING "i2c: Could not get armxor_ck\n");
 232                         armxor_rate = 12000000;
 233                 } else {
 234                         armxor_rate = clk_get_rate(armxor_ck);
 235                         clk_put(armxor_ck);
 236                 }
 237
 238                 if (armxor_rate > 16000000)
 239                         psc = (armxor_rate + 8000000) / 12000000;
 240                 else
 241                         psc = 0;
 242
 243                 fclk_rate = armxor_rate;
 244         } else if (cpu_class_is_omap2()) {
 245                 fclk_rate = 12000000;
 246                 psc = 0;
 247         }
 248
 249         /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
 250         omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
 251
 252         /* Program desired operating rate */
 253         fclk_rate /= (psc + 1) * 1000;
 254         if (psc > 2)
 255                 psc = 2;
 256
 257         omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG,
 258                            fclk_rate / (clock * 2) - 7 + psc);
 259         omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG,
 260                            fclk_rate / (clock * 2) - 7 + psc);
 261
 262         /* Set Own Address: */
 263         omap_i2c_write_reg(dev, OMAP_I2C_OA_REG, dev->own_address);
 264
 265         /* Take the I2C module out of reset: */
 266         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
 267
 268         /* Enable interrupts */
 269         omap_i2c_write_reg(dev, OMAP_I2C_IE_REG,
 270                            (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
 271                             OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
 272                             OMAP_I2C_IE_AL));
 273 }
 274
 275 /*
 276  * Waiting on Bus Busy
 277  */
 278 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
 279 {
 280         unsigned long timeout;
 281
 282         timeout = jiffies + OMAP_I2C_TIMEOUT;
 283         while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
 284                 if (time_after(jiffies, timeout)) {
 285                         dev_warn(dev->dev, "timeout waiting for bus ready\n");
 286                         return -ETIMEDOUT;
 287                 }
 288                 msleep(1);
 289         }
 290
 291         return 0;
 292 }
 293
 294 /*
 295  * Low level master read/write transaction.
 296  */
 297 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
 298                              struct i2c_msg *msg, int stop)
 299 {
 300         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 301         int r;
 302         u16 w;
 303         u8 zero_byte = 0;
 304
 305         dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
 306                 msg->addr, msg->len, msg->flags, stop);
 307
 308         omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
 309
 310         /* Sigh, seems we can't do zero length transactions. Thus, we
 311          * can't probe for devices w/o actually sending/receiving at least
 312          * a single byte. So we'll set count to 1 for the zero length
 313          * transaction case and hope we don't cause grief for some
 314          * arbitrary device due to random byte write/read during
 315          * probes.
 316          */
 317         /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
 318         if (msg->len == 0) {
 319                 dev->buf = &zero_byte;
 320                 dev->buf_len = 1;
 321         } else {
 322                 dev->buf = msg->buf;
 323                 dev->buf_len = msg->len;
 324         }
 325         omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
 326
 327         init_completion(&dev->cmd_complete);
 328         dev->cmd_err = 0;
 329
 330         w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
 331         if (msg->flags & I2C_M_TEN)
 332                 w |= OMAP_I2C_CON_XA;
 333         if (!(msg->flags & I2C_M_RD))
 334                 w |= OMAP_I2C_CON_TRX;
 335         if (stop)
 336                 w |= OMAP_I2C_CON_STP;
 337         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 338
 339         r = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
 340                                                       OMAP_I2C_TIMEOUT);
 341         dev->buf_len = 0;
 342         if (r < 0)
 343                 return r;
 344         if (r == 0) {
 345                 dev_err(dev->dev, "controller timed out\n");
 346                 omap_i2c_reset(dev);
 347                 return -ETIMEDOUT;
 348         }
 349
 350         if (likely(!dev->cmd_err))
 351                 return 0;
 352
 353         /* We have an error */
 354         if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
 355                 if (msg->flags & I2C_M_IGNORE_NAK)
 356                         return 0;
 357                 if (stop) {
 358                         u16 w;
 359
 360                         w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
 361                         w |= OMAP_I2C_CON_STP;
 362                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
 363                 }
 364                 return -EREMOTEIO;
 365         }
 366         if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
 367                             OMAP_I2C_STAT_XUDF))
 368                 omap_i2c_reset(dev);
 369         return -EIO;
 370 }
 371
 372
 373 /*
 374  * Prepare controller for a transaction and call omap_i2c_xfer_msg
 375  * to do the work during IRQ processing.
 376  */
 377 static int
 378 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 379 {
 380         struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
 381         int i;
 382         int r = 0;
 383
 384         if (num < 1 || num > MAX_MESSAGES)
 385                 return -EINVAL;
 386
 387         /* Check for valid parameters in messages */
 388         for (i = 0; i < num; i++)
 389                 if (msgs[i].buf == NULL)
 390                         return -EINVAL;
 391
 392         omap_i2c_enable_clocks(dev);
 393
 394         /* REVISIT: initialize and use adap->retries */
 395         if ((r = omap_i2c_wait_for_bb(dev)) < 0)
 396                 goto out;
 397
 398         for (i = 0; i < num; i++) {
 399                 dev_dbg(dev->dev, "msg: %d, addr: 0x%04x, len: %d, flags: 0x%x\n",
 400                         i, msgs[i].addr, msgs[i].len, msgs[i].flags);
 401                 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
 402                 if (r != 0)
 403                         break;
 404         }
 405
 406         if (r == 0 && num > 1)
 407                 r = num;
 408 out:
 409         omap_i2c_disable_clocks(dev);
 410         return r;
 411 }
 412
 413 static u32
 414 omap_i2c_func(struct i2c_adapter *adap)
 415 {
 416         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 417 }
 418
 419 static inline void
 420 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
 421 {
 422         dev->cmd_err |= err;
 423         complete(&dev->cmd_complete);
 424 }
 425
 426 static inline void
 427 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
 428 {
 429         omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 430 }
 431
 432 static irqreturn_t
 433 omap_i2c_isr(int this_irq, void *dev_id, struct pt_regs *regs)
 434 {
 435         struct omap_i2c_dev *dev = dev_id;
 436         u16 bits;
 437         u16 stat, w;
 438         int count = 0;
 439         u16 iv_read;
 440
 441         bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
 442         while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
 443                 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
 444                 if (count++ == 100) {
 445                         dev_warn(dev->dev, "Too much work in one IRQ\n");
 446                         break;
 447                 }
 448
 449                 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
 450
 451                 if (stat & OMAP_I2C_STAT_ARDY) {
 452                         omap_i2c_complete_cmd(dev, 0);
 453                         if (dev->rev1)
 454                                 iv_read = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 455                         continue;
 456                 }
 457                 if (stat & OMAP_I2C_STAT_RRDY) {
 458                         w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
 459                         if (dev->buf_len) {
 460                                 *dev->buf++ = w;
 461                                 dev->buf_len--;
 462                                 if (dev->buf_len) {
 463                                         *dev->buf++ = w >> 8;
 464                                         dev->buf_len--;
 465                                 }
 466                                 if (dev->rev1 && !dev->buf_len)
 467                                         omap_i2c_complete_cmd(dev, 0);
 468                         } else
 469                                 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
 470                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
 471                         if (dev->rev1)
 472                                 iv_read = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 473                         continue;
 474                 }
 475                 if (stat & OMAP_I2C_STAT_XRDY) {
 476                         int bail_out = 0;
 477
 478                         w = 0;
 479                         if (dev->buf_len) {
 480                                 w = *dev->buf++;
 481                                 dev->buf_len--;
 482                                 if (dev->buf_len) {
 483                                         w |= *dev->buf++ << 8;
 484                                         dev->buf_len--;
 485                                 }
 486                         } else
 487                                 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
 488 #if 0
 489                         if (!(stat & OMAP_I2C_STAT_BB)) {
 490                                 dev_warn(dev->dev, "XRDY while bus not busy\n");
 491                                 bail_out = 1;
 492                         }
 493 #endif
 494                         omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
 495                         omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
 496                         if (dev->rev1) {
 497                                 iv_read = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 498                                 if (!dev->buf_len)
 499                                         omap_i2c_complete_cmd(dev, 0);
 500                         }
 501                         if (bail_out)
 502                                 omap_i2c_complete_cmd(dev, 1 << 15);
 503                         continue;
 504                 }
 505                 if (stat & OMAP_I2C_STAT_ROVR) {
 506                         dev_err(dev->dev, "Receive overrun\n");
 507                         dev->cmd_err |= OMAP_I2C_STAT_ROVR;
 508                 }
 509                 if (stat & OMAP_I2C_STAT_XUDF) {
 510                         dev_err(dev->dev, "Transmit overflow\n");
 511                         dev->cmd_err |= OMAP_I2C_STAT_XUDF;
 512                 }
 513                 if (stat & OMAP_I2C_STAT_NACK) {
 514                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
 515                         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
 516                 }
 517                 if (stat & OMAP_I2C_STAT_AL) {
 518                         dev_err(dev->dev, "Arbitration lost\n");
 519                         omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
 520                 }
 521                 if (dev->rev1)
 522                         iv_read = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
 523         }
 524
 525         return count ? IRQ_HANDLED : IRQ_NONE;
 526 }
 527
 528 static struct i2c_algorithm omap_i2c_algo = {
 529         .master_xfer    = omap_i2c_xfer,
 530         .functionality  = omap_i2c_func,
 531 };
 532
 533 static int
 534 omap_i2c_probe(struct platform_device *pdev)
 535 {
 536         struct omap_i2c_dev     *dev;
 537         struct i2c_adapter      *adap;
 538         struct resource         *mem, *irq;
 539         int r;
 540
 541         /* NOTE: driver uses the static register mapping */
 542         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 543         if (!mem) {
 544                 dev_err(&pdev->dev, "no mem resource?\n");
 545                 return -ENODEV;
 546         }
 547         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 548         if (!irq) {
 549                 dev_err(&pdev->dev, "no irq resource?\n");
 550                 return -ENODEV;
 551         }
 552
 553         r = (int) request_mem_region(mem->start, (mem->end - mem->start) + 1,
 554                         driver_name);
 555         if (!r) {
 556                 dev_err(&pdev->dev, "I2C region already claimed\n");
 557                 return -EBUSY;
 558         }
 559
 560         if (clock > 200)
 561                 clock = 400;    /* Fast mode */
 562         else
 563                 clock = 100;    /* Standard mode */
 564
 565         dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
 566         if (!dev) {
 567                 r = -ENOMEM;
 568                 goto do_release_region;
 569         }
 570
 571         /* FIXME: Get own address from platform_data */
 572         if (own >= 1 && own < 0x7f)
 573                 dev->own_address = own;
 574         else
 575                 own = DEFAULT_OWN;
 576
 577         dev->dev = &pdev->dev;
 578         dev->irq = irq->start;
 579         dev->base = (void __iomem *) IO_ADDRESS(mem->start);
 580         platform_set_drvdata(pdev, dev);
 581
 582         if ((r = omap_i2c_get_clocks(dev, pdev->id)) != 0)
 583                 goto do_free_mem;
 584
 585         omap_i2c_enable_clocks(dev);
 586
 587 #ifdef CONFIG_ARCH_OMAP15XX
 588         dev->rev1 = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) < 0x20;
 589 #endif
 590
 591         /* reset ASAP, clearing any IRQs */
 592         omap_i2c_reset(dev);
 593
 594         r = request_irq(dev->irq, omap_i2c_isr, 0,
 595                         driver_name, dev);
 596         if (r) {
 597                 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
 598                 goto do_unuse_clocks;
 599         }
 600         r = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
 601         dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
 602                  pdev->id - 1, r >> 4, r & 0xf, clock);
 603
 604         adap = &dev->adapter;
 605         i2c_set_adapdata(adap, dev);
 606         adap->owner = THIS_MODULE;
 607         adap->class = I2C_CLASS_HWMON;
 608         strncpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
 609         adap->algo = &omap_i2c_algo;
 610         adap->dev.parent = &pdev->dev;
 611
 612         /* i2c device drivers may be active on return from add_adapter() */
 613         r = i2c_add_adapter(adap);
 614         if (r) {
 615                 dev_err(dev->dev, "failure adding adapter\n");
 616                 goto do_free_irq;
 617         }
 618
 619         omap_i2c_disable_clocks(dev);
 620
 621         return 0;
 622
 623 do_free_irq:
 624         free_irq(dev->irq, dev);
 625 do_unuse_clocks:
 626         omap_i2c_enable_clocks(dev);
 627         omap_i2c_put_clocks(dev);
 628 do_free_mem:
 629         kfree(dev);
 630 do_release_region:
 631         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 632         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 633
 634         return r;
 635 }
 636
 637 static int
 638 omap_i2c_remove(struct platform_device *pdev)
 639 {
 640         struct omap_i2c_dev     *dev = platform_get_drvdata(pdev);
 641         struct resource         *mem;
 642
 643         free_irq(dev->irq, dev);
 644         i2c_del_adapter(&dev->adapter);
 645         omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
 646         omap_i2c_put_clocks(dev);
 647         kfree(dev);
 648         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 649         release_mem_region(mem->start, (mem->end - mem->start) + 1);
 650         return 0;
 651 }
 652
 653 static struct platform_driver omap_i2c_driver = {
 654         .probe          = omap_i2c_probe,
 655         .remove         = omap_i2c_remove,
 656         .driver         = {
 657                 .name   = (char *)driver_name,
 658         },
 659 };
 660
 661 /* I2C may be needed to bring up other drivers */
 662 static int __init
 663 omap_i2c_init_driver(void)
 664 {
 665         return platform_driver_register(&omap_i2c_driver);
 666 }
 667 subsys_initcall(omap_i2c_init_driver);
 668
 669 static void __exit omap_i2c_exit_driver(void)
 670 {
 671         platform_driver_unregister(&omap_i2c_driver);
 672 }
 673 module_exit(omap_i2c_exit_driver);
 674
 675 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
 676 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
 677 MODULE_LICENSE("GPL");