drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.8
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/init.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_i2c.h>
  22
  23 #include <linux/io.h>
  24 #include <linux/fsl_devices.h>
  25 #include <linux/i2c.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/delay.h>
  28
  29 #define DRV_NAME "mpc-i2c"
  30
  31 #define MPC_I2C_FDR   0x04
  32 #define MPC_I2C_CR    0x08
  33 #define MPC_I2C_SR    0x0c
  34 #define MPC_I2C_DR    0x10
  35 #define MPC_I2C_DFSRR 0x14
  36
  37 #define CCR_MEN  0x80
  38 #define CCR_MIEN 0x40
  39 #define CCR_MSTA 0x20
  40 #define CCR_MTX  0x10
  41 #define CCR_TXAK 0x08
  42 #define CCR_RSTA 0x04
  43
  44 #define CSR_MCF  0x80
  45 #define CSR_MAAS 0x40
  46 #define CSR_MBB  0x20
  47 #define CSR_MAL  0x10
  48 #define CSR_SRW  0x04
  49 #define CSR_MIF  0x02
  50 #define CSR_RXAK 0x01
  51
  52 struct mpc_i2c {
  53         void __iomem *base;
  54         u32 interrupt;
  55         wait_queue_head_t queue;
  56         struct i2c_adapter adap;
  57         int irq;
  58         u32 flags;
  59 };
  60
  61 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
  62 {
  63         writeb(x, i2c->base + MPC_I2C_CR);
  64 }
  65
  66 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  67 {
  68         struct mpc_i2c *i2c = dev_id;
  69         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  70                 /* Read again to allow register to stabilise */
  71                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  72                 writeb(0, i2c->base + MPC_I2C_SR);
  73                 wake_up(&i2c->queue);
  74         }
  75         return IRQ_HANDLED;
  76 }
  77
  78 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  79  * the bus, because it wants to send ACK.
  80  * Following sequence of enabling/disabling and sending start/stop generates
  81  * the pulse, so it's all OK.
  82  */
  83 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
  84 {
  85         writeccr(i2c, 0);
  86         udelay(30);
  87         writeccr(i2c, CCR_MEN);
  88         udelay(30);
  89         writeccr(i2c, CCR_MSTA | CCR_MTX);
  90         udelay(30);
  91         writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
  92         udelay(30);
  93         writeccr(i2c, CCR_MEN);
  94         udelay(30);
  95 }
  96
  97 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
  98 {
  99         unsigned long orig_jiffies = jiffies;
 100         u32 x;
 101         int result = 0;
 102
 103         if (i2c->irq == NO_IRQ) {
 104                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
 105                         schedule();
 106                         if (time_after(jiffies, orig_jiffies + timeout)) {
 107                                 pr_debug("I2C: timeout\n");
 108                                 writeccr(i2c, 0);
 109                                 result = -EIO;
 110                                 break;
 111                         }
 112                 }
 113                 x = readb(i2c->base + MPC_I2C_SR);
 114                 writeb(0, i2c->base + MPC_I2C_SR);
 115         } else {
 116                 /* Interrupt mode */
 117                 result = wait_event_timeout(i2c->queue,
 118                         (i2c->interrupt & CSR_MIF), timeout);
 119
 120                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
 121                         pr_debug("I2C: wait timeout\n");
 122                         writeccr(i2c, 0);
 123                         result = -ETIMEDOUT;
 124                 }
 125
 126                 x = i2c->interrupt;
 127                 i2c->interrupt = 0;
 128         }
 129
 130         if (result < 0)
 131                 return result;
 132
 133         if (!(x & CSR_MCF)) {
 134                 pr_debug("I2C: unfinished\n");
 135                 return -EIO;
 136         }
 137
 138         if (x & CSR_MAL) {
 139                 pr_debug("I2C: MAL\n");
 140                 return -EIO;
 141         }
 142
 143         if (writing && (x & CSR_RXAK)) {
 144                 pr_debug("I2C: No RXAK\n");
 145                 /* generate stop */
 146                 writeccr(i2c, CCR_MEN);
 147                 return -EIO;
 148         }
 149         return 0;
 150 }
 151
 152 static void mpc_i2c_setclock(struct mpc_i2c *i2c)
 153 {
 154         /* Set clock and filters */
 155         if (i2c->flags & FSL_I2C_DEV_SEPARATE_DFSRR) {
 156                 writeb(0x31, i2c->base + MPC_I2C_FDR);
 157                 writeb(0x10, i2c->base + MPC_I2C_DFSRR);
 158         } else if (i2c->flags & FSL_I2C_DEV_CLOCK_5200)
 159                 writeb(0x3f, i2c->base + MPC_I2C_FDR);
 160         else
 161                 writel(0x1031, i2c->base + MPC_I2C_FDR);
 162 }
 163
 164 static void mpc_i2c_start(struct mpc_i2c *i2c)
 165 {
 166         /* Clear arbitration */
 167         writeb(0, i2c->base + MPC_I2C_SR);
 168         /* Start with MEN */
 169         writeccr(i2c, CCR_MEN);
 170 }
 171
 172 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 173 {
 174         writeccr(i2c, CCR_MEN);
 175 }
 176
 177 static int mpc_write(struct mpc_i2c *i2c, int target,
 178                      const u8 *data, int length, int restart)
 179 {
 180         int i, result;
 181         unsigned timeout = i2c->adap.timeout;
 182         u32 flags = restart ? CCR_RSTA : 0;
 183
 184         /* Start with MEN */
 185         if (!restart)
 186                 writeccr(i2c, CCR_MEN);
 187         /* Start as master */
 188         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 189         /* Write target byte */
 190         writeb((target << 1), i2c->base + MPC_I2C_DR);
 191
 192         result = i2c_wait(i2c, timeout, 1);
 193         if (result < 0)
 194                 return result;
 195
 196         for (i = 0; i < length; i++) {
 197                 /* Write data byte */
 198                 writeb(data[i], i2c->base + MPC_I2C_DR);
 199
 200                 result = i2c_wait(i2c, timeout, 1);
 201                 if (result < 0)
 202                         return result;
 203         }
 204
 205         return 0;
 206 }
 207
 208 static int mpc_read(struct mpc_i2c *i2c, int target,
 209                     u8 *data, int length, int restart)
 210 {
 211         unsigned timeout = i2c->adap.timeout;
 212         int i, result;
 213         u32 flags = restart ? CCR_RSTA : 0;
 214
 215         /* Start with MEN */
 216         if (!restart)
 217                 writeccr(i2c, CCR_MEN);
 218         /* Switch to read - restart */
 219         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 220         /* Write target address byte - this time with the read flag set */
 221         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 222
 223         result = i2c_wait(i2c, timeout, 1);
 224         if (result < 0)
 225                 return result;
 226
 227         if (length) {
 228                 if (length == 1)
 229                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 230                 else
 231                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 232                 /* Dummy read */
 233                 readb(i2c->base + MPC_I2C_DR);
 234         }
 235
 236         for (i = 0; i < length; i++) {
 237                 result = i2c_wait(i2c, timeout, 0);
 238                 if (result < 0)
 239                         return result;
 240
 241                 /* Generate txack on next to last byte */
 242                 if (i == length - 2)
 243                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 244                 /* Generate stop on last byte */
 245                 if (i == length - 1)
 246                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_TXAK);
 247                 data[i] = readb(i2c->base + MPC_I2C_DR);
 248         }
 249
 250         return length;
 251 }
 252
 253 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 254 {
 255         struct i2c_msg *pmsg;
 256         int i;
 257         int ret = 0;
 258         unsigned long orig_jiffies = jiffies;
 259         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 260
 261         mpc_i2c_start(i2c);
 262
 263         /* Allow bus up to 1s to become not busy */
 264         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 265                 if (signal_pending(current)) {
 266                         pr_debug("I2C: Interrupted\n");
 267                         writeccr(i2c, 0);
 268                         return -EINTR;
 269                 }
 270                 if (time_after(jiffies, orig_jiffies + HZ)) {
 271                         pr_debug("I2C: timeout\n");
 272                         if (readb(i2c->base + MPC_I2C_SR) ==
 273                             (CSR_MCF | CSR_MBB | CSR_RXAK))
 274                                 mpc_i2c_fixup(i2c);
 275                         return -EIO;
 276                 }
 277                 schedule();
 278         }
 279
 280         for (i = 0; ret >= 0 && i < num; i++) {
 281                 pmsg = &msgs[i];
 282                 pr_debug("Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 283                          pmsg->flags & I2C_M_RD ? "read" : "write",
 284                          pmsg->len, pmsg->addr, i + 1, num);
 285                 if (pmsg->flags & I2C_M_RD)
 286                         ret =
 287                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 288                 else
 289                         ret =
 290                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 291         }
 292         mpc_i2c_stop(i2c);
 293         return (ret < 0) ? ret : num;
 294 }
 295
 296 static u32 mpc_functionality(struct i2c_adapter *adap)
 297 {
 298         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 299 }
 300
 301 static const struct i2c_algorithm mpc_algo = {
 302         .master_xfer = mpc_xfer,
 303         .functionality = mpc_functionality,
 304 };
 305
 306 static struct i2c_adapter mpc_ops = {
 307         .owner = THIS_MODULE,
 308         .name = "MPC adapter",
 309         .algo = &mpc_algo,
 310         .timeout = HZ,
 311 };
 312
 313 static int __devinit fsl_i2c_probe(struct of_device *op,
 314                                    const struct of_device_id *match)
 315 {
 316         int result = 0;
 317         struct mpc_i2c *i2c;
 318
 319         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 320         if (!i2c)
 321                 return -ENOMEM;
 322
 323         if (of_get_property(op->node, "dfsrr", NULL))
 324                 i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
 325
 326         if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
 327                         of_device_is_compatible(op->node, "mpc5200-i2c"))
 328                 i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
 329
 330         init_waitqueue_head(&i2c->queue);
 331
 332         i2c->base = of_iomap(op->node, 0);
 333         if (!i2c->base) {
 334                 printk(KERN_ERR "i2c-mpc - failed to map controller\n");
 335                 result = -ENOMEM;
 336                 goto fail_map;
 337         }
 338
 339         i2c->irq = irq_of_parse_and_map(op->node, 0);
 340         if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
 341                 result = request_irq(i2c->irq, mpc_i2c_isr,
 342                                      IRQF_SHARED, "i2c-mpc", i2c);
 343                 if (result < 0) {
 344                         printk(KERN_ERR
 345                                "i2c-mpc - failed to attach interrupt\n");
 346                         goto fail_request;
 347                 }
 348         }
 349
 350         mpc_i2c_setclock(i2c);
 351
 352         dev_set_drvdata(&op->dev, i2c);
 353
 354         i2c->adap = mpc_ops;
 355         i2c_set_adapdata(&i2c->adap, i2c);
 356         i2c->adap.dev.parent = &op->dev;
 357
 358         result = i2c_add_adapter(&i2c->adap);
 359         if (result < 0) {
 360                 printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
 361                 goto fail_add;
 362         }
 363         of_register_i2c_devices(&i2c->adap, op->node);
 364
 365         return result;
 366
 367  fail_add:
 368         dev_set_drvdata(&op->dev, NULL);
 369         free_irq(i2c->irq, i2c);
 370  fail_request:
 371         irq_dispose_mapping(i2c->irq);
 372         iounmap(i2c->base);
 373  fail_map:
 374         kfree(i2c);
 375         return result;
 376 };
 377
 378 static int __devexit fsl_i2c_remove(struct of_device *op)
 379 {
 380         struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
 381
 382         i2c_del_adapter(&i2c->adap);
 383         dev_set_drvdata(&op->dev, NULL);
 384
 385         if (i2c->irq != NO_IRQ)
 386                 free_irq(i2c->irq, i2c);
 387
 388         irq_dispose_mapping(i2c->irq);
 389         iounmap(i2c->base);
 390         kfree(i2c);
 391         return 0;
 392 };
 393
 394 static const struct of_device_id mpc_i2c_of_match[] = {
 395         {.compatible = "fsl-i2c",},
 396         {},
 397 };
 398 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 399
 400
 401 /* Structure for a device driver */
 402 static struct of_platform_driver mpc_i2c_driver = {
 403         .match_table    = mpc_i2c_of_match,
 404         .probe          = fsl_i2c_probe,
 405         .remove         = __devexit_p(fsl_i2c_remove),
 406         .driver         = {
 407                 .owner  = THIS_MODULE,
 408                 .name   = DRV_NAME,
 409         },
 410 };
 411
 412 static int __init fsl_i2c_init(void)
 413 {
 414         int rv;
 415
 416         rv = of_register_platform_driver(&mpc_i2c_driver);
 417         if (rv)
 418                 printk(KERN_ERR DRV_NAME
 419                        " of_register_platform_driver failed (%i)\n", rv);
 420         return rv;
 421 }
 422
 423 static void __exit fsl_i2c_exit(void)
 424 {
 425         of_unregister_platform_driver(&mpc_i2c_driver);
 426 }
 427
 428 module_init(fsl_i2c_init);
 429 module_exit(fsl_i2c_exit);
 430
 431 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 432 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 433                    "MPC824x/85xx/52xx processors");
 434 MODULE_LICENSE("GPL");