2 * Copyright (C) 2002 Motorola GSG-China
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307,
20 * Darius Augulis, Teltonika Inc.
23 * Implementation of I2C Adapter/Algorithm Driver
24 * for I2C Bus integrated in Freescale i.MX/MXC processors
26 * Derived from Motorola GSG China I2C example driver
28 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de
29 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de
30 * Copyright (C) 2007 RightHand Technologies, Inc.
31 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt>
35 /** Includes *******************************************************************
36 *******************************************************************************/
38 #include <linux/init.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/errno.h>
42 #include <linux/err.h>
43 #include <linux/interrupt.h>
44 #include <linux/delay.h>
45 #include <linux/i2c.h>
47 #include <linux/sched.h>
48 #include <linux/platform_device.h>
49 #include <linux/clk.h>
51 #include <mach/irqs.h>
52 #include <mach/hardware.h>
55 /** Defines ********************************************************************
56 *******************************************************************************/
58 /* This will be the driver name the kernel reports */
59 #define DRIVER_NAME "imx-i2c"
62 #define IMX_I2C_BIT_RATE 100000 /* 100kHz */
64 /* IMX I2C registers */
65 #define IMX_I2C_IADR 0x00 /* i2c slave address */
66 #define IMX_I2C_IFDR 0x04 /* i2c frequency divider */
67 #define IMX_I2C_I2CR 0x08 /* i2c control */
68 #define IMX_I2C_I2SR 0x0C /* i2c status */
69 #define IMX_I2C_I2DR 0x10 /* i2c transfer data */
71 /* Bits of IMX I2C registers */
72 #define I2SR_RXAK 0x01
77 #define I2SR_IAAS 0x40
79 #define I2CR_RSTA 0x04
80 #define I2CR_TXAK 0x08
82 #define I2CR_MSTA 0x20
83 #define I2CR_IIEN 0x40
86 /** Variables ******************************************************************
87 *******************************************************************************/
89 static unsigned int disable_delay; /* Dummy delay */
92 * sorted list of clock divider, register value pairs
93 * taken from table 26-5, p.26-9, Freescale i.MX
94 * Integrated Portable System Processor Reference Manual
95 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007
97 * Duplicated divider values removed from list
100 static u16 __initdata i2c_clk_div[50][2] = {
101 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 },
102 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 },
103 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 },
104 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B },
105 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A },
106 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 },
107 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 },
108 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 },
109 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 },
110 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B },
111 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E },
112 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D },
113 { 3072, 0x1E }, { 3840, 0x1F }
116 struct imx_i2c_struct {
117 struct i2c_adapter adapter;
118 struct resource *res;
122 wait_queue_head_t queue;
126 /** Functions for IMX I2C adapter driver ***************************************
127 *******************************************************************************/
129 static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx)
131 unsigned long orig_jiffies = jiffies;
133 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
135 /* wait for bus not busy */
136 while (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_IBB) {
137 if (signal_pending(current)) {
138 dev_dbg(&i2c_imx->adapter.dev,
139 "<%s> I2C Interrupted\n", __func__);
142 if (time_after(jiffies, orig_jiffies + HZ / 1000)) {
143 dev_dbg(&i2c_imx->adapter.dev,
144 "<%s> I2C bus is busy\n", __func__);
153 static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx)
157 result = wait_event_interruptible_timeout(i2c_imx->queue,
158 i2c_imx->i2csr & I2SR_IIF, HZ / 10);
160 if (unlikely(result < 0)) {
161 dev_dbg(&i2c_imx->adapter.dev, "<%s> result < 0\n", __func__);
163 } else if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) {
164 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__);
167 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__);
172 static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx)
174 if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) {
175 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__);
176 return -EIO; /* No ACK */
179 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__);
183 static void i2c_imx_start(struct imx_i2c_struct *i2c_imx)
185 unsigned int temp = 0;
187 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
189 /* Enable I2C controller */
190 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
191 /* Start I2C transaction */
192 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
194 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
195 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK;
196 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
199 static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
201 unsigned int temp = 0;
203 /* Stop I2C transaction */
204 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
205 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
207 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
208 /* setup chip registers to defaults */
209 writeb(I2CR_IEN, i2c_imx->base + IMX_I2C_I2CR);
210 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
212 * This delay caused by an i.MXL hardware bug.
213 * If no (or too short) delay, no "STOP" bit will be generated.
215 udelay(disable_delay);
216 /* Disable I2C controller */
217 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
220 static void __init i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx,
223 unsigned int i2c_clk_rate;
227 /* Divider value calculation */
228 i2c_clk_rate = clk_get_rate(i2c_imx->clk);
229 div = (i2c_clk_rate + rate - 1) / rate;
230 if (div < i2c_clk_div[0][0])
232 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0])
233 i = ARRAY_SIZE(i2c_clk_div) - 1;
235 for (i = 0; i2c_clk_div[i][0] < div; i++);
237 /* Write divider value to register */
238 writeb(i2c_clk_div[i][1], i2c_imx->base + IMX_I2C_IFDR);
241 * There dummy delay is calculated.
242 * It should be about one I2C clock period long.
243 * This delay is used in I2C bus disable function
244 * to fix chip hardware bug.
246 disable_delay = (500000U * i2c_clk_div[i][0]
247 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2);
249 /* dev_dbg() can't be used, because adapter is not yet registered */
250 #ifdef CONFIG_I2C_DEBUG_BUS
251 printk(KERN_DEBUG "I2C: <%s> I2C_CLK=%d, REQ DIV=%d\n",
252 __func__, i2c_clk_rate, div);
253 printk(KERN_DEBUG "I2C: <%s> IFDR[IC]=0x%x, REAL DIV=%d\n",
254 __func__, i2c_clk_div[i][1], i2c_clk_div[i][0]);
258 static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
260 struct imx_i2c_struct *i2c_imx = dev_id;
263 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
264 if (temp & I2SR_IIF) {
265 /* save status register */
266 i2c_imx->i2csr = temp;
268 writeb(temp, i2c_imx->base + IMX_I2C_I2SR);
269 wake_up_interruptible(&i2c_imx->queue);
276 static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
280 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n",
281 __func__, msgs->addr << 1);
283 /* write slave address */
284 writeb(msgs->addr << 1, i2c_imx->base + IMX_I2C_I2DR);
285 result = i2c_imx_trx_complete(i2c_imx);
288 result = i2c_imx_acked(i2c_imx);
291 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__);
294 for (i = 0; i < msgs->len; i++) {
295 dev_dbg(&i2c_imx->adapter.dev,
296 "<%s> write byte: B%d=0x%X\n",
297 __func__, i, msgs->buf[i]);
298 writeb(msgs->buf[i], i2c_imx->base + IMX_I2C_I2DR);
299 result = i2c_imx_trx_complete(i2c_imx);
302 result = i2c_imx_acked(i2c_imx);
309 static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs)
314 dev_dbg(&i2c_imx->adapter.dev,
315 "<%s> write slave address: addr=0x%x\n",
316 __func__, (msgs->addr << 1) | 0x01);
318 /* write slave address */
319 writeb((msgs->addr << 1) | 0x01, i2c_imx->base + IMX_I2C_I2DR);
320 result = i2c_imx_trx_complete(i2c_imx);
323 result = i2c_imx_acked(i2c_imx);
327 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__);
329 /* setup bus to read data */
330 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
334 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
335 readb(i2c_imx->base + IMX_I2C_I2DR); /* dummy read */
337 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__);
340 for (i = 0; i < msgs->len; i++) {
341 result = i2c_imx_trx_complete(i2c_imx);
344 if (i == (msgs->len - 1)) {
345 dev_dbg(&i2c_imx->adapter.dev,
346 "<%s> clear MSTA\n", __func__);
347 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
349 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
350 } else if (i == (msgs->len - 2)) {
351 dev_dbg(&i2c_imx->adapter.dev,
352 "<%s> set TXAK\n", __func__);
353 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
355 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
357 msgs->buf[i] = readb(i2c_imx->base + IMX_I2C_I2DR);
358 dev_dbg(&i2c_imx->adapter.dev,
359 "<%s> read byte: B%d=0x%X\n",
360 __func__, i, msgs->buf[i]);
365 static int i2c_imx_xfer(struct i2c_adapter *adapter,
366 struct i2c_msg *msgs, int num)
368 unsigned int i, temp;
370 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter);
372 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__);
374 /* Check if i2c bus is not busy */
375 result = i2c_imx_bus_busy(i2c_imx);
379 /* Start I2C transfer */
380 i2c_imx_start(i2c_imx);
382 /* read/write data */
383 for (i = 0; i < num; i++) {
385 dev_dbg(&i2c_imx->adapter.dev,
386 "<%s> repeated start\n", __func__);
387 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
389 writeb(temp, i2c_imx->base + IMX_I2C_I2CR);
391 dev_dbg(&i2c_imx->adapter.dev,
392 "<%s> transfer message: %d\n", __func__, i);
393 /* write/read data */
394 #ifdef CONFIG_I2C_DEBUG_BUS
395 temp = readb(i2c_imx->base + IMX_I2C_I2CR);
396 dev_dbg(&i2c_imx->adapter.dev, "<%s> CONTROL: IEN=%d, IIEN=%d, "
397 "MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", __func__,
398 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0),
399 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0),
400 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0));
401 temp = readb(i2c_imx->base + IMX_I2C_I2SR);
402 dev_dbg(&i2c_imx->adapter.dev,
403 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, "
404 "IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", __func__,
405 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0),
406 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0),
407 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0),
408 (temp & I2SR_RXAK ? 1 : 0));
410 if (msgs[i].flags & I2C_M_RD)
411 result = i2c_imx_read(i2c_imx, &msgs[i]);
413 result = i2c_imx_write(i2c_imx, &msgs[i]);
417 /* Stop I2C transfer */
418 i2c_imx_stop(i2c_imx);
420 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__,
421 (result < 0) ? "error" : "success msg",
422 (result < 0) ? result : num);
423 return (result < 0) ? result : num;
426 static u32 i2c_imx_func(struct i2c_adapter *adapter)
428 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
431 static struct i2c_algorithm i2c_imx_algo = {
432 .master_xfer = i2c_imx_xfer,
433 .functionality = i2c_imx_func,
436 static int __init i2c_imx_probe(struct platform_device *pdev)
438 struct imx_i2c_struct *i2c_imx;
439 struct resource *res;
440 struct imxi2c_platform_data *pdata;
442 resource_size_t res_size;
446 dev_dbg(&pdev->dev, "<%s>\n", __func__);
448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
450 dev_err(&pdev->dev, "can't get device resources\n");
453 irq = platform_get_irq(pdev, 0);
455 dev_err(&pdev->dev, "can't get irq number\n");
459 pdata = pdev->dev.platform_data;
461 if (pdata && pdata->init) {
462 ret = pdata->init(&pdev->dev);
467 res_size = resource_size(res);
468 base = ioremap(res->start, res_size);
470 dev_err(&pdev->dev, "ioremap failed\n");
475 i2c_imx = kzalloc(sizeof(struct imx_i2c_struct), GFP_KERNEL);
477 dev_err(&pdev->dev, "can't allocate interface\n");
482 if (!request_mem_region(res->start, res_size, DRIVER_NAME)) {
487 /* Setup i2c_imx driver structure */
488 strcpy(i2c_imx->adapter.name, pdev->name);
489 i2c_imx->adapter.owner = THIS_MODULE;
490 i2c_imx->adapter.algo = &i2c_imx_algo;
491 i2c_imx->adapter.dev.parent = &pdev->dev;
492 i2c_imx->adapter.nr = pdev->id;
494 i2c_imx->base = base;
498 i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk");
499 if (IS_ERR(i2c_imx->clk)) {
500 ret = PTR_ERR(i2c_imx->clk);
501 dev_err(&pdev->dev, "can't get I2C clock\n");
504 clk_enable(i2c_imx->clk);
507 ret = request_irq(i2c_imx->irq, i2c_imx_isr, 0, pdev->name, i2c_imx);
509 dev_err(&pdev->dev, "can't claim irq %d\n", i2c_imx->irq);
514 init_waitqueue_head(&i2c_imx->queue);
516 /* Set up adapter data */
517 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx);
519 /* Set up clock divider */
520 if (pdata && pdata->bitrate)
521 i2c_imx_set_clk(i2c_imx, pdata->bitrate);
523 i2c_imx_set_clk(i2c_imx, IMX_I2C_BIT_RATE);
525 /* Set up chip registers to defaults */
526 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
527 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
529 /* Add I2C adapter */
530 ret = i2c_add_numbered_adapter(&i2c_imx->adapter);
532 dev_err(&pdev->dev, "registration failed\n");
536 /* Set up platform driver data */
537 platform_set_drvdata(pdev, i2c_imx);
539 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", i2c_imx->irq);
540 dev_dbg(&i2c_imx->adapter.dev, "device resources from 0x%x to 0x%x\n",
541 i2c_imx->res->start, i2c_imx->res->end);
542 dev_dbg(&i2c_imx->adapter.dev, "allocated %d bytes at 0x%x \n",
543 res_size, i2c_imx->res->start);
544 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n",
545 i2c_imx->adapter.name);
546 dev_dbg(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n");
548 return 0; /* Return OK */
551 free_irq(i2c_imx->irq, i2c_imx);
553 clk_disable(i2c_imx->clk);
554 clk_put(i2c_imx->clk);
556 release_mem_region(i2c_imx->res->start, resource_size(res));
562 if (pdata && pdata->exit)
563 pdata->exit(&pdev->dev);
564 return ret; /* Return error number */
567 static int __exit i2c_imx_remove(struct platform_device *pdev)
569 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev);
570 struct imxi2c_platform_data *pdata = pdev->dev.platform_data;
573 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n");
574 i2c_del_adapter(&i2c_imx->adapter);
575 platform_set_drvdata(pdev, NULL);
578 free_irq(i2c_imx->irq, i2c_imx);
580 /* setup chip registers to defaults */
581 writeb(0, i2c_imx->base + IMX_I2C_IADR);
582 writeb(0, i2c_imx->base + IMX_I2C_IFDR);
583 writeb(0, i2c_imx->base + IMX_I2C_I2CR);
584 writeb(0, i2c_imx->base + IMX_I2C_I2SR);
586 /* Shut down hardware */
587 if (pdata && pdata->exit)
588 pdata->exit(&pdev->dev);
590 /* Disable I2C clock */
591 clk_disable(i2c_imx->clk);
592 clk_put(i2c_imx->clk);
594 release_mem_region(i2c_imx->res->start, resource_size(i2c_imx->res));
595 iounmap(i2c_imx->base);
600 static struct platform_driver i2c_imx_driver = {
601 .probe = i2c_imx_probe,
602 .remove = __exit_p(i2c_imx_remove),
605 .owner = THIS_MODULE,
609 static int __init i2c_adap_imx_init(void)
611 return platform_driver_probe(&i2c_imx_driver, i2c_imx_probe);
614 static void __exit i2c_adap_imx_exit(void)
616 platform_driver_unregister(&i2c_imx_driver);
619 module_init(i2c_adap_imx_init);
620 module_exit(i2c_adap_imx_exit);
622 MODULE_LICENSE("GPL");
623 MODULE_AUTHOR("Darius Augulis");
624 MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus");
625 MODULE_ALIAS("platform:" DRIVER_NAME);