2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
7 Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 Tolapai 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
47 Features supported by this driver:
51 Block process call transaction no
52 I2C block read transaction yes (doesn't use the block buffer)
54 See the file Documentation/i2c/busses/i2c-i801 for details.
57 /* Note: we assume there can only be one I801, with one SMBus interface */
59 #include <linux/module.h>
60 #include <linux/pci.h>
61 #include <linux/kernel.h>
62 #include <linux/stddef.h>
63 #include <linux/delay.h>
64 #include <linux/ioport.h>
65 #include <linux/init.h>
66 #include <linux/i2c.h>
69 /* I801 SMBus address offsets */
70 #define SMBHSTSTS (0 + i801_smba)
71 #define SMBHSTCNT (2 + i801_smba)
72 #define SMBHSTCMD (3 + i801_smba)
73 #define SMBHSTADD (4 + i801_smba)
74 #define SMBHSTDAT0 (5 + i801_smba)
75 #define SMBHSTDAT1 (6 + i801_smba)
76 #define SMBBLKDAT (7 + i801_smba)
77 #define SMBPEC (8 + i801_smba) /* ICH3 and later */
78 #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
79 #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
81 /* PCI Address Constants */
83 #define SMBHSTCFG 0x040
85 /* Host configuration bits for SMBHSTCFG */
86 #define SMBHSTCFG_HST_EN 1
87 #define SMBHSTCFG_SMB_SMI_EN 2
88 #define SMBHSTCFG_I2C_EN 4
90 /* Auxillary control register bits, ICH4+ only */
91 #define SMBAUXCTL_CRC 1
92 #define SMBAUXCTL_E32B 2
94 /* kill bit for SMBHSTCNT */
95 #define SMBHSTCNT_KILL 2
98 #define MAX_TIMEOUT 100
99 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
101 /* I801 command constants */
102 #define I801_QUICK 0x00
103 #define I801_BYTE 0x04
104 #define I801_BYTE_DATA 0x08
105 #define I801_WORD_DATA 0x0C
106 #define I801_PROC_CALL 0x10 /* unimplemented */
107 #define I801_BLOCK_DATA 0x14
108 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
109 #define I801_BLOCK_LAST 0x34
110 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
111 #define I801_START 0x40
112 #define I801_PEC_EN 0x80 /* ICH3 and later */
114 /* I801 Hosts Status register bits */
115 #define SMBHSTSTS_BYTE_DONE 0x80
116 #define SMBHSTSTS_INUSE_STS 0x40
117 #define SMBHSTSTS_SMBALERT_STS 0x20
118 #define SMBHSTSTS_FAILED 0x10
119 #define SMBHSTSTS_BUS_ERR 0x08
120 #define SMBHSTSTS_DEV_ERR 0x04
121 #define SMBHSTSTS_INTR 0x02
122 #define SMBHSTSTS_HOST_BUSY 0x01
124 static unsigned long i801_smba;
125 static unsigned char i801_original_hstcfg;
126 static struct pci_driver i801_driver;
127 static struct pci_dev *I801_dev;
129 #define FEATURE_SMBUS_PEC (1 << 0)
130 #define FEATURE_BLOCK_BUFFER (1 << 1)
131 #define FEATURE_BLOCK_PROC (1 << 2)
132 #define FEATURE_I2C_BLOCK_READ (1 << 3)
133 static unsigned int i801_features;
135 static int i801_transaction(int xact)
141 /* Make sure the SMBus host is ready to start transmitting */
142 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
143 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
144 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
146 outb_p(temp, SMBHSTSTS);
147 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
148 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
151 dev_dbg(&I801_dev->dev, "Successful!\n");
155 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
156 * INTREN, SMBSCMD are passed in xact */
157 outb_p(xact | I801_START, SMBHSTCNT);
159 /* We will always wait for a fraction of a second! */
162 temp = inb_p(SMBHSTSTS);
163 } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
165 /* If the SMBus is still busy, we give up */
166 if (timeout >= MAX_TIMEOUT) {
167 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
169 /* try to stop the current command */
170 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
171 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
173 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
176 if (temp & SMBHSTSTS_FAILED) {
178 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
181 if (temp & SMBHSTSTS_BUS_ERR) {
183 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
184 "until next hard reset. (sorry!)\n");
185 /* Clock stops and slave is stuck in mid-transmission */
188 if (temp & SMBHSTSTS_DEV_ERR) {
190 dev_dbg(&I801_dev->dev, "Error: no response!\n");
193 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
194 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
196 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
197 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
203 /* wait for INTR bit as advised by Intel */
204 static void i801_wait_hwpec(void)
211 temp = inb_p(SMBHSTSTS);
212 } while ((!(temp & SMBHSTSTS_INTR))
213 && (timeout++ < MAX_TIMEOUT));
215 if (timeout >= MAX_TIMEOUT) {
216 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
218 outb_p(temp, SMBHSTSTS);
221 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
222 char read_write, int hwpec)
227 inb_p(SMBHSTCNT); /* reset the data buffer index */
229 /* Use 32-byte buffer to process this transaction */
230 if (read_write == I2C_SMBUS_WRITE) {
231 len = data->block[0];
232 outb_p(len, SMBHSTDAT0);
233 for (i = 0; i < len; i++)
234 outb_p(data->block[i+1], SMBBLKDAT);
237 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
238 I801_PEC_EN * hwpec);
242 if (read_write == I2C_SMBUS_READ) {
243 len = inb_p(SMBHSTDAT0);
244 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
247 data->block[0] = len;
248 for (i = 0; i < len; i++)
249 data->block[i + 1] = inb_p(SMBBLKDAT);
254 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
255 char read_write, int command,
263 unsigned char errmask;
265 len = data->block[0];
267 if (read_write == I2C_SMBUS_WRITE) {
268 outb_p(len, SMBHSTDAT0);
269 outb_p(data->block[1], SMBBLKDAT);
272 for (i = 1; i <= len; i++) {
273 if (i == len && read_write == I2C_SMBUS_READ) {
274 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
275 smbcmd = I801_I2C_BLOCK_LAST;
277 smbcmd = I801_BLOCK_LAST;
279 if (command == I2C_SMBUS_I2C_BLOCK_DATA
280 && read_write == I2C_SMBUS_READ)
281 smbcmd = I801_I2C_BLOCK_DATA;
283 smbcmd = I801_BLOCK_DATA;
285 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
287 /* Make sure the SMBus host is ready to start transmitting */
288 temp = inb_p(SMBHSTSTS);
290 /* Erroneous conditions before transaction:
291 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
294 /* Erroneous conditions during transaction:
295 * Failed, Bus_Err, Dev_Err, Intr */
298 if (temp & errmask) {
299 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
300 "Resetting...\n", temp);
301 outb_p(temp, SMBHSTSTS);
302 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
303 dev_err(&I801_dev->dev,
304 "Reset failed! (%02x)\n", temp);
308 /* if die in middle of block transaction, fail */
313 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
315 /* We will always wait for a fraction of a second! */
319 temp = inb_p(SMBHSTSTS);
321 while ((!(temp & SMBHSTSTS_BYTE_DONE))
322 && (timeout++ < MAX_TIMEOUT));
324 /* If the SMBus is still busy, we give up */
325 if (timeout >= MAX_TIMEOUT) {
326 /* try to stop the current command */
327 dev_dbg(&I801_dev->dev, "Terminating the current "
329 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
331 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
334 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
337 if (temp & SMBHSTSTS_FAILED) {
339 dev_dbg(&I801_dev->dev,
340 "Error: Failed bus transaction\n");
341 } else if (temp & SMBHSTSTS_BUS_ERR) {
343 dev_err(&I801_dev->dev, "Bus collision!\n");
344 } else if (temp & SMBHSTSTS_DEV_ERR) {
346 dev_dbg(&I801_dev->dev, "Error: no response!\n");
349 if (i == 1 && read_write == I2C_SMBUS_READ
350 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
351 len = inb_p(SMBHSTDAT0);
352 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
354 data->block[0] = len;
357 /* Retrieve/store value in SMBBLKDAT */
358 if (read_write == I2C_SMBUS_READ)
359 data->block[i] = inb_p(SMBBLKDAT);
360 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
361 outb_p(data->block[i+1], SMBBLKDAT);
362 if ((temp & 0x9e) != 0x00)
363 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
365 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
366 dev_dbg(&I801_dev->dev,
367 "Bad status (%02x) at end of transaction\n",
377 static int i801_set_block_buffer_mode(void)
379 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
380 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
385 /* Block transaction function */
386 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
387 int command, int hwpec)
392 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
393 if (read_write == I2C_SMBUS_WRITE) {
394 /* set I2C_EN bit in configuration register */
395 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
396 pci_write_config_byte(I801_dev, SMBHSTCFG,
397 hostc | SMBHSTCFG_I2C_EN);
398 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
399 dev_err(&I801_dev->dev,
400 "I2C block read is unsupported!\n");
405 if (read_write == I2C_SMBUS_WRITE
406 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
407 if (data->block[0] < 1)
409 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
410 data->block[0] = I2C_SMBUS_BLOCK_MAX;
412 data->block[0] = 32; /* max for SMBus block reads */
415 if ((i801_features & FEATURE_BLOCK_BUFFER)
416 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
417 && read_write == I2C_SMBUS_READ)
418 && i801_set_block_buffer_mode() == 0)
419 result = i801_block_transaction_by_block(data, read_write,
422 result = i801_block_transaction_byte_by_byte(data, read_write,
425 if (result == 0 && hwpec)
428 if (command == I2C_SMBUS_I2C_BLOCK_DATA
429 && read_write == I2C_SMBUS_WRITE) {
430 /* restore saved configuration register value */
431 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
436 /* Return negative errno on error. */
437 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
438 unsigned short flags, char read_write, u8 command,
439 int size, union i2c_smbus_data * data)
445 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
446 && size != I2C_SMBUS_QUICK
447 && size != I2C_SMBUS_I2C_BLOCK_DATA;
450 case I2C_SMBUS_QUICK:
451 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
456 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
458 if (read_write == I2C_SMBUS_WRITE)
459 outb_p(command, SMBHSTCMD);
462 case I2C_SMBUS_BYTE_DATA:
463 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
465 outb_p(command, SMBHSTCMD);
466 if (read_write == I2C_SMBUS_WRITE)
467 outb_p(data->byte, SMBHSTDAT0);
468 xact = I801_BYTE_DATA;
470 case I2C_SMBUS_WORD_DATA:
471 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
473 outb_p(command, SMBHSTCMD);
474 if (read_write == I2C_SMBUS_WRITE) {
475 outb_p(data->word & 0xff, SMBHSTDAT0);
476 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
478 xact = I801_WORD_DATA;
480 case I2C_SMBUS_BLOCK_DATA:
481 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
483 outb_p(command, SMBHSTCMD);
486 case I2C_SMBUS_I2C_BLOCK_DATA:
487 /* NB: page 240 of ICH5 datasheet shows that the R/#W
488 * bit should be cleared here, even when reading */
489 outb_p((addr & 0x7f) << 1, SMBHSTADD);
490 if (read_write == I2C_SMBUS_READ) {
491 /* NB: page 240 of ICH5 datasheet also shows
492 * that DATA1 is the cmd field when reading */
493 outb_p(command, SMBHSTDAT1);
495 outb_p(command, SMBHSTCMD);
499 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
503 if (hwpec) /* enable/disable hardware PEC */
504 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
506 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
509 ret = i801_block_transaction(data, read_write, size, hwpec);
511 ret = i801_transaction(xact | ENABLE_INT9);
513 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
514 time, so we forcibly disable it after every transaction. Turn off
515 E32B for the same reason. */
517 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
524 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
527 switch (xact & 0x7f) {
528 case I801_BYTE: /* Result put in SMBHSTDAT0 */
530 data->byte = inb_p(SMBHSTDAT0);
533 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
540 static u32 i801_func(struct i2c_adapter *adapter)
542 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
543 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
544 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
545 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
546 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
547 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
550 static const struct i2c_algorithm smbus_algorithm = {
551 .smbus_xfer = i801_access,
552 .functionality = i801_func,
555 static struct i2c_adapter i801_adapter = {
556 .owner = THIS_MODULE,
557 .id = I2C_HW_SMBUS_I801,
558 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
559 .algo = &smbus_algorithm,
562 static struct pci_device_id i801_ids[] = {
563 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
564 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
565 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
566 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
567 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
568 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
569 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
570 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
571 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
572 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
573 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
574 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
575 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
576 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
577 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
581 MODULE_DEVICE_TABLE (pci, i801_ids);
583 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
590 switch (dev->device) {
591 case PCI_DEVICE_ID_INTEL_82801EB_3:
592 case PCI_DEVICE_ID_INTEL_ESB_4:
593 case PCI_DEVICE_ID_INTEL_ICH6_16:
594 case PCI_DEVICE_ID_INTEL_ICH7_17:
595 case PCI_DEVICE_ID_INTEL_ESB2_17:
596 case PCI_DEVICE_ID_INTEL_ICH8_5:
597 case PCI_DEVICE_ID_INTEL_ICH9_6:
598 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
599 case PCI_DEVICE_ID_INTEL_ICH10_4:
600 case PCI_DEVICE_ID_INTEL_ICH10_5:
601 i801_features |= FEATURE_I2C_BLOCK_READ;
603 case PCI_DEVICE_ID_INTEL_82801DB_3:
604 i801_features |= FEATURE_SMBUS_PEC;
605 i801_features |= FEATURE_BLOCK_BUFFER;
609 err = pci_enable_device(dev);
611 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
616 /* Determine the address of the SMBus area */
617 i801_smba = pci_resource_start(dev, SMBBAR);
619 dev_err(&dev->dev, "SMBus base address uninitialized, "
625 err = pci_request_region(dev, SMBBAR, i801_driver.name);
627 dev_err(&dev->dev, "Failed to request SMBus region "
628 "0x%lx-0x%Lx\n", i801_smba,
629 (unsigned long long)pci_resource_end(dev, SMBBAR));
633 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
634 i801_original_hstcfg = temp;
635 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
636 if (!(temp & SMBHSTCFG_HST_EN)) {
637 dev_info(&dev->dev, "Enabling SMBus device\n");
638 temp |= SMBHSTCFG_HST_EN;
640 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
642 if (temp & SMBHSTCFG_SMB_SMI_EN)
643 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
645 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
647 /* Clear special mode bits */
648 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
649 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
652 /* set up the sysfs linkage to our parent device */
653 i801_adapter.dev.parent = &dev->dev;
655 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
656 "SMBus I801 adapter at %04lx", i801_smba);
657 err = i2c_add_adapter(&i801_adapter);
659 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
665 pci_release_region(dev, SMBBAR);
670 static void __devexit i801_remove(struct pci_dev *dev)
672 i2c_del_adapter(&i801_adapter);
673 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
674 pci_release_region(dev, SMBBAR);
676 * do not call pci_disable_device(dev) since it can cause hard hangs on
677 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
682 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
685 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
686 pci_set_power_state(dev, pci_choose_state(dev, mesg));
690 static int i801_resume(struct pci_dev *dev)
692 pci_set_power_state(dev, PCI_D0);
693 pci_restore_state(dev);
694 return pci_enable_device(dev);
697 #define i801_suspend NULL
698 #define i801_resume NULL
701 static struct pci_driver i801_driver = {
702 .name = "i801_smbus",
703 .id_table = i801_ids,
705 .remove = __devexit_p(i801_remove),
706 .suspend = i801_suspend,
707 .resume = i801_resume,
710 static int __init i2c_i801_init(void)
712 return pci_register_driver(&i801_driver);
715 static void __exit i2c_i801_exit(void)
717 pci_unregister_driver(&i801_driver);
720 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
721 "Jean Delvare <khali@linux-fr.org>");
722 MODULE_DESCRIPTION("I801 SMBus driver");
723 MODULE_LICENSE("GPL");
725 module_init(i2c_i801_init);
726 module_exit(i2c_i801_exit);