2 i2c-i801.c - Part of lm_sensors, Linux kernel modules for hardware
4 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
5 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
7 Copyright (C) 2007 Jean Delvare <khali@linux-fr.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 Tolapai 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
47 Features supported by this driver:
51 Block process call transaction no
52 I2C block read transaction yes (doesn't use the block buffer)
54 See the file Documentation/i2c/busses/i2c-i801 for details.
57 /* Note: we assume there can only be one I801, with one SMBus interface */
59 #include <linux/module.h>
60 #include <linux/pci.h>
61 #include <linux/kernel.h>
62 #include <linux/stddef.h>
63 #include <linux/delay.h>
64 #include <linux/ioport.h>
65 #include <linux/init.h>
66 #include <linux/i2c.h>
69 /* I801 SMBus address offsets */
70 #define SMBHSTSTS (0 + i801_smba)
71 #define SMBHSTCNT (2 + i801_smba)
72 #define SMBHSTCMD (3 + i801_smba)
73 #define SMBHSTADD (4 + i801_smba)
74 #define SMBHSTDAT0 (5 + i801_smba)
75 #define SMBHSTDAT1 (6 + i801_smba)
76 #define SMBBLKDAT (7 + i801_smba)
77 #define SMBPEC (8 + i801_smba) /* ICH3 and later */
78 #define SMBAUXSTS (12 + i801_smba) /* ICH4 and later */
79 #define SMBAUXCTL (13 + i801_smba) /* ICH4 and later */
81 /* PCI Address Constants */
83 #define SMBHSTCFG 0x040
85 /* Host configuration bits for SMBHSTCFG */
86 #define SMBHSTCFG_HST_EN 1
87 #define SMBHSTCFG_SMB_SMI_EN 2
88 #define SMBHSTCFG_I2C_EN 4
90 /* Auxillary control register bits, ICH4+ only */
91 #define SMBAUXCTL_CRC 1
92 #define SMBAUXCTL_E32B 2
94 /* kill bit for SMBHSTCNT */
95 #define SMBHSTCNT_KILL 2
98 #define MAX_TIMEOUT 100
99 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
101 /* I801 command constants */
102 #define I801_QUICK 0x00
103 #define I801_BYTE 0x04
104 #define I801_BYTE_DATA 0x08
105 #define I801_WORD_DATA 0x0C
106 #define I801_PROC_CALL 0x10 /* unimplemented */
107 #define I801_BLOCK_DATA 0x14
108 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
109 #define I801_BLOCK_LAST 0x34
110 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
111 #define I801_START 0x40
112 #define I801_PEC_EN 0x80 /* ICH3 and later */
114 /* I801 Hosts Status register bits */
115 #define SMBHSTSTS_BYTE_DONE 0x80
116 #define SMBHSTSTS_INUSE_STS 0x40
117 #define SMBHSTSTS_SMBALERT_STS 0x20
118 #define SMBHSTSTS_FAILED 0x10
119 #define SMBHSTSTS_BUS_ERR 0x08
120 #define SMBHSTSTS_DEV_ERR 0x04
121 #define SMBHSTSTS_INTR 0x02
122 #define SMBHSTSTS_HOST_BUSY 0x01
124 static unsigned long i801_smba;
125 static unsigned char i801_original_hstcfg;
126 static struct pci_driver i801_driver;
127 static struct pci_dev *I801_dev;
129 #define FEATURE_SMBUS_PEC (1 << 0)
130 #define FEATURE_BLOCK_BUFFER (1 << 1)
131 #define FEATURE_BLOCK_PROC (1 << 2)
132 #define FEATURE_I2C_BLOCK_READ (1 << 3)
133 static unsigned int i801_features;
135 static int i801_transaction(int xact)
141 dev_dbg(&I801_dev->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
142 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
143 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
146 /* Make sure the SMBus host is ready to start transmitting */
147 /* 0x1f = Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
148 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
149 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). Resetting...\n",
151 outb_p(temp, SMBHSTSTS);
152 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
153 dev_dbg(&I801_dev->dev, "Failed! (%02x)\n", temp);
156 dev_dbg(&I801_dev->dev, "Successful!\n");
160 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
161 * INTREN, SMBSCMD are passed in xact */
162 outb_p(xact | I801_START, SMBHSTCNT);
164 /* We will always wait for a fraction of a second! */
167 temp = inb_p(SMBHSTSTS);
168 } while ((temp & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
170 /* If the SMBus is still busy, we give up */
171 if (timeout >= MAX_TIMEOUT) {
172 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
174 /* try to stop the current command */
175 dev_dbg(&I801_dev->dev, "Terminating the current operation\n");
176 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
178 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL), SMBHSTCNT);
181 if (temp & SMBHSTSTS_FAILED) {
183 dev_dbg(&I801_dev->dev, "Error: Failed bus transaction\n");
186 if (temp & SMBHSTSTS_BUS_ERR) {
188 dev_err(&I801_dev->dev, "Bus collision! SMBus may be locked "
189 "until next hard reset. (sorry!)\n");
190 /* Clock stops and slave is stuck in mid-transmission */
193 if (temp & SMBHSTSTS_DEV_ERR) {
195 dev_dbg(&I801_dev->dev, "Error: no response!\n");
198 if ((inb_p(SMBHSTSTS) & 0x1f) != 0x00)
199 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
201 if ((temp = (0x1f & inb_p(SMBHSTSTS))) != 0x00) {
202 dev_dbg(&I801_dev->dev, "Failed reset at end of transaction "
205 dev_dbg(&I801_dev->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
206 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
207 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
212 /* wait for INTR bit as advised by Intel */
213 static void i801_wait_hwpec(void)
220 temp = inb_p(SMBHSTSTS);
221 } while ((!(temp & SMBHSTSTS_INTR))
222 && (timeout++ < MAX_TIMEOUT));
224 if (timeout >= MAX_TIMEOUT) {
225 dev_dbg(&I801_dev->dev, "PEC Timeout!\n");
227 outb_p(temp, SMBHSTSTS);
230 static int i801_block_transaction_by_block(union i2c_smbus_data *data,
231 char read_write, int hwpec)
236 inb_p(SMBHSTCNT); /* reset the data buffer index */
238 /* Use 32-byte buffer to process this transaction */
239 if (read_write == I2C_SMBUS_WRITE) {
240 len = data->block[0];
241 outb_p(len, SMBHSTDAT0);
242 for (i = 0; i < len; i++)
243 outb_p(data->block[i+1], SMBBLKDAT);
246 status = i801_transaction(I801_BLOCK_DATA | ENABLE_INT9 |
247 I801_PEC_EN * hwpec);
251 if (read_write == I2C_SMBUS_READ) {
252 len = inb_p(SMBHSTDAT0);
253 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
256 data->block[0] = len;
257 for (i = 0; i < len; i++)
258 data->block[i + 1] = inb_p(SMBBLKDAT);
263 static int i801_block_transaction_byte_by_byte(union i2c_smbus_data *data,
264 char read_write, int command,
272 unsigned char errmask;
274 len = data->block[0];
276 if (read_write == I2C_SMBUS_WRITE) {
277 outb_p(len, SMBHSTDAT0);
278 outb_p(data->block[1], SMBBLKDAT);
281 for (i = 1; i <= len; i++) {
282 if (i == len && read_write == I2C_SMBUS_READ) {
283 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
284 smbcmd = I801_I2C_BLOCK_LAST;
286 smbcmd = I801_BLOCK_LAST;
288 if (command == I2C_SMBUS_I2C_BLOCK_DATA
289 && read_write == I2C_SMBUS_READ)
290 smbcmd = I801_I2C_BLOCK_DATA;
292 smbcmd = I801_BLOCK_DATA;
294 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT);
296 dev_dbg(&I801_dev->dev, "Block (pre %d): CNT=%02x, CMD=%02x, "
297 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
298 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
299 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
301 /* Make sure the SMBus host is ready to start transmitting */
302 temp = inb_p(SMBHSTSTS);
304 /* Erroneous conditions before transaction:
305 * Byte_Done, Failed, Bus_Err, Dev_Err, Intr, Host_Busy */
308 /* Erroneous conditions during transaction:
309 * Failed, Bus_Err, Dev_Err, Intr */
312 if (temp & errmask) {
313 dev_dbg(&I801_dev->dev, "SMBus busy (%02x). "
314 "Resetting...\n", temp);
315 outb_p(temp, SMBHSTSTS);
316 if (((temp = inb_p(SMBHSTSTS)) & errmask) != 0x00) {
317 dev_err(&I801_dev->dev,
318 "Reset failed! (%02x)\n", temp);
322 /* if die in middle of block transaction, fail */
327 outb_p(inb(SMBHSTCNT) | I801_START, SMBHSTCNT);
329 /* We will always wait for a fraction of a second! */
333 temp = inb_p(SMBHSTSTS);
335 while ((!(temp & SMBHSTSTS_BYTE_DONE))
336 && (timeout++ < MAX_TIMEOUT));
338 /* If the SMBus is still busy, we give up */
339 if (timeout >= MAX_TIMEOUT) {
340 /* try to stop the current command */
341 dev_dbg(&I801_dev->dev, "Terminating the current "
343 outb_p(inb_p(SMBHSTCNT) | SMBHSTCNT_KILL, SMBHSTCNT);
345 outb_p(inb_p(SMBHSTCNT) & (~SMBHSTCNT_KILL),
348 dev_dbg(&I801_dev->dev, "SMBus Timeout!\n");
351 if (temp & SMBHSTSTS_FAILED) {
353 dev_dbg(&I801_dev->dev,
354 "Error: Failed bus transaction\n");
355 } else if (temp & SMBHSTSTS_BUS_ERR) {
357 dev_err(&I801_dev->dev, "Bus collision!\n");
358 } else if (temp & SMBHSTSTS_DEV_ERR) {
360 dev_dbg(&I801_dev->dev, "Error: no response!\n");
363 if (i == 1 && read_write == I2C_SMBUS_READ
364 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
365 len = inb_p(SMBHSTDAT0);
366 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
368 data->block[0] = len;
371 /* Retrieve/store value in SMBBLKDAT */
372 if (read_write == I2C_SMBUS_READ)
373 data->block[i] = inb_p(SMBBLKDAT);
374 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
375 outb_p(data->block[i+1], SMBBLKDAT);
376 if ((temp & 0x9e) != 0x00)
377 outb_p(temp, SMBHSTSTS); /* signals SMBBLKDAT ready */
379 if ((temp = (0x1e & inb_p(SMBHSTSTS))) != 0x00) {
380 dev_dbg(&I801_dev->dev,
381 "Bad status (%02x) at end of transaction\n",
384 dev_dbg(&I801_dev->dev, "Block (post %d): CNT=%02x, CMD=%02x, "
385 "ADD=%02x, DAT0=%02x, DAT1=%02x, BLKDAT=%02x\n", i,
386 inb_p(SMBHSTCNT), inb_p(SMBHSTCMD), inb_p(SMBHSTADD),
387 inb_p(SMBHSTDAT0), inb_p(SMBHSTDAT1), inb_p(SMBBLKDAT));
395 static int i801_set_block_buffer_mode(void)
397 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_E32B, SMBAUXCTL);
398 if ((inb_p(SMBAUXCTL) & SMBAUXCTL_E32B) == 0)
403 /* Block transaction function */
404 static int i801_block_transaction(union i2c_smbus_data *data, char read_write,
405 int command, int hwpec)
410 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
411 if (read_write == I2C_SMBUS_WRITE) {
412 /* set I2C_EN bit in configuration register */
413 pci_read_config_byte(I801_dev, SMBHSTCFG, &hostc);
414 pci_write_config_byte(I801_dev, SMBHSTCFG,
415 hostc | SMBHSTCFG_I2C_EN);
416 } else if (!(i801_features & FEATURE_I2C_BLOCK_READ)) {
417 dev_err(&I801_dev->dev,
418 "I2C block read is unsupported!\n");
423 if (read_write == I2C_SMBUS_WRITE
424 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
425 if (data->block[0] < 1)
427 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
428 data->block[0] = I2C_SMBUS_BLOCK_MAX;
430 data->block[0] = 32; /* max for SMBus block reads */
433 if ((i801_features & FEATURE_BLOCK_BUFFER)
434 && !(command == I2C_SMBUS_I2C_BLOCK_DATA
435 && read_write == I2C_SMBUS_READ)
436 && i801_set_block_buffer_mode() == 0)
437 result = i801_block_transaction_by_block(data, read_write,
440 result = i801_block_transaction_byte_by_byte(data, read_write,
443 if (result == 0 && hwpec)
446 if (command == I2C_SMBUS_I2C_BLOCK_DATA
447 && read_write == I2C_SMBUS_WRITE) {
448 /* restore saved configuration register value */
449 pci_write_config_byte(I801_dev, SMBHSTCFG, hostc);
454 /* Return negative errno on error. */
455 static s32 i801_access(struct i2c_adapter * adap, u16 addr,
456 unsigned short flags, char read_write, u8 command,
457 int size, union i2c_smbus_data * data)
463 hwpec = (i801_features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
464 && size != I2C_SMBUS_QUICK
465 && size != I2C_SMBUS_I2C_BLOCK_DATA;
468 case I2C_SMBUS_QUICK:
469 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
474 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
476 if (read_write == I2C_SMBUS_WRITE)
477 outb_p(command, SMBHSTCMD);
480 case I2C_SMBUS_BYTE_DATA:
481 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
483 outb_p(command, SMBHSTCMD);
484 if (read_write == I2C_SMBUS_WRITE)
485 outb_p(data->byte, SMBHSTDAT0);
486 xact = I801_BYTE_DATA;
488 case I2C_SMBUS_WORD_DATA:
489 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
491 outb_p(command, SMBHSTCMD);
492 if (read_write == I2C_SMBUS_WRITE) {
493 outb_p(data->word & 0xff, SMBHSTDAT0);
494 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
496 xact = I801_WORD_DATA;
498 case I2C_SMBUS_BLOCK_DATA:
499 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
501 outb_p(command, SMBHSTCMD);
504 case I2C_SMBUS_I2C_BLOCK_DATA:
505 /* NB: page 240 of ICH5 datasheet shows that the R/#W
506 * bit should be cleared here, even when reading */
507 outb_p((addr & 0x7f) << 1, SMBHSTADD);
508 if (read_write == I2C_SMBUS_READ) {
509 /* NB: page 240 of ICH5 datasheet also shows
510 * that DATA1 is the cmd field when reading */
511 outb_p(command, SMBHSTDAT1);
513 outb_p(command, SMBHSTCMD);
517 dev_err(&I801_dev->dev, "Unsupported transaction %d\n", size);
521 if (hwpec) /* enable/disable hardware PEC */
522 outb_p(inb_p(SMBAUXCTL) | SMBAUXCTL_CRC, SMBAUXCTL);
524 outb_p(inb_p(SMBAUXCTL) & (~SMBAUXCTL_CRC), SMBAUXCTL);
527 ret = i801_block_transaction(data, read_write, size, hwpec);
529 ret = i801_transaction(xact | ENABLE_INT9);
531 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
532 time, so we forcibly disable it after every transaction. Turn off
533 E32B for the same reason. */
535 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
542 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
545 switch (xact & 0x7f) {
546 case I801_BYTE: /* Result put in SMBHSTDAT0 */
548 data->byte = inb_p(SMBHSTDAT0);
551 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
558 static u32 i801_func(struct i2c_adapter *adapter)
560 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
561 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
562 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
563 ((i801_features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
564 ((i801_features & FEATURE_I2C_BLOCK_READ) ?
565 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
568 static const struct i2c_algorithm smbus_algorithm = {
569 .smbus_xfer = i801_access,
570 .functionality = i801_func,
573 static struct i2c_adapter i801_adapter = {
574 .owner = THIS_MODULE,
575 .id = I2C_HW_SMBUS_I801,
576 .class = I2C_CLASS_HWMON | I2C_CLASS_SPD,
577 .algo = &smbus_algorithm,
580 static struct pci_device_id i801_ids[] = {
581 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
582 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
583 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
584 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
585 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
586 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
587 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
588 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
589 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
590 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
591 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
592 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
593 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TOLAPAI_1) },
594 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
595 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
599 MODULE_DEVICE_TABLE (pci, i801_ids);
601 static int __devinit i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
608 switch (dev->device) {
609 case PCI_DEVICE_ID_INTEL_82801EB_3:
610 case PCI_DEVICE_ID_INTEL_ESB_4:
611 case PCI_DEVICE_ID_INTEL_ICH6_16:
612 case PCI_DEVICE_ID_INTEL_ICH7_17:
613 case PCI_DEVICE_ID_INTEL_ESB2_17:
614 case PCI_DEVICE_ID_INTEL_ICH8_5:
615 case PCI_DEVICE_ID_INTEL_ICH9_6:
616 case PCI_DEVICE_ID_INTEL_TOLAPAI_1:
617 case PCI_DEVICE_ID_INTEL_ICH10_4:
618 case PCI_DEVICE_ID_INTEL_ICH10_5:
619 i801_features |= FEATURE_I2C_BLOCK_READ;
621 case PCI_DEVICE_ID_INTEL_82801DB_3:
622 i801_features |= FEATURE_SMBUS_PEC;
623 i801_features |= FEATURE_BLOCK_BUFFER;
627 err = pci_enable_device(dev);
629 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
634 /* Determine the address of the SMBus area */
635 i801_smba = pci_resource_start(dev, SMBBAR);
637 dev_err(&dev->dev, "SMBus base address uninitialized, "
643 err = pci_request_region(dev, SMBBAR, i801_driver.name);
645 dev_err(&dev->dev, "Failed to request SMBus region "
646 "0x%lx-0x%Lx\n", i801_smba,
647 (unsigned long long)pci_resource_end(dev, SMBBAR));
651 pci_read_config_byte(I801_dev, SMBHSTCFG, &temp);
652 i801_original_hstcfg = temp;
653 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
654 if (!(temp & SMBHSTCFG_HST_EN)) {
655 dev_info(&dev->dev, "Enabling SMBus device\n");
656 temp |= SMBHSTCFG_HST_EN;
658 pci_write_config_byte(I801_dev, SMBHSTCFG, temp);
660 if (temp & SMBHSTCFG_SMB_SMI_EN)
661 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
663 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
665 /* Clear special mode bits */
666 if (i801_features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
667 outb_p(inb_p(SMBAUXCTL) & ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B),
670 /* set up the sysfs linkage to our parent device */
671 i801_adapter.dev.parent = &dev->dev;
673 snprintf(i801_adapter.name, sizeof(i801_adapter.name),
674 "SMBus I801 adapter at %04lx", i801_smba);
675 err = i2c_add_adapter(&i801_adapter);
677 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
683 pci_release_region(dev, SMBBAR);
688 static void __devexit i801_remove(struct pci_dev *dev)
690 i2c_del_adapter(&i801_adapter);
691 pci_write_config_byte(I801_dev, SMBHSTCFG, i801_original_hstcfg);
692 pci_release_region(dev, SMBBAR);
694 * do not call pci_disable_device(dev) since it can cause hard hangs on
695 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
700 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
703 pci_write_config_byte(dev, SMBHSTCFG, i801_original_hstcfg);
704 pci_set_power_state(dev, pci_choose_state(dev, mesg));
708 static int i801_resume(struct pci_dev *dev)
710 pci_set_power_state(dev, PCI_D0);
711 pci_restore_state(dev);
712 return pci_enable_device(dev);
715 #define i801_suspend NULL
716 #define i801_resume NULL
719 static struct pci_driver i801_driver = {
720 .name = "i801_smbus",
721 .id_table = i801_ids,
723 .remove = __devexit_p(i801_remove),
724 .suspend = i801_suspend,
725 .resume = i801_resume,
728 static int __init i2c_i801_init(void)
730 return pci_register_driver(&i801_driver);
733 static void __exit i2c_i801_exit(void)
735 pci_unregister_driver(&i801_driver);
738 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
739 "Jean Delvare <khali@linux-fr.org>");
740 MODULE_DESCRIPTION("I801 SMBus driver");
741 MODULE_LICENSE("GPL");
743 module_init(i2c_i801_init);
744 module_exit(i2c_i801_exit);