1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
38 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
40 drm_radeon_private_t *dev_priv = dev->dev_private;
43 dev_priv->irq_enable_reg |= mask;
45 dev_priv->irq_enable_reg &= ~mask;
47 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
50 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
52 drm_radeon_private_t *dev_priv = dev->dev_private;
55 dev_priv->r500_disp_irq_reg |= mask;
57 dev_priv->r500_disp_irq_reg &= ~mask;
59 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
62 int radeon_enable_vblank(struct drm_device *dev, int crtc)
64 drm_radeon_private_t *dev_priv = dev->dev_private;
66 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
69 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
72 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
75 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
82 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
85 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
88 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
97 void radeon_disable_vblank(struct drm_device *dev, int crtc)
99 drm_radeon_private_t *dev_priv = dev->dev_private;
101 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
104 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
107 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
110 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
117 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
120 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
123 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
130 static inline u32 radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv, u32 *r500_disp_int)
132 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
133 u32 irq_mask = RADEON_SW_INT_TEST;
136 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
137 /* vbl interrupts in a different place */
139 if (irqs & R500_DISPLAY_INT_STATUS) {
140 /* if a display interrupt */
143 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
145 *r500_disp_int = disp_irq;
146 if (disp_irq & R500_D1_VBLANK_INTERRUPT)
147 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
148 if (disp_irq & R500_D2_VBLANK_INTERRUPT)
149 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
151 irq_mask |= R500_DISPLAY_INT_STATUS;
153 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
158 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
163 /* Interrupts - Used for device synchronization and flushing in the
164 * following circumstances:
166 * - Exclusive FB access with hw idle:
167 * - Wait for GUI Idle (?) interrupt, then do normal flush.
169 * - Frame throttling, NV_fence:
170 * - Drop marker irq's into command stream ahead of time.
171 * - Wait on irq's with lock *not held*
172 * - Check each for termination condition
174 * - Internally in cp_getbuffer, etc:
175 * - as above, but wait with lock held???
177 * NOTE: These functions are misleadingly named -- the irq's aren't
178 * tied to dma at all, this is just a hangover from dri prehistory.
181 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
183 struct drm_device *dev = (struct drm_device *) arg;
184 drm_radeon_private_t *dev_priv =
185 (drm_radeon_private_t *) dev->dev_private;
189 /* Only consider the bits we're interested in - others could be used
192 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
196 stat &= dev_priv->irq_enable_reg;
199 if (stat & RADEON_SW_INT_TEST)
200 DRM_WAKEUP(&dev_priv->swi_queue);
202 /* VBLANK interrupt */
203 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
204 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
205 drm_handle_vblank(dev, 0);
206 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
207 drm_handle_vblank(dev, 1);
209 if (stat & RADEON_CRTC_VBLANK_STAT)
210 drm_handle_vblank(dev, 0);
211 if (stat & RADEON_CRTC2_VBLANK_STAT)
212 drm_handle_vblank(dev, 1);
217 static int radeon_emit_irq(struct drm_device * dev)
219 drm_radeon_private_t *dev_priv = dev->dev_private;
223 atomic_inc(&dev_priv->swi_emitted);
224 ret = atomic_read(&dev_priv->swi_emitted);
227 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
228 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
235 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
237 drm_radeon_private_t *dev_priv =
238 (drm_radeon_private_t *) dev->dev_private;
241 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
244 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
246 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
247 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
252 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
254 drm_radeon_private_t *dev_priv = dev->dev_private;
257 DRM_ERROR("called with no initialization\n");
261 if (crtc < 0 || crtc > 1) {
262 DRM_ERROR("Invalid crtc %d\n", crtc);
266 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
268 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
270 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
273 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
275 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
279 /* Needs the lock as it touches the ring.
281 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
283 drm_radeon_private_t *dev_priv = dev->dev_private;
284 drm_radeon_irq_emit_t *emit = data;
287 LOCK_TEST_WITH_RETURN(dev, file_priv);
290 DRM_ERROR("called with no initialization\n");
294 result = radeon_emit_irq(dev);
296 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
297 DRM_ERROR("copy_to_user\n");
304 /* Doesn't need the hardware lock.
306 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
308 drm_radeon_private_t *dev_priv = dev->dev_private;
309 drm_radeon_irq_wait_t *irqwait = data;
312 DRM_ERROR("called with no initialization\n");
316 return radeon_wait_irq(dev, irqwait->irq_seq);
321 void radeon_driver_irq_preinstall(struct drm_device * dev)
323 drm_radeon_private_t *dev_priv =
324 (drm_radeon_private_t *) dev->dev_private;
327 /* Disable *all* interrupts */
328 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
329 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
330 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
332 /* Clear bits if they're already high */
333 radeon_acknowledge_irqs(dev_priv, &dummy);
336 int radeon_driver_irq_postinstall(struct drm_device *dev)
338 drm_radeon_private_t *dev_priv =
339 (drm_radeon_private_t *) dev->dev_private;
342 atomic_set(&dev_priv->swi_emitted, 0);
343 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
345 ret = drm_vblank_init(dev, 2);
349 dev->max_vblank_count = 0x001fffff;
351 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
356 void radeon_driver_irq_uninstall(struct drm_device * dev)
358 drm_radeon_private_t *dev_priv =
359 (drm_radeon_private_t *) dev->dev_private;
363 dev_priv->irq_enabled = 0;
365 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690)
366 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
367 /* Disable *all* interrupts */
368 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
372 int radeon_vblank_crtc_get(struct drm_device *dev)
374 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
376 return dev_priv->vblank_crtc;
379 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
381 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
382 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
383 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
386 dev_priv->vblank_crtc = (unsigned int)value;