1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define MAX_NOPID ((u32)~0)
36 /** These are the interrupts used by the driver */
37 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
38 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT | \
39 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
42 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
44 if ((dev_priv->irq_mask_reg & mask) != 0) {
45 dev_priv->irq_mask_reg &= ~mask;
46 I915_WRITE(IMR, dev_priv->irq_mask_reg);
47 (void) I915_READ(IMR);
52 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
54 if ((dev_priv->irq_mask_reg & mask) != mask) {
55 dev_priv->irq_mask_reg |= mask;
56 I915_WRITE(IMR, dev_priv->irq_mask_reg);
57 (void) I915_READ(IMR);
62 * Emit blits for scheduled buffer swaps.
64 * This function will be called with the HW lock held.
66 static void i915_vblank_tasklet(struct drm_device *dev)
68 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
69 unsigned long irqflags;
70 struct list_head *list, *tmp, hits, *hit;
71 int nhits, nrects, slice[2], upper[2], lower[2], i;
72 unsigned counter[2] = { atomic_read(&dev->vbl_received),
73 atomic_read(&dev->vbl_received2) };
74 struct drm_drawable_info *drw;
75 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
76 u32 cpp = dev_priv->cpp;
77 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
78 XY_SRC_COPY_BLT_WRITE_ALPHA |
79 XY_SRC_COPY_BLT_WRITE_RGB)
80 : XY_SRC_COPY_BLT_CMD;
81 u32 src_pitch = sarea_priv->pitch * cpp;
82 u32 dst_pitch = sarea_priv->pitch * cpp;
83 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
86 if (IS_I965G(dev) && sarea_priv->front_tiled) {
87 cmd |= XY_SRC_COPY_BLT_DST_TILED;
90 if (IS_I965G(dev) && sarea_priv->back_tiled) {
91 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
97 INIT_LIST_HEAD(&hits);
101 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
103 /* Find buffer swaps scheduled for this vertical blank */
104 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
105 drm_i915_vbl_swap_t *vbl_swap =
106 list_entry(list, drm_i915_vbl_swap_t, head);
108 if ((counter[vbl_swap->pipe] - vbl_swap->sequence) > (1<<23))
112 dev_priv->swaps_pending--;
114 spin_unlock(&dev_priv->swaps_lock);
115 spin_lock(&dev->drw_lock);
117 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
120 spin_unlock(&dev->drw_lock);
121 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
122 spin_lock(&dev_priv->swaps_lock);
126 list_for_each(hit, &hits) {
127 drm_i915_vbl_swap_t *swap_cmp =
128 list_entry(hit, drm_i915_vbl_swap_t, head);
129 struct drm_drawable_info *drw_cmp =
130 drm_get_drawable_info(dev, swap_cmp->drw_id);
133 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
134 list_add_tail(list, hit);
139 spin_unlock(&dev->drw_lock);
141 /* List of hits was empty, or we reached the end of it */
143 list_add_tail(list, hits.prev);
147 spin_lock(&dev_priv->swaps_lock);
151 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
155 spin_unlock(&dev_priv->swaps_lock);
157 i915_kernel_lost_context(dev);
162 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
164 OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
170 OUT_RING(GFX_OP_DRAWRECT_INFO);
173 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
174 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
180 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
182 upper[0] = upper[1] = 0;
183 slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
184 slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
185 lower[0] = sarea_priv->pipeA_y + slice[0];
186 lower[1] = sarea_priv->pipeB_y + slice[0];
188 spin_lock(&dev->drw_lock);
190 /* Emit blits for buffer swaps, partitioning both outputs into as many
191 * slices as there are buffer swaps scheduled in order to avoid tearing
192 * (based on the assumption that a single buffer swap would always
193 * complete before scanout starts).
195 for (i = 0; i++ < nhits;
196 upper[0] = lower[0], lower[0] += slice[0],
197 upper[1] = lower[1], lower[1] += slice[1]) {
199 lower[0] = lower[1] = sarea_priv->height;
201 list_for_each(hit, &hits) {
202 drm_i915_vbl_swap_t *swap_hit =
203 list_entry(hit, drm_i915_vbl_swap_t, head);
204 struct drm_clip_rect *rect;
206 unsigned short top, bottom;
208 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
214 pipe = swap_hit->pipe;
216 bottom = lower[pipe];
218 for (num_rects = drw->num_rects; num_rects--; rect++) {
219 int y1 = max(rect->y1, top);
220 int y2 = min(rect->y2, bottom);
228 OUT_RING(ropcpp | dst_pitch);
229 OUT_RING((y1 << 16) | rect->x1);
230 OUT_RING((y2 << 16) | rect->x2);
231 OUT_RING(sarea_priv->front_offset);
232 OUT_RING((y1 << 16) | rect->x1);
234 OUT_RING(sarea_priv->back_offset);
241 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
243 list_for_each_safe(hit, tmp, &hits) {
244 drm_i915_vbl_swap_t *swap_hit =
245 list_entry(hit, drm_i915_vbl_swap_t, head);
249 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
253 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
255 struct drm_device *dev = (struct drm_device *) arg;
256 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
257 u32 pipea_stats, pipeb_stats;
260 pipea_stats = I915_READ(PIPEASTAT);
261 pipeb_stats = I915_READ(PIPEBSTAT);
263 if (dev->pdev->msi_enabled)
265 iir = I915_READ(IIR);
267 DRM_DEBUG("iir=%08x\n", iir);
270 if (dev->pdev->msi_enabled) {
271 I915_WRITE(IMR, dev_priv->irq_mask_reg);
272 (void) I915_READ(IMR);
277 I915_WRITE(IIR, iir);
278 if (dev->pdev->msi_enabled)
279 I915_WRITE(IMR, dev_priv->irq_mask_reg);
280 (void) I915_READ(IIR); /* Flush posted writes */
282 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
284 if (iir & I915_USER_INTERRUPT)
285 DRM_WAKEUP(&dev_priv->irq_queue);
287 if (iir & (I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
288 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)) {
289 int vblank_pipe = dev_priv->vblank_pipe;
292 (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B))
293 == (DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B)) {
294 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
295 atomic_inc(&dev->vbl_received);
296 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
297 atomic_inc(&dev->vbl_received2);
298 } else if (((iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) &&
299 (vblank_pipe & DRM_I915_VBLANK_PIPE_A)) ||
300 ((iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) &&
301 (vblank_pipe & DRM_I915_VBLANK_PIPE_B)))
302 atomic_inc(&dev->vbl_received);
304 DRM_WAKEUP(&dev->vbl_queue);
305 drm_vbl_send_signals(dev);
307 if (dev_priv->swaps_pending > 0)
308 drm_locked_tasklet(dev, i915_vblank_tasklet);
309 I915_WRITE(PIPEASTAT,
310 pipea_stats|I915_VBLANK_INTERRUPT_ENABLE|
311 PIPE_VBLANK_INTERRUPT_STATUS);
312 I915_WRITE(PIPEBSTAT,
313 pipeb_stats|I915_VBLANK_INTERRUPT_ENABLE|
314 PIPE_VBLANK_INTERRUPT_STATUS);
320 static int i915_emit_irq(struct drm_device * dev)
322 drm_i915_private_t *dev_priv = dev->dev_private;
325 i915_kernel_lost_context(dev);
329 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
331 if (dev_priv->counter > 0x7FFFFFFFUL)
332 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
335 OUT_RING(MI_STORE_DWORD_INDEX);
336 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
337 OUT_RING(dev_priv->counter);
340 OUT_RING(MI_USER_INTERRUPT);
343 return dev_priv->counter;
346 static void i915_user_irq_get(struct drm_device *dev)
348 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
350 spin_lock(&dev_priv->user_irq_lock);
351 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
352 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
353 spin_unlock(&dev_priv->user_irq_lock);
356 static void i915_user_irq_put(struct drm_device *dev)
358 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
360 spin_lock(&dev_priv->user_irq_lock);
361 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
362 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
363 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
364 spin_unlock(&dev_priv->user_irq_lock);
367 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
369 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
372 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
373 READ_BREADCRUMB(dev_priv));
375 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
376 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
380 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
382 i915_user_irq_get(dev);
383 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
384 READ_BREADCRUMB(dev_priv) >= irq_nr);
385 i915_user_irq_put(dev);
388 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
389 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
392 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
396 static int i915_driver_vblank_do_wait(struct drm_device *dev, unsigned int *sequence,
399 drm_i915_private_t *dev_priv = dev->dev_private;
400 unsigned int cur_vblank;
404 DRM_ERROR("called with no initialization\n");
408 DRM_WAIT_ON(ret, dev->vbl_queue, 3 * DRM_HZ,
409 (((cur_vblank = atomic_read(counter))
410 - *sequence) <= (1<<23)));
412 *sequence = cur_vblank;
418 int i915_driver_vblank_wait(struct drm_device *dev, unsigned int *sequence)
420 return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received);
423 int i915_driver_vblank_wait2(struct drm_device *dev, unsigned int *sequence)
425 return i915_driver_vblank_do_wait(dev, sequence, &dev->vbl_received2);
428 /* Needs the lock as it touches the ring.
430 int i915_irq_emit(struct drm_device *dev, void *data,
431 struct drm_file *file_priv)
433 drm_i915_private_t *dev_priv = dev->dev_private;
434 drm_i915_irq_emit_t *emit = data;
437 LOCK_TEST_WITH_RETURN(dev, file_priv);
440 DRM_ERROR("called with no initialization\n");
444 result = i915_emit_irq(dev);
446 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
447 DRM_ERROR("copy_to_user\n");
454 /* Doesn't need the hardware lock.
456 int i915_irq_wait(struct drm_device *dev, void *data,
457 struct drm_file *file_priv)
459 drm_i915_private_t *dev_priv = dev->dev_private;
460 drm_i915_irq_wait_t *irqwait = data;
463 DRM_ERROR("called with no initialization\n");
467 return i915_wait_irq(dev, irqwait->irq_seq);
470 /* Set the vblank monitor pipe
472 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
473 struct drm_file *file_priv)
475 drm_i915_private_t *dev_priv = dev->dev_private;
476 drm_i915_vblank_pipe_t *pipe = data;
477 u32 enable_mask = 0, disable_mask = 0;
480 DRM_ERROR("called with no initialization\n");
484 if (pipe->pipe & ~(DRM_I915_VBLANK_PIPE_A|DRM_I915_VBLANK_PIPE_B)) {
485 DRM_ERROR("called with invalid pipe 0x%x\n", pipe->pipe);
489 if (pipe->pipe & DRM_I915_VBLANK_PIPE_A)
490 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
492 disable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
494 if (pipe->pipe & DRM_I915_VBLANK_PIPE_B)
495 enable_mask |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
497 disable_mask |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
499 i915_enable_irq(dev_priv, enable_mask);
500 i915_disable_irq(dev_priv, disable_mask);
502 dev_priv->vblank_pipe = pipe->pipe;
507 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
508 struct drm_file *file_priv)
510 drm_i915_private_t *dev_priv = dev->dev_private;
511 drm_i915_vblank_pipe_t *pipe = data;
515 DRM_ERROR("called with no initialization\n");
519 flag = I915_READ(IMR);
521 if (flag & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT)
522 pipe->pipe |= DRM_I915_VBLANK_PIPE_A;
523 if (flag & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT)
524 pipe->pipe |= DRM_I915_VBLANK_PIPE_B;
530 * Schedule buffer swap at given vertical blank.
532 int i915_vblank_swap(struct drm_device *dev, void *data,
533 struct drm_file *file_priv)
535 drm_i915_private_t *dev_priv = dev->dev_private;
536 drm_i915_vblank_swap_t *swap = data;
537 drm_i915_vbl_swap_t *vbl_swap;
538 unsigned int pipe, seqtype, curseq;
539 unsigned long irqflags;
540 struct list_head *list;
543 DRM_ERROR("%s called with no initialization\n", __func__);
547 if (dev_priv->sarea_priv->rotation) {
548 DRM_DEBUG("Rotation not supported\n");
552 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
553 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
554 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
558 pipe = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
560 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
562 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
563 DRM_ERROR("Invalid pipe %d\n", pipe);
567 spin_lock_irqsave(&dev->drw_lock, irqflags);
569 if (!drm_get_drawable_info(dev, swap->drawable)) {
570 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
571 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
575 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
577 curseq = atomic_read(pipe ? &dev->vbl_received2 : &dev->vbl_received);
579 if (seqtype == _DRM_VBLANK_RELATIVE)
580 swap->sequence += curseq;
582 if ((curseq - swap->sequence) <= (1<<23)) {
583 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
584 swap->sequence = curseq + 1;
586 DRM_DEBUG("Missed target sequence\n");
591 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
593 list_for_each(list, &dev_priv->vbl_swaps.head) {
594 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
596 if (vbl_swap->drw_id == swap->drawable &&
597 vbl_swap->pipe == pipe &&
598 vbl_swap->sequence == swap->sequence) {
599 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
600 DRM_DEBUG("Already scheduled\n");
605 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
607 if (dev_priv->swaps_pending >= 100) {
608 DRM_DEBUG("Too many swaps queued\n");
612 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
615 DRM_ERROR("Failed to allocate memory to queue swap\n");
621 vbl_swap->drw_id = swap->drawable;
622 vbl_swap->pipe = pipe;
623 vbl_swap->sequence = swap->sequence;
625 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
627 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
628 dev_priv->swaps_pending++;
630 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
637 void i915_driver_irq_preinstall(struct drm_device * dev)
639 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
641 I915_WRITE(HWSTAM, 0xfffe);
642 I915_WRITE(IMR, 0x0);
643 I915_WRITE(IER, 0x0);
646 void i915_driver_irq_postinstall(struct drm_device * dev)
648 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
650 spin_lock_init(&dev_priv->swaps_lock);
651 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
652 dev_priv->swaps_pending = 0;
654 if (!dev_priv->vblank_pipe)
655 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A;
657 /* Set initial unmasked IRQs to just the selected vblank pipes. */
658 dev_priv->irq_mask_reg = ~0;
659 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
660 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
661 if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
662 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
664 I915_WRITE(IMR, dev_priv->irq_mask_reg);
665 I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
666 (void) I915_READ(IER);
668 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
671 void i915_driver_irq_uninstall(struct drm_device * dev)
673 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
679 I915_WRITE(HWSTAM, 0xffff);
680 I915_WRITE(IMR, 0xffff);
681 I915_WRITE(IER, 0x0);
683 temp = I915_READ(IIR);
684 I915_WRITE(IIR, temp);