1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #define MAX_NOPID ((u32)~0)
36 /** These are the interrupts used by the driver */
37 #define I915_INTERRUPT_ENABLE_MASK (I915_USER_INTERRUPT | \
38 I915_ASLE_INTERRUPT | \
39 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
40 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
43 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
45 if ((dev_priv->irq_mask_reg & mask) != 0) {
46 dev_priv->irq_mask_reg &= ~mask;
47 I915_WRITE(IMR, dev_priv->irq_mask_reg);
48 (void) I915_READ(IMR);
53 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
55 if ((dev_priv->irq_mask_reg & mask) != mask) {
56 dev_priv->irq_mask_reg |= mask;
57 I915_WRITE(IMR, dev_priv->irq_mask_reg);
58 (void) I915_READ(IMR);
63 * i915_get_pipe - return the the pipe associated with a given plane
65 * @plane: plane to look for
67 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
68 * rather than a pipe number, since they may not always be equal. This routine
69 * maps the given @plane back to a pipe number.
72 i915_get_pipe(struct drm_device *dev, int plane)
74 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
77 dspcntr = plane ? I915_READ(DSPBCNTR) : I915_READ(DSPACNTR);
79 return dspcntr & DISPPLANE_SEL_PIPE_MASK ? 1 : 0;
83 * i915_get_plane - return the the plane associated with a given pipe
85 * @pipe: pipe to look for
87 * The Intel Mesa & 2D drivers call the vblank routines with a plane number
88 * rather than a plane number, since they may not always be equal. This routine
89 * maps the given @pipe back to a plane number.
92 i915_get_plane(struct drm_device *dev, int pipe)
94 if (i915_get_pipe(dev, 0) == pipe)
100 * i915_pipe_enabled - check if a pipe is enabled
102 * @pipe: pipe to check
104 * Reading certain registers when the pipe is disabled can hang the chip.
105 * Use this routine to make sure the PLL is running and the pipe is active
106 * before reading such registers if unsure.
109 i915_pipe_enabled(struct drm_device *dev, int pipe)
111 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
112 unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
114 if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
121 * Emit blits for scheduled buffer swaps.
123 * This function will be called with the HW lock held.
125 static void i915_vblank_tasklet(struct drm_device *dev)
127 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
128 unsigned long irqflags;
129 struct list_head *list, *tmp, hits, *hit;
130 int nhits, nrects, slice[2], upper[2], lower[2], i;
132 struct drm_drawable_info *drw;
133 drm_i915_sarea_t *sarea_priv = dev_priv->sarea_priv;
134 u32 cpp = dev_priv->cpp;
135 u32 cmd = (cpp == 4) ? (XY_SRC_COPY_BLT_CMD |
136 XY_SRC_COPY_BLT_WRITE_ALPHA |
137 XY_SRC_COPY_BLT_WRITE_RGB)
138 : XY_SRC_COPY_BLT_CMD;
139 u32 src_pitch = sarea_priv->pitch * cpp;
140 u32 dst_pitch = sarea_priv->pitch * cpp;
141 u32 ropcpp = (0xcc << 16) | ((cpp - 1) << 24);
144 if (IS_I965G(dev) && sarea_priv->front_tiled) {
145 cmd |= XY_SRC_COPY_BLT_DST_TILED;
148 if (IS_I965G(dev) && sarea_priv->back_tiled) {
149 cmd |= XY_SRC_COPY_BLT_SRC_TILED;
153 counter[0] = drm_vblank_count(dev, 0);
154 counter[1] = drm_vblank_count(dev, 1);
158 INIT_LIST_HEAD(&hits);
162 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
164 /* Find buffer swaps scheduled for this vertical blank */
165 list_for_each_safe(list, tmp, &dev_priv->vbl_swaps.head) {
166 drm_i915_vbl_swap_t *vbl_swap =
167 list_entry(list, drm_i915_vbl_swap_t, head);
168 int pipe = i915_get_pipe(dev, vbl_swap->plane);
170 if ((counter[pipe] - vbl_swap->sequence) > (1<<23))
174 dev_priv->swaps_pending--;
175 drm_vblank_put(dev, pipe);
177 spin_unlock(&dev_priv->swaps_lock);
178 spin_lock(&dev->drw_lock);
180 drw = drm_get_drawable_info(dev, vbl_swap->drw_id);
183 spin_unlock(&dev->drw_lock);
184 drm_free(vbl_swap, sizeof(*vbl_swap), DRM_MEM_DRIVER);
185 spin_lock(&dev_priv->swaps_lock);
189 list_for_each(hit, &hits) {
190 drm_i915_vbl_swap_t *swap_cmp =
191 list_entry(hit, drm_i915_vbl_swap_t, head);
192 struct drm_drawable_info *drw_cmp =
193 drm_get_drawable_info(dev, swap_cmp->drw_id);
196 drw_cmp->rects[0].y1 > drw->rects[0].y1) {
197 list_add_tail(list, hit);
202 spin_unlock(&dev->drw_lock);
204 /* List of hits was empty, or we reached the end of it */
206 list_add_tail(list, hits.prev);
210 spin_lock(&dev_priv->swaps_lock);
214 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
218 spin_unlock(&dev_priv->swaps_lock);
220 i915_kernel_lost_context(dev);
225 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
227 OUT_RING(((sarea_priv->width - 1) & 0xffff) | ((sarea_priv->height - 1) << 16));
233 OUT_RING(GFX_OP_DRAWRECT_INFO);
236 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
237 OUT_RING(sarea_priv->width | sarea_priv->height << 16);
243 sarea_priv->ctxOwner = DRM_KERNEL_CONTEXT;
245 upper[0] = upper[1] = 0;
246 slice[0] = max(sarea_priv->pipeA_h / nhits, 1);
247 slice[1] = max(sarea_priv->pipeB_h / nhits, 1);
248 lower[0] = sarea_priv->pipeA_y + slice[0];
249 lower[1] = sarea_priv->pipeB_y + slice[0];
251 spin_lock(&dev->drw_lock);
253 /* Emit blits for buffer swaps, partitioning both outputs into as many
254 * slices as there are buffer swaps scheduled in order to avoid tearing
255 * (based on the assumption that a single buffer swap would always
256 * complete before scanout starts).
258 for (i = 0; i++ < nhits;
259 upper[0] = lower[0], lower[0] += slice[0],
260 upper[1] = lower[1], lower[1] += slice[1]) {
262 lower[0] = lower[1] = sarea_priv->height;
264 list_for_each(hit, &hits) {
265 drm_i915_vbl_swap_t *swap_hit =
266 list_entry(hit, drm_i915_vbl_swap_t, head);
267 struct drm_clip_rect *rect;
268 int num_rects, plane;
269 unsigned short top, bottom;
271 drw = drm_get_drawable_info(dev, swap_hit->drw_id);
277 plane = swap_hit->plane;
279 bottom = lower[plane];
281 for (num_rects = drw->num_rects; num_rects--; rect++) {
282 int y1 = max(rect->y1, top);
283 int y2 = min(rect->y2, bottom);
291 OUT_RING(ropcpp | dst_pitch);
292 OUT_RING((y1 << 16) | rect->x1);
293 OUT_RING((y2 << 16) | rect->x2);
294 OUT_RING(sarea_priv->front_offset);
295 OUT_RING((y1 << 16) | rect->x1);
297 OUT_RING(sarea_priv->back_offset);
304 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
306 list_for_each_safe(hit, tmp, &hits) {
307 drm_i915_vbl_swap_t *swap_hit =
308 list_entry(hit, drm_i915_vbl_swap_t, head);
312 drm_free(swap_hit, sizeof(*swap_hit), DRM_MEM_DRIVER);
316 u32 i915_get_vblank_counter(struct drm_device *dev, int plane)
318 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
319 unsigned long high_frame;
320 unsigned long low_frame;
321 u32 high1, high2, low, count;
324 pipe = i915_get_pipe(dev, plane);
325 high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
326 low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
328 if (!i915_pipe_enabled(dev, pipe)) {
329 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
334 * High & low register fields aren't synchronized, so make sure
335 * we get a low value that's stable across two reads of the high
339 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
340 PIPE_FRAME_HIGH_SHIFT);
341 low = ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
342 PIPE_FRAME_LOW_SHIFT);
343 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
344 PIPE_FRAME_HIGH_SHIFT);
345 } while (high1 != high2);
347 count = (high1 << 8) | low;
352 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
354 struct drm_device *dev = (struct drm_device *) arg;
355 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
357 u32 pipea_stats, pipeb_stats;
360 if (dev->pdev->msi_enabled)
362 iir = I915_READ(IIR);
365 if (dev->pdev->msi_enabled) {
366 I915_WRITE(IMR, dev_priv->irq_mask_reg);
367 (void) I915_READ(IMR);
373 * Clear the PIPE(A|B)STAT regs before the IIR otherwise
374 * we may get extra interrupts.
376 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
377 pipea_stats = I915_READ(PIPEASTAT);
378 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A))
379 pipea_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
380 PIPE_VBLANK_INTERRUPT_ENABLE);
381 else if (pipea_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
382 PIPE_VBLANK_INTERRUPT_STATUS)) {
384 drm_handle_vblank(dev, i915_get_plane(dev, 0));
387 I915_WRITE(PIPEASTAT, pipea_stats);
389 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
390 pipeb_stats = I915_READ(PIPEBSTAT);
392 I915_WRITE(PIPEBSTAT, pipeb_stats);
394 /* The vblank interrupt gets enabled even if we didn't ask for
395 it, so make sure it's shut down again */
396 if (!(dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B))
397 pipeb_stats &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
398 PIPE_VBLANK_INTERRUPT_ENABLE);
399 else if (pipeb_stats & (PIPE_START_VBLANK_INTERRUPT_STATUS|
400 PIPE_VBLANK_INTERRUPT_STATUS)) {
402 drm_handle_vblank(dev, i915_get_plane(dev, 1));
405 if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS)
406 opregion_asle_intr(dev);
407 I915_WRITE(PIPEBSTAT, pipeb_stats);
410 I915_WRITE(IIR, iir);
411 if (dev->pdev->msi_enabled)
412 I915_WRITE(IMR, dev_priv->irq_mask_reg);
413 (void) I915_READ(IIR); /* Flush posted writes */
415 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
417 if (iir & I915_USER_INTERRUPT) {
418 dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
419 DRM_WAKEUP(&dev_priv->irq_queue);
422 if (iir & I915_ASLE_INTERRUPT)
423 opregion_asle_intr(dev);
425 if (vblank && dev_priv->swaps_pending > 0)
426 drm_locked_tasklet(dev, i915_vblank_tasklet);
431 static int i915_emit_irq(struct drm_device * dev)
433 drm_i915_private_t *dev_priv = dev->dev_private;
436 i915_kernel_lost_context(dev);
440 dev_priv->sarea_priv->last_enqueue = ++dev_priv->counter;
442 if (dev_priv->counter > 0x7FFFFFFFUL)
443 dev_priv->sarea_priv->last_enqueue = dev_priv->counter = 1;
446 OUT_RING(MI_STORE_DWORD_INDEX);
447 OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
448 OUT_RING(dev_priv->counter);
451 OUT_RING(MI_USER_INTERRUPT);
454 return dev_priv->counter;
457 void i915_user_irq_get(struct drm_device *dev)
459 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
461 spin_lock(&dev_priv->user_irq_lock);
462 if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
463 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
464 spin_unlock(&dev_priv->user_irq_lock);
467 void i915_user_irq_put(struct drm_device *dev)
469 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
471 spin_lock(&dev_priv->user_irq_lock);
472 BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
473 if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
474 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
475 spin_unlock(&dev_priv->user_irq_lock);
478 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
480 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
483 DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
484 READ_BREADCRUMB(dev_priv));
486 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
487 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
491 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
493 i915_user_irq_get(dev);
494 DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
495 READ_BREADCRUMB(dev_priv) >= irq_nr);
496 i915_user_irq_put(dev);
499 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
500 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
503 dev_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
508 /* Needs the lock as it touches the ring.
510 int i915_irq_emit(struct drm_device *dev, void *data,
511 struct drm_file *file_priv)
513 drm_i915_private_t *dev_priv = dev->dev_private;
514 drm_i915_irq_emit_t *emit = data;
517 LOCK_TEST_WITH_RETURN(dev, file_priv);
520 DRM_ERROR("called with no initialization\n");
524 result = i915_emit_irq(dev);
526 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
527 DRM_ERROR("copy_to_user\n");
534 /* Doesn't need the hardware lock.
536 int i915_irq_wait(struct drm_device *dev, void *data,
537 struct drm_file *file_priv)
539 drm_i915_private_t *dev_priv = dev->dev_private;
540 drm_i915_irq_wait_t *irqwait = data;
543 DRM_ERROR("called with no initialization\n");
547 return i915_wait_irq(dev, irqwait->irq_seq);
550 int i915_enable_vblank(struct drm_device *dev, int plane)
552 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
553 int pipe = i915_get_pipe(dev, plane);
554 u32 pipestat_reg = 0;
559 pipestat_reg = PIPEASTAT;
560 i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT);
563 pipestat_reg = PIPEBSTAT;
564 i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
567 DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
573 pipestat = I915_READ(pipestat_reg);
575 pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
577 pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
578 /* Clear any stale interrupt status */
579 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
580 PIPE_VBLANK_INTERRUPT_STATUS);
581 I915_WRITE(pipestat_reg, pipestat);
587 void i915_disable_vblank(struct drm_device *dev, int plane)
589 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
590 int pipe = i915_get_pipe(dev, plane);
591 u32 pipestat_reg = 0;
596 pipestat_reg = PIPEASTAT;
597 i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT);
600 pipestat_reg = PIPEBSTAT;
601 i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
604 DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
610 pipestat = I915_READ(pipestat_reg);
611 pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
612 PIPE_VBLANK_INTERRUPT_ENABLE);
613 /* Clear any stale interrupt status */
614 pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
615 PIPE_VBLANK_INTERRUPT_STATUS);
616 I915_WRITE(pipestat_reg, pipestat);
620 /* Set the vblank monitor pipe
622 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
623 struct drm_file *file_priv)
625 drm_i915_private_t *dev_priv = dev->dev_private;
628 DRM_ERROR("called with no initialization\n");
635 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
636 struct drm_file *file_priv)
638 drm_i915_private_t *dev_priv = dev->dev_private;
639 drm_i915_vblank_pipe_t *pipe = data;
642 DRM_ERROR("called with no initialization\n");
646 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
652 * Schedule buffer swap at given vertical blank.
654 int i915_vblank_swap(struct drm_device *dev, void *data,
655 struct drm_file *file_priv)
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 drm_i915_vblank_swap_t *swap = data;
659 drm_i915_vbl_swap_t *vbl_swap;
660 unsigned int pipe, seqtype, curseq, plane;
661 unsigned long irqflags;
662 struct list_head *list;
666 DRM_ERROR("%s called with no initialization\n", __func__);
670 if (dev_priv->sarea_priv->rotation) {
671 DRM_DEBUG("Rotation not supported\n");
675 if (swap->seqtype & ~(_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE |
676 _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS)) {
677 DRM_ERROR("Invalid sequence type 0x%x\n", swap->seqtype);
681 plane = (swap->seqtype & _DRM_VBLANK_SECONDARY) ? 1 : 0;
682 pipe = i915_get_pipe(dev, plane);
684 seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
686 if (!(dev_priv->vblank_pipe & (1 << pipe))) {
687 DRM_ERROR("Invalid pipe %d\n", pipe);
691 spin_lock_irqsave(&dev->drw_lock, irqflags);
693 if (!drm_get_drawable_info(dev, swap->drawable)) {
694 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
695 DRM_DEBUG("Invalid drawable ID %d\n", swap->drawable);
699 spin_unlock_irqrestore(&dev->drw_lock, irqflags);
702 * We take the ref here and put it when the swap actually completes
705 ret = drm_vblank_get(dev, pipe);
708 curseq = drm_vblank_count(dev, pipe);
710 if (seqtype == _DRM_VBLANK_RELATIVE)
711 swap->sequence += curseq;
713 if ((curseq - swap->sequence) <= (1<<23)) {
714 if (swap->seqtype & _DRM_VBLANK_NEXTONMISS) {
715 swap->sequence = curseq + 1;
717 DRM_DEBUG("Missed target sequence\n");
718 drm_vblank_put(dev, pipe);
723 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
725 list_for_each(list, &dev_priv->vbl_swaps.head) {
726 vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
728 if (vbl_swap->drw_id == swap->drawable &&
729 vbl_swap->plane == plane &&
730 vbl_swap->sequence == swap->sequence) {
731 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
732 DRM_DEBUG("Already scheduled\n");
737 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
739 if (dev_priv->swaps_pending >= 100) {
740 DRM_DEBUG("Too many swaps queued\n");
741 drm_vblank_put(dev, pipe);
745 vbl_swap = drm_calloc(1, sizeof(*vbl_swap), DRM_MEM_DRIVER);
748 DRM_ERROR("Failed to allocate memory to queue swap\n");
749 drm_vblank_put(dev, pipe);
755 vbl_swap->drw_id = swap->drawable;
756 vbl_swap->plane = plane;
757 vbl_swap->sequence = swap->sequence;
759 spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
761 list_add_tail(&vbl_swap->head, &dev_priv->vbl_swaps.head);
762 dev_priv->swaps_pending++;
764 spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
771 void i915_driver_irq_preinstall(struct drm_device * dev)
773 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
775 I915_WRITE(HWSTAM, 0xeffe);
776 I915_WRITE(IMR, 0xffffffff);
777 I915_WRITE(IER, 0x0);
780 int i915_driver_irq_postinstall(struct drm_device *dev)
782 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
783 int ret, num_pipes = 2;
785 spin_lock_init(&dev_priv->swaps_lock);
786 INIT_LIST_HEAD(&dev_priv->vbl_swaps.head);
787 dev_priv->swaps_pending = 0;
789 /* Set initial unmasked IRQs to just the selected vblank pipes. */
790 dev_priv->irq_mask_reg = ~0;
792 ret = drm_vblank_init(dev, num_pipes);
796 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
797 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
798 dev_priv->irq_mask_reg &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
800 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
802 dev_priv->irq_mask_reg &= I915_INTERRUPT_ENABLE_MASK;
804 I915_WRITE(IMR, dev_priv->irq_mask_reg);
805 I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
806 (void) I915_READ(IER);
808 opregion_enable_asle(dev);
809 DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
814 void i915_driver_irq_uninstall(struct drm_device * dev)
816 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
822 dev_priv->vblank_pipe = 0;
824 I915_WRITE(HWSTAM, 0xffffffff);
825 I915_WRITE(IMR, 0xffffffff);
826 I915_WRITE(IER, 0x0);
828 temp = I915_READ(PIPEASTAT);
829 I915_WRITE(PIPEASTAT, temp);
830 temp = I915_READ(PIPEBSTAT);
831 I915_WRITE(PIPEBSTAT, temp);
832 temp = I915_READ(IIR);
833 I915_WRITE(IIR, temp);