drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "i915_drm.h"
  32 #include "i915_drv.h"
  33
  34 #define MAX_NOPID ((u32)~0)
  35
  36 /**
  37  * Interrupts that are always left unmasked.
  38  *
  39  * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
  40  * we leave them always unmasked in IMR and then control enabling them through
  41  * PIPESTAT alone.
  42  */
  43 #define I915_INTERRUPT_ENABLE_FIX (I915_ASLE_INTERRUPT | \
  44                                    I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |  \
  45                                    I915_DISPLAY_PIPE_B_EVENT_INTERRUPT)
  46
  47 /** Interrupts that we mask and unmask at runtime. */
  48 #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT)
  49
  50 /** These are all of the interrupts used by the driver */
  51 #define I915_INTERRUPT_ENABLE_MASK (I915_INTERRUPT_ENABLE_FIX | \
  52                                     I915_INTERRUPT_ENABLE_VAR)
  53
  54 void
  55 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
  56 {
  57         if ((dev_priv->irq_mask_reg & mask) != 0) {
  58                 dev_priv->irq_mask_reg &= ~mask;
  59                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  60                 (void) I915_READ(IMR);
  61         }
  62 }
  63
  64 static inline void
  65 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
  66 {
  67         if ((dev_priv->irq_mask_reg & mask) != mask) {
  68                 dev_priv->irq_mask_reg |= mask;
  69                 I915_WRITE(IMR, dev_priv->irq_mask_reg);
  70                 (void) I915_READ(IMR);
  71         }
  72 }
  73
  74 static inline u32
  75 i915_pipestat(int pipe)
  76 {
  77         if (pipe == 0)
  78                 return PIPEASTAT;
  79         if (pipe == 1)
  80                 return PIPEBSTAT;
  81         BUG_ON(1);
  82 }
  83
  84 void
  85 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  86 {
  87         if ((dev_priv->pipestat[pipe] & mask) != mask) {
  88                 u32 reg = i915_pipestat(pipe);
  89
  90                 dev_priv->pipestat[pipe] |= mask;
  91                 /* Enable the interrupt, clear any pending status */
  92                 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
  93                 (void) I915_READ(reg);
  94         }
  95 }
  96
  97 void
  98 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
  99 {
 100         if ((dev_priv->pipestat[pipe] & mask) != 0) {
 101                 u32 reg = i915_pipestat(pipe);
 102
 103                 dev_priv->pipestat[pipe] &= ~mask;
 104                 I915_WRITE(reg, dev_priv->pipestat[pipe]);
 105                 (void) I915_READ(reg);
 106         }
 107 }
 108
 109 /**
 110  * i915_pipe_enabled - check if a pipe is enabled
 111  * @dev: DRM device
 112  * @pipe: pipe to check
 113  *
 114  * Reading certain registers when the pipe is disabled can hang the chip.
 115  * Use this routine to make sure the PLL is running and the pipe is active
 116  * before reading such registers if unsure.
 117  */
 118 static int
 119 i915_pipe_enabled(struct drm_device *dev, int pipe)
 120 {
 121         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 122         unsigned long pipeconf = pipe ? PIPEBCONF : PIPEACONF;
 123
 124         if (I915_READ(pipeconf) & PIPEACONF_ENABLE)
 125                 return 1;
 126
 127         return 0;
 128 }
 129
 130 /* Called from drm generic code, passed a 'crtc', which
 131  * we use as a pipe index
 132  */
 133 u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 134 {
 135         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 136         unsigned long high_frame;
 137         unsigned long low_frame;
 138         u32 high1, high2, low, count;
 139
 140         high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH;
 141         low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL;
 142
 143         if (!i915_pipe_enabled(dev, pipe)) {
 144                 DRM_ERROR("trying to get vblank count for disabled pipe %d\n", pipe);
 145                 return 0;
 146         }
 147
 148         /*
 149          * High & low register fields aren't synchronized, so make sure
 150          * we get a low value that's stable across two reads of the high
 151          * register.
 152          */
 153         do {
 154                 high1 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 155                          PIPE_FRAME_HIGH_SHIFT);
 156                 low =  ((I915_READ(low_frame) & PIPE_FRAME_LOW_MASK) >>
 157                         PIPE_FRAME_LOW_SHIFT);
 158                 high2 = ((I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK) >>
 159                          PIPE_FRAME_HIGH_SHIFT);
 160         } while (high1 != high2);
 161
 162         count = (high1 << 8) | low;
 163
 164         return count;
 165 }
 166
 167 irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
 168 {
 169         struct drm_device *dev = (struct drm_device *) arg;
 170         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 171         u32 iir, new_iir;
 172         u32 pipea_stats, pipeb_stats;
 173         int vblank = 0;
 174         unsigned long irqflags;
 175
 176         atomic_inc(&dev_priv->irq_received);
 177
 178         iir = I915_READ(IIR);
 179
 180         if (iir == 0)
 181                 return IRQ_NONE;
 182
 183         do {
 184                 pipea_stats = 0;
 185                 pipeb_stats = 0;
 186                 /*
 187                  * Clear the PIPE(A|B)STAT regs before the IIR
 188                  */
 189                 if (iir & I915_DISPLAY_PIPE_A_EVENT_INTERRUPT) {
 190                         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 191                         pipea_stats = I915_READ(PIPEASTAT);
 192                         I915_WRITE(PIPEASTAT, pipea_stats);
 193                         spin_unlock_irqrestore(&dev_priv->user_irq_lock,
 194                                                irqflags);
 195                 }
 196
 197                 if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
 198                         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 199                         pipeb_stats = I915_READ(PIPEBSTAT);
 200                         I915_WRITE(PIPEBSTAT, pipeb_stats);
 201                         spin_unlock_irqrestore(&dev_priv->user_irq_lock,
 202                                                irqflags);
 203                 }
 204
 205                 I915_WRITE(IIR, iir);
 206                 new_iir = I915_READ(IIR); /* Flush posted writes */
 207
 208                 if (dev_priv->sarea_priv)
 209                         dev_priv->sarea_priv->last_dispatch =
 210                                 READ_BREADCRUMB(dev_priv);
 211
 212                 if (iir & I915_USER_INTERRUPT) {
 213                         dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
 214                         DRM_WAKEUP(&dev_priv->irq_queue);
 215                 }
 216
 217                 if (pipea_stats & I915_VBLANK_INTERRUPT_STATUS) {
 218                         vblank++;
 219                         drm_handle_vblank(dev, 0);
 220                 }
 221
 222                 if (pipeb_stats & I915_VBLANK_INTERRUPT_STATUS) {
 223                         vblank++;
 224                         drm_handle_vblank(dev, 1);
 225                 }
 226
 227                 if ((pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS) ||
 228                     (iir & I915_ASLE_INTERRUPT))
 229                         opregion_asle_intr(dev);
 230
 231                 /* With MSI, interrupts are only generated when iir
 232                  * transitions from zero to nonzero.  If another bit got
 233                  * set while we were handling the existing iir bits, then
 234                  * we would never get another interrupt.
 235                  *
 236                  * This is fine on non-MSI as well, as if we hit this path
 237                  * we avoid exiting the interrupt handler only to generate
 238                  * another one.
 239                  *
 240                  * Note that for MSI this could cause a stray interrupt report
 241                  * if an interrupt landed in the time between writing IIR and
 242                  * the posting read.  This should be rare enough to never
 243                  * trigger the 99% of 100,000 interrupts test for disabling
 244                  * stray interrupts.
 245                  */
 246                 iir = new_iir;
 247         } while (iir != 0);
 248
 249         return IRQ_HANDLED;
 250 }
 251
 252 static int i915_emit_irq(struct drm_device * dev)
 253 {
 254         drm_i915_private_t *dev_priv = dev->dev_private;
 255         RING_LOCALS;
 256
 257         i915_kernel_lost_context(dev);
 258
 259         DRM_DEBUG("\n");
 260
 261         dev_priv->counter++;
 262         if (dev_priv->counter > 0x7FFFFFFFUL)
 263                 dev_priv->counter = 1;
 264         if (dev_priv->sarea_priv)
 265                 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
 266
 267         BEGIN_LP_RING(4);
 268         OUT_RING(MI_STORE_DWORD_INDEX);
 269         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 270         OUT_RING(dev_priv->counter);
 271         OUT_RING(MI_USER_INTERRUPT);
 272         ADVANCE_LP_RING();
 273
 274         return dev_priv->counter;
 275 }
 276
 277 void i915_user_irq_get(struct drm_device *dev)
 278 {
 279         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 280         unsigned long irqflags;
 281
 282         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 283         if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
 284                 i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
 285         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 286 }
 287
 288 void i915_user_irq_put(struct drm_device *dev)
 289 {
 290         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 291         unsigned long irqflags;
 292
 293         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 294         BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
 295         if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
 296                 i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
 297         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 298 }
 299
 300 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 301 {
 302         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 303         int ret = 0;
 304
 305         DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
 306                   READ_BREADCRUMB(dev_priv));
 307
 308         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 309                 if (dev_priv->sarea_priv) {
 310                         dev_priv->sarea_priv->last_dispatch =
 311                                 READ_BREADCRUMB(dev_priv);
 312                 }
 313                 return 0;
 314         }
 315
 316         if (dev_priv->sarea_priv)
 317                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 318
 319         i915_user_irq_get(dev);
 320         DRM_WAIT_ON(ret, dev_priv->irq_queue, 3 * DRM_HZ,
 321                     READ_BREADCRUMB(dev_priv) >= irq_nr);
 322         i915_user_irq_put(dev);
 323
 324         if (ret == -EBUSY) {
 325                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 326                           READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
 327         }
 328
 329         if (dev_priv->sarea_priv)
 330                 dev_priv->sarea_priv->last_dispatch =
 331                         READ_BREADCRUMB(dev_priv);
 332
 333         return ret;
 334 }
 335
 336 /* Needs the lock as it touches the ring.
 337  */
 338 int i915_irq_emit(struct drm_device *dev, void *data,
 339                          struct drm_file *file_priv)
 340 {
 341         drm_i915_private_t *dev_priv = dev->dev_private;
 342         drm_i915_irq_emit_t *emit = data;
 343         int result;
 344
 345         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 346
 347         if (!dev_priv) {
 348                 DRM_ERROR("called with no initialization\n");
 349                 return -EINVAL;
 350         }
 351         mutex_lock(&dev->struct_mutex);
 352         result = i915_emit_irq(dev);
 353         mutex_unlock(&dev->struct_mutex);
 354
 355         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 356                 DRM_ERROR("copy_to_user\n");
 357                 return -EFAULT;
 358         }
 359
 360         return 0;
 361 }
 362
 363 /* Doesn't need the hardware lock.
 364  */
 365 int i915_irq_wait(struct drm_device *dev, void *data,
 366                          struct drm_file *file_priv)
 367 {
 368         drm_i915_private_t *dev_priv = dev->dev_private;
 369         drm_i915_irq_wait_t *irqwait = data;
 370
 371         if (!dev_priv) {
 372                 DRM_ERROR("called with no initialization\n");
 373                 return -EINVAL;
 374         }
 375
 376         return i915_wait_irq(dev, irqwait->irq_seq);
 377 }
 378
 379 /* Called from drm generic code, passed 'crtc' which
 380  * we use as a pipe index
 381  */
 382 int i915_enable_vblank(struct drm_device *dev, int pipe)
 383 {
 384         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 385         unsigned long irqflags;
 386
 387         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 388         if (IS_I965G(dev))
 389                 i915_enable_pipestat(dev_priv, pipe,
 390                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
 391         else
 392                 i915_enable_pipestat(dev_priv, pipe,
 393                                      PIPE_VBLANK_INTERRUPT_ENABLE);
 394         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 395         return 0;
 396 }
 397
 398 /* Called from drm generic code, passed 'crtc' which
 399  * we use as a pipe index
 400  */
 401 void i915_disable_vblank(struct drm_device *dev, int pipe)
 402 {
 403         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 404         unsigned long irqflags;
 405
 406         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
 407         i915_disable_pipestat(dev_priv, pipe,
 408                               PIPE_VBLANK_INTERRUPT_ENABLE |
 409                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
 410         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
 411 }
 412
 413 /* Set the vblank monitor pipe
 414  */
 415 int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 416                          struct drm_file *file_priv)
 417 {
 418         drm_i915_private_t *dev_priv = dev->dev_private;
 419
 420         if (!dev_priv) {
 421                 DRM_ERROR("called with no initialization\n");
 422                 return -EINVAL;
 423         }
 424
 425         return 0;
 426 }
 427
 428 int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 429                          struct drm_file *file_priv)
 430 {
 431         drm_i915_private_t *dev_priv = dev->dev_private;
 432         drm_i915_vblank_pipe_t *pipe = data;
 433
 434         if (!dev_priv) {
 435                 DRM_ERROR("called with no initialization\n");
 436                 return -EINVAL;
 437         }
 438
 439         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 440
 441         return 0;
 442 }
 443
 444 /**
 445  * Schedule buffer swap at given vertical blank.
 446  */
 447 int i915_vblank_swap(struct drm_device *dev, void *data,
 448                      struct drm_file *file_priv)
 449 {
 450         /* The delayed swap mechanism was fundamentally racy, and has been
 451          * removed.  The model was that the client requested a delayed flip/swap
 452          * from the kernel, then waited for vblank before continuing to perform
 453          * rendering.  The problem was that the kernel might wake the client
 454          * up before it dispatched the vblank swap (since the lock has to be
 455          * held while touching the ringbuffer), in which case the client would
 456          * clear and start the next frame before the swap occurred, and
 457          * flicker would occur in addition to likely missing the vblank.
 458          *
 459          * In the absence of this ioctl, userland falls back to a correct path
 460          * of waiting for a vblank, then dispatching the swap on its own.
 461          * Context switching to userland and back is plenty fast enough for
 462          * meeting the requirements of vblank swapping.
 463          */
 464         return -EINVAL;
 465 }
 466
 467 /* drm_dma.h hooks
 468 */
 469 void i915_driver_irq_preinstall(struct drm_device * dev)
 470 {
 471         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 472
 473         I915_WRITE(HWSTAM, 0xeffe);
 474         I915_WRITE(PIPEASTAT, 0);
 475         I915_WRITE(PIPEBSTAT, 0);
 476         I915_WRITE(IMR, 0xffffffff);
 477         I915_WRITE(IER, 0x0);
 478         (void) I915_READ(IER);
 479 }
 480
 481 int i915_driver_irq_postinstall(struct drm_device *dev)
 482 {
 483         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 484         int ret, num_pipes = 2;
 485
 486         ret = drm_vblank_init(dev, num_pipes);
 487         if (ret)
 488                 return ret;
 489
 490         dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 491
 492         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
 493
 494         /* Unmask the interrupts that we always want on. */
 495         dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX;
 496
 497         dev_priv->pipestat[0] = 0;
 498         dev_priv->pipestat[1] = 0;
 499
 500         /* Disable pipe interrupt enables, clear pending pipe status */
 501         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 502         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 503         /* Clear pending interrupt status */
 504         I915_WRITE(IIR, I915_READ(IIR));
 505
 506         I915_WRITE(IER, I915_INTERRUPT_ENABLE_MASK);
 507         I915_WRITE(IMR, dev_priv->irq_mask_reg);
 508         (void) I915_READ(IER);
 509
 510         opregion_enable_asle(dev);
 511         DRM_INIT_WAITQUEUE(&dev_priv->irq_queue);
 512
 513         return 0;
 514 }
 515
 516 void i915_driver_irq_uninstall(struct drm_device * dev)
 517 {
 518         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 519
 520         if (!dev_priv)
 521                 return;
 522
 523         dev_priv->vblank_pipe = 0;
 524
 525         I915_WRITE(HWSTAM, 0xffffffff);
 526         I915_WRITE(PIPEASTAT, 0);
 527         I915_WRITE(PIPEBSTAT, 0);
 528         I915_WRITE(IMR, 0xffffffff);
 529         I915_WRITE(IER, 0x0);
 530
 531         I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff);
 532         I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff);
 533         I915_WRITE(IIR, I915_READ(IIR));
 534 }