2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include <linux/swap.h>
35 i915_gem_object_set_domain(struct drm_gem_object *obj,
36 uint32_t read_domains,
37 uint32_t write_domain);
39 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
42 uint32_t read_domains,
43 uint32_t write_domain);
45 i915_gem_set_domain(struct drm_gem_object *obj,
46 struct drm_file *file_priv,
47 uint32_t read_domains,
48 uint32_t write_domain);
49 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
50 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
54 i915_gem_init_ioctl(struct drm_device *dev, void *data,
55 struct drm_file *file_priv)
57 drm_i915_private_t *dev_priv = dev->dev_private;
58 struct drm_i915_gem_init *args = data;
60 mutex_lock(&dev->struct_mutex);
62 if (args->gtt_start >= args->gtt_end ||
63 (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
64 (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
65 mutex_unlock(&dev->struct_mutex);
69 drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start,
70 args->gtt_end - args->gtt_start);
72 dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
74 mutex_unlock(&dev->struct_mutex);
81 * Creates a new mm object and returns a handle to it.
84 i915_gem_create_ioctl(struct drm_device *dev, void *data,
85 struct drm_file *file_priv)
87 struct drm_i915_gem_create *args = data;
88 struct drm_gem_object *obj;
91 args->size = roundup(args->size, PAGE_SIZE);
93 /* Allocate the new object */
94 obj = drm_gem_object_alloc(dev, args->size);
98 ret = drm_gem_handle_create(file_priv, obj, &handle);
99 mutex_lock(&dev->struct_mutex);
100 drm_gem_object_handle_unreference(obj);
101 mutex_unlock(&dev->struct_mutex);
106 args->handle = handle;
112 * Reads data from the object referenced by handle.
114 * On error, the contents of *data are undefined.
117 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
118 struct drm_file *file_priv)
120 struct drm_i915_gem_pread *args = data;
121 struct drm_gem_object *obj;
122 struct drm_i915_gem_object *obj_priv;
127 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
130 obj_priv = obj->driver_private;
132 /* Bounds check source.
134 * XXX: This could use review for overflow issues...
136 if (args->offset > obj->size || args->size > obj->size ||
137 args->offset + args->size > obj->size) {
138 drm_gem_object_unreference(obj);
142 mutex_lock(&dev->struct_mutex);
144 ret = i915_gem_object_set_domain_range(obj, args->offset, args->size,
145 I915_GEM_DOMAIN_CPU, 0);
147 drm_gem_object_unreference(obj);
148 mutex_unlock(&dev->struct_mutex);
151 offset = args->offset;
153 read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
154 args->size, &offset);
155 if (read != args->size) {
156 drm_gem_object_unreference(obj);
157 mutex_unlock(&dev->struct_mutex);
164 drm_gem_object_unreference(obj);
165 mutex_unlock(&dev->struct_mutex);
171 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
172 struct drm_i915_gem_pwrite *args,
173 struct drm_file *file_priv)
175 struct drm_i915_gem_object *obj_priv = obj->driver_private;
178 char __user *user_data;
184 unsigned long unwritten;
186 user_data = (char __user *) (uintptr_t) args->data_ptr;
188 if (!access_ok(VERIFY_READ, user_data, remain))
192 mutex_lock(&dev->struct_mutex);
193 ret = i915_gem_object_pin(obj, 0);
195 mutex_unlock(&dev->struct_mutex);
198 ret = i915_gem_set_domain(obj, file_priv,
199 I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
203 obj_priv = obj->driver_private;
204 offset = obj_priv->gtt_offset + args->offset;
208 /* Operation in this page
211 * o = offset within page
214 i = offset >> PAGE_SHIFT;
215 o = offset & (PAGE_SIZE-1);
217 if ((o + l) > PAGE_SIZE)
220 pfn = (dev->agp->base >> PAGE_SHIFT) + i;
222 #ifdef CONFIG_HIGHMEM
223 /* This is a workaround for the low performance of iounmap
224 * (approximate 10% cpu cost on normal 3D workloads).
225 * kmap_atomic on HIGHMEM kernels happens to let us map card
226 * memory without taking IPIs. When the vmap rework lands
227 * we should be able to dump this hack.
229 vaddr_atomic = kmap_atomic_pfn(pfn, KM_USER0);
231 DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n",
232 i, o, l, pfn, vaddr_atomic);
234 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + o,
236 kunmap_atomic(vaddr_atomic, KM_USER0);
239 #endif /* CONFIG_HIGHMEM */
241 vaddr = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE);
243 DRM_INFO("pwrite slow i %d o %d l %d "
244 "pfn %ld vaddr %p\n",
245 i, o, l, pfn, vaddr);
251 unwritten = __copy_from_user(vaddr + o, user_data, l);
253 DRM_INFO("unwritten %ld\n", unwritten);
266 #if WATCH_PWRITE && 1
267 i915_gem_clflush_object(obj);
268 i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0);
269 i915_gem_clflush_object(obj);
273 i915_gem_object_unpin(obj);
274 mutex_unlock(&dev->struct_mutex);
280 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
281 struct drm_i915_gem_pwrite *args,
282 struct drm_file *file_priv)
288 mutex_lock(&dev->struct_mutex);
290 ret = i915_gem_set_domain(obj, file_priv,
291 I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU);
293 mutex_unlock(&dev->struct_mutex);
297 offset = args->offset;
299 written = vfs_write(obj->filp,
300 (char __user *)(uintptr_t) args->data_ptr,
301 args->size, &offset);
302 if (written != args->size) {
303 mutex_unlock(&dev->struct_mutex);
310 mutex_unlock(&dev->struct_mutex);
316 * Writes data to the object referenced by handle.
318 * On error, the contents of the buffer that were to be modified are undefined.
321 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
322 struct drm_file *file_priv)
324 struct drm_i915_gem_pwrite *args = data;
325 struct drm_gem_object *obj;
326 struct drm_i915_gem_object *obj_priv;
329 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
332 obj_priv = obj->driver_private;
334 /* Bounds check destination.
336 * XXX: This could use review for overflow issues...
338 if (args->offset > obj->size || args->size > obj->size ||
339 args->offset + args->size > obj->size) {
340 drm_gem_object_unreference(obj);
344 /* We can only do the GTT pwrite on untiled buffers, as otherwise
345 * it would end up going through the fenced access, and we'll get
346 * different detiling behavior between reading and writing.
347 * pread/pwrite currently are reading and writing from the CPU
348 * perspective, requiring manual detiling by the client.
350 if (obj_priv->tiling_mode == I915_TILING_NONE &&
352 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
354 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
358 DRM_INFO("pwrite failed %d\n", ret);
361 drm_gem_object_unreference(obj);
367 * Called when user space prepares to use an object
370 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
371 struct drm_file *file_priv)
373 struct drm_i915_gem_set_domain *args = data;
374 struct drm_gem_object *obj;
377 if (!(dev->driver->driver_features & DRIVER_GEM))
380 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
384 mutex_lock(&dev->struct_mutex);
386 DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
387 obj, obj->size, args->read_domains, args->write_domain);
389 ret = i915_gem_set_domain(obj, file_priv,
390 args->read_domains, args->write_domain);
391 drm_gem_object_unreference(obj);
392 mutex_unlock(&dev->struct_mutex);
397 * Called when user space has done writes to this buffer
400 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
401 struct drm_file *file_priv)
403 struct drm_i915_gem_sw_finish *args = data;
404 struct drm_gem_object *obj;
405 struct drm_i915_gem_object *obj_priv;
408 if (!(dev->driver->driver_features & DRIVER_GEM))
411 mutex_lock(&dev->struct_mutex);
412 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
414 mutex_unlock(&dev->struct_mutex);
419 DRM_INFO("%s: sw_finish %d (%p %d)\n",
420 __func__, args->handle, obj, obj->size);
422 obj_priv = obj->driver_private;
424 /* Pinned buffers may be scanout, so flush the cache */
425 if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) {
426 i915_gem_clflush_object(obj);
427 drm_agp_chipset_flush(dev);
429 drm_gem_object_unreference(obj);
430 mutex_unlock(&dev->struct_mutex);
435 * Maps the contents of an object, returning the address it is mapped
438 * While the mapping holds a reference on the contents of the object, it doesn't
439 * imply a ref on the object itself.
442 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
443 struct drm_file *file_priv)
445 struct drm_i915_gem_mmap *args = data;
446 struct drm_gem_object *obj;
450 if (!(dev->driver->driver_features & DRIVER_GEM))
453 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
457 offset = args->offset;
459 down_write(¤t->mm->mmap_sem);
460 addr = do_mmap(obj->filp, 0, args->size,
461 PROT_READ | PROT_WRITE, MAP_SHARED,
463 up_write(¤t->mm->mmap_sem);
464 mutex_lock(&dev->struct_mutex);
465 drm_gem_object_unreference(obj);
466 mutex_unlock(&dev->struct_mutex);
467 if (IS_ERR((void *)addr))
470 args->addr_ptr = (uint64_t) addr;
476 i915_gem_object_free_page_list(struct drm_gem_object *obj)
478 struct drm_i915_gem_object *obj_priv = obj->driver_private;
479 int page_count = obj->size / PAGE_SIZE;
482 if (obj_priv->page_list == NULL)
486 for (i = 0; i < page_count; i++)
487 if (obj_priv->page_list[i] != NULL) {
489 set_page_dirty(obj_priv->page_list[i]);
490 mark_page_accessed(obj_priv->page_list[i]);
491 page_cache_release(obj_priv->page_list[i]);
495 drm_free(obj_priv->page_list,
496 page_count * sizeof(struct page *),
498 obj_priv->page_list = NULL;
502 i915_gem_object_move_to_active(struct drm_gem_object *obj)
504 struct drm_device *dev = obj->dev;
505 drm_i915_private_t *dev_priv = dev->dev_private;
506 struct drm_i915_gem_object *obj_priv = obj->driver_private;
508 /* Add a reference if we're newly entering the active list. */
509 if (!obj_priv->active) {
510 drm_gem_object_reference(obj);
511 obj_priv->active = 1;
513 /* Move from whatever list we were on to the tail of execution. */
514 list_move_tail(&obj_priv->list,
515 &dev_priv->mm.active_list);
520 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
522 struct drm_device *dev = obj->dev;
523 drm_i915_private_t *dev_priv = dev->dev_private;
524 struct drm_i915_gem_object *obj_priv = obj->driver_private;
526 i915_verify_inactive(dev, __FILE__, __LINE__);
527 if (obj_priv->pin_count != 0)
528 list_del_init(&obj_priv->list);
530 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
532 if (obj_priv->active) {
533 obj_priv->active = 0;
534 drm_gem_object_unreference(obj);
536 i915_verify_inactive(dev, __FILE__, __LINE__);
540 * Creates a new sequence number, emitting a write of it to the status page
541 * plus an interrupt, which will trigger i915_user_interrupt_handler.
543 * Must be called with struct_lock held.
545 * Returned sequence numbers are nonzero on success.
548 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
550 drm_i915_private_t *dev_priv = dev->dev_private;
551 struct drm_i915_gem_request *request;
556 request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
560 /* Grab the seqno we're going to make this request be, and bump the
561 * next (skipping 0 so it can be the reserved no-seqno value).
563 seqno = dev_priv->mm.next_gem_seqno;
564 dev_priv->mm.next_gem_seqno++;
565 if (dev_priv->mm.next_gem_seqno == 0)
566 dev_priv->mm.next_gem_seqno++;
569 OUT_RING(MI_STORE_DWORD_INDEX);
570 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
573 OUT_RING(MI_USER_INTERRUPT);
576 DRM_DEBUG("%d\n", seqno);
578 request->seqno = seqno;
579 request->emitted_jiffies = jiffies;
580 request->flush_domains = flush_domains;
581 was_empty = list_empty(&dev_priv->mm.request_list);
582 list_add_tail(&request->list, &dev_priv->mm.request_list);
585 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
590 * Command execution barrier
592 * Ensures that all commands in the ring are finished
593 * before signalling the CPU
596 i915_retire_commands(struct drm_device *dev)
598 drm_i915_private_t *dev_priv = dev->dev_private;
599 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
600 uint32_t flush_domains = 0;
603 /* The sampler always gets flushed on i965 (sigh) */
605 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
608 OUT_RING(0); /* noop */
610 return flush_domains;
614 * Moves buffers associated only with the given active seqno from the active
615 * to inactive list, potentially freeing them.
618 i915_gem_retire_request(struct drm_device *dev,
619 struct drm_i915_gem_request *request)
621 drm_i915_private_t *dev_priv = dev->dev_private;
623 /* Move any buffers on the active list that are no longer referenced
624 * by the ringbuffer to the flushing/inactive lists as appropriate.
626 while (!list_empty(&dev_priv->mm.active_list)) {
627 struct drm_gem_object *obj;
628 struct drm_i915_gem_object *obj_priv;
630 obj_priv = list_first_entry(&dev_priv->mm.active_list,
631 struct drm_i915_gem_object,
635 /* If the seqno being retired doesn't match the oldest in the
636 * list, then the oldest in the list must still be newer than
639 if (obj_priv->last_rendering_seqno != request->seqno)
642 DRM_INFO("%s: retire %d moves to inactive list %p\n",
643 __func__, request->seqno, obj);
646 if (obj->write_domain != 0) {
647 list_move_tail(&obj_priv->list,
648 &dev_priv->mm.flushing_list);
650 i915_gem_object_move_to_inactive(obj);
654 if (request->flush_domains != 0) {
655 struct drm_i915_gem_object *obj_priv, *next;
657 /* Clear the write domain and activity from any buffers
658 * that are just waiting for a flush matching the one retired.
660 list_for_each_entry_safe(obj_priv, next,
661 &dev_priv->mm.flushing_list, list) {
662 struct drm_gem_object *obj = obj_priv->obj;
664 if (obj->write_domain & request->flush_domains) {
665 obj->write_domain = 0;
666 i915_gem_object_move_to_inactive(obj);
674 * Returns true if seq1 is later than seq2.
677 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
679 return (int32_t)(seq1 - seq2) >= 0;
683 i915_get_gem_seqno(struct drm_device *dev)
685 drm_i915_private_t *dev_priv = dev->dev_private;
687 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
691 * This function clears the request list as sequence numbers are passed.
694 i915_gem_retire_requests(struct drm_device *dev)
696 drm_i915_private_t *dev_priv = dev->dev_private;
699 seqno = i915_get_gem_seqno(dev);
701 while (!list_empty(&dev_priv->mm.request_list)) {
702 struct drm_i915_gem_request *request;
703 uint32_t retiring_seqno;
705 request = list_first_entry(&dev_priv->mm.request_list,
706 struct drm_i915_gem_request,
708 retiring_seqno = request->seqno;
710 if (i915_seqno_passed(seqno, retiring_seqno) ||
711 dev_priv->mm.wedged) {
712 i915_gem_retire_request(dev, request);
714 list_del(&request->list);
715 drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
722 i915_gem_retire_work_handler(struct work_struct *work)
724 drm_i915_private_t *dev_priv;
725 struct drm_device *dev;
727 dev_priv = container_of(work, drm_i915_private_t,
728 mm.retire_work.work);
731 mutex_lock(&dev->struct_mutex);
732 i915_gem_retire_requests(dev);
733 if (!list_empty(&dev_priv->mm.request_list))
734 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
735 mutex_unlock(&dev->struct_mutex);
739 * Waits for a sequence number to be signaled, and cleans up the
740 * request and object lists appropriately for that event.
743 i915_wait_request(struct drm_device *dev, uint32_t seqno)
745 drm_i915_private_t *dev_priv = dev->dev_private;
750 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
751 dev_priv->mm.waiting_gem_seqno = seqno;
752 i915_user_irq_get(dev);
753 ret = wait_event_interruptible(dev_priv->irq_queue,
754 i915_seqno_passed(i915_get_gem_seqno(dev),
756 dev_priv->mm.wedged);
757 i915_user_irq_put(dev);
758 dev_priv->mm.waiting_gem_seqno = 0;
760 if (dev_priv->mm.wedged)
763 if (ret && ret != -ERESTARTSYS)
764 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
765 __func__, ret, seqno, i915_get_gem_seqno(dev));
767 /* Directly dispatch request retiring. While we have the work queue
768 * to handle this, the waiter on a request often wants an associated
769 * buffer to have made it to the inactive list, and we would need
770 * a separate wait queue to handle that.
773 i915_gem_retire_requests(dev);
779 i915_gem_flush(struct drm_device *dev,
780 uint32_t invalidate_domains,
781 uint32_t flush_domains)
783 drm_i915_private_t *dev_priv = dev->dev_private;
788 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
789 invalidate_domains, flush_domains);
792 if (flush_domains & I915_GEM_DOMAIN_CPU)
793 drm_agp_chipset_flush(dev);
795 if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
796 I915_GEM_DOMAIN_GTT)) {
800 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
801 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
802 * also flushed at 2d versus 3d pipeline switches.
806 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
807 * MI_READ_FLUSH is set, and is always flushed on 965.
809 * I915_GEM_DOMAIN_COMMAND may not exist?
811 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
812 * invalidated when MI_EXE_FLUSH is set.
814 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
815 * invalidated with every MI_FLUSH.
819 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
820 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
821 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
822 * are flushed at any MI_FLUSH.
825 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
826 if ((invalidate_domains|flush_domains) &
827 I915_GEM_DOMAIN_RENDER)
828 cmd &= ~MI_NO_WRITE_FLUSH;
829 if (!IS_I965G(dev)) {
831 * On the 965, the sampler cache always gets flushed
832 * and this bit is reserved.
834 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
835 cmd |= MI_READ_FLUSH;
837 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
841 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
845 OUT_RING(0); /* noop */
851 * Ensures that all rendering to the object has completed and the object is
852 * safe to unbind from the GTT or access from the CPU.
855 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
857 struct drm_device *dev = obj->dev;
858 struct drm_i915_gem_object *obj_priv = obj->driver_private;
861 /* If there are writes queued to the buffer, flush and
862 * create a new seqno to wait for.
864 if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) {
865 uint32_t write_domain = obj->write_domain;
867 DRM_INFO("%s: flushing object %p from write domain %08x\n",
868 __func__, obj, write_domain);
870 i915_gem_flush(dev, 0, write_domain);
872 i915_gem_object_move_to_active(obj);
873 obj_priv->last_rendering_seqno = i915_add_request(dev,
875 BUG_ON(obj_priv->last_rendering_seqno == 0);
877 DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj);
881 /* If there is rendering queued on the buffer being evicted, wait for
884 if (obj_priv->active) {
886 DRM_INFO("%s: object %p wait for seqno %08x\n",
887 __func__, obj, obj_priv->last_rendering_seqno);
889 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
898 * Unbinds an object from the GTT aperture.
901 i915_gem_object_unbind(struct drm_gem_object *obj)
903 struct drm_device *dev = obj->dev;
904 struct drm_i915_gem_object *obj_priv = obj->driver_private;
908 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
909 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
911 if (obj_priv->gtt_space == NULL)
914 if (obj_priv->pin_count != 0) {
915 DRM_ERROR("Attempting to unbind pinned buffer\n");
919 /* Wait for any rendering to complete
921 ret = i915_gem_object_wait_rendering(obj);
923 DRM_ERROR("wait_rendering failed: %d\n", ret);
927 /* Move the object to the CPU domain to ensure that
928 * any possible CPU writes while it's not in the GTT
929 * are flushed when we go to remap it. This will
930 * also ensure that all pending GPU writes are finished
933 ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU,
934 I915_GEM_DOMAIN_CPU);
936 DRM_ERROR("set_domain failed: %d\n", ret);
940 if (obj_priv->agp_mem != NULL) {
941 drm_unbind_agp(obj_priv->agp_mem);
942 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
943 obj_priv->agp_mem = NULL;
946 BUG_ON(obj_priv->active);
948 i915_gem_object_free_page_list(obj);
950 if (obj_priv->gtt_space) {
951 atomic_dec(&dev->gtt_count);
952 atomic_sub(obj->size, &dev->gtt_memory);
954 drm_mm_put_block(obj_priv->gtt_space);
955 obj_priv->gtt_space = NULL;
958 /* Remove ourselves from the LRU list if present. */
959 if (!list_empty(&obj_priv->list))
960 list_del_init(&obj_priv->list);
966 i915_gem_evict_something(struct drm_device *dev)
968 drm_i915_private_t *dev_priv = dev->dev_private;
969 struct drm_gem_object *obj;
970 struct drm_i915_gem_object *obj_priv;
974 /* If there's an inactive buffer available now, grab it
977 if (!list_empty(&dev_priv->mm.inactive_list)) {
978 obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
979 struct drm_i915_gem_object,
982 BUG_ON(obj_priv->pin_count != 0);
984 DRM_INFO("%s: evicting %p\n", __func__, obj);
986 BUG_ON(obj_priv->active);
988 /* Wait on the rendering and unbind the buffer. */
989 ret = i915_gem_object_unbind(obj);
993 /* If we didn't get anything, but the ring is still processing
994 * things, wait for one of those things to finish and hopefully
995 * leave us a buffer to evict.
997 if (!list_empty(&dev_priv->mm.request_list)) {
998 struct drm_i915_gem_request *request;
1000 request = list_first_entry(&dev_priv->mm.request_list,
1001 struct drm_i915_gem_request,
1004 ret = i915_wait_request(dev, request->seqno);
1008 /* if waiting caused an object to become inactive,
1009 * then loop around and wait for it. Otherwise, we
1010 * assume that waiting freed and unbound something,
1011 * so there should now be some space in the GTT
1013 if (!list_empty(&dev_priv->mm.inactive_list))
1018 /* If we didn't have anything on the request list but there
1019 * are buffers awaiting a flush, emit one and try again.
1020 * When we wait on it, those buffers waiting for that flush
1021 * will get moved to inactive.
1023 if (!list_empty(&dev_priv->mm.flushing_list)) {
1024 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1025 struct drm_i915_gem_object,
1027 obj = obj_priv->obj;
1032 i915_add_request(dev, obj->write_domain);
1038 DRM_ERROR("inactive empty %d request empty %d "
1039 "flushing empty %d\n",
1040 list_empty(&dev_priv->mm.inactive_list),
1041 list_empty(&dev_priv->mm.request_list),
1042 list_empty(&dev_priv->mm.flushing_list));
1043 /* If we didn't do any of the above, there's nothing to be done
1044 * and we just can't fit it in.
1052 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1054 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1056 struct address_space *mapping;
1057 struct inode *inode;
1061 if (obj_priv->page_list)
1064 /* Get the list of pages out of our struct file. They'll be pinned
1065 * at this point until we release them.
1067 page_count = obj->size / PAGE_SIZE;
1068 BUG_ON(obj_priv->page_list != NULL);
1069 obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1071 if (obj_priv->page_list == NULL) {
1072 DRM_ERROR("Faled to allocate page list\n");
1076 inode = obj->filp->f_path.dentry->d_inode;
1077 mapping = inode->i_mapping;
1078 for (i = 0; i < page_count; i++) {
1079 page = read_mapping_page(mapping, i, NULL);
1081 ret = PTR_ERR(page);
1082 DRM_ERROR("read_mapping_page failed: %d\n", ret);
1083 i915_gem_object_free_page_list(obj);
1086 obj_priv->page_list[i] = page;
1092 * Finds free space in the GTT aperture and binds the object there.
1095 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1097 struct drm_device *dev = obj->dev;
1098 drm_i915_private_t *dev_priv = dev->dev_private;
1099 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1100 struct drm_mm_node *free_space;
1101 int page_count, ret;
1104 alignment = PAGE_SIZE;
1105 if (alignment & (PAGE_SIZE - 1)) {
1106 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1111 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1112 obj->size, alignment, 0);
1113 if (free_space != NULL) {
1114 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1116 if (obj_priv->gtt_space != NULL) {
1117 obj_priv->gtt_space->private = obj;
1118 obj_priv->gtt_offset = obj_priv->gtt_space->start;
1121 if (obj_priv->gtt_space == NULL) {
1122 /* If the gtt is empty and we're still having trouble
1123 * fitting our object in, we're out of memory.
1126 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1128 if (list_empty(&dev_priv->mm.inactive_list) &&
1129 list_empty(&dev_priv->mm.flushing_list) &&
1130 list_empty(&dev_priv->mm.active_list)) {
1131 DRM_ERROR("GTT full, but LRU list empty\n");
1135 ret = i915_gem_evict_something(dev);
1137 DRM_ERROR("Failed to evict a buffer %d\n", ret);
1144 DRM_INFO("Binding object of size %d at 0x%08x\n",
1145 obj->size, obj_priv->gtt_offset);
1147 ret = i915_gem_object_get_page_list(obj);
1149 drm_mm_put_block(obj_priv->gtt_space);
1150 obj_priv->gtt_space = NULL;
1154 page_count = obj->size / PAGE_SIZE;
1155 /* Create an AGP memory structure pointing at our pages, and bind it
1158 obj_priv->agp_mem = drm_agp_bind_pages(dev,
1159 obj_priv->page_list,
1161 obj_priv->gtt_offset);
1162 if (obj_priv->agp_mem == NULL) {
1163 i915_gem_object_free_page_list(obj);
1164 drm_mm_put_block(obj_priv->gtt_space);
1165 obj_priv->gtt_space = NULL;
1168 atomic_inc(&dev->gtt_count);
1169 atomic_add(obj->size, &dev->gtt_memory);
1171 /* Assert that the object is not currently in any GPU domain. As it
1172 * wasn't in the GTT, there shouldn't be any way it could have been in
1175 BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1176 BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1182 i915_gem_clflush_object(struct drm_gem_object *obj)
1184 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1186 /* If we don't have a page list set up, then we're not pinned
1187 * to GPU, and we can ignore the cache flush because it'll happen
1188 * again at bind time.
1190 if (obj_priv->page_list == NULL)
1193 drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1197 * Set the next domain for the specified object. This
1198 * may not actually perform the necessary flushing/invaliding though,
1199 * as that may want to be batched with other set_domain operations
1201 * This is (we hope) the only really tricky part of gem. The goal
1202 * is fairly simple -- track which caches hold bits of the object
1203 * and make sure they remain coherent. A few concrete examples may
1204 * help to explain how it works. For shorthand, we use the notation
1205 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1206 * a pair of read and write domain masks.
1208 * Case 1: the batch buffer
1214 * 5. Unmapped from GTT
1217 * Let's take these a step at a time
1220 * Pages allocated from the kernel may still have
1221 * cache contents, so we set them to (CPU, CPU) always.
1222 * 2. Written by CPU (using pwrite)
1223 * The pwrite function calls set_domain (CPU, CPU) and
1224 * this function does nothing (as nothing changes)
1226 * This function asserts that the object is not
1227 * currently in any GPU-based read or write domains
1229 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
1230 * As write_domain is zero, this function adds in the
1231 * current read domains (CPU+COMMAND, 0).
1232 * flush_domains is set to CPU.
1233 * invalidate_domains is set to COMMAND
1234 * clflush is run to get data out of the CPU caches
1235 * then i915_dev_set_domain calls i915_gem_flush to
1236 * emit an MI_FLUSH and drm_agp_chipset_flush
1237 * 5. Unmapped from GTT
1238 * i915_gem_object_unbind calls set_domain (CPU, CPU)
1239 * flush_domains and invalidate_domains end up both zero
1240 * so no flushing/invalidating happens
1244 * Case 2: The shared render buffer
1248 * 3. Read/written by GPU
1249 * 4. set_domain to (CPU,CPU)
1250 * 5. Read/written by CPU
1251 * 6. Read/written by GPU
1254 * Same as last example, (CPU, CPU)
1256 * Nothing changes (assertions find that it is not in the GPU)
1257 * 3. Read/written by GPU
1258 * execbuffer calls set_domain (RENDER, RENDER)
1259 * flush_domains gets CPU
1260 * invalidate_domains gets GPU
1262 * MI_FLUSH and drm_agp_chipset_flush
1263 * 4. set_domain (CPU, CPU)
1264 * flush_domains gets GPU
1265 * invalidate_domains gets CPU
1266 * wait_rendering (obj) to make sure all drawing is complete.
1267 * This will include an MI_FLUSH to get the data from GPU
1269 * clflush (obj) to invalidate the CPU cache
1270 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1271 * 5. Read/written by CPU
1272 * cache lines are loaded and dirtied
1273 * 6. Read written by GPU
1274 * Same as last GPU access
1276 * Case 3: The constant buffer
1281 * 4. Updated (written) by CPU again
1290 * flush_domains = CPU
1291 * invalidate_domains = RENDER
1294 * drm_agp_chipset_flush
1295 * 4. Updated (written) by CPU again
1297 * flush_domains = 0 (no previous write domain)
1298 * invalidate_domains = 0 (no new read domains)
1301 * flush_domains = CPU
1302 * invalidate_domains = RENDER
1305 * drm_agp_chipset_flush
1308 i915_gem_object_set_domain(struct drm_gem_object *obj,
1309 uint32_t read_domains,
1310 uint32_t write_domain)
1312 struct drm_device *dev = obj->dev;
1313 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1314 uint32_t invalidate_domains = 0;
1315 uint32_t flush_domains = 0;
1319 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1321 obj->read_domains, read_domains,
1322 obj->write_domain, write_domain);
1325 * If the object isn't moving to a new write domain,
1326 * let the object stay in multiple read domains
1328 if (write_domain == 0)
1329 read_domains |= obj->read_domains;
1331 obj_priv->dirty = 1;
1334 * Flush the current write domain if
1335 * the new read domains don't match. Invalidate
1336 * any read domains which differ from the old
1339 if (obj->write_domain && obj->write_domain != read_domains) {
1340 flush_domains |= obj->write_domain;
1341 invalidate_domains |= read_domains & ~obj->write_domain;
1344 * Invalidate any read caches which may have
1345 * stale data. That is, any new read domains.
1347 invalidate_domains |= read_domains & ~obj->read_domains;
1348 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1350 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1351 __func__, flush_domains, invalidate_domains);
1354 * If we're invaliding the CPU cache and flushing a GPU cache,
1355 * then pause for rendering so that the GPU caches will be
1356 * flushed before the cpu cache is invalidated
1358 if ((invalidate_domains & I915_GEM_DOMAIN_CPU) &&
1359 (flush_domains & ~(I915_GEM_DOMAIN_CPU |
1360 I915_GEM_DOMAIN_GTT))) {
1361 ret = i915_gem_object_wait_rendering(obj);
1365 i915_gem_clflush_object(obj);
1368 if ((write_domain | flush_domains) != 0)
1369 obj->write_domain = write_domain;
1371 /* If we're invalidating the CPU domain, clear the per-page CPU
1372 * domain list as well.
1374 if (obj_priv->page_cpu_valid != NULL &&
1375 (write_domain != 0 ||
1376 read_domains & I915_GEM_DOMAIN_CPU)) {
1377 drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
1379 obj_priv->page_cpu_valid = NULL;
1381 obj->read_domains = read_domains;
1383 dev->invalidate_domains |= invalidate_domains;
1384 dev->flush_domains |= flush_domains;
1386 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1388 obj->read_domains, obj->write_domain,
1389 dev->invalidate_domains, dev->flush_domains);
1395 * Set the read/write domain on a range of the object.
1397 * Currently only implemented for CPU reads, otherwise drops to normal
1398 * i915_gem_object_set_domain().
1401 i915_gem_object_set_domain_range(struct drm_gem_object *obj,
1404 uint32_t read_domains,
1405 uint32_t write_domain)
1407 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1410 if (obj->read_domains & I915_GEM_DOMAIN_CPU)
1413 if (read_domains != I915_GEM_DOMAIN_CPU ||
1415 return i915_gem_object_set_domain(obj,
1416 read_domains, write_domain);
1418 /* Wait on any GPU rendering to the object to be flushed. */
1419 if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) {
1420 ret = i915_gem_object_wait_rendering(obj);
1425 if (obj_priv->page_cpu_valid == NULL) {
1426 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1430 /* Flush the cache on any pages that are still invalid from the CPU's
1433 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) {
1434 if (obj_priv->page_cpu_valid[i])
1437 drm_clflush_pages(obj_priv->page_list + i, 1);
1439 obj_priv->page_cpu_valid[i] = 1;
1446 * Once all of the objects have been set in the proper domain,
1447 * perform the necessary flush and invalidate operations.
1449 * Returns the write domains flushed, for use in flush tracking.
1452 i915_gem_dev_set_domain(struct drm_device *dev)
1454 uint32_t flush_domains = dev->flush_domains;
1457 * Now that all the buffers are synced to the proper domains,
1458 * flush and invalidate the collected domains
1460 if (dev->invalidate_domains | dev->flush_domains) {
1462 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
1464 dev->invalidate_domains,
1465 dev->flush_domains);
1468 dev->invalidate_domains,
1469 dev->flush_domains);
1470 dev->invalidate_domains = 0;
1471 dev->flush_domains = 0;
1474 return flush_domains;
1478 * Pin an object to the GTT and evaluate the relocations landing in it.
1481 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1482 struct drm_file *file_priv,
1483 struct drm_i915_gem_exec_object *entry)
1485 struct drm_device *dev = obj->dev;
1486 struct drm_i915_gem_relocation_entry reloc;
1487 struct drm_i915_gem_relocation_entry __user *relocs;
1488 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1490 uint32_t last_reloc_offset = -1;
1491 void __iomem *reloc_page = NULL;
1493 /* Choose the GTT offset for our buffer and put it there. */
1494 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1498 entry->offset = obj_priv->gtt_offset;
1500 relocs = (struct drm_i915_gem_relocation_entry __user *)
1501 (uintptr_t) entry->relocs_ptr;
1502 /* Apply the relocations, using the GTT aperture to avoid cache
1503 * flushing requirements.
1505 for (i = 0; i < entry->relocation_count; i++) {
1506 struct drm_gem_object *target_obj;
1507 struct drm_i915_gem_object *target_obj_priv;
1508 uint32_t reloc_val, reloc_offset;
1509 uint32_t __iomem *reloc_entry;
1511 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1513 i915_gem_object_unpin(obj);
1517 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1518 reloc.target_handle);
1519 if (target_obj == NULL) {
1520 i915_gem_object_unpin(obj);
1523 target_obj_priv = target_obj->driver_private;
1525 /* The target buffer should have appeared before us in the
1526 * exec_object list, so it should have a GTT space bound by now.
1528 if (target_obj_priv->gtt_space == NULL) {
1529 DRM_ERROR("No GTT space found for object %d\n",
1530 reloc.target_handle);
1531 drm_gem_object_unreference(target_obj);
1532 i915_gem_object_unpin(obj);
1536 if (reloc.offset > obj->size - 4) {
1537 DRM_ERROR("Relocation beyond object bounds: "
1538 "obj %p target %d offset %d size %d.\n",
1539 obj, reloc.target_handle,
1540 (int) reloc.offset, (int) obj->size);
1541 drm_gem_object_unreference(target_obj);
1542 i915_gem_object_unpin(obj);
1545 if (reloc.offset & 3) {
1546 DRM_ERROR("Relocation not 4-byte aligned: "
1547 "obj %p target %d offset %d.\n",
1548 obj, reloc.target_handle,
1549 (int) reloc.offset);
1550 drm_gem_object_unreference(target_obj);
1551 i915_gem_object_unpin(obj);
1555 if (reloc.write_domain && target_obj->pending_write_domain &&
1556 reloc.write_domain != target_obj->pending_write_domain) {
1557 DRM_ERROR("Write domain conflict: "
1558 "obj %p target %d offset %d "
1559 "new %08x old %08x\n",
1560 obj, reloc.target_handle,
1563 target_obj->pending_write_domain);
1564 drm_gem_object_unreference(target_obj);
1565 i915_gem_object_unpin(obj);
1570 DRM_INFO("%s: obj %p offset %08x target %d "
1571 "read %08x write %08x gtt %08x "
1572 "presumed %08x delta %08x\n",
1576 (int) reloc.target_handle,
1577 (int) reloc.read_domains,
1578 (int) reloc.write_domain,
1579 (int) target_obj_priv->gtt_offset,
1580 (int) reloc.presumed_offset,
1584 target_obj->pending_read_domains |= reloc.read_domains;
1585 target_obj->pending_write_domain |= reloc.write_domain;
1587 /* If the relocation already has the right value in it, no
1588 * more work needs to be done.
1590 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1591 drm_gem_object_unreference(target_obj);
1595 /* Now that we're going to actually write some data in,
1596 * make sure that any rendering using this buffer's contents
1599 i915_gem_object_wait_rendering(obj);
1601 /* As we're writing through the gtt, flush
1602 * any CPU writes before we write the relocations
1604 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
1605 i915_gem_clflush_object(obj);
1606 drm_agp_chipset_flush(dev);
1607 obj->write_domain = 0;
1610 /* Map the page containing the relocation we're going to
1613 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1614 if (reloc_page == NULL ||
1615 (last_reloc_offset & ~(PAGE_SIZE - 1)) !=
1616 (reloc_offset & ~(PAGE_SIZE - 1))) {
1617 if (reloc_page != NULL)
1618 iounmap(reloc_page);
1620 reloc_page = ioremap_wc(dev->agp->base +
1624 last_reloc_offset = reloc_offset;
1625 if (reloc_page == NULL) {
1626 drm_gem_object_unreference(target_obj);
1627 i915_gem_object_unpin(obj);
1632 reloc_entry = (uint32_t __iomem *)(reloc_page +
1633 (reloc_offset & (PAGE_SIZE - 1)));
1634 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1637 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1638 obj, (unsigned int) reloc.offset,
1639 readl(reloc_entry), reloc_val);
1641 writel(reloc_val, reloc_entry);
1643 /* Write the updated presumed offset for this entry back out
1646 reloc.presumed_offset = target_obj_priv->gtt_offset;
1647 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1649 drm_gem_object_unreference(target_obj);
1650 i915_gem_object_unpin(obj);
1654 drm_gem_object_unreference(target_obj);
1657 if (reloc_page != NULL)
1658 iounmap(reloc_page);
1662 i915_gem_dump_object(obj, 128, __func__, ~0);
1667 /** Dispatch a batchbuffer to the ring
1670 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1671 struct drm_i915_gem_execbuffer *exec,
1672 uint64_t exec_offset)
1674 drm_i915_private_t *dev_priv = dev->dev_private;
1675 struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1676 (uintptr_t) exec->cliprects_ptr;
1677 int nbox = exec->num_cliprects;
1679 uint32_t exec_start, exec_len;
1682 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1683 exec_len = (uint32_t) exec->batch_len;
1685 if ((exec_start | exec_len) & 0x7) {
1686 DRM_ERROR("alignment\n");
1693 count = nbox ? nbox : 1;
1695 for (i = 0; i < count; i++) {
1697 int ret = i915_emit_box(dev, boxes, i,
1698 exec->DR1, exec->DR4);
1703 if (IS_I830(dev) || IS_845G(dev)) {
1705 OUT_RING(MI_BATCH_BUFFER);
1706 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1707 OUT_RING(exec_start + exec_len - 4);
1712 if (IS_I965G(dev)) {
1713 OUT_RING(MI_BATCH_BUFFER_START |
1715 MI_BATCH_NON_SECURE_I965);
1716 OUT_RING(exec_start);
1718 OUT_RING(MI_BATCH_BUFFER_START |
1720 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1726 /* XXX breadcrumb */
1730 /* Throttle our rendering by waiting until the ring has completed our requests
1731 * emitted over 20 msec ago.
1733 * This should get us reasonable parallelism between CPU and GPU but also
1734 * relatively low latency when blocking on a particular request to finish.
1737 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1739 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1743 mutex_lock(&dev->struct_mutex);
1744 seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1745 i915_file_priv->mm.last_gem_throttle_seqno =
1746 i915_file_priv->mm.last_gem_seqno;
1748 ret = i915_wait_request(dev, seqno);
1749 mutex_unlock(&dev->struct_mutex);
1754 i915_gem_execbuffer(struct drm_device *dev, void *data,
1755 struct drm_file *file_priv)
1757 drm_i915_private_t *dev_priv = dev->dev_private;
1758 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1759 struct drm_i915_gem_execbuffer *args = data;
1760 struct drm_i915_gem_exec_object *exec_list = NULL;
1761 struct drm_gem_object **object_list = NULL;
1762 struct drm_gem_object *batch_obj;
1763 int ret, i, pinned = 0;
1764 uint64_t exec_offset;
1765 uint32_t seqno, flush_domains;
1768 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1769 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1772 if (args->buffer_count < 1) {
1773 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1776 /* Copy in the exec list from userland */
1777 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1779 object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1781 if (exec_list == NULL || object_list == NULL) {
1782 DRM_ERROR("Failed to allocate exec or object list "
1784 args->buffer_count);
1788 ret = copy_from_user(exec_list,
1789 (struct drm_i915_relocation_entry __user *)
1790 (uintptr_t) args->buffers_ptr,
1791 sizeof(*exec_list) * args->buffer_count);
1793 DRM_ERROR("copy %d exec entries failed %d\n",
1794 args->buffer_count, ret);
1798 mutex_lock(&dev->struct_mutex);
1800 i915_verify_inactive(dev, __FILE__, __LINE__);
1802 if (dev_priv->mm.wedged) {
1803 DRM_ERROR("Execbuf while wedged\n");
1804 mutex_unlock(&dev->struct_mutex);
1808 if (dev_priv->mm.suspended) {
1809 DRM_ERROR("Execbuf while VT-switched.\n");
1810 mutex_unlock(&dev->struct_mutex);
1814 /* Zero the gloabl flush/invalidate flags. These
1815 * will be modified as each object is bound to the
1818 dev->invalidate_domains = 0;
1819 dev->flush_domains = 0;
1821 /* Look up object handles and perform the relocations */
1822 for (i = 0; i < args->buffer_count; i++) {
1823 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1824 exec_list[i].handle);
1825 if (object_list[i] == NULL) {
1826 DRM_ERROR("Invalid object handle %d at index %d\n",
1827 exec_list[i].handle, i);
1832 object_list[i]->pending_read_domains = 0;
1833 object_list[i]->pending_write_domain = 0;
1834 ret = i915_gem_object_pin_and_relocate(object_list[i],
1838 DRM_ERROR("object bind and relocate failed %d\n", ret);
1844 /* Set the pending read domains for the batch buffer to COMMAND */
1845 batch_obj = object_list[args->buffer_count-1];
1846 batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1847 batch_obj->pending_write_domain = 0;
1849 i915_verify_inactive(dev, __FILE__, __LINE__);
1851 for (i = 0; i < args->buffer_count; i++) {
1852 struct drm_gem_object *obj = object_list[i];
1853 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1855 if (obj_priv->gtt_space == NULL) {
1856 /* We evicted the buffer in the process of validating
1857 * our set of buffers in. We could try to recover by
1858 * kicking them everything out and trying again from
1865 /* make sure all previous memory operations have passed */
1866 ret = i915_gem_object_set_domain(obj,
1867 obj->pending_read_domains,
1868 obj->pending_write_domain);
1873 i915_verify_inactive(dev, __FILE__, __LINE__);
1875 /* Flush/invalidate caches and chipset buffer */
1876 flush_domains = i915_gem_dev_set_domain(dev);
1878 i915_verify_inactive(dev, __FILE__, __LINE__);
1881 for (i = 0; i < args->buffer_count; i++) {
1882 i915_gem_object_check_coherency(object_list[i],
1883 exec_list[i].handle);
1887 exec_offset = exec_list[args->buffer_count - 1].offset;
1890 i915_gem_dump_object(object_list[args->buffer_count - 1],
1896 (void)i915_add_request(dev, flush_domains);
1898 /* Exec the batchbuffer */
1899 ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
1901 DRM_ERROR("dispatch failed %d\n", ret);
1906 * Ensure that the commands in the batch buffer are
1907 * finished before the interrupt fires
1909 flush_domains = i915_retire_commands(dev);
1911 i915_verify_inactive(dev, __FILE__, __LINE__);
1914 * Get a seqno representing the execution of the current buffer,
1915 * which we can wait on. We would like to mitigate these interrupts,
1916 * likely by only creating seqnos occasionally (so that we have
1917 * *some* interrupts representing completion of buffers that we can
1918 * wait on when trying to clear up gtt space).
1920 seqno = i915_add_request(dev, flush_domains);
1922 i915_file_priv->mm.last_gem_seqno = seqno;
1923 for (i = 0; i < args->buffer_count; i++) {
1924 struct drm_gem_object *obj = object_list[i];
1925 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1927 i915_gem_object_move_to_active(obj);
1928 obj_priv->last_rendering_seqno = seqno;
1930 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
1934 i915_dump_lru(dev, __func__);
1937 i915_verify_inactive(dev, __FILE__, __LINE__);
1939 /* Copy the new buffer offsets back to the user's exec list. */
1940 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1941 (uintptr_t) args->buffers_ptr,
1943 sizeof(*exec_list) * args->buffer_count);
1945 DRM_ERROR("failed to copy %d exec entries "
1946 "back to user (%d)\n",
1947 args->buffer_count, ret);
1949 if (object_list != NULL) {
1950 for (i = 0; i < pinned; i++)
1951 i915_gem_object_unpin(object_list[i]);
1953 for (i = 0; i < args->buffer_count; i++)
1954 drm_gem_object_unreference(object_list[i]);
1956 mutex_unlock(&dev->struct_mutex);
1959 drm_free(object_list, sizeof(*object_list) * args->buffer_count,
1961 drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
1968 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
1970 struct drm_device *dev = obj->dev;
1971 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1974 i915_verify_inactive(dev, __FILE__, __LINE__);
1975 if (obj_priv->gtt_space == NULL) {
1976 ret = i915_gem_object_bind_to_gtt(obj, alignment);
1978 DRM_ERROR("Failure to bind: %d", ret);
1982 obj_priv->pin_count++;
1984 /* If the object is not active and not pending a flush,
1985 * remove it from the inactive list
1987 if (obj_priv->pin_count == 1) {
1988 atomic_inc(&dev->pin_count);
1989 atomic_add(obj->size, &dev->pin_memory);
1990 if (!obj_priv->active &&
1991 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
1992 I915_GEM_DOMAIN_GTT)) == 0 &&
1993 !list_empty(&obj_priv->list))
1994 list_del_init(&obj_priv->list);
1996 i915_verify_inactive(dev, __FILE__, __LINE__);
2002 i915_gem_object_unpin(struct drm_gem_object *obj)
2004 struct drm_device *dev = obj->dev;
2005 drm_i915_private_t *dev_priv = dev->dev_private;
2006 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2008 i915_verify_inactive(dev, __FILE__, __LINE__);
2009 obj_priv->pin_count--;
2010 BUG_ON(obj_priv->pin_count < 0);
2011 BUG_ON(obj_priv->gtt_space == NULL);
2013 /* If the object is no longer pinned, and is
2014 * neither active nor being flushed, then stick it on
2017 if (obj_priv->pin_count == 0) {
2018 if (!obj_priv->active &&
2019 (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2020 I915_GEM_DOMAIN_GTT)) == 0)
2021 list_move_tail(&obj_priv->list,
2022 &dev_priv->mm.inactive_list);
2023 atomic_dec(&dev->pin_count);
2024 atomic_sub(obj->size, &dev->pin_memory);
2026 i915_verify_inactive(dev, __FILE__, __LINE__);
2030 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *file_priv)
2033 struct drm_i915_gem_pin *args = data;
2034 struct drm_gem_object *obj;
2035 struct drm_i915_gem_object *obj_priv;
2038 mutex_lock(&dev->struct_mutex);
2040 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2042 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2044 mutex_unlock(&dev->struct_mutex);
2047 obj_priv = obj->driver_private;
2049 ret = i915_gem_object_pin(obj, args->alignment);
2051 drm_gem_object_unreference(obj);
2052 mutex_unlock(&dev->struct_mutex);
2056 /* XXX - flush the CPU caches for pinned objects
2057 * as the X server doesn't manage domains yet
2059 if (obj->write_domain & I915_GEM_DOMAIN_CPU) {
2060 i915_gem_clflush_object(obj);
2061 drm_agp_chipset_flush(dev);
2062 obj->write_domain = 0;
2064 args->offset = obj_priv->gtt_offset;
2065 drm_gem_object_unreference(obj);
2066 mutex_unlock(&dev->struct_mutex);
2072 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2073 struct drm_file *file_priv)
2075 struct drm_i915_gem_pin *args = data;
2076 struct drm_gem_object *obj;
2078 mutex_lock(&dev->struct_mutex);
2080 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2082 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2084 mutex_unlock(&dev->struct_mutex);
2088 i915_gem_object_unpin(obj);
2090 drm_gem_object_unreference(obj);
2091 mutex_unlock(&dev->struct_mutex);
2096 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2097 struct drm_file *file_priv)
2099 struct drm_i915_gem_busy *args = data;
2100 struct drm_gem_object *obj;
2101 struct drm_i915_gem_object *obj_priv;
2103 mutex_lock(&dev->struct_mutex);
2104 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2106 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2108 mutex_unlock(&dev->struct_mutex);
2112 obj_priv = obj->driver_private;
2113 args->busy = obj_priv->active;
2115 drm_gem_object_unreference(obj);
2116 mutex_unlock(&dev->struct_mutex);
2121 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2122 struct drm_file *file_priv)
2124 return i915_gem_ring_throttle(dev, file_priv);
2127 int i915_gem_init_object(struct drm_gem_object *obj)
2129 struct drm_i915_gem_object *obj_priv;
2131 obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2132 if (obj_priv == NULL)
2136 * We've just allocated pages from the kernel,
2137 * so they've just been written by the CPU with
2138 * zeros. They'll need to be clflushed before we
2139 * use them with the GPU.
2141 obj->write_domain = I915_GEM_DOMAIN_CPU;
2142 obj->read_domains = I915_GEM_DOMAIN_CPU;
2144 obj->driver_private = obj_priv;
2145 obj_priv->obj = obj;
2146 INIT_LIST_HEAD(&obj_priv->list);
2150 void i915_gem_free_object(struct drm_gem_object *obj)
2152 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2154 while (obj_priv->pin_count > 0)
2155 i915_gem_object_unpin(obj);
2157 i915_gem_object_unbind(obj);
2159 drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2160 drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2164 i915_gem_set_domain(struct drm_gem_object *obj,
2165 struct drm_file *file_priv,
2166 uint32_t read_domains,
2167 uint32_t write_domain)
2169 struct drm_device *dev = obj->dev;
2171 uint32_t flush_domains;
2173 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
2175 ret = i915_gem_object_set_domain(obj, read_domains, write_domain);
2178 flush_domains = i915_gem_dev_set_domain(obj->dev);
2180 if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT))
2181 (void) i915_add_request(dev, flush_domains);
2186 /** Unbinds all objects that are on the given buffer list. */
2188 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2190 struct drm_gem_object *obj;
2191 struct drm_i915_gem_object *obj_priv;
2194 while (!list_empty(head)) {
2195 obj_priv = list_first_entry(head,
2196 struct drm_i915_gem_object,
2198 obj = obj_priv->obj;
2200 if (obj_priv->pin_count != 0) {
2201 DRM_ERROR("Pinned object in unbind list\n");
2202 mutex_unlock(&dev->struct_mutex);
2206 ret = i915_gem_object_unbind(obj);
2208 DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2210 mutex_unlock(&dev->struct_mutex);
2220 i915_gem_idle(struct drm_device *dev)
2222 drm_i915_private_t *dev_priv = dev->dev_private;
2223 uint32_t seqno, cur_seqno, last_seqno;
2226 if (dev_priv->mm.suspended)
2229 /* Hack! Don't let anybody do execbuf while we don't control the chip.
2230 * We need to replace this with a semaphore, or something.
2232 dev_priv->mm.suspended = 1;
2234 i915_kernel_lost_context(dev);
2236 /* Flush the GPU along with all non-CPU write domains
2238 i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2239 ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2240 seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2241 I915_GEM_DOMAIN_GTT));
2244 mutex_unlock(&dev->struct_mutex);
2248 dev_priv->mm.waiting_gem_seqno = seqno;
2252 cur_seqno = i915_get_gem_seqno(dev);
2253 if (i915_seqno_passed(cur_seqno, seqno))
2255 if (last_seqno == cur_seqno) {
2256 if (stuck++ > 100) {
2257 DRM_ERROR("hardware wedged\n");
2258 dev_priv->mm.wedged = 1;
2259 DRM_WAKEUP(&dev_priv->irq_queue);
2264 last_seqno = cur_seqno;
2266 dev_priv->mm.waiting_gem_seqno = 0;
2268 i915_gem_retire_requests(dev);
2270 /* Active and flushing should now be empty as we've
2271 * waited for a sequence higher than any pending execbuffer
2273 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2274 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2276 /* Request should now be empty as we've also waited
2277 * for the last request in the list
2279 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2281 /* Move all buffers out of the GTT. */
2282 ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2286 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2287 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2288 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2289 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2294 i915_gem_init_hws(struct drm_device *dev)
2296 drm_i915_private_t *dev_priv = dev->dev_private;
2297 struct drm_gem_object *obj;
2298 struct drm_i915_gem_object *obj_priv;
2301 /* If we need a physical address for the status page, it's already
2302 * initialized at driver load time.
2304 if (!I915_NEED_GFX_HWS(dev))
2307 obj = drm_gem_object_alloc(dev, 4096);
2309 DRM_ERROR("Failed to allocate status page\n");
2312 obj_priv = obj->driver_private;
2314 ret = i915_gem_object_pin(obj, 4096);
2316 drm_gem_object_unreference(obj);
2320 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2321 dev_priv->hws_map.offset = dev->agp->base + obj_priv->gtt_offset;
2322 dev_priv->hws_map.size = 4096;
2323 dev_priv->hws_map.type = 0;
2324 dev_priv->hws_map.flags = 0;
2325 dev_priv->hws_map.mtrr = 0;
2327 /* Ioremapping here is the wrong thing to do. We want cached access.
2329 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
2330 if (dev_priv->hws_map.handle == NULL) {
2331 DRM_ERROR("Failed to map status page.\n");
2332 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2333 drm_gem_object_unreference(obj);
2336 dev_priv->hws_obj = obj;
2337 dev_priv->hw_status_page = dev_priv->hws_map.handle;
2338 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2339 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2340 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2346 i915_gem_init_ringbuffer(struct drm_device *dev)
2348 drm_i915_private_t *dev_priv = dev->dev_private;
2349 struct drm_gem_object *obj;
2350 struct drm_i915_gem_object *obj_priv;
2353 ret = i915_gem_init_hws(dev);
2357 obj = drm_gem_object_alloc(dev, 128 * 1024);
2359 DRM_ERROR("Failed to allocate ringbuffer\n");
2362 obj_priv = obj->driver_private;
2364 ret = i915_gem_object_pin(obj, 4096);
2366 drm_gem_object_unreference(obj);
2370 /* Set up the kernel mapping for the ring. */
2371 dev_priv->ring.Size = obj->size;
2372 dev_priv->ring.tail_mask = obj->size - 1;
2374 dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2375 dev_priv->ring.map.size = obj->size;
2376 dev_priv->ring.map.type = 0;
2377 dev_priv->ring.map.flags = 0;
2378 dev_priv->ring.map.mtrr = 0;
2380 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
2381 if (dev_priv->ring.map.handle == NULL) {
2382 DRM_ERROR("Failed to map ringbuffer.\n");
2383 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2384 drm_gem_object_unreference(obj);
2387 dev_priv->ring.ring_obj = obj;
2388 dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2390 /* Stop the ring if it's running. */
2391 I915_WRITE(PRB0_CTL, 0);
2392 I915_WRITE(PRB0_HEAD, 0);
2393 I915_WRITE(PRB0_TAIL, 0);
2394 I915_WRITE(PRB0_START, 0);
2396 /* Initialize the ring. */
2397 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2398 I915_WRITE(PRB0_CTL,
2399 ((obj->size - 4096) & RING_NR_PAGES) |
2403 /* Update our cache of the ring state */
2404 i915_kernel_lost_context(dev);
2410 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2412 drm_i915_private_t *dev_priv = dev->dev_private;
2414 if (dev_priv->ring.ring_obj == NULL)
2417 drm_core_ioremapfree(&dev_priv->ring.map, dev);
2419 i915_gem_object_unpin(dev_priv->ring.ring_obj);
2420 drm_gem_object_unreference(dev_priv->ring.ring_obj);
2421 dev_priv->ring.ring_obj = NULL;
2422 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2424 if (dev_priv->hws_obj != NULL) {
2425 i915_gem_object_unpin(dev_priv->hws_obj);
2426 drm_gem_object_unreference(dev_priv->hws_obj);
2427 dev_priv->hws_obj = NULL;
2428 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2430 /* Write high address into HWS_PGA when disabling. */
2431 I915_WRITE(HWS_PGA, 0x1ffff000);
2436 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2437 struct drm_file *file_priv)
2439 drm_i915_private_t *dev_priv = dev->dev_private;
2442 if (dev_priv->mm.wedged) {
2443 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2444 dev_priv->mm.wedged = 0;
2447 ret = i915_gem_init_ringbuffer(dev);
2451 mutex_lock(&dev->struct_mutex);
2452 BUG_ON(!list_empty(&dev_priv->mm.active_list));
2453 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2454 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2455 BUG_ON(!list_empty(&dev_priv->mm.request_list));
2456 dev_priv->mm.suspended = 0;
2457 mutex_unlock(&dev->struct_mutex);
2459 drm_irq_install(dev);
2465 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2466 struct drm_file *file_priv)
2470 mutex_lock(&dev->struct_mutex);
2471 ret = i915_gem_idle(dev);
2473 i915_gem_cleanup_ringbuffer(dev);
2474 mutex_unlock(&dev->struct_mutex);
2476 drm_irq_uninstall(dev);
2482 i915_gem_lastclose(struct drm_device *dev)
2485 drm_i915_private_t *dev_priv = dev->dev_private;
2487 mutex_lock(&dev->struct_mutex);
2489 if (dev_priv->ring.ring_obj != NULL) {
2490 ret = i915_gem_idle(dev);
2492 DRM_ERROR("failed to idle hardware: %d\n", ret);
2494 i915_gem_cleanup_ringbuffer(dev);
2497 mutex_unlock(&dev->struct_mutex);
2501 i915_gem_load(struct drm_device *dev)
2503 drm_i915_private_t *dev_priv = dev->dev_private;
2505 INIT_LIST_HEAD(&dev_priv->mm.active_list);
2506 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2507 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2508 INIT_LIST_HEAD(&dev_priv->mm.request_list);
2509 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2510 i915_gem_retire_work_handler);
2511 INIT_WORK(&dev_priv->mm.vblank_work,
2512 i915_gem_vblank_work_handler);
2513 dev_priv->mm.next_gem_seqno = 1;
2515 i915_gem_detect_bit_6_swizzle(dev);