drivers/gpu/drm/i915/i915_gem.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *
  26  */
  27
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "i915_drm.h"
  31 #include "i915_drv.h"
  32 #include <linux/swap.h>
  33
  34 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  35
  36 static void
  37 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
  38                                   uint32_t read_domains,
  39                                   uint32_t write_domain);
  40 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
  41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
  42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
  43 static int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
  44                                              int write);
  45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
  46                                              int write);
  47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
  48                                                      uint64_t offset,
  49                                                      uint64_t size);
  50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
  51 static int i915_gem_object_get_page_list(struct drm_gem_object *obj);
  52 static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
  53 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
  54
  55 static void
  56 i915_gem_cleanup_ringbuffer(struct drm_device *dev);
  57
  58 int
  59 i915_gem_init_ioctl(struct drm_device *dev, void *data,
  60                     struct drm_file *file_priv)
  61 {
  62         drm_i915_private_t *dev_priv = dev->dev_private;
  63         struct drm_i915_gem_init *args = data;
  64
  65         mutex_lock(&dev->struct_mutex);
  66
  67         if (args->gtt_start >= args->gtt_end ||
  68             (args->gtt_start & (PAGE_SIZE - 1)) != 0 ||
  69             (args->gtt_end & (PAGE_SIZE - 1)) != 0) {
  70                 mutex_unlock(&dev->struct_mutex);
  71                 return -EINVAL;
  72         }
  73
  74         drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start,
  75             args->gtt_end - args->gtt_start);
  76
  77         dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start);
  78
  79         mutex_unlock(&dev->struct_mutex);
  80
  81         return 0;
  82 }
  83
  84 int
  85 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
  86                             struct drm_file *file_priv)
  87 {
  88         struct drm_i915_gem_get_aperture *args = data;
  89
  90         if (!(dev->driver->driver_features & DRIVER_GEM))
  91                 return -ENODEV;
  92
  93         args->aper_size = dev->gtt_total;
  94         args->aper_available_size = (args->aper_size -
  95                                      atomic_read(&dev->pin_memory));
  96
  97         return 0;
  98 }
  99
 100
 101 /**
 102  * Creates a new mm object and returns a handle to it.
 103  */
 104 int
 105 i915_gem_create_ioctl(struct drm_device *dev, void *data,
 106                       struct drm_file *file_priv)
 107 {
 108         struct drm_i915_gem_create *args = data;
 109         struct drm_gem_object *obj;
 110         int handle, ret;
 111
 112         args->size = roundup(args->size, PAGE_SIZE);
 113
 114         /* Allocate the new object */
 115         obj = drm_gem_object_alloc(dev, args->size);
 116         if (obj == NULL)
 117                 return -ENOMEM;
 118
 119         ret = drm_gem_handle_create(file_priv, obj, &handle);
 120         mutex_lock(&dev->struct_mutex);
 121         drm_gem_object_handle_unreference(obj);
 122         mutex_unlock(&dev->struct_mutex);
 123
 124         if (ret)
 125                 return ret;
 126
 127         args->handle = handle;
 128
 129         return 0;
 130 }
 131
 132 /**
 133  * Reads data from the object referenced by handle.
 134  *
 135  * On error, the contents of *data are undefined.
 136  */
 137 int
 138 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 139                      struct drm_file *file_priv)
 140 {
 141         struct drm_i915_gem_pread *args = data;
 142         struct drm_gem_object *obj;
 143         struct drm_i915_gem_object *obj_priv;
 144         ssize_t read;
 145         loff_t offset;
 146         int ret;
 147
 148         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 149         if (obj == NULL)
 150                 return -EBADF;
 151         obj_priv = obj->driver_private;
 152
 153         /* Bounds check source.
 154          *
 155          * XXX: This could use review for overflow issues...
 156          */
 157         if (args->offset > obj->size || args->size > obj->size ||
 158             args->offset + args->size > obj->size) {
 159                 drm_gem_object_unreference(obj);
 160                 return -EINVAL;
 161         }
 162
 163         mutex_lock(&dev->struct_mutex);
 164
 165         ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
 166                                                         args->size);
 167         if (ret != 0) {
 168                 drm_gem_object_unreference(obj);
 169                 mutex_unlock(&dev->struct_mutex);
 170                 return ret;
 171         }
 172
 173         offset = args->offset;
 174
 175         read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr,
 176                         args->size, &offset);
 177         if (read != args->size) {
 178                 drm_gem_object_unreference(obj);
 179                 mutex_unlock(&dev->struct_mutex);
 180                 if (read < 0)
 181                         return read;
 182                 else
 183                         return -EINVAL;
 184         }
 185
 186         drm_gem_object_unreference(obj);
 187         mutex_unlock(&dev->struct_mutex);
 188
 189         return 0;
 190 }
 191
 192 /* This is the fast write path which cannot handle
 193  * page faults in the source data
 194  */
 195
 196 static inline int
 197 fast_user_write(struct io_mapping *mapping,
 198                 loff_t page_base, int page_offset,
 199                 char __user *user_data,
 200                 int length)
 201 {
 202         char *vaddr_atomic;
 203         unsigned long unwritten;
 204
 205         vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
 206         unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
 207                                                       user_data, length);
 208         io_mapping_unmap_atomic(vaddr_atomic);
 209         if (unwritten)
 210                 return -EFAULT;
 211         return 0;
 212 }
 213
 214 /* Here's the write path which can sleep for
 215  * page faults
 216  */
 217
 218 static inline int
 219 slow_user_write(struct io_mapping *mapping,
 220                 loff_t page_base, int page_offset,
 221                 char __user *user_data,
 222                 int length)
 223 {
 224         char __iomem *vaddr;
 225         unsigned long unwritten;
 226
 227         vaddr = io_mapping_map_wc(mapping, page_base);
 228         if (vaddr == NULL)
 229                 return -EFAULT;
 230         unwritten = __copy_from_user(vaddr + page_offset,
 231                                      user_data, length);
 232         io_mapping_unmap(vaddr);
 233         if (unwritten)
 234                 return -EFAULT;
 235         return 0;
 236 }
 237
 238 static int
 239 i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 240                     struct drm_i915_gem_pwrite *args,
 241                     struct drm_file *file_priv)
 242 {
 243         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 244         drm_i915_private_t *dev_priv = dev->dev_private;
 245         ssize_t remain;
 246         loff_t offset, page_base;
 247         char __user *user_data;
 248         int page_offset, page_length;
 249         int ret;
 250
 251         user_data = (char __user *) (uintptr_t) args->data_ptr;
 252         remain = args->size;
 253         if (!access_ok(VERIFY_READ, user_data, remain))
 254                 return -EFAULT;
 255
 256
 257         mutex_lock(&dev->struct_mutex);
 258         ret = i915_gem_object_pin(obj, 0);
 259         if (ret) {
 260                 mutex_unlock(&dev->struct_mutex);
 261                 return ret;
 262         }
 263         ret = i915_gem_object_set_to_gtt_domain(obj, 1);
 264         if (ret)
 265                 goto fail;
 266
 267         obj_priv = obj->driver_private;
 268         offset = obj_priv->gtt_offset + args->offset;
 269         obj_priv->dirty = 1;
 270
 271         while (remain > 0) {
 272                 /* Operation in this page
 273                  *
 274                  * page_base = page offset within aperture
 275                  * page_offset = offset within page
 276                  * page_length = bytes to copy for this page
 277                  */
 278                 page_base = (offset & ~(PAGE_SIZE-1));
 279                 page_offset = offset & (PAGE_SIZE-1);
 280                 page_length = remain;
 281                 if ((page_offset + remain) > PAGE_SIZE)
 282                         page_length = PAGE_SIZE - page_offset;
 283
 284                 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
 285                                        page_offset, user_data, page_length);
 286
 287                 /* If we get a fault while copying data, then (presumably) our
 288                  * source page isn't available. In this case, use the
 289                  * non-atomic function
 290                  */
 291                 if (ret) {
 292                         ret = slow_user_write (dev_priv->mm.gtt_mapping,
 293                                                page_base, page_offset,
 294                                                user_data, page_length);
 295                         if (ret)
 296                                 goto fail;
 297                 }
 298
 299                 remain -= page_length;
 300                 user_data += page_length;
 301                 offset += page_length;
 302         }
 303
 304 fail:
 305         i915_gem_object_unpin(obj);
 306         mutex_unlock(&dev->struct_mutex);
 307
 308         return ret;
 309 }
 310
 311 static int
 312 i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
 313                       struct drm_i915_gem_pwrite *args,
 314                       struct drm_file *file_priv)
 315 {
 316         int ret;
 317         loff_t offset;
 318         ssize_t written;
 319
 320         mutex_lock(&dev->struct_mutex);
 321
 322         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 323         if (ret) {
 324                 mutex_unlock(&dev->struct_mutex);
 325                 return ret;
 326         }
 327
 328         offset = args->offset;
 329
 330         written = vfs_write(obj->filp,
 331                             (char __user *)(uintptr_t) args->data_ptr,
 332                             args->size, &offset);
 333         if (written != args->size) {
 334                 mutex_unlock(&dev->struct_mutex);
 335                 if (written < 0)
 336                         return written;
 337                 else
 338                         return -EINVAL;
 339         }
 340
 341         mutex_unlock(&dev->struct_mutex);
 342
 343         return 0;
 344 }
 345
 346 /**
 347  * Writes data to the object referenced by handle.
 348  *
 349  * On error, the contents of the buffer that were to be modified are undefined.
 350  */
 351 int
 352 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 353                       struct drm_file *file_priv)
 354 {
 355         struct drm_i915_gem_pwrite *args = data;
 356         struct drm_gem_object *obj;
 357         struct drm_i915_gem_object *obj_priv;
 358         int ret = 0;
 359
 360         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 361         if (obj == NULL)
 362                 return -EBADF;
 363         obj_priv = obj->driver_private;
 364
 365         /* Bounds check destination.
 366          *
 367          * XXX: This could use review for overflow issues...
 368          */
 369         if (args->offset > obj->size || args->size > obj->size ||
 370             args->offset + args->size > obj->size) {
 371                 drm_gem_object_unreference(obj);
 372                 return -EINVAL;
 373         }
 374
 375         /* We can only do the GTT pwrite on untiled buffers, as otherwise
 376          * it would end up going through the fenced access, and we'll get
 377          * different detiling behavior between reading and writing.
 378          * pread/pwrite currently are reading and writing from the CPU
 379          * perspective, requiring manual detiling by the client.
 380          */
 381         if (obj_priv->tiling_mode == I915_TILING_NONE &&
 382             dev->gtt_total != 0)
 383                 ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv);
 384         else
 385                 ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv);
 386
 387 #if WATCH_PWRITE
 388         if (ret)
 389                 DRM_INFO("pwrite failed %d\n", ret);
 390 #endif
 391
 392         drm_gem_object_unreference(obj);
 393
 394         return ret;
 395 }
 396
 397 /**
 398  * Called when user space prepares to use an object with the CPU, either
 399  * through the mmap ioctl's mapping or a GTT mapping.
 400  */
 401 int
 402 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 403                           struct drm_file *file_priv)
 404 {
 405         struct drm_i915_gem_set_domain *args = data;
 406         struct drm_gem_object *obj;
 407         uint32_t read_domains = args->read_domains;
 408         uint32_t write_domain = args->write_domain;
 409         int ret;
 410
 411         if (!(dev->driver->driver_features & DRIVER_GEM))
 412                 return -ENODEV;
 413
 414         /* Only handle setting domains to types used by the CPU. */
 415         if (write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 416                 return -EINVAL;
 417
 418         if (read_domains & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
 419                 return -EINVAL;
 420
 421         /* Having something in the write domain implies it's in the read
 422          * domain, and only that read domain.  Enforce that in the request.
 423          */
 424         if (write_domain != 0 && read_domains != write_domain)
 425                 return -EINVAL;
 426
 427         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 428         if (obj == NULL)
 429                 return -EBADF;
 430
 431         mutex_lock(&dev->struct_mutex);
 432 #if WATCH_BUF
 433         DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n",
 434                  obj, obj->size, read_domains, write_domain);
 435 #endif
 436         if (read_domains & I915_GEM_DOMAIN_GTT) {
 437                 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
 438         } else {
 439                 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
 440         }
 441
 442         drm_gem_object_unreference(obj);
 443         mutex_unlock(&dev->struct_mutex);
 444         return ret;
 445 }
 446
 447 /**
 448  * Called when user space has done writes to this buffer
 449  */
 450 int
 451 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 452                       struct drm_file *file_priv)
 453 {
 454         struct drm_i915_gem_sw_finish *args = data;
 455         struct drm_gem_object *obj;
 456         struct drm_i915_gem_object *obj_priv;
 457         int ret = 0;
 458
 459         if (!(dev->driver->driver_features & DRIVER_GEM))
 460                 return -ENODEV;
 461
 462         mutex_lock(&dev->struct_mutex);
 463         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 464         if (obj == NULL) {
 465                 mutex_unlock(&dev->struct_mutex);
 466                 return -EBADF;
 467         }
 468
 469 #if WATCH_BUF
 470         DRM_INFO("%s: sw_finish %d (%p %d)\n",
 471                  __func__, args->handle, obj, obj->size);
 472 #endif
 473         obj_priv = obj->driver_private;
 474
 475         /* Pinned buffers may be scanout, so flush the cache */
 476         if (obj_priv->pin_count)
 477                 i915_gem_object_flush_cpu_write_domain(obj);
 478
 479         drm_gem_object_unreference(obj);
 480         mutex_unlock(&dev->struct_mutex);
 481         return ret;
 482 }
 483
 484 /**
 485  * Maps the contents of an object, returning the address it is mapped
 486  * into.
 487  *
 488  * While the mapping holds a reference on the contents of the object, it doesn't
 489  * imply a ref on the object itself.
 490  */
 491 int
 492 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 493                    struct drm_file *file_priv)
 494 {
 495         struct drm_i915_gem_mmap *args = data;
 496         struct drm_gem_object *obj;
 497         loff_t offset;
 498         unsigned long addr;
 499
 500         if (!(dev->driver->driver_features & DRIVER_GEM))
 501                 return -ENODEV;
 502
 503         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
 504         if (obj == NULL)
 505                 return -EBADF;
 506
 507         offset = args->offset;
 508
 509         down_write(&current->mm->mmap_sem);
 510         addr = do_mmap(obj->filp, 0, args->size,
 511                        PROT_READ | PROT_WRITE, MAP_SHARED,
 512                        args->offset);
 513         up_write(&current->mm->mmap_sem);
 514         mutex_lock(&dev->struct_mutex);
 515         drm_gem_object_unreference(obj);
 516         mutex_unlock(&dev->struct_mutex);
 517         if (IS_ERR((void *)addr))
 518                 return addr;
 519
 520         args->addr_ptr = (uint64_t) addr;
 521
 522         return 0;
 523 }
 524
 525 static void
 526 i915_gem_object_free_page_list(struct drm_gem_object *obj)
 527 {
 528         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 529         int page_count = obj->size / PAGE_SIZE;
 530         int i;
 531
 532         if (obj_priv->page_list == NULL)
 533                 return;
 534
 535
 536         for (i = 0; i < page_count; i++)
 537                 if (obj_priv->page_list[i] != NULL) {
 538                         if (obj_priv->dirty)
 539                                 set_page_dirty(obj_priv->page_list[i]);
 540                         mark_page_accessed(obj_priv->page_list[i]);
 541                         page_cache_release(obj_priv->page_list[i]);
 542                 }
 543         obj_priv->dirty = 0;
 544
 545         drm_free(obj_priv->page_list,
 546                  page_count * sizeof(struct page *),
 547                  DRM_MEM_DRIVER);
 548         obj_priv->page_list = NULL;
 549 }
 550
 551 static void
 552 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
 553 {
 554         struct drm_device *dev = obj->dev;
 555         drm_i915_private_t *dev_priv = dev->dev_private;
 556         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 557
 558         /* Add a reference if we're newly entering the active list. */
 559         if (!obj_priv->active) {
 560                 drm_gem_object_reference(obj);
 561                 obj_priv->active = 1;
 562         }
 563         /* Move from whatever list we were on to the tail of execution. */
 564         list_move_tail(&obj_priv->list,
 565                        &dev_priv->mm.active_list);
 566         obj_priv->last_rendering_seqno = seqno;
 567 }
 568
 569 static void
 570 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
 571 {
 572         struct drm_device *dev = obj->dev;
 573         drm_i915_private_t *dev_priv = dev->dev_private;
 574         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 575
 576         BUG_ON(!obj_priv->active);
 577         list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
 578         obj_priv->last_rendering_seqno = 0;
 579 }
 580
 581 static void
 582 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
 583 {
 584         struct drm_device *dev = obj->dev;
 585         drm_i915_private_t *dev_priv = dev->dev_private;
 586         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 587
 588         i915_verify_inactive(dev, __FILE__, __LINE__);
 589         if (obj_priv->pin_count != 0)
 590                 list_del_init(&obj_priv->list);
 591         else
 592                 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
 593
 594         obj_priv->last_rendering_seqno = 0;
 595         if (obj_priv->active) {
 596                 obj_priv->active = 0;
 597                 drm_gem_object_unreference(obj);
 598         }
 599         i915_verify_inactive(dev, __FILE__, __LINE__);
 600 }
 601
 602 /**
 603  * Creates a new sequence number, emitting a write of it to the status page
 604  * plus an interrupt, which will trigger i915_user_interrupt_handler.
 605  *
 606  * Must be called with struct_lock held.
 607  *
 608  * Returned sequence numbers are nonzero on success.
 609  */
 610 static uint32_t
 611 i915_add_request(struct drm_device *dev, uint32_t flush_domains)
 612 {
 613         drm_i915_private_t *dev_priv = dev->dev_private;
 614         struct drm_i915_gem_request *request;
 615         uint32_t seqno;
 616         int was_empty;
 617         RING_LOCALS;
 618
 619         request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER);
 620         if (request == NULL)
 621                 return 0;
 622
 623         /* Grab the seqno we're going to make this request be, and bump the
 624          * next (skipping 0 so it can be the reserved no-seqno value).
 625          */
 626         seqno = dev_priv->mm.next_gem_seqno;
 627         dev_priv->mm.next_gem_seqno++;
 628         if (dev_priv->mm.next_gem_seqno == 0)
 629                 dev_priv->mm.next_gem_seqno++;
 630
 631         BEGIN_LP_RING(4);
 632         OUT_RING(MI_STORE_DWORD_INDEX);
 633         OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 634         OUT_RING(seqno);
 635
 636         OUT_RING(MI_USER_INTERRUPT);
 637         ADVANCE_LP_RING();
 638
 639         DRM_DEBUG("%d\n", seqno);
 640
 641         request->seqno = seqno;
 642         request->emitted_jiffies = jiffies;
 643         was_empty = list_empty(&dev_priv->mm.request_list);
 644         list_add_tail(&request->list, &dev_priv->mm.request_list);
 645
 646         /* Associate any objects on the flushing list matching the write
 647          * domain we're flushing with our flush.
 648          */
 649         if (flush_domains != 0) {
 650                 struct drm_i915_gem_object *obj_priv, *next;
 651
 652                 list_for_each_entry_safe(obj_priv, next,
 653                                          &dev_priv->mm.flushing_list, list) {
 654                         struct drm_gem_object *obj = obj_priv->obj;
 655
 656                         if ((obj->write_domain & flush_domains) ==
 657                             obj->write_domain) {
 658                                 obj->write_domain = 0;
 659                                 i915_gem_object_move_to_active(obj, seqno);
 660                         }
 661                 }
 662
 663         }
 664
 665         if (was_empty && !dev_priv->mm.suspended)
 666                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 667         return seqno;
 668 }
 669
 670 /**
 671  * Command execution barrier
 672  *
 673  * Ensures that all commands in the ring are finished
 674  * before signalling the CPU
 675  */
 676 static uint32_t
 677 i915_retire_commands(struct drm_device *dev)
 678 {
 679         drm_i915_private_t *dev_priv = dev->dev_private;
 680         uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 681         uint32_t flush_domains = 0;
 682         RING_LOCALS;
 683
 684         /* The sampler always gets flushed on i965 (sigh) */
 685         if (IS_I965G(dev))
 686                 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
 687         BEGIN_LP_RING(2);
 688         OUT_RING(cmd);
 689         OUT_RING(0); /* noop */
 690         ADVANCE_LP_RING();
 691         return flush_domains;
 692 }
 693
 694 /**
 695  * Moves buffers associated only with the given active seqno from the active
 696  * to inactive list, potentially freeing them.
 697  */
 698 static void
 699 i915_gem_retire_request(struct drm_device *dev,
 700                         struct drm_i915_gem_request *request)
 701 {
 702         drm_i915_private_t *dev_priv = dev->dev_private;
 703
 704         /* Move any buffers on the active list that are no longer referenced
 705          * by the ringbuffer to the flushing/inactive lists as appropriate.
 706          */
 707         while (!list_empty(&dev_priv->mm.active_list)) {
 708                 struct drm_gem_object *obj;
 709                 struct drm_i915_gem_object *obj_priv;
 710
 711                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
 712                                             struct drm_i915_gem_object,
 713                                             list);
 714                 obj = obj_priv->obj;
 715
 716                 /* If the seqno being retired doesn't match the oldest in the
 717                  * list, then the oldest in the list must still be newer than
 718                  * this seqno.
 719                  */
 720                 if (obj_priv->last_rendering_seqno != request->seqno)
 721                         return;
 722 #if WATCH_LRU
 723                 DRM_INFO("%s: retire %d moves to inactive list %p\n",
 724                          __func__, request->seqno, obj);
 725 #endif
 726
 727                 if (obj->write_domain != 0)
 728                         i915_gem_object_move_to_flushing(obj);
 729                 else
 730                         i915_gem_object_move_to_inactive(obj);
 731         }
 732 }
 733
 734 /**
 735  * Returns true if seq1 is later than seq2.
 736  */
 737 static int
 738 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
 739 {
 740         return (int32_t)(seq1 - seq2) >= 0;
 741 }
 742
 743 uint32_t
 744 i915_get_gem_seqno(struct drm_device *dev)
 745 {
 746         drm_i915_private_t *dev_priv = dev->dev_private;
 747
 748         return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
 749 }
 750
 751 /**
 752  * This function clears the request list as sequence numbers are passed.
 753  */
 754 void
 755 i915_gem_retire_requests(struct drm_device *dev)
 756 {
 757         drm_i915_private_t *dev_priv = dev->dev_private;
 758         uint32_t seqno;
 759
 760         seqno = i915_get_gem_seqno(dev);
 761
 762         while (!list_empty(&dev_priv->mm.request_list)) {
 763                 struct drm_i915_gem_request *request;
 764                 uint32_t retiring_seqno;
 765
 766                 request = list_first_entry(&dev_priv->mm.request_list,
 767                                            struct drm_i915_gem_request,
 768                                            list);
 769                 retiring_seqno = request->seqno;
 770
 771                 if (i915_seqno_passed(seqno, retiring_seqno) ||
 772                     dev_priv->mm.wedged) {
 773                         i915_gem_retire_request(dev, request);
 774
 775                         list_del(&request->list);
 776                         drm_free(request, sizeof(*request), DRM_MEM_DRIVER);
 777                 } else
 778                         break;
 779         }
 780 }
 781
 782 void
 783 i915_gem_retire_work_handler(struct work_struct *work)
 784 {
 785         drm_i915_private_t *dev_priv;
 786         struct drm_device *dev;
 787
 788         dev_priv = container_of(work, drm_i915_private_t,
 789                                 mm.retire_work.work);
 790         dev = dev_priv->dev;
 791
 792         mutex_lock(&dev->struct_mutex);
 793         i915_gem_retire_requests(dev);
 794         if (!dev_priv->mm.suspended &&
 795             !list_empty(&dev_priv->mm.request_list))
 796                 schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
 797         mutex_unlock(&dev->struct_mutex);
 798 }
 799
 800 /**
 801  * Waits for a sequence number to be signaled, and cleans up the
 802  * request and object lists appropriately for that event.
 803  */
 804 static int
 805 i915_wait_request(struct drm_device *dev, uint32_t seqno)
 806 {
 807         drm_i915_private_t *dev_priv = dev->dev_private;
 808         int ret = 0;
 809
 810         BUG_ON(seqno == 0);
 811
 812         if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
 813                 dev_priv->mm.waiting_gem_seqno = seqno;
 814                 i915_user_irq_get(dev);
 815                 ret = wait_event_interruptible(dev_priv->irq_queue,
 816                                                i915_seqno_passed(i915_get_gem_seqno(dev),
 817                                                                  seqno) ||
 818                                                dev_priv->mm.wedged);
 819                 i915_user_irq_put(dev);
 820                 dev_priv->mm.waiting_gem_seqno = 0;
 821         }
 822         if (dev_priv->mm.wedged)
 823                 ret = -EIO;
 824
 825         if (ret && ret != -ERESTARTSYS)
 826                 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
 827                           __func__, ret, seqno, i915_get_gem_seqno(dev));
 828
 829         /* Directly dispatch request retiring.  While we have the work queue
 830          * to handle this, the waiter on a request often wants an associated
 831          * buffer to have made it to the inactive list, and we would need
 832          * a separate wait queue to handle that.
 833          */
 834         if (ret == 0)
 835                 i915_gem_retire_requests(dev);
 836
 837         return ret;
 838 }
 839
 840 static void
 841 i915_gem_flush(struct drm_device *dev,
 842                uint32_t invalidate_domains,
 843                uint32_t flush_domains)
 844 {
 845         drm_i915_private_t *dev_priv = dev->dev_private;
 846         uint32_t cmd;
 847         RING_LOCALS;
 848
 849 #if WATCH_EXEC
 850         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
 851                   invalidate_domains, flush_domains);
 852 #endif
 853
 854         if (flush_domains & I915_GEM_DOMAIN_CPU)
 855                 drm_agp_chipset_flush(dev);
 856
 857         if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU |
 858                                                      I915_GEM_DOMAIN_GTT)) {
 859                 /*
 860                  * read/write caches:
 861                  *
 862                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
 863                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
 864                  * also flushed at 2d versus 3d pipeline switches.
 865                  *
 866                  * read-only caches:
 867                  *
 868                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
 869                  * MI_READ_FLUSH is set, and is always flushed on 965.
 870                  *
 871                  * I915_GEM_DOMAIN_COMMAND may not exist?
 872                  *
 873                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 874                  * invalidated when MI_EXE_FLUSH is set.
 875                  *
 876                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 877                  * invalidated with every MI_FLUSH.
 878                  *
 879                  * TLBs:
 880                  *
 881                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 882                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 883                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 884                  * are flushed at any MI_FLUSH.
 885                  */
 886
 887                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 888                 if ((invalidate_domains|flush_domains) &
 889                     I915_GEM_DOMAIN_RENDER)
 890                         cmd &= ~MI_NO_WRITE_FLUSH;
 891                 if (!IS_I965G(dev)) {
 892                         /*
 893                          * On the 965, the sampler cache always gets flushed
 894                          * and this bit is reserved.
 895                          */
 896                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
 897                                 cmd |= MI_READ_FLUSH;
 898                 }
 899                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 900                         cmd |= MI_EXE_FLUSH;
 901
 902 #if WATCH_EXEC
 903                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
 904 #endif
 905                 BEGIN_LP_RING(2);
 906                 OUT_RING(cmd);
 907                 OUT_RING(0); /* noop */
 908                 ADVANCE_LP_RING();
 909         }
 910 }
 911
 912 /**
 913  * Ensures that all rendering to the object has completed and the object is
 914  * safe to unbind from the GTT or access from the CPU.
 915  */
 916 static int
 917 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
 918 {
 919         struct drm_device *dev = obj->dev;
 920         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 921         int ret;
 922
 923         /* This function only exists to support waiting for existing rendering,
 924          * not for emitting required flushes.
 925          */
 926         BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
 927
 928         /* If there is rendering queued on the buffer being evicted, wait for
 929          * it.
 930          */
 931         if (obj_priv->active) {
 932 #if WATCH_BUF
 933                 DRM_INFO("%s: object %p wait for seqno %08x\n",
 934                           __func__, obj, obj_priv->last_rendering_seqno);
 935 #endif
 936                 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
 937                 if (ret != 0)
 938                         return ret;
 939         }
 940
 941         return 0;
 942 }
 943
 944 /**
 945  * Unbinds an object from the GTT aperture.
 946  */
 947 static int
 948 i915_gem_object_unbind(struct drm_gem_object *obj)
 949 {
 950         struct drm_device *dev = obj->dev;
 951         struct drm_i915_gem_object *obj_priv = obj->driver_private;
 952         int ret = 0;
 953
 954 #if WATCH_BUF
 955         DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
 956         DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
 957 #endif
 958         if (obj_priv->gtt_space == NULL)
 959                 return 0;
 960
 961         if (obj_priv->pin_count != 0) {
 962                 DRM_ERROR("Attempting to unbind pinned buffer\n");
 963                 return -EINVAL;
 964         }
 965
 966         /* Move the object to the CPU domain to ensure that
 967          * any possible CPU writes while it's not in the GTT
 968          * are flushed when we go to remap it. This will
 969          * also ensure that all pending GPU writes are finished
 970          * before we unbind.
 971          */
 972         ret = i915_gem_object_set_to_cpu_domain(obj, 1);
 973         if (ret) {
 974                 if (ret != -ERESTARTSYS)
 975                         DRM_ERROR("set_domain failed: %d\n", ret);
 976                 return ret;
 977         }
 978
 979         if (obj_priv->agp_mem != NULL) {
 980                 drm_unbind_agp(obj_priv->agp_mem);
 981                 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
 982                 obj_priv->agp_mem = NULL;
 983         }
 984
 985         BUG_ON(obj_priv->active);
 986
 987         i915_gem_object_free_page_list(obj);
 988
 989         if (obj_priv->gtt_space) {
 990                 atomic_dec(&dev->gtt_count);
 991                 atomic_sub(obj->size, &dev->gtt_memory);
 992
 993                 drm_mm_put_block(obj_priv->gtt_space);
 994                 obj_priv->gtt_space = NULL;
 995         }
 996
 997         /* Remove ourselves from the LRU list if present. */
 998         if (!list_empty(&obj_priv->list))
 999                 list_del_init(&obj_priv->list);
1000
1001         return 0;
1002 }
1003
1004 static int
1005 i915_gem_evict_something(struct drm_device *dev)
1006 {
1007         drm_i915_private_t *dev_priv = dev->dev_private;
1008         struct drm_gem_object *obj;
1009         struct drm_i915_gem_object *obj_priv;
1010         int ret = 0;
1011
1012         for (;;) {
1013                 /* If there's an inactive buffer available now, grab it
1014                  * and be done.
1015                  */
1016                 if (!list_empty(&dev_priv->mm.inactive_list)) {
1017                         obj_priv = list_first_entry(&dev_priv->mm.inactive_list,
1018                                                     struct drm_i915_gem_object,
1019                                                     list);
1020                         obj = obj_priv->obj;
1021                         BUG_ON(obj_priv->pin_count != 0);
1022 #if WATCH_LRU
1023                         DRM_INFO("%s: evicting %p\n", __func__, obj);
1024 #endif
1025                         BUG_ON(obj_priv->active);
1026
1027                         /* Wait on the rendering and unbind the buffer. */
1028                         ret = i915_gem_object_unbind(obj);
1029                         break;
1030                 }
1031
1032                 /* If we didn't get anything, but the ring is still processing
1033                  * things, wait for one of those things to finish and hopefully
1034                  * leave us a buffer to evict.
1035                  */
1036                 if (!list_empty(&dev_priv->mm.request_list)) {
1037                         struct drm_i915_gem_request *request;
1038
1039                         request = list_first_entry(&dev_priv->mm.request_list,
1040                                                    struct drm_i915_gem_request,
1041                                                    list);
1042
1043                         ret = i915_wait_request(dev, request->seqno);
1044                         if (ret)
1045                                 break;
1046
1047                         /* if waiting caused an object to become inactive,
1048                          * then loop around and wait for it. Otherwise, we
1049                          * assume that waiting freed and unbound something,
1050                          * so there should now be some space in the GTT
1051                          */
1052                         if (!list_empty(&dev_priv->mm.inactive_list))
1053                                 continue;
1054                         break;
1055                 }
1056
1057                 /* If we didn't have anything on the request list but there
1058                  * are buffers awaiting a flush, emit one and try again.
1059                  * When we wait on it, those buffers waiting for that flush
1060                  * will get moved to inactive.
1061                  */
1062                 if (!list_empty(&dev_priv->mm.flushing_list)) {
1063                         obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1064                                                     struct drm_i915_gem_object,
1065                                                     list);
1066                         obj = obj_priv->obj;
1067
1068                         i915_gem_flush(dev,
1069                                        obj->write_domain,
1070                                        obj->write_domain);
1071                         i915_add_request(dev, obj->write_domain);
1072
1073                         obj = NULL;
1074                         continue;
1075                 }
1076
1077                 DRM_ERROR("inactive empty %d request empty %d "
1078                           "flushing empty %d\n",
1079                           list_empty(&dev_priv->mm.inactive_list),
1080                           list_empty(&dev_priv->mm.request_list),
1081                           list_empty(&dev_priv->mm.flushing_list));
1082                 /* If we didn't do any of the above, there's nothing to be done
1083                  * and we just can't fit it in.
1084                  */
1085                 return -ENOMEM;
1086         }
1087         return ret;
1088 }
1089
1090 static int
1091 i915_gem_object_get_page_list(struct drm_gem_object *obj)
1092 {
1093         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1094         int page_count, i;
1095         struct address_space *mapping;
1096         struct inode *inode;
1097         struct page *page;
1098         int ret;
1099
1100         if (obj_priv->page_list)
1101                 return 0;
1102
1103         /* Get the list of pages out of our struct file.  They'll be pinned
1104          * at this point until we release them.
1105          */
1106         page_count = obj->size / PAGE_SIZE;
1107         BUG_ON(obj_priv->page_list != NULL);
1108         obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *),
1109                                          DRM_MEM_DRIVER);
1110         if (obj_priv->page_list == NULL) {
1111                 DRM_ERROR("Faled to allocate page list\n");
1112                 return -ENOMEM;
1113         }
1114
1115         inode = obj->filp->f_path.dentry->d_inode;
1116         mapping = inode->i_mapping;
1117         for (i = 0; i < page_count; i++) {
1118                 page = read_mapping_page(mapping, i, NULL);
1119                 if (IS_ERR(page)) {
1120                         ret = PTR_ERR(page);
1121                         DRM_ERROR("read_mapping_page failed: %d\n", ret);
1122                         i915_gem_object_free_page_list(obj);
1123                         return ret;
1124                 }
1125                 obj_priv->page_list[i] = page;
1126         }
1127         return 0;
1128 }
1129
1130 /**
1131  * Finds free space in the GTT aperture and binds the object there.
1132  */
1133 static int
1134 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
1135 {
1136         struct drm_device *dev = obj->dev;
1137         drm_i915_private_t *dev_priv = dev->dev_private;
1138         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1139         struct drm_mm_node *free_space;
1140         int page_count, ret;
1141
1142         if (alignment == 0)
1143                 alignment = PAGE_SIZE;
1144         if (alignment & (PAGE_SIZE - 1)) {
1145                 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
1146                 return -EINVAL;
1147         }
1148
1149  search_free:
1150         free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
1151                                         obj->size, alignment, 0);
1152         if (free_space != NULL) {
1153                 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
1154                                                        alignment);
1155                 if (obj_priv->gtt_space != NULL) {
1156                         obj_priv->gtt_space->private = obj;
1157                         obj_priv->gtt_offset = obj_priv->gtt_space->start;
1158                 }
1159         }
1160         if (obj_priv->gtt_space == NULL) {
1161                 /* If the gtt is empty and we're still having trouble
1162                  * fitting our object in, we're out of memory.
1163                  */
1164 #if WATCH_LRU
1165                 DRM_INFO("%s: GTT full, evicting something\n", __func__);
1166 #endif
1167                 if (list_empty(&dev_priv->mm.inactive_list) &&
1168                     list_empty(&dev_priv->mm.flushing_list) &&
1169                     list_empty(&dev_priv->mm.active_list)) {
1170                         DRM_ERROR("GTT full, but LRU list empty\n");
1171                         return -ENOMEM;
1172                 }
1173
1174                 ret = i915_gem_evict_something(dev);
1175                 if (ret != 0) {
1176                         DRM_ERROR("Failed to evict a buffer %d\n", ret);
1177                         return ret;
1178                 }
1179                 goto search_free;
1180         }
1181
1182 #if WATCH_BUF
1183         DRM_INFO("Binding object of size %d at 0x%08x\n",
1184                  obj->size, obj_priv->gtt_offset);
1185 #endif
1186         ret = i915_gem_object_get_page_list(obj);
1187         if (ret) {
1188                 drm_mm_put_block(obj_priv->gtt_space);
1189                 obj_priv->gtt_space = NULL;
1190                 return ret;
1191         }
1192
1193         page_count = obj->size / PAGE_SIZE;
1194         /* Create an AGP memory structure pointing at our pages, and bind it
1195          * into the GTT.
1196          */
1197         obj_priv->agp_mem = drm_agp_bind_pages(dev,
1198                                                obj_priv->page_list,
1199                                                page_count,
1200                                                obj_priv->gtt_offset,
1201                                                obj_priv->agp_type);
1202         if (obj_priv->agp_mem == NULL) {
1203                 i915_gem_object_free_page_list(obj);
1204                 drm_mm_put_block(obj_priv->gtt_space);
1205                 obj_priv->gtt_space = NULL;
1206                 return -ENOMEM;
1207         }
1208         atomic_inc(&dev->gtt_count);
1209         atomic_add(obj->size, &dev->gtt_memory);
1210
1211         /* Assert that the object is not currently in any GPU domain. As it
1212          * wasn't in the GTT, there shouldn't be any way it could have been in
1213          * a GPU cache
1214          */
1215         BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1216         BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
1217
1218         return 0;
1219 }
1220
1221 void
1222 i915_gem_clflush_object(struct drm_gem_object *obj)
1223 {
1224         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1225
1226         /* If we don't have a page list set up, then we're not pinned
1227          * to GPU, and we can ignore the cache flush because it'll happen
1228          * again at bind time.
1229          */
1230         if (obj_priv->page_list == NULL)
1231                 return;
1232
1233         drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE);
1234 }
1235
1236 /** Flushes any GPU write domain for the object if it's dirty. */
1237 static void
1238 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
1239 {
1240         struct drm_device *dev = obj->dev;
1241         uint32_t seqno;
1242
1243         if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
1244                 return;
1245
1246         /* Queue the GPU write cache flushing we need. */
1247         i915_gem_flush(dev, 0, obj->write_domain);
1248         seqno = i915_add_request(dev, obj->write_domain);
1249         obj->write_domain = 0;
1250         i915_gem_object_move_to_active(obj, seqno);
1251 }
1252
1253 /** Flushes the GTT write domain for the object if it's dirty. */
1254 static void
1255 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
1256 {
1257         if (obj->write_domain != I915_GEM_DOMAIN_GTT)
1258                 return;
1259
1260         /* No actual flushing is required for the GTT write domain.   Writes
1261          * to it immediately go to main memory as far as we know, so there's
1262          * no chipset flush.  It also doesn't land in render cache.
1263          */
1264         obj->write_domain = 0;
1265 }
1266
1267 /** Flushes the CPU write domain for the object if it's dirty. */
1268 static void
1269 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
1270 {
1271         struct drm_device *dev = obj->dev;
1272
1273         if (obj->write_domain != I915_GEM_DOMAIN_CPU)
1274                 return;
1275
1276         i915_gem_clflush_object(obj);
1277         drm_agp_chipset_flush(dev);
1278         obj->write_domain = 0;
1279 }
1280
1281 /**
1282  * Moves a single object to the GTT read, and possibly write domain.
1283  *
1284  * This function returns when the move is complete, including waiting on
1285  * flushes to occur.
1286  */
1287 static int
1288 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
1289 {
1290         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1291         int ret;
1292
1293         i915_gem_object_flush_gpu_write_domain(obj);
1294         /* Wait on any GPU rendering and flushing to occur. */
1295         ret = i915_gem_object_wait_rendering(obj);
1296         if (ret != 0)
1297                 return ret;
1298
1299         /* If we're writing through the GTT domain, then CPU and GPU caches
1300          * will need to be invalidated at next use.
1301          */
1302         if (write)
1303                 obj->read_domains &= I915_GEM_DOMAIN_GTT;
1304
1305         i915_gem_object_flush_cpu_write_domain(obj);
1306
1307         /* It should now be out of any other write domains, and we can update
1308          * the domain values for our changes.
1309          */
1310         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
1311         obj->read_domains |= I915_GEM_DOMAIN_GTT;
1312         if (write) {
1313                 obj->write_domain = I915_GEM_DOMAIN_GTT;
1314                 obj_priv->dirty = 1;
1315         }
1316
1317         return 0;
1318 }
1319
1320 /**
1321  * Moves a single object to the CPU read, and possibly write domain.
1322  *
1323  * This function returns when the move is complete, including waiting on
1324  * flushes to occur.
1325  */
1326 static int
1327 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
1328 {
1329         struct drm_device *dev = obj->dev;
1330         int ret;
1331
1332         i915_gem_object_flush_gpu_write_domain(obj);
1333         /* Wait on any GPU rendering and flushing to occur. */
1334         ret = i915_gem_object_wait_rendering(obj);
1335         if (ret != 0)
1336                 return ret;
1337
1338         i915_gem_object_flush_gtt_write_domain(obj);
1339
1340         /* If we have a partially-valid cache of the object in the CPU,
1341          * finish invalidating it and free the per-page flags.
1342          */
1343         i915_gem_object_set_to_full_cpu_read_domain(obj);
1344
1345         /* Flush the CPU cache if it's still invalid. */
1346         if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
1347                 i915_gem_clflush_object(obj);
1348                 drm_agp_chipset_flush(dev);
1349
1350                 obj->read_domains |= I915_GEM_DOMAIN_CPU;
1351         }
1352
1353         /* It should now be out of any other write domains, and we can update
1354          * the domain values for our changes.
1355          */
1356         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1357
1358         /* If we're writing through the CPU, then the GPU read domains will
1359          * need to be invalidated at next use.
1360          */
1361         if (write) {
1362                 obj->read_domains &= I915_GEM_DOMAIN_CPU;
1363                 obj->write_domain = I915_GEM_DOMAIN_CPU;
1364         }
1365
1366         return 0;
1367 }
1368
1369 /*
1370  * Set the next domain for the specified object. This
1371  * may not actually perform the necessary flushing/invaliding though,
1372  * as that may want to be batched with other set_domain operations
1373  *
1374  * This is (we hope) the only really tricky part of gem. The goal
1375  * is fairly simple -- track which caches hold bits of the object
1376  * and make sure they remain coherent. A few concrete examples may
1377  * help to explain how it works. For shorthand, we use the notation
1378  * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
1379  * a pair of read and write domain masks.
1380  *
1381  * Case 1: the batch buffer
1382  *
1383  *      1. Allocated
1384  *      2. Written by CPU
1385  *      3. Mapped to GTT
1386  *      4. Read by GPU
1387  *      5. Unmapped from GTT
1388  *      6. Freed
1389  *
1390  *      Let's take these a step at a time
1391  *
1392  *      1. Allocated
1393  *              Pages allocated from the kernel may still have
1394  *              cache contents, so we set them to (CPU, CPU) always.
1395  *      2. Written by CPU (using pwrite)
1396  *              The pwrite function calls set_domain (CPU, CPU) and
1397  *              this function does nothing (as nothing changes)
1398  *      3. Mapped by GTT
1399  *              This function asserts that the object is not
1400  *              currently in any GPU-based read or write domains
1401  *      4. Read by GPU
1402  *              i915_gem_execbuffer calls set_domain (COMMAND, 0).
1403  *              As write_domain is zero, this function adds in the
1404  *              current read domains (CPU+COMMAND, 0).
1405  *              flush_domains is set to CPU.
1406  *              invalidate_domains is set to COMMAND
1407  *              clflush is run to get data out of the CPU caches
1408  *              then i915_dev_set_domain calls i915_gem_flush to
1409  *              emit an MI_FLUSH and drm_agp_chipset_flush
1410  *      5. Unmapped from GTT
1411  *              i915_gem_object_unbind calls set_domain (CPU, CPU)
1412  *              flush_domains and invalidate_domains end up both zero
1413  *              so no flushing/invalidating happens
1414  *      6. Freed
1415  *              yay, done
1416  *
1417  * Case 2: The shared render buffer
1418  *
1419  *      1. Allocated
1420  *      2. Mapped to GTT
1421  *      3. Read/written by GPU
1422  *      4. set_domain to (CPU,CPU)
1423  *      5. Read/written by CPU
1424  *      6. Read/written by GPU
1425  *
1426  *      1. Allocated
1427  *              Same as last example, (CPU, CPU)
1428  *      2. Mapped to GTT
1429  *              Nothing changes (assertions find that it is not in the GPU)
1430  *      3. Read/written by GPU
1431  *              execbuffer calls set_domain (RENDER, RENDER)
1432  *              flush_domains gets CPU
1433  *              invalidate_domains gets GPU
1434  *              clflush (obj)
1435  *              MI_FLUSH and drm_agp_chipset_flush
1436  *      4. set_domain (CPU, CPU)
1437  *              flush_domains gets GPU
1438  *              invalidate_domains gets CPU
1439  *              wait_rendering (obj) to make sure all drawing is complete.
1440  *              This will include an MI_FLUSH to get the data from GPU
1441  *              to memory
1442  *              clflush (obj) to invalidate the CPU cache
1443  *              Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
1444  *      5. Read/written by CPU
1445  *              cache lines are loaded and dirtied
1446  *      6. Read written by GPU
1447  *              Same as last GPU access
1448  *
1449  * Case 3: The constant buffer
1450  *
1451  *      1. Allocated
1452  *      2. Written by CPU
1453  *      3. Read by GPU
1454  *      4. Updated (written) by CPU again
1455  *      5. Read by GPU
1456  *
1457  *      1. Allocated
1458  *              (CPU, CPU)
1459  *      2. Written by CPU
1460  *              (CPU, CPU)
1461  *      3. Read by GPU
1462  *              (CPU+RENDER, 0)
1463  *              flush_domains = CPU
1464  *              invalidate_domains = RENDER
1465  *              clflush (obj)
1466  *              MI_FLUSH
1467  *              drm_agp_chipset_flush
1468  *      4. Updated (written) by CPU again
1469  *              (CPU, CPU)
1470  *              flush_domains = 0 (no previous write domain)
1471  *              invalidate_domains = 0 (no new read domains)
1472  *      5. Read by GPU
1473  *              (CPU+RENDER, 0)
1474  *              flush_domains = CPU
1475  *              invalidate_domains = RENDER
1476  *              clflush (obj)
1477  *              MI_FLUSH
1478  *              drm_agp_chipset_flush
1479  */
1480 static void
1481 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj,
1482                                   uint32_t read_domains,
1483                                   uint32_t write_domain)
1484 {
1485         struct drm_device               *dev = obj->dev;
1486         struct drm_i915_gem_object      *obj_priv = obj->driver_private;
1487         uint32_t                        invalidate_domains = 0;
1488         uint32_t                        flush_domains = 0;
1489
1490         BUG_ON(read_domains & I915_GEM_DOMAIN_CPU);
1491         BUG_ON(write_domain == I915_GEM_DOMAIN_CPU);
1492
1493 #if WATCH_BUF
1494         DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
1495                  __func__, obj,
1496                  obj->read_domains, read_domains,
1497                  obj->write_domain, write_domain);
1498 #endif
1499         /*
1500          * If the object isn't moving to a new write domain,
1501          * let the object stay in multiple read domains
1502          */
1503         if (write_domain == 0)
1504                 read_domains |= obj->read_domains;
1505         else
1506                 obj_priv->dirty = 1;
1507
1508         /*
1509          * Flush the current write domain if
1510          * the new read domains don't match. Invalidate
1511          * any read domains which differ from the old
1512          * write domain
1513          */
1514         if (obj->write_domain && obj->write_domain != read_domains) {
1515                 flush_domains |= obj->write_domain;
1516                 invalidate_domains |= read_domains & ~obj->write_domain;
1517         }
1518         /*
1519          * Invalidate any read caches which may have
1520          * stale data. That is, any new read domains.
1521          */
1522         invalidate_domains |= read_domains & ~obj->read_domains;
1523         if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
1524 #if WATCH_BUF
1525                 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
1526                          __func__, flush_domains, invalidate_domains);
1527 #endif
1528                 i915_gem_clflush_object(obj);
1529         }
1530
1531         if ((write_domain | flush_domains) != 0)
1532                 obj->write_domain = write_domain;
1533         obj->read_domains = read_domains;
1534
1535         dev->invalidate_domains |= invalidate_domains;
1536         dev->flush_domains |= flush_domains;
1537 #if WATCH_BUF
1538         DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
1539                  __func__,
1540                  obj->read_domains, obj->write_domain,
1541                  dev->invalidate_domains, dev->flush_domains);
1542 #endif
1543 }
1544
1545 /**
1546  * Moves the object from a partially CPU read to a full one.
1547  *
1548  * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
1549  * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
1550  */
1551 static void
1552 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
1553 {
1554         struct drm_device *dev = obj->dev;
1555         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1556
1557         if (!obj_priv->page_cpu_valid)
1558                 return;
1559
1560         /* If we're partially in the CPU read domain, finish moving it in.
1561          */
1562         if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
1563                 int i;
1564
1565                 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
1566                         if (obj_priv->page_cpu_valid[i])
1567                                 continue;
1568                         drm_clflush_pages(obj_priv->page_list + i, 1);
1569                 }
1570                 drm_agp_chipset_flush(dev);
1571         }
1572
1573         /* Free the page_cpu_valid mappings which are now stale, whether
1574          * or not we've got I915_GEM_DOMAIN_CPU.
1575          */
1576         drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE,
1577                  DRM_MEM_DRIVER);
1578         obj_priv->page_cpu_valid = NULL;
1579 }
1580
1581 /**
1582  * Set the CPU read domain on a range of the object.
1583  *
1584  * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
1585  * not entirely valid.  The page_cpu_valid member of the object flags which
1586  * pages have been flushed, and will be respected by
1587  * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
1588  * of the whole object.
1589  *
1590  * This function returns when the move is complete, including waiting on
1591  * flushes to occur.
1592  */
1593 static int
1594 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
1595                                           uint64_t offset, uint64_t size)
1596 {
1597         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1598         int i, ret;
1599
1600         if (offset == 0 && size == obj->size)
1601                 return i915_gem_object_set_to_cpu_domain(obj, 0);
1602
1603         i915_gem_object_flush_gpu_write_domain(obj);
1604         /* Wait on any GPU rendering and flushing to occur. */
1605         ret = i915_gem_object_wait_rendering(obj);
1606         if (ret != 0)
1607                 return ret;
1608         i915_gem_object_flush_gtt_write_domain(obj);
1609
1610         /* If we're already fully in the CPU read domain, we're done. */
1611         if (obj_priv->page_cpu_valid == NULL &&
1612             (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
1613                 return 0;
1614
1615         /* Otherwise, create/clear the per-page CPU read domain flag if we're
1616          * newly adding I915_GEM_DOMAIN_CPU
1617          */
1618         if (obj_priv->page_cpu_valid == NULL) {
1619                 obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE,
1620                                                       DRM_MEM_DRIVER);
1621                 if (obj_priv->page_cpu_valid == NULL)
1622                         return -ENOMEM;
1623         } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
1624                 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
1625
1626         /* Flush the cache on any pages that are still invalid from the CPU's
1627          * perspective.
1628          */
1629         for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
1630              i++) {
1631                 if (obj_priv->page_cpu_valid[i])
1632                         continue;
1633
1634                 drm_clflush_pages(obj_priv->page_list + i, 1);
1635
1636                 obj_priv->page_cpu_valid[i] = 1;
1637         }
1638
1639         /* It should now be out of any other write domains, and we can update
1640          * the domain values for our changes.
1641          */
1642         BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
1643
1644         obj->read_domains |= I915_GEM_DOMAIN_CPU;
1645
1646         return 0;
1647 }
1648
1649 /**
1650  * Pin an object to the GTT and evaluate the relocations landing in it.
1651  */
1652 static int
1653 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
1654                                  struct drm_file *file_priv,
1655                                  struct drm_i915_gem_exec_object *entry)
1656 {
1657         struct drm_device *dev = obj->dev;
1658         drm_i915_private_t *dev_priv = dev->dev_private;
1659         struct drm_i915_gem_relocation_entry reloc;
1660         struct drm_i915_gem_relocation_entry __user *relocs;
1661         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1662         int i, ret;
1663         void __iomem *reloc_page;
1664
1665         /* Choose the GTT offset for our buffer and put it there. */
1666         ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
1667         if (ret)
1668                 return ret;
1669
1670         entry->offset = obj_priv->gtt_offset;
1671
1672         relocs = (struct drm_i915_gem_relocation_entry __user *)
1673                  (uintptr_t) entry->relocs_ptr;
1674         /* Apply the relocations, using the GTT aperture to avoid cache
1675          * flushing requirements.
1676          */
1677         for (i = 0; i < entry->relocation_count; i++) {
1678                 struct drm_gem_object *target_obj;
1679                 struct drm_i915_gem_object *target_obj_priv;
1680                 uint32_t reloc_val, reloc_offset;
1681                 uint32_t __iomem *reloc_entry;
1682
1683                 ret = copy_from_user(&reloc, relocs + i, sizeof(reloc));
1684                 if (ret != 0) {
1685                         i915_gem_object_unpin(obj);
1686                         return ret;
1687                 }
1688
1689                 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
1690                                                    reloc.target_handle);
1691                 if (target_obj == NULL) {
1692                         i915_gem_object_unpin(obj);
1693                         return -EBADF;
1694                 }
1695                 target_obj_priv = target_obj->driver_private;
1696
1697                 /* The target buffer should have appeared before us in the
1698                  * exec_object list, so it should have a GTT space bound by now.
1699                  */
1700                 if (target_obj_priv->gtt_space == NULL) {
1701                         DRM_ERROR("No GTT space found for object %d\n",
1702                                   reloc.target_handle);
1703                         drm_gem_object_unreference(target_obj);
1704                         i915_gem_object_unpin(obj);
1705                         return -EINVAL;
1706                 }
1707
1708                 if (reloc.offset > obj->size - 4) {
1709                         DRM_ERROR("Relocation beyond object bounds: "
1710                                   "obj %p target %d offset %d size %d.\n",
1711                                   obj, reloc.target_handle,
1712                                   (int) reloc.offset, (int) obj->size);
1713                         drm_gem_object_unreference(target_obj);
1714                         i915_gem_object_unpin(obj);
1715                         return -EINVAL;
1716                 }
1717                 if (reloc.offset & 3) {
1718                         DRM_ERROR("Relocation not 4-byte aligned: "
1719                                   "obj %p target %d offset %d.\n",
1720                                   obj, reloc.target_handle,
1721                                   (int) reloc.offset);
1722                         drm_gem_object_unreference(target_obj);
1723                         i915_gem_object_unpin(obj);
1724                         return -EINVAL;
1725                 }
1726
1727                 if (reloc.write_domain & I915_GEM_DOMAIN_CPU ||
1728                     reloc.read_domains & I915_GEM_DOMAIN_CPU) {
1729                         DRM_ERROR("reloc with read/write CPU domains: "
1730                                   "obj %p target %d offset %d "
1731                                   "read %08x write %08x",
1732                                   obj, reloc.target_handle,
1733                                   (int) reloc.offset,
1734                                   reloc.read_domains,
1735                                   reloc.write_domain);
1736                         return -EINVAL;
1737                 }
1738
1739                 if (reloc.write_domain && target_obj->pending_write_domain &&
1740                     reloc.write_domain != target_obj->pending_write_domain) {
1741                         DRM_ERROR("Write domain conflict: "
1742                                   "obj %p target %d offset %d "
1743                                   "new %08x old %08x\n",
1744                                   obj, reloc.target_handle,
1745                                   (int) reloc.offset,
1746                                   reloc.write_domain,
1747                                   target_obj->pending_write_domain);
1748                         drm_gem_object_unreference(target_obj);
1749                         i915_gem_object_unpin(obj);
1750                         return -EINVAL;
1751                 }
1752
1753 #if WATCH_RELOC
1754                 DRM_INFO("%s: obj %p offset %08x target %d "
1755                          "read %08x write %08x gtt %08x "
1756                          "presumed %08x delta %08x\n",
1757                          __func__,
1758                          obj,
1759                          (int) reloc.offset,
1760                          (int) reloc.target_handle,
1761                          (int) reloc.read_domains,
1762                          (int) reloc.write_domain,
1763                          (int) target_obj_priv->gtt_offset,
1764                          (int) reloc.presumed_offset,
1765                          reloc.delta);
1766 #endif
1767
1768                 target_obj->pending_read_domains |= reloc.read_domains;
1769                 target_obj->pending_write_domain |= reloc.write_domain;
1770
1771                 /* If the relocation already has the right value in it, no
1772                  * more work needs to be done.
1773                  */
1774                 if (target_obj_priv->gtt_offset == reloc.presumed_offset) {
1775                         drm_gem_object_unreference(target_obj);
1776                         continue;
1777                 }
1778
1779                 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
1780                 if (ret != 0) {
1781                         drm_gem_object_unreference(target_obj);
1782                         i915_gem_object_unpin(obj);
1783                         return -EINVAL;
1784                 }
1785
1786                 /* Map the page containing the relocation we're going to
1787                  * perform.
1788                  */
1789                 reloc_offset = obj_priv->gtt_offset + reloc.offset;
1790                 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1791                                                       (reloc_offset &
1792                                                        ~(PAGE_SIZE - 1)));
1793                 reloc_entry = (uint32_t __iomem *)(reloc_page +
1794                                                    (reloc_offset & (PAGE_SIZE - 1)));
1795                 reloc_val = target_obj_priv->gtt_offset + reloc.delta;
1796
1797 #if WATCH_BUF
1798                 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
1799                           obj, (unsigned int) reloc.offset,
1800                           readl(reloc_entry), reloc_val);
1801 #endif
1802                 writel(reloc_val, reloc_entry);
1803                 io_mapping_unmap_atomic(reloc_page);
1804
1805                 /* Write the updated presumed offset for this entry back out
1806                  * to the user.
1807                  */
1808                 reloc.presumed_offset = target_obj_priv->gtt_offset;
1809                 ret = copy_to_user(relocs + i, &reloc, sizeof(reloc));
1810                 if (ret != 0) {
1811                         drm_gem_object_unreference(target_obj);
1812                         i915_gem_object_unpin(obj);
1813                         return ret;
1814                 }
1815
1816                 drm_gem_object_unreference(target_obj);
1817         }
1818
1819 #if WATCH_BUF
1820         if (0)
1821                 i915_gem_dump_object(obj, 128, __func__, ~0);
1822 #endif
1823         return 0;
1824 }
1825
1826 /** Dispatch a batchbuffer to the ring
1827  */
1828 static int
1829 i915_dispatch_gem_execbuffer(struct drm_device *dev,
1830                               struct drm_i915_gem_execbuffer *exec,
1831                               uint64_t exec_offset)
1832 {
1833         drm_i915_private_t *dev_priv = dev->dev_private;
1834         struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *)
1835                                              (uintptr_t) exec->cliprects_ptr;
1836         int nbox = exec->num_cliprects;
1837         int i = 0, count;
1838         uint32_t        exec_start, exec_len;
1839         RING_LOCALS;
1840
1841         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
1842         exec_len = (uint32_t) exec->batch_len;
1843
1844         if ((exec_start | exec_len) & 0x7) {
1845                 DRM_ERROR("alignment\n");
1846                 return -EINVAL;
1847         }
1848
1849         if (!exec_start)
1850                 return -EINVAL;
1851
1852         count = nbox ? nbox : 1;
1853
1854         for (i = 0; i < count; i++) {
1855                 if (i < nbox) {
1856                         int ret = i915_emit_box(dev, boxes, i,
1857                                                 exec->DR1, exec->DR4);
1858                         if (ret)
1859                                 return ret;
1860                 }
1861
1862                 if (IS_I830(dev) || IS_845G(dev)) {
1863                         BEGIN_LP_RING(4);
1864                         OUT_RING(MI_BATCH_BUFFER);
1865                         OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1866                         OUT_RING(exec_start + exec_len - 4);
1867                         OUT_RING(0);
1868                         ADVANCE_LP_RING();
1869                 } else {
1870                         BEGIN_LP_RING(2);
1871                         if (IS_I965G(dev)) {
1872                                 OUT_RING(MI_BATCH_BUFFER_START |
1873                                          (2 << 6) |
1874                                          MI_BATCH_NON_SECURE_I965);
1875                                 OUT_RING(exec_start);
1876                         } else {
1877                                 OUT_RING(MI_BATCH_BUFFER_START |
1878                                          (2 << 6));
1879                                 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
1880                         }
1881                         ADVANCE_LP_RING();
1882                 }
1883         }
1884
1885         /* XXX breadcrumb */
1886         return 0;
1887 }
1888
1889 /* Throttle our rendering by waiting until the ring has completed our requests
1890  * emitted over 20 msec ago.
1891  *
1892  * This should get us reasonable parallelism between CPU and GPU but also
1893  * relatively low latency when blocking on a particular request to finish.
1894  */
1895 static int
1896 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
1897 {
1898         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1899         int ret = 0;
1900         uint32_t seqno;
1901
1902         mutex_lock(&dev->struct_mutex);
1903         seqno = i915_file_priv->mm.last_gem_throttle_seqno;
1904         i915_file_priv->mm.last_gem_throttle_seqno =
1905                 i915_file_priv->mm.last_gem_seqno;
1906         if (seqno)
1907                 ret = i915_wait_request(dev, seqno);
1908         mutex_unlock(&dev->struct_mutex);
1909         return ret;
1910 }
1911
1912 int
1913 i915_gem_execbuffer(struct drm_device *dev, void *data,
1914                     struct drm_file *file_priv)
1915 {
1916         drm_i915_private_t *dev_priv = dev->dev_private;
1917         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1918         struct drm_i915_gem_execbuffer *args = data;
1919         struct drm_i915_gem_exec_object *exec_list = NULL;
1920         struct drm_gem_object **object_list = NULL;
1921         struct drm_gem_object *batch_obj;
1922         int ret, i, pinned = 0;
1923         uint64_t exec_offset;
1924         uint32_t seqno, flush_domains;
1925
1926 #if WATCH_EXEC
1927         DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
1928                   (int) args->buffers_ptr, args->buffer_count, args->batch_len);
1929 #endif
1930
1931         if (args->buffer_count < 1) {
1932                 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
1933                 return -EINVAL;
1934         }
1935         /* Copy in the exec list from userland */
1936         exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count,
1937                                DRM_MEM_DRIVER);
1938         object_list = drm_calloc(sizeof(*object_list), args->buffer_count,
1939                                  DRM_MEM_DRIVER);
1940         if (exec_list == NULL || object_list == NULL) {
1941                 DRM_ERROR("Failed to allocate exec or object list "
1942                           "for %d buffers\n",
1943                           args->buffer_count);
1944                 ret = -ENOMEM;
1945                 goto pre_mutex_err;
1946         }
1947         ret = copy_from_user(exec_list,
1948                              (struct drm_i915_relocation_entry __user *)
1949                              (uintptr_t) args->buffers_ptr,
1950                              sizeof(*exec_list) * args->buffer_count);
1951         if (ret != 0) {
1952                 DRM_ERROR("copy %d exec entries failed %d\n",
1953                           args->buffer_count, ret);
1954                 goto pre_mutex_err;
1955         }
1956
1957         mutex_lock(&dev->struct_mutex);
1958
1959         i915_verify_inactive(dev, __FILE__, __LINE__);
1960
1961         if (dev_priv->mm.wedged) {
1962                 DRM_ERROR("Execbuf while wedged\n");
1963                 mutex_unlock(&dev->struct_mutex);
1964                 return -EIO;
1965         }
1966
1967         if (dev_priv->mm.suspended) {
1968                 DRM_ERROR("Execbuf while VT-switched.\n");
1969                 mutex_unlock(&dev->struct_mutex);
1970                 return -EBUSY;
1971         }
1972
1973         /* Look up object handles and perform the relocations */
1974         for (i = 0; i < args->buffer_count; i++) {
1975                 object_list[i] = drm_gem_object_lookup(dev, file_priv,
1976                                                        exec_list[i].handle);
1977                 if (object_list[i] == NULL) {
1978                         DRM_ERROR("Invalid object handle %d at index %d\n",
1979                                    exec_list[i].handle, i);
1980                         ret = -EBADF;
1981                         goto err;
1982                 }
1983
1984                 object_list[i]->pending_read_domains = 0;
1985                 object_list[i]->pending_write_domain = 0;
1986                 ret = i915_gem_object_pin_and_relocate(object_list[i],
1987                                                        file_priv,
1988                                                        &exec_list[i]);
1989                 if (ret) {
1990                         DRM_ERROR("object bind and relocate failed %d\n", ret);
1991                         goto err;
1992                 }
1993                 pinned = i + 1;
1994         }
1995
1996         /* Set the pending read domains for the batch buffer to COMMAND */
1997         batch_obj = object_list[args->buffer_count-1];
1998         batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND;
1999         batch_obj->pending_write_domain = 0;
2000
2001         i915_verify_inactive(dev, __FILE__, __LINE__);
2002
2003         /* Zero the global flush/invalidate flags. These
2004          * will be modified as new domains are computed
2005          * for each object
2006          */
2007         dev->invalidate_domains = 0;
2008         dev->flush_domains = 0;
2009
2010         for (i = 0; i < args->buffer_count; i++) {
2011                 struct drm_gem_object *obj = object_list[i];
2012
2013                 /* Compute new gpu domains and update invalidate/flush */
2014                 i915_gem_object_set_to_gpu_domain(obj,
2015                                                   obj->pending_read_domains,
2016                                                   obj->pending_write_domain);
2017         }
2018
2019         i915_verify_inactive(dev, __FILE__, __LINE__);
2020
2021         if (dev->invalidate_domains | dev->flush_domains) {
2022 #if WATCH_EXEC
2023                 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
2024                           __func__,
2025                          dev->invalidate_domains,
2026                          dev->flush_domains);
2027 #endif
2028                 i915_gem_flush(dev,
2029                                dev->invalidate_domains,
2030                                dev->flush_domains);
2031                 if (dev->flush_domains)
2032                         (void)i915_add_request(dev, dev->flush_domains);
2033         }
2034
2035         i915_verify_inactive(dev, __FILE__, __LINE__);
2036
2037 #if WATCH_COHERENCY
2038         for (i = 0; i < args->buffer_count; i++) {
2039                 i915_gem_object_check_coherency(object_list[i],
2040                                                 exec_list[i].handle);
2041         }
2042 #endif
2043
2044         exec_offset = exec_list[args->buffer_count - 1].offset;
2045
2046 #if WATCH_EXEC
2047         i915_gem_dump_object(object_list[args->buffer_count - 1],
2048                               args->batch_len,
2049                               __func__,
2050                               ~0);
2051 #endif
2052
2053         /* Exec the batchbuffer */
2054         ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset);
2055         if (ret) {
2056                 DRM_ERROR("dispatch failed %d\n", ret);
2057                 goto err;
2058         }
2059
2060         /*
2061          * Ensure that the commands in the batch buffer are
2062          * finished before the interrupt fires
2063          */
2064         flush_domains = i915_retire_commands(dev);
2065
2066         i915_verify_inactive(dev, __FILE__, __LINE__);
2067
2068         /*
2069          * Get a seqno representing the execution of the current buffer,
2070          * which we can wait on.  We would like to mitigate these interrupts,
2071          * likely by only creating seqnos occasionally (so that we have
2072          * *some* interrupts representing completion of buffers that we can
2073          * wait on when trying to clear up gtt space).
2074          */
2075         seqno = i915_add_request(dev, flush_domains);
2076         BUG_ON(seqno == 0);
2077         i915_file_priv->mm.last_gem_seqno = seqno;
2078         for (i = 0; i < args->buffer_count; i++) {
2079                 struct drm_gem_object *obj = object_list[i];
2080
2081                 i915_gem_object_move_to_active(obj, seqno);
2082 #if WATCH_LRU
2083                 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
2084 #endif
2085         }
2086 #if WATCH_LRU
2087         i915_dump_lru(dev, __func__);
2088 #endif
2089
2090         i915_verify_inactive(dev, __FILE__, __LINE__);
2091
2092         /* Copy the new buffer offsets back to the user's exec list. */
2093         ret = copy_to_user((struct drm_i915_relocation_entry __user *)
2094                            (uintptr_t) args->buffers_ptr,
2095                            exec_list,
2096                            sizeof(*exec_list) * args->buffer_count);
2097         if (ret)
2098                 DRM_ERROR("failed to copy %d exec entries "
2099                           "back to user (%d)\n",
2100                            args->buffer_count, ret);
2101 err:
2102         if (object_list != NULL) {
2103                 for (i = 0; i < pinned; i++)
2104                         i915_gem_object_unpin(object_list[i]);
2105
2106                 for (i = 0; i < args->buffer_count; i++)
2107                         drm_gem_object_unreference(object_list[i]);
2108         }
2109         mutex_unlock(&dev->struct_mutex);
2110
2111 pre_mutex_err:
2112         drm_free(object_list, sizeof(*object_list) * args->buffer_count,
2113                  DRM_MEM_DRIVER);
2114         drm_free(exec_list, sizeof(*exec_list) * args->buffer_count,
2115                  DRM_MEM_DRIVER);
2116
2117         return ret;
2118 }
2119
2120 int
2121 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
2122 {
2123         struct drm_device *dev = obj->dev;
2124         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2125         int ret;
2126
2127         i915_verify_inactive(dev, __FILE__, __LINE__);
2128         if (obj_priv->gtt_space == NULL) {
2129                 ret = i915_gem_object_bind_to_gtt(obj, alignment);
2130                 if (ret != 0) {
2131                         DRM_ERROR("Failure to bind: %d", ret);
2132                         return ret;
2133                 }
2134         }
2135         obj_priv->pin_count++;
2136
2137         /* If the object is not active and not pending a flush,
2138          * remove it from the inactive list
2139          */
2140         if (obj_priv->pin_count == 1) {
2141                 atomic_inc(&dev->pin_count);
2142                 atomic_add(obj->size, &dev->pin_memory);
2143                 if (!obj_priv->active &&
2144                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2145                                            I915_GEM_DOMAIN_GTT)) == 0 &&
2146                     !list_empty(&obj_priv->list))
2147                         list_del_init(&obj_priv->list);
2148         }
2149         i915_verify_inactive(dev, __FILE__, __LINE__);
2150
2151         return 0;
2152 }
2153
2154 void
2155 i915_gem_object_unpin(struct drm_gem_object *obj)
2156 {
2157         struct drm_device *dev = obj->dev;
2158         drm_i915_private_t *dev_priv = dev->dev_private;
2159         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2160
2161         i915_verify_inactive(dev, __FILE__, __LINE__);
2162         obj_priv->pin_count--;
2163         BUG_ON(obj_priv->pin_count < 0);
2164         BUG_ON(obj_priv->gtt_space == NULL);
2165
2166         /* If the object is no longer pinned, and is
2167          * neither active nor being flushed, then stick it on
2168          * the inactive list
2169          */
2170         if (obj_priv->pin_count == 0) {
2171                 if (!obj_priv->active &&
2172                     (obj->write_domain & ~(I915_GEM_DOMAIN_CPU |
2173                                            I915_GEM_DOMAIN_GTT)) == 0)
2174                         list_move_tail(&obj_priv->list,
2175                                        &dev_priv->mm.inactive_list);
2176                 atomic_dec(&dev->pin_count);
2177                 atomic_sub(obj->size, &dev->pin_memory);
2178         }
2179         i915_verify_inactive(dev, __FILE__, __LINE__);
2180 }
2181
2182 int
2183 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2184                    struct drm_file *file_priv)
2185 {
2186         struct drm_i915_gem_pin *args = data;
2187         struct drm_gem_object *obj;
2188         struct drm_i915_gem_object *obj_priv;
2189         int ret;
2190
2191         mutex_lock(&dev->struct_mutex);
2192
2193         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2194         if (obj == NULL) {
2195                 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
2196                           args->handle);
2197                 mutex_unlock(&dev->struct_mutex);
2198                 return -EBADF;
2199         }
2200         obj_priv = obj->driver_private;
2201
2202         ret = i915_gem_object_pin(obj, args->alignment);
2203         if (ret != 0) {
2204                 drm_gem_object_unreference(obj);
2205                 mutex_unlock(&dev->struct_mutex);
2206                 return ret;
2207         }
2208
2209         /* XXX - flush the CPU caches for pinned objects
2210          * as the X server doesn't manage domains yet
2211          */
2212         i915_gem_object_flush_cpu_write_domain(obj);
2213         args->offset = obj_priv->gtt_offset;
2214         drm_gem_object_unreference(obj);
2215         mutex_unlock(&dev->struct_mutex);
2216
2217         return 0;
2218 }
2219
2220 int
2221 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2222                      struct drm_file *file_priv)
2223 {
2224         struct drm_i915_gem_pin *args = data;
2225         struct drm_gem_object *obj;
2226
2227         mutex_lock(&dev->struct_mutex);
2228
2229         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2230         if (obj == NULL) {
2231                 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
2232                           args->handle);
2233                 mutex_unlock(&dev->struct_mutex);
2234                 return -EBADF;
2235         }
2236
2237         i915_gem_object_unpin(obj);
2238
2239         drm_gem_object_unreference(obj);
2240         mutex_unlock(&dev->struct_mutex);
2241         return 0;
2242 }
2243
2244 int
2245 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2246                     struct drm_file *file_priv)
2247 {
2248         struct drm_i915_gem_busy *args = data;
2249         struct drm_gem_object *obj;
2250         struct drm_i915_gem_object *obj_priv;
2251
2252         mutex_lock(&dev->struct_mutex);
2253         obj = drm_gem_object_lookup(dev, file_priv, args->handle);
2254         if (obj == NULL) {
2255                 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
2256                           args->handle);
2257                 mutex_unlock(&dev->struct_mutex);
2258                 return -EBADF;
2259         }
2260
2261         obj_priv = obj->driver_private;
2262         args->busy = obj_priv->active;
2263
2264         drm_gem_object_unreference(obj);
2265         mutex_unlock(&dev->struct_mutex);
2266         return 0;
2267 }
2268
2269 int
2270 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2271                         struct drm_file *file_priv)
2272 {
2273     return i915_gem_ring_throttle(dev, file_priv);
2274 }
2275
2276 int i915_gem_init_object(struct drm_gem_object *obj)
2277 {
2278         struct drm_i915_gem_object *obj_priv;
2279
2280         obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER);
2281         if (obj_priv == NULL)
2282                 return -ENOMEM;
2283
2284         /*
2285          * We've just allocated pages from the kernel,
2286          * so they've just been written by the CPU with
2287          * zeros. They'll need to be clflushed before we
2288          * use them with the GPU.
2289          */
2290         obj->write_domain = I915_GEM_DOMAIN_CPU;
2291         obj->read_domains = I915_GEM_DOMAIN_CPU;
2292
2293         obj_priv->agp_type = AGP_USER_MEMORY;
2294
2295         obj->driver_private = obj_priv;
2296         obj_priv->obj = obj;
2297         INIT_LIST_HEAD(&obj_priv->list);
2298         return 0;
2299 }
2300
2301 void i915_gem_free_object(struct drm_gem_object *obj)
2302 {
2303         struct drm_i915_gem_object *obj_priv = obj->driver_private;
2304
2305         while (obj_priv->pin_count > 0)
2306                 i915_gem_object_unpin(obj);
2307
2308         i915_gem_object_unbind(obj);
2309
2310         drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER);
2311         drm_free(obj->driver_private, 1, DRM_MEM_DRIVER);
2312 }
2313
2314 /** Unbinds all objects that are on the given buffer list. */
2315 static int
2316 i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head)
2317 {
2318         struct drm_gem_object *obj;
2319         struct drm_i915_gem_object *obj_priv;
2320         int ret;
2321
2322         while (!list_empty(head)) {
2323                 obj_priv = list_first_entry(head,
2324                                             struct drm_i915_gem_object,
2325                                             list);
2326                 obj = obj_priv->obj;
2327
2328                 if (obj_priv->pin_count != 0) {
2329                         DRM_ERROR("Pinned object in unbind list\n");
2330                         mutex_unlock(&dev->struct_mutex);
2331                         return -EINVAL;
2332                 }
2333
2334                 ret = i915_gem_object_unbind(obj);
2335                 if (ret != 0) {
2336                         DRM_ERROR("Error unbinding object in LeaveVT: %d\n",
2337                                   ret);
2338                         mutex_unlock(&dev->struct_mutex);
2339                         return ret;
2340                 }
2341         }
2342
2343
2344         return 0;
2345 }
2346
2347 static int
2348 i915_gem_idle(struct drm_device *dev)
2349 {
2350         drm_i915_private_t *dev_priv = dev->dev_private;
2351         uint32_t seqno, cur_seqno, last_seqno;
2352         int stuck, ret;
2353
2354         mutex_lock(&dev->struct_mutex);
2355
2356         if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
2357                 mutex_unlock(&dev->struct_mutex);
2358                 return 0;
2359         }
2360
2361         /* Hack!  Don't let anybody do execbuf while we don't control the chip.
2362          * We need to replace this with a semaphore, or something.
2363          */
2364         dev_priv->mm.suspended = 1;
2365
2366         /* Cancel the retire work handler, wait for it to finish if running
2367          */
2368         mutex_unlock(&dev->struct_mutex);
2369         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2370         mutex_lock(&dev->struct_mutex);
2371
2372         i915_kernel_lost_context(dev);
2373
2374         /* Flush the GPU along with all non-CPU write domains
2375          */
2376         i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT),
2377                        ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT));
2378         seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU |
2379                                         I915_GEM_DOMAIN_GTT));
2380
2381         if (seqno == 0) {
2382                 mutex_unlock(&dev->struct_mutex);
2383                 return -ENOMEM;
2384         }
2385
2386         dev_priv->mm.waiting_gem_seqno = seqno;
2387         last_seqno = 0;
2388         stuck = 0;
2389         for (;;) {
2390                 cur_seqno = i915_get_gem_seqno(dev);
2391                 if (i915_seqno_passed(cur_seqno, seqno))
2392                         break;
2393                 if (last_seqno == cur_seqno) {
2394                         if (stuck++ > 100) {
2395                                 DRM_ERROR("hardware wedged\n");
2396                                 dev_priv->mm.wedged = 1;
2397                                 DRM_WAKEUP(&dev_priv->irq_queue);
2398                                 break;
2399                         }
2400                 }
2401                 msleep(10);
2402                 last_seqno = cur_seqno;
2403         }
2404         dev_priv->mm.waiting_gem_seqno = 0;
2405
2406         i915_gem_retire_requests(dev);
2407
2408         if (!dev_priv->mm.wedged) {
2409                 /* Active and flushing should now be empty as we've
2410                  * waited for a sequence higher than any pending execbuffer
2411                  */
2412                 WARN_ON(!list_empty(&dev_priv->mm.active_list));
2413                 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
2414                 /* Request should now be empty as we've also waited
2415                  * for the last request in the list
2416                  */
2417                 WARN_ON(!list_empty(&dev_priv->mm.request_list));
2418         }
2419
2420         /* Empty the active and flushing lists to inactive.  If there's
2421          * anything left at this point, it means that we're wedged and
2422          * nothing good's going to happen by leaving them there.  So strip
2423          * the GPU domains and just stuff them onto inactive.
2424          */
2425         while (!list_empty(&dev_priv->mm.active_list)) {
2426                 struct drm_i915_gem_object *obj_priv;
2427
2428                 obj_priv = list_first_entry(&dev_priv->mm.active_list,
2429                                             struct drm_i915_gem_object,
2430                                             list);
2431                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2432                 i915_gem_object_move_to_inactive(obj_priv->obj);
2433         }
2434
2435         while (!list_empty(&dev_priv->mm.flushing_list)) {
2436                 struct drm_i915_gem_object *obj_priv;
2437
2438                 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
2439                                             struct drm_i915_gem_object,
2440                                             list);
2441                 obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
2442                 i915_gem_object_move_to_inactive(obj_priv->obj);
2443         }
2444
2445
2446         /* Move all inactive buffers out of the GTT. */
2447         ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
2448         WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
2449         if (ret) {
2450                 mutex_unlock(&dev->struct_mutex);
2451                 return ret;
2452         }
2453
2454         i915_gem_cleanup_ringbuffer(dev);
2455         mutex_unlock(&dev->struct_mutex);
2456
2457         return 0;
2458 }
2459
2460 static int
2461 i915_gem_init_hws(struct drm_device *dev)
2462 {
2463         drm_i915_private_t *dev_priv = dev->dev_private;
2464         struct drm_gem_object *obj;
2465         struct drm_i915_gem_object *obj_priv;
2466         int ret;
2467
2468         /* If we need a physical address for the status page, it's already
2469          * initialized at driver load time.
2470          */
2471         if (!I915_NEED_GFX_HWS(dev))
2472                 return 0;
2473
2474         obj = drm_gem_object_alloc(dev, 4096);
2475         if (obj == NULL) {
2476                 DRM_ERROR("Failed to allocate status page\n");
2477                 return -ENOMEM;
2478         }
2479         obj_priv = obj->driver_private;
2480         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
2481
2482         ret = i915_gem_object_pin(obj, 4096);
2483         if (ret != 0) {
2484                 drm_gem_object_unreference(obj);
2485                 return ret;
2486         }
2487
2488         dev_priv->status_gfx_addr = obj_priv->gtt_offset;
2489
2490         dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
2491         if (dev_priv->hw_status_page == NULL) {
2492                 DRM_ERROR("Failed to map status page.\n");
2493                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2494                 drm_gem_object_unreference(obj);
2495                 return -EINVAL;
2496         }
2497         dev_priv->hws_obj = obj;
2498         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
2499         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
2500         I915_READ(HWS_PGA); /* posting read */
2501         DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
2502
2503         return 0;
2504 }
2505
2506 static int
2507 i915_gem_init_ringbuffer(struct drm_device *dev)
2508 {
2509         drm_i915_private_t *dev_priv = dev->dev_private;
2510         struct drm_gem_object *obj;
2511         struct drm_i915_gem_object *obj_priv;
2512         int ret;
2513         u32 head;
2514
2515         ret = i915_gem_init_hws(dev);
2516         if (ret != 0)
2517                 return ret;
2518
2519         obj = drm_gem_object_alloc(dev, 128 * 1024);
2520         if (obj == NULL) {
2521                 DRM_ERROR("Failed to allocate ringbuffer\n");
2522                 return -ENOMEM;
2523         }
2524         obj_priv = obj->driver_private;
2525
2526         ret = i915_gem_object_pin(obj, 4096);
2527         if (ret != 0) {
2528                 drm_gem_object_unreference(obj);
2529                 return ret;
2530         }
2531
2532         /* Set up the kernel mapping for the ring. */
2533         dev_priv->ring.Size = obj->size;
2534         dev_priv->ring.tail_mask = obj->size - 1;
2535
2536         dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset;
2537         dev_priv->ring.map.size = obj->size;
2538         dev_priv->ring.map.type = 0;
2539         dev_priv->ring.map.flags = 0;
2540         dev_priv->ring.map.mtrr = 0;
2541
2542         drm_core_ioremap_wc(&dev_priv->ring.map, dev);
2543         if (dev_priv->ring.map.handle == NULL) {
2544                 DRM_ERROR("Failed to map ringbuffer.\n");
2545                 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2546                 drm_gem_object_unreference(obj);
2547                 return -EINVAL;
2548         }
2549         dev_priv->ring.ring_obj = obj;
2550         dev_priv->ring.virtual_start = dev_priv->ring.map.handle;
2551
2552         /* Stop the ring if it's running. */
2553         I915_WRITE(PRB0_CTL, 0);
2554         I915_WRITE(PRB0_TAIL, 0);
2555         I915_WRITE(PRB0_HEAD, 0);
2556
2557         /* Initialize the ring. */
2558         I915_WRITE(PRB0_START, obj_priv->gtt_offset);
2559         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2560
2561         /* G45 ring initialization fails to reset head to zero */
2562         if (head != 0) {
2563                 DRM_ERROR("Ring head not reset to zero "
2564                           "ctl %08x head %08x tail %08x start %08x\n",
2565                           I915_READ(PRB0_CTL),
2566                           I915_READ(PRB0_HEAD),
2567                           I915_READ(PRB0_TAIL),
2568                           I915_READ(PRB0_START));
2569                 I915_WRITE(PRB0_HEAD, 0);
2570
2571                 DRM_ERROR("Ring head forced to zero "
2572                           "ctl %08x head %08x tail %08x start %08x\n",
2573                           I915_READ(PRB0_CTL),
2574                           I915_READ(PRB0_HEAD),
2575                           I915_READ(PRB0_TAIL),
2576                           I915_READ(PRB0_START));
2577         }
2578
2579         I915_WRITE(PRB0_CTL,
2580                    ((obj->size - 4096) & RING_NR_PAGES) |
2581                    RING_NO_REPORT |
2582                    RING_VALID);
2583
2584         head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
2585
2586         /* If the head is still not zero, the ring is dead */
2587         if (head != 0) {
2588                 DRM_ERROR("Ring initialization failed "
2589                           "ctl %08x head %08x tail %08x start %08x\n",
2590                           I915_READ(PRB0_CTL),
2591                           I915_READ(PRB0_HEAD),
2592                           I915_READ(PRB0_TAIL),
2593                           I915_READ(PRB0_START));
2594                 return -EIO;
2595         }
2596
2597         /* Update our cache of the ring state */
2598         i915_kernel_lost_context(dev);
2599
2600         return 0;
2601 }
2602
2603 static void
2604 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
2605 {
2606         drm_i915_private_t *dev_priv = dev->dev_private;
2607
2608         if (dev_priv->ring.ring_obj == NULL)
2609                 return;
2610
2611         drm_core_ioremapfree(&dev_priv->ring.map, dev);
2612
2613         i915_gem_object_unpin(dev_priv->ring.ring_obj);
2614         drm_gem_object_unreference(dev_priv->ring.ring_obj);
2615         dev_priv->ring.ring_obj = NULL;
2616         memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
2617
2618         if (dev_priv->hws_obj != NULL) {
2619                 struct drm_gem_object *obj = dev_priv->hws_obj;
2620                 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2621
2622                 kunmap(obj_priv->page_list[0]);
2623                 i915_gem_object_unpin(obj);
2624                 drm_gem_object_unreference(obj);
2625                 dev_priv->hws_obj = NULL;
2626                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
2627                 dev_priv->hw_status_page = NULL;
2628
2629                 /* Write high address into HWS_PGA when disabling. */
2630                 I915_WRITE(HWS_PGA, 0x1ffff000);
2631         }
2632 }
2633
2634 int
2635 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2636                        struct drm_file *file_priv)
2637 {
2638         drm_i915_private_t *dev_priv = dev->dev_private;
2639         int ret;
2640
2641         if (dev_priv->mm.wedged) {
2642                 DRM_ERROR("Reenabling wedged hardware, good luck\n");
2643                 dev_priv->mm.wedged = 0;
2644         }
2645
2646         ret = i915_gem_init_ringbuffer(dev);
2647         if (ret != 0)
2648                 return ret;
2649
2650         dev_priv->mm.gtt_mapping = io_mapping_create_wc(dev->agp->base,
2651                                                         dev->agp->agp_info.aper_size
2652                                                         * 1024 * 1024);
2653
2654         mutex_lock(&dev->struct_mutex);
2655         BUG_ON(!list_empty(&dev_priv->mm.active_list));
2656         BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2657         BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
2658         BUG_ON(!list_empty(&dev_priv->mm.request_list));
2659         dev_priv->mm.suspended = 0;
2660         mutex_unlock(&dev->struct_mutex);
2661
2662         drm_irq_install(dev);
2663
2664         return 0;
2665 }
2666
2667 int
2668 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2669                        struct drm_file *file_priv)
2670 {
2671         drm_i915_private_t *dev_priv = dev->dev_private;
2672         int ret;
2673
2674         ret = i915_gem_idle(dev);
2675         drm_irq_uninstall(dev);
2676
2677         io_mapping_free(dev_priv->mm.gtt_mapping);
2678         return ret;
2679 }
2680
2681 void
2682 i915_gem_lastclose(struct drm_device *dev)
2683 {
2684         int ret;
2685
2686         ret = i915_gem_idle(dev);
2687         if (ret)
2688                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2689 }
2690
2691 void
2692 i915_gem_load(struct drm_device *dev)
2693 {
2694         drm_i915_private_t *dev_priv = dev->dev_private;
2695
2696         INIT_LIST_HEAD(&dev_priv->mm.active_list);
2697         INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
2698         INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
2699         INIT_LIST_HEAD(&dev_priv->mm.request_list);
2700         INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
2701                           i915_gem_retire_work_handler);
2702         dev_priv->mm.next_gem_seqno = 1;
2703
2704         i915_gem_detect_bit_6_swizzle(dev);
2705 }